1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "smuio/smuio_11_0_0_offset.h" 39 #include "smuio/smuio_11_0_0_sh_mask.h" 40 #include "navi10_enum.h" 41 #include "hdp/hdp_5_0_0_offset.h" 42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 43 44 #include "soc15.h" 45 #include "soc15d.h" 46 #include "soc15_common.h" 47 #include "clearstate_gfx10.h" 48 #include "v10_structs.h" 49 #include "gfx_v10_0.h" 50 #include "nbio_v2_3.h" 51 52 /** 53 * Navi10 has two graphic rings to share each graphic pipe. 54 * 1. Primary ring 55 * 2. Async ring 56 */ 57 #define GFX10_NUM_GFX_RINGS_NV1X 1 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 75 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 76 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 77 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 78 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 79 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 80 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 81 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 82 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 83 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 84 85 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 86 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 87 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 88 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 89 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 90 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 91 92 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 93 { 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 134 }; 135 136 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 137 { 138 /* Pending on emulation bring up */ 139 }; 140 141 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 142 { 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 181 }; 182 183 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 184 { 185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000) 225 }; 226 227 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 228 { 229 /* Pending on emulation bring up */ 230 }; 231 232 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 233 { 234 /* Pending on emulation bring up */ 235 }; 236 237 #define DEFAULT_SH_MEM_CONFIG \ 238 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 239 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 240 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 241 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 242 243 244 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 245 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 246 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 247 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 248 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 249 struct amdgpu_cu_info *cu_info); 250 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 251 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 252 u32 sh_num, u32 instance); 253 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 254 255 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 256 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 257 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 258 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 259 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 260 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 261 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 262 263 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 264 { 265 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 266 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 267 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 268 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 269 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 270 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 271 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 272 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 273 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 274 } 275 276 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 277 struct amdgpu_ring *ring) 278 { 279 struct amdgpu_device *adev = kiq_ring->adev; 280 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 281 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 282 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 283 284 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 285 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 286 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 287 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 288 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 289 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 290 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 291 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 292 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 293 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 294 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 295 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 296 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 297 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 298 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 299 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 300 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 301 } 302 303 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 304 struct amdgpu_ring *ring, 305 enum amdgpu_unmap_queues_action action, 306 u64 gpu_addr, u64 seq) 307 { 308 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 309 310 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 311 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 312 PACKET3_UNMAP_QUEUES_ACTION(action) | 313 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 314 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 315 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 316 amdgpu_ring_write(kiq_ring, 317 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 318 319 if (action == PREEMPT_QUEUES_NO_UNMAP) { 320 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 321 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 322 amdgpu_ring_write(kiq_ring, seq); 323 } else { 324 amdgpu_ring_write(kiq_ring, 0); 325 amdgpu_ring_write(kiq_ring, 0); 326 amdgpu_ring_write(kiq_ring, 0); 327 } 328 } 329 330 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 331 struct amdgpu_ring *ring, 332 u64 addr, 333 u64 seq) 334 { 335 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 336 337 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 338 amdgpu_ring_write(kiq_ring, 339 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 340 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 341 PACKET3_QUERY_STATUS_COMMAND(2)); 342 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 343 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 344 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 345 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 346 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 347 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 348 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 349 } 350 351 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 352 uint16_t pasid, uint32_t flush_type, 353 bool all_hub) 354 { 355 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 356 amdgpu_ring_write(kiq_ring, 357 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 358 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 359 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 360 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 361 } 362 363 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 364 .kiq_set_resources = gfx10_kiq_set_resources, 365 .kiq_map_queues = gfx10_kiq_map_queues, 366 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 367 .kiq_query_status = gfx10_kiq_query_status, 368 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 369 .set_resources_size = 8, 370 .map_queues_size = 7, 371 .unmap_queues_size = 6, 372 .query_status_size = 7, 373 .invalidate_tlbs_size = 2, 374 }; 375 376 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 377 { 378 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 379 } 380 381 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 382 { 383 switch (adev->asic_type) { 384 case CHIP_NAVI10: 385 soc15_program_register_sequence(adev, 386 golden_settings_gc_10_1, 387 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 388 soc15_program_register_sequence(adev, 389 golden_settings_gc_10_0_nv10, 390 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 391 break; 392 case CHIP_NAVI14: 393 soc15_program_register_sequence(adev, 394 golden_settings_gc_10_1_1, 395 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 396 soc15_program_register_sequence(adev, 397 golden_settings_gc_10_1_nv14, 398 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 399 break; 400 case CHIP_NAVI12: 401 soc15_program_register_sequence(adev, 402 golden_settings_gc_10_1_2, 403 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 404 soc15_program_register_sequence(adev, 405 golden_settings_gc_10_1_2_nv12, 406 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 407 break; 408 default: 409 break; 410 } 411 } 412 413 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 414 { 415 adev->gfx.scratch.num_reg = 8; 416 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 417 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 418 } 419 420 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 421 bool wc, uint32_t reg, uint32_t val) 422 { 423 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 424 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 425 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 426 amdgpu_ring_write(ring, reg); 427 amdgpu_ring_write(ring, 0); 428 amdgpu_ring_write(ring, val); 429 } 430 431 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 432 int mem_space, int opt, uint32_t addr0, 433 uint32_t addr1, uint32_t ref, uint32_t mask, 434 uint32_t inv) 435 { 436 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 437 amdgpu_ring_write(ring, 438 /* memory (1) or register (0) */ 439 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 440 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 441 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 442 WAIT_REG_MEM_ENGINE(eng_sel))); 443 444 if (mem_space) 445 BUG_ON(addr0 & 0x3); /* Dword align */ 446 amdgpu_ring_write(ring, addr0); 447 amdgpu_ring_write(ring, addr1); 448 amdgpu_ring_write(ring, ref); 449 amdgpu_ring_write(ring, mask); 450 amdgpu_ring_write(ring, inv); /* poll interval */ 451 } 452 453 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 454 { 455 struct amdgpu_device *adev = ring->adev; 456 uint32_t scratch; 457 uint32_t tmp = 0; 458 unsigned i; 459 int r; 460 461 r = amdgpu_gfx_scratch_get(adev, &scratch); 462 if (r) { 463 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 464 return r; 465 } 466 467 WREG32(scratch, 0xCAFEDEAD); 468 469 r = amdgpu_ring_alloc(ring, 3); 470 if (r) { 471 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 472 ring->idx, r); 473 amdgpu_gfx_scratch_free(adev, scratch); 474 return r; 475 } 476 477 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 478 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 479 amdgpu_ring_write(ring, 0xDEADBEEF); 480 amdgpu_ring_commit(ring); 481 482 for (i = 0; i < adev->usec_timeout; i++) { 483 tmp = RREG32(scratch); 484 if (tmp == 0xDEADBEEF) 485 break; 486 if (amdgpu_emu_mode == 1) 487 msleep(1); 488 else 489 udelay(1); 490 } 491 492 if (i >= adev->usec_timeout) 493 r = -ETIMEDOUT; 494 495 amdgpu_gfx_scratch_free(adev, scratch); 496 497 return r; 498 } 499 500 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 501 { 502 struct amdgpu_device *adev = ring->adev; 503 struct amdgpu_ib ib; 504 struct dma_fence *f = NULL; 505 unsigned index; 506 uint64_t gpu_addr; 507 uint32_t tmp; 508 long r; 509 510 r = amdgpu_device_wb_get(adev, &index); 511 if (r) 512 return r; 513 514 gpu_addr = adev->wb.gpu_addr + (index * 4); 515 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 516 memset(&ib, 0, sizeof(ib)); 517 r = amdgpu_ib_get(adev, NULL, 16, &ib); 518 if (r) 519 goto err1; 520 521 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 522 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 523 ib.ptr[2] = lower_32_bits(gpu_addr); 524 ib.ptr[3] = upper_32_bits(gpu_addr); 525 ib.ptr[4] = 0xDEADBEEF; 526 ib.length_dw = 5; 527 528 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 529 if (r) 530 goto err2; 531 532 r = dma_fence_wait_timeout(f, false, timeout); 533 if (r == 0) { 534 r = -ETIMEDOUT; 535 goto err2; 536 } else if (r < 0) { 537 goto err2; 538 } 539 540 tmp = adev->wb.wb[index]; 541 if (tmp == 0xDEADBEEF) 542 r = 0; 543 else 544 r = -EINVAL; 545 err2: 546 amdgpu_ib_free(adev, &ib, NULL); 547 dma_fence_put(f); 548 err1: 549 amdgpu_device_wb_free(adev, index); 550 return r; 551 } 552 553 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 554 { 555 release_firmware(adev->gfx.pfp_fw); 556 adev->gfx.pfp_fw = NULL; 557 release_firmware(adev->gfx.me_fw); 558 adev->gfx.me_fw = NULL; 559 release_firmware(adev->gfx.ce_fw); 560 adev->gfx.ce_fw = NULL; 561 release_firmware(adev->gfx.rlc_fw); 562 adev->gfx.rlc_fw = NULL; 563 release_firmware(adev->gfx.mec_fw); 564 adev->gfx.mec_fw = NULL; 565 release_firmware(adev->gfx.mec2_fw); 566 adev->gfx.mec2_fw = NULL; 567 568 kfree(adev->gfx.rlc.register_list_format); 569 } 570 571 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 572 { 573 adev->gfx.cp_fw_write_wait = false; 574 575 switch (adev->asic_type) { 576 case CHIP_NAVI10: 577 case CHIP_NAVI12: 578 case CHIP_NAVI14: 579 if ((adev->gfx.me_fw_version >= 0x00000046) && 580 (adev->gfx.me_feature_version >= 27) && 581 (adev->gfx.pfp_fw_version >= 0x00000068) && 582 (adev->gfx.pfp_feature_version >= 27) && 583 (adev->gfx.mec_fw_version >= 0x0000005b) && 584 (adev->gfx.mec_feature_version >= 27)) 585 adev->gfx.cp_fw_write_wait = true; 586 break; 587 default: 588 break; 589 } 590 591 if (adev->gfx.cp_fw_write_wait == false) 592 DRM_WARN_ONCE("CP firmware version too old, please update!"); 593 } 594 595 596 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 597 { 598 const struct rlc_firmware_header_v2_1 *rlc_hdr; 599 600 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 601 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 602 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 603 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 604 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 605 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 606 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 607 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 608 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 609 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 610 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 611 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 612 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 613 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 614 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 615 } 616 617 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 618 { 619 bool ret = false; 620 621 switch (adev->pdev->revision) { 622 case 0xc2: 623 case 0xc3: 624 ret = true; 625 break; 626 default: 627 ret = false; 628 break; 629 } 630 631 return ret ; 632 } 633 634 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 635 { 636 switch (adev->asic_type) { 637 case CHIP_NAVI10: 638 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 639 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 640 break; 641 default: 642 break; 643 } 644 } 645 646 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 647 { 648 const char *chip_name; 649 char fw_name[40]; 650 char wks[10]; 651 int err; 652 struct amdgpu_firmware_info *info = NULL; 653 const struct common_firmware_header *header = NULL; 654 const struct gfx_firmware_header_v1_0 *cp_hdr; 655 const struct rlc_firmware_header_v2_0 *rlc_hdr; 656 unsigned int *tmp = NULL; 657 unsigned int i = 0; 658 uint16_t version_major; 659 uint16_t version_minor; 660 661 DRM_DEBUG("\n"); 662 663 memset(wks, 0, sizeof(wks)); 664 switch (adev->asic_type) { 665 case CHIP_NAVI10: 666 chip_name = "navi10"; 667 break; 668 case CHIP_NAVI14: 669 chip_name = "navi14"; 670 if (!(adev->pdev->device == 0x7340 && 671 adev->pdev->revision != 0x00)) 672 snprintf(wks, sizeof(wks), "_wks"); 673 break; 674 case CHIP_NAVI12: 675 chip_name = "navi12"; 676 break; 677 default: 678 BUG(); 679 } 680 681 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 682 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 683 if (err) 684 goto out; 685 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 686 if (err) 687 goto out; 688 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 689 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 690 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 691 692 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 693 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 694 if (err) 695 goto out; 696 err = amdgpu_ucode_validate(adev->gfx.me_fw); 697 if (err) 698 goto out; 699 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 700 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 701 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 702 703 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 704 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 705 if (err) 706 goto out; 707 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 708 if (err) 709 goto out; 710 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 711 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 712 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 713 714 if (!amdgpu_sriov_vf(adev)) { 715 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 716 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 717 if (err) 718 goto out; 719 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 720 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 721 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 722 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 723 if (version_major == 2 && version_minor == 1) 724 adev->gfx.rlc.is_rlc_v2_1 = true; 725 726 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 727 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 728 adev->gfx.rlc.save_and_restore_offset = 729 le32_to_cpu(rlc_hdr->save_and_restore_offset); 730 adev->gfx.rlc.clear_state_descriptor_offset = 731 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 732 adev->gfx.rlc.avail_scratch_ram_locations = 733 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 734 adev->gfx.rlc.reg_restore_list_size = 735 le32_to_cpu(rlc_hdr->reg_restore_list_size); 736 adev->gfx.rlc.reg_list_format_start = 737 le32_to_cpu(rlc_hdr->reg_list_format_start); 738 adev->gfx.rlc.reg_list_format_separate_start = 739 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 740 adev->gfx.rlc.starting_offsets_start = 741 le32_to_cpu(rlc_hdr->starting_offsets_start); 742 adev->gfx.rlc.reg_list_format_size_bytes = 743 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 744 adev->gfx.rlc.reg_list_size_bytes = 745 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 746 adev->gfx.rlc.register_list_format = 747 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 748 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 749 if (!adev->gfx.rlc.register_list_format) { 750 err = -ENOMEM; 751 goto out; 752 } 753 754 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 755 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 756 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 757 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 758 759 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 760 761 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 762 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 763 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 764 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 765 766 if (adev->gfx.rlc.is_rlc_v2_1) 767 gfx_v10_0_init_rlc_ext_microcode(adev); 768 } 769 770 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 771 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 772 if (err) 773 goto out; 774 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 775 if (err) 776 goto out; 777 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 778 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 779 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 780 781 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 782 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 783 if (!err) { 784 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 785 if (err) 786 goto out; 787 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 788 adev->gfx.mec2_fw->data; 789 adev->gfx.mec2_fw_version = 790 le32_to_cpu(cp_hdr->header.ucode_version); 791 adev->gfx.mec2_feature_version = 792 le32_to_cpu(cp_hdr->ucode_feature_version); 793 } else { 794 err = 0; 795 adev->gfx.mec2_fw = NULL; 796 } 797 798 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 799 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 800 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 801 info->fw = adev->gfx.pfp_fw; 802 header = (const struct common_firmware_header *)info->fw->data; 803 adev->firmware.fw_size += 804 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 805 806 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 807 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 808 info->fw = adev->gfx.me_fw; 809 header = (const struct common_firmware_header *)info->fw->data; 810 adev->firmware.fw_size += 811 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 812 813 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 814 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 815 info->fw = adev->gfx.ce_fw; 816 header = (const struct common_firmware_header *)info->fw->data; 817 adev->firmware.fw_size += 818 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 819 820 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 821 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 822 info->fw = adev->gfx.rlc_fw; 823 if (info->fw) { 824 header = (const struct common_firmware_header *)info->fw->data; 825 adev->firmware.fw_size += 826 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 827 } 828 if (adev->gfx.rlc.is_rlc_v2_1 && 829 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 830 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 831 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 832 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 833 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 834 info->fw = adev->gfx.rlc_fw; 835 adev->firmware.fw_size += 836 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 837 838 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 839 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 840 info->fw = adev->gfx.rlc_fw; 841 adev->firmware.fw_size += 842 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 843 844 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 845 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 846 info->fw = adev->gfx.rlc_fw; 847 adev->firmware.fw_size += 848 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 849 } 850 851 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 852 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 853 info->fw = adev->gfx.mec_fw; 854 header = (const struct common_firmware_header *)info->fw->data; 855 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 856 adev->firmware.fw_size += 857 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 858 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 859 860 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 861 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 862 info->fw = adev->gfx.mec_fw; 863 adev->firmware.fw_size += 864 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 865 866 if (adev->gfx.mec2_fw) { 867 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 868 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 869 info->fw = adev->gfx.mec2_fw; 870 header = (const struct common_firmware_header *)info->fw->data; 871 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 872 adev->firmware.fw_size += 873 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 874 le32_to_cpu(cp_hdr->jt_size) * 4, 875 PAGE_SIZE); 876 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 877 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 878 info->fw = adev->gfx.mec2_fw; 879 adev->firmware.fw_size += 880 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 881 PAGE_SIZE); 882 } 883 } 884 885 gfx_v10_0_check_fw_write_wait(adev); 886 out: 887 if (err) { 888 dev_err(adev->dev, 889 "gfx10: Failed to load firmware \"%s\"\n", 890 fw_name); 891 release_firmware(adev->gfx.pfp_fw); 892 adev->gfx.pfp_fw = NULL; 893 release_firmware(adev->gfx.me_fw); 894 adev->gfx.me_fw = NULL; 895 release_firmware(adev->gfx.ce_fw); 896 adev->gfx.ce_fw = NULL; 897 release_firmware(adev->gfx.rlc_fw); 898 adev->gfx.rlc_fw = NULL; 899 release_firmware(adev->gfx.mec_fw); 900 adev->gfx.mec_fw = NULL; 901 release_firmware(adev->gfx.mec2_fw); 902 adev->gfx.mec2_fw = NULL; 903 } 904 905 gfx_v10_0_check_gfxoff_flag(adev); 906 907 return err; 908 } 909 910 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 911 { 912 u32 count = 0; 913 const struct cs_section_def *sect = NULL; 914 const struct cs_extent_def *ext = NULL; 915 916 /* begin clear state */ 917 count += 2; 918 /* context control state */ 919 count += 3; 920 921 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 922 for (ext = sect->section; ext->extent != NULL; ++ext) { 923 if (sect->id == SECT_CONTEXT) 924 count += 2 + ext->reg_count; 925 else 926 return 0; 927 } 928 } 929 930 /* set PA_SC_TILE_STEERING_OVERRIDE */ 931 count += 3; 932 /* end clear state */ 933 count += 2; 934 /* clear state */ 935 count += 2; 936 937 return count; 938 } 939 940 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 941 volatile u32 *buffer) 942 { 943 u32 count = 0, i; 944 const struct cs_section_def *sect = NULL; 945 const struct cs_extent_def *ext = NULL; 946 int ctx_reg_offset; 947 948 if (adev->gfx.rlc.cs_data == NULL) 949 return; 950 if (buffer == NULL) 951 return; 952 953 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 954 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 955 956 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 957 buffer[count++] = cpu_to_le32(0x80000000); 958 buffer[count++] = cpu_to_le32(0x80000000); 959 960 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 961 for (ext = sect->section; ext->extent != NULL; ++ext) { 962 if (sect->id == SECT_CONTEXT) { 963 buffer[count++] = 964 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 965 buffer[count++] = cpu_to_le32(ext->reg_index - 966 PACKET3_SET_CONTEXT_REG_START); 967 for (i = 0; i < ext->reg_count; i++) 968 buffer[count++] = cpu_to_le32(ext->extent[i]); 969 } else { 970 return; 971 } 972 } 973 } 974 975 ctx_reg_offset = 976 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 977 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 978 buffer[count++] = cpu_to_le32(ctx_reg_offset); 979 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 980 981 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 982 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 983 984 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 985 buffer[count++] = cpu_to_le32(0); 986 } 987 988 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 989 { 990 /* clear state block */ 991 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 992 &adev->gfx.rlc.clear_state_gpu_addr, 993 (void **)&adev->gfx.rlc.cs_ptr); 994 995 /* jump table block */ 996 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 997 &adev->gfx.rlc.cp_table_gpu_addr, 998 (void **)&adev->gfx.rlc.cp_table_ptr); 999 } 1000 1001 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 1002 { 1003 const struct cs_section_def *cs_data; 1004 int r; 1005 1006 adev->gfx.rlc.cs_data = gfx10_cs_data; 1007 1008 cs_data = adev->gfx.rlc.cs_data; 1009 1010 if (cs_data) { 1011 /* init clear state block */ 1012 r = amdgpu_gfx_rlc_init_csb(adev); 1013 if (r) 1014 return r; 1015 } 1016 1017 /* init spm vmid with 0xf */ 1018 if (adev->gfx.rlc.funcs->update_spm_vmid) 1019 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 1020 1021 return 0; 1022 } 1023 1024 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 1025 { 1026 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 1027 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 1028 } 1029 1030 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 1031 { 1032 int r; 1033 1034 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 1035 1036 amdgpu_gfx_graphics_queue_acquire(adev); 1037 1038 r = gfx_v10_0_init_microcode(adev); 1039 if (r) 1040 DRM_ERROR("Failed to load gfx firmware!\n"); 1041 1042 return r; 1043 } 1044 1045 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 1046 { 1047 int r; 1048 u32 *hpd; 1049 const __le32 *fw_data = NULL; 1050 unsigned fw_size; 1051 u32 *fw = NULL; 1052 size_t mec_hpd_size; 1053 1054 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 1055 1056 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 1057 1058 /* take ownership of the relevant compute queues */ 1059 amdgpu_gfx_compute_queue_acquire(adev); 1060 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 1061 1062 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 1063 AMDGPU_GEM_DOMAIN_GTT, 1064 &adev->gfx.mec.hpd_eop_obj, 1065 &adev->gfx.mec.hpd_eop_gpu_addr, 1066 (void **)&hpd); 1067 if (r) { 1068 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 1069 gfx_v10_0_mec_fini(adev); 1070 return r; 1071 } 1072 1073 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 1074 1075 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 1076 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 1077 1078 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1079 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 1080 1081 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 1082 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 1083 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 1084 1085 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 1086 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 1087 &adev->gfx.mec.mec_fw_obj, 1088 &adev->gfx.mec.mec_fw_gpu_addr, 1089 (void **)&fw); 1090 if (r) { 1091 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 1092 gfx_v10_0_mec_fini(adev); 1093 return r; 1094 } 1095 1096 memcpy(fw, fw_data, fw_size); 1097 1098 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1099 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1100 } 1101 1102 return 0; 1103 } 1104 1105 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1106 { 1107 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1108 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1109 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1110 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1111 } 1112 1113 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1114 uint32_t thread, uint32_t regno, 1115 uint32_t num, uint32_t *out) 1116 { 1117 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1118 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1119 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1120 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1121 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1122 while (num--) 1123 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1124 } 1125 1126 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1127 { 1128 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1129 * field when performing a select_se_sh so it should be 1130 * zero here */ 1131 WARN_ON(simd != 0); 1132 1133 /* type 2 wave data */ 1134 dst[(*no_fields)++] = 2; 1135 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1136 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1137 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1138 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1139 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1140 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1141 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1142 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1143 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1144 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1145 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1146 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1147 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1148 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1149 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1150 } 1151 1152 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1153 uint32_t wave, uint32_t start, 1154 uint32_t size, uint32_t *dst) 1155 { 1156 WARN_ON(simd != 0); 1157 1158 wave_read_regs( 1159 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1160 dst); 1161 } 1162 1163 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1164 uint32_t wave, uint32_t thread, 1165 uint32_t start, uint32_t size, 1166 uint32_t *dst) 1167 { 1168 wave_read_regs( 1169 adev, wave, thread, 1170 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1171 } 1172 1173 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1174 u32 me, u32 pipe, u32 q, u32 vm) 1175 { 1176 nv_grbm_select(adev, me, pipe, q, vm); 1177 } 1178 1179 1180 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1181 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1182 .select_se_sh = &gfx_v10_0_select_se_sh, 1183 .read_wave_data = &gfx_v10_0_read_wave_data, 1184 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1185 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1186 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1187 }; 1188 1189 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1190 { 1191 u32 gb_addr_config; 1192 1193 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1194 1195 switch (adev->asic_type) { 1196 case CHIP_NAVI10: 1197 case CHIP_NAVI14: 1198 case CHIP_NAVI12: 1199 adev->gfx.config.max_hw_contexts = 8; 1200 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1201 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1202 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1203 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1204 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1205 break; 1206 default: 1207 BUG(); 1208 break; 1209 } 1210 1211 adev->gfx.config.gb_addr_config = gb_addr_config; 1212 1213 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1214 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1215 GB_ADDR_CONFIG, NUM_PIPES); 1216 1217 adev->gfx.config.max_tile_pipes = 1218 adev->gfx.config.gb_addr_config_fields.num_pipes; 1219 1220 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1221 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1222 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1223 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1224 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1225 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1226 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1227 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1228 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1229 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1230 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1231 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1232 } 1233 1234 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1235 int me, int pipe, int queue) 1236 { 1237 int r; 1238 struct amdgpu_ring *ring; 1239 unsigned int irq_type; 1240 1241 ring = &adev->gfx.gfx_ring[ring_id]; 1242 1243 ring->me = me; 1244 ring->pipe = pipe; 1245 ring->queue = queue; 1246 1247 ring->ring_obj = NULL; 1248 ring->use_doorbell = true; 1249 1250 if (!ring_id) 1251 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1252 else 1253 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1254 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1255 1256 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1257 r = amdgpu_ring_init(adev, ring, 1024, 1258 &adev->gfx.eop_irq, irq_type); 1259 if (r) 1260 return r; 1261 return 0; 1262 } 1263 1264 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1265 int mec, int pipe, int queue) 1266 { 1267 int r; 1268 unsigned irq_type; 1269 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1270 1271 ring = &adev->gfx.compute_ring[ring_id]; 1272 1273 /* mec0 is me1 */ 1274 ring->me = mec + 1; 1275 ring->pipe = pipe; 1276 ring->queue = queue; 1277 1278 ring->ring_obj = NULL; 1279 ring->use_doorbell = true; 1280 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1281 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1282 + (ring_id * GFX10_MEC_HPD_SIZE); 1283 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1284 1285 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1286 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1287 + ring->pipe; 1288 1289 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1290 r = amdgpu_ring_init(adev, ring, 1024, 1291 &adev->gfx.eop_irq, irq_type); 1292 if (r) 1293 return r; 1294 1295 return 0; 1296 } 1297 1298 static int gfx_v10_0_sw_init(void *handle) 1299 { 1300 int i, j, k, r, ring_id = 0; 1301 struct amdgpu_kiq *kiq; 1302 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1303 1304 switch (adev->asic_type) { 1305 case CHIP_NAVI10: 1306 case CHIP_NAVI14: 1307 case CHIP_NAVI12: 1308 adev->gfx.me.num_me = 1; 1309 adev->gfx.me.num_pipe_per_me = 1; 1310 adev->gfx.me.num_queue_per_pipe = 1; 1311 adev->gfx.mec.num_mec = 2; 1312 adev->gfx.mec.num_pipe_per_mec = 4; 1313 adev->gfx.mec.num_queue_per_pipe = 8; 1314 break; 1315 default: 1316 adev->gfx.me.num_me = 1; 1317 adev->gfx.me.num_pipe_per_me = 1; 1318 adev->gfx.me.num_queue_per_pipe = 1; 1319 adev->gfx.mec.num_mec = 1; 1320 adev->gfx.mec.num_pipe_per_mec = 4; 1321 adev->gfx.mec.num_queue_per_pipe = 8; 1322 break; 1323 } 1324 1325 /* KIQ event */ 1326 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1327 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1328 &adev->gfx.kiq.irq); 1329 if (r) 1330 return r; 1331 1332 /* EOP Event */ 1333 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1334 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1335 &adev->gfx.eop_irq); 1336 if (r) 1337 return r; 1338 1339 /* Privileged reg */ 1340 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1341 &adev->gfx.priv_reg_irq); 1342 if (r) 1343 return r; 1344 1345 /* Privileged inst */ 1346 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1347 &adev->gfx.priv_inst_irq); 1348 if (r) 1349 return r; 1350 1351 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1352 1353 gfx_v10_0_scratch_init(adev); 1354 1355 r = gfx_v10_0_me_init(adev); 1356 if (r) 1357 return r; 1358 1359 r = gfx_v10_0_rlc_init(adev); 1360 if (r) { 1361 DRM_ERROR("Failed to init rlc BOs!\n"); 1362 return r; 1363 } 1364 1365 r = gfx_v10_0_mec_init(adev); 1366 if (r) { 1367 DRM_ERROR("Failed to init MEC BOs!\n"); 1368 return r; 1369 } 1370 1371 /* set up the gfx ring */ 1372 for (i = 0; i < adev->gfx.me.num_me; i++) { 1373 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1374 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1375 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1376 continue; 1377 1378 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1379 i, k, j); 1380 if (r) 1381 return r; 1382 ring_id++; 1383 } 1384 } 1385 } 1386 1387 ring_id = 0; 1388 /* set up the compute queues - allocate horizontally across pipes */ 1389 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1390 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1391 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1392 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1393 j)) 1394 continue; 1395 1396 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1397 i, k, j); 1398 if (r) 1399 return r; 1400 1401 ring_id++; 1402 } 1403 } 1404 } 1405 1406 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1407 if (r) { 1408 DRM_ERROR("Failed to init KIQ BOs!\n"); 1409 return r; 1410 } 1411 1412 kiq = &adev->gfx.kiq; 1413 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1414 if (r) 1415 return r; 1416 1417 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1418 if (r) 1419 return r; 1420 1421 /* allocate visible FB for rlc auto-loading fw */ 1422 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1423 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1424 if (r) 1425 return r; 1426 } 1427 1428 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1429 1430 gfx_v10_0_gpu_early_init(adev); 1431 1432 return 0; 1433 } 1434 1435 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1436 { 1437 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1438 &adev->gfx.pfp.pfp_fw_gpu_addr, 1439 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1440 } 1441 1442 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1443 { 1444 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1445 &adev->gfx.ce.ce_fw_gpu_addr, 1446 (void **)&adev->gfx.ce.ce_fw_ptr); 1447 } 1448 1449 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1450 { 1451 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1452 &adev->gfx.me.me_fw_gpu_addr, 1453 (void **)&adev->gfx.me.me_fw_ptr); 1454 } 1455 1456 static int gfx_v10_0_sw_fini(void *handle) 1457 { 1458 int i; 1459 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1460 1461 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1462 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1463 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1464 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1465 1466 amdgpu_gfx_mqd_sw_fini(adev); 1467 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 1468 amdgpu_gfx_kiq_fini(adev); 1469 1470 gfx_v10_0_pfp_fini(adev); 1471 gfx_v10_0_ce_fini(adev); 1472 gfx_v10_0_me_fini(adev); 1473 gfx_v10_0_rlc_fini(adev); 1474 gfx_v10_0_mec_fini(adev); 1475 1476 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1477 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1478 1479 gfx_v10_0_free_microcode(adev); 1480 1481 return 0; 1482 } 1483 1484 1485 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1486 { 1487 /* TODO */ 1488 } 1489 1490 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1491 u32 sh_num, u32 instance) 1492 { 1493 u32 data; 1494 1495 if (instance == 0xffffffff) 1496 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1497 INSTANCE_BROADCAST_WRITES, 1); 1498 else 1499 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1500 instance); 1501 1502 if (se_num == 0xffffffff) 1503 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1504 1); 1505 else 1506 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1507 1508 if (sh_num == 0xffffffff) 1509 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1510 1); 1511 else 1512 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1513 1514 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1515 } 1516 1517 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1518 { 1519 u32 data, mask; 1520 1521 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1522 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1523 1524 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1525 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1526 1527 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1528 adev->gfx.config.max_sh_per_se); 1529 1530 return (~data) & mask; 1531 } 1532 1533 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1534 { 1535 int i, j; 1536 u32 data; 1537 u32 active_rbs = 0; 1538 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1539 adev->gfx.config.max_sh_per_se; 1540 1541 mutex_lock(&adev->grbm_idx_mutex); 1542 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1543 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1544 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1545 data = gfx_v10_0_get_rb_active_bitmap(adev); 1546 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1547 rb_bitmap_width_per_sh); 1548 } 1549 } 1550 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1551 mutex_unlock(&adev->grbm_idx_mutex); 1552 1553 adev->gfx.config.backend_enable_mask = active_rbs; 1554 adev->gfx.config.num_rbs = hweight32(active_rbs); 1555 } 1556 1557 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1558 { 1559 uint32_t num_sc; 1560 uint32_t enabled_rb_per_sh; 1561 uint32_t active_rb_bitmap; 1562 uint32_t num_rb_per_sc; 1563 uint32_t num_packer_per_sc; 1564 uint32_t pa_sc_tile_steering_override; 1565 1566 /* init num_sc */ 1567 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1568 adev->gfx.config.num_sc_per_sh; 1569 /* init num_rb_per_sc */ 1570 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1571 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1572 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1573 /* init num_packer_per_sc */ 1574 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1575 1576 pa_sc_tile_steering_override = 0; 1577 pa_sc_tile_steering_override |= 1578 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1579 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1580 pa_sc_tile_steering_override |= 1581 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1582 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1583 pa_sc_tile_steering_override |= 1584 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1585 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1586 1587 return pa_sc_tile_steering_override; 1588 } 1589 1590 #define DEFAULT_SH_MEM_BASES (0x6000) 1591 #define FIRST_COMPUTE_VMID (8) 1592 #define LAST_COMPUTE_VMID (16) 1593 1594 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1595 { 1596 int i; 1597 uint32_t sh_mem_bases; 1598 1599 /* 1600 * Configure apertures: 1601 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1602 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1603 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1604 */ 1605 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1606 1607 mutex_lock(&adev->srbm_mutex); 1608 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1609 nv_grbm_select(adev, 0, 0, 0, i); 1610 /* CP and shaders */ 1611 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1612 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1613 } 1614 nv_grbm_select(adev, 0, 0, 0, 0); 1615 mutex_unlock(&adev->srbm_mutex); 1616 1617 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 1618 acccess. These should be enabled by FW for target VMIDs. */ 1619 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1620 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 1621 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 1622 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 1623 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 1624 } 1625 } 1626 1627 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 1628 { 1629 int vmid; 1630 1631 /* 1632 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1633 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1634 * the driver can enable them for graphics. VMID0 should maintain 1635 * access so that HWS firmware can save/restore entries. 1636 */ 1637 for (vmid = 1; vmid < 16; vmid++) { 1638 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 1639 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 1640 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 1641 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 1642 } 1643 } 1644 1645 1646 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1647 { 1648 int i, j, k; 1649 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1650 u32 tmp, wgp_active_bitmap = 0; 1651 u32 gcrd_targets_disable_tcp = 0; 1652 u32 utcl_invreq_disable = 0; 1653 /* 1654 * GCRD_TARGETS_DISABLE field contains 1655 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1656 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1657 */ 1658 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1659 2 * max_wgp_per_sh + /* TCP */ 1660 max_wgp_per_sh + /* SQC */ 1661 4); /* GL1C */ 1662 /* 1663 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1664 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1665 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1666 */ 1667 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1668 2 * max_wgp_per_sh + /* TCP */ 1669 2 * max_wgp_per_sh + /* SQC */ 1670 4 + /* RMI */ 1671 1); /* SQG */ 1672 1673 if (adev->asic_type == CHIP_NAVI10 || 1674 adev->asic_type == CHIP_NAVI14 || 1675 adev->asic_type == CHIP_NAVI12) { 1676 mutex_lock(&adev->grbm_idx_mutex); 1677 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1678 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1679 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1680 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1681 /* 1682 * Set corresponding TCP bits for the inactive WGPs in 1683 * GCRD_SA_TARGETS_DISABLE 1684 */ 1685 gcrd_targets_disable_tcp = 0; 1686 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1687 utcl_invreq_disable = 0; 1688 1689 for (k = 0; k < max_wgp_per_sh; k++) { 1690 if (!(wgp_active_bitmap & (1 << k))) { 1691 gcrd_targets_disable_tcp |= 3 << (2 * k); 1692 utcl_invreq_disable |= (3 << (2 * k)) | 1693 (3 << (2 * (max_wgp_per_sh + k))); 1694 } 1695 } 1696 1697 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1698 /* only override TCP & SQC bits */ 1699 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1700 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1701 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1702 1703 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1704 /* only override TCP bits */ 1705 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1706 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1707 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1708 } 1709 } 1710 1711 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1712 mutex_unlock(&adev->grbm_idx_mutex); 1713 } 1714 } 1715 1716 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 1717 { 1718 /* TCCs are global (not instanced). */ 1719 uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 1720 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 1721 1722 adev->gfx.config.tcc_disabled_mask = 1723 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 1724 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 1725 } 1726 1727 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1728 { 1729 u32 tmp; 1730 int i; 1731 1732 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1733 1734 gfx_v10_0_tiling_mode_table_init(adev); 1735 1736 gfx_v10_0_setup_rb(adev); 1737 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1738 gfx_v10_0_get_tcc_info(adev); 1739 adev->gfx.config.pa_sc_tile_steering_override = 1740 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1741 1742 /* XXX SH_MEM regs */ 1743 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1744 mutex_lock(&adev->srbm_mutex); 1745 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1746 nv_grbm_select(adev, 0, 0, 0, i); 1747 /* CP and shaders */ 1748 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1749 if (i != 0) { 1750 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1751 (adev->gmc.private_aperture_start >> 48)); 1752 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1753 (adev->gmc.shared_aperture_start >> 48)); 1754 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1755 } 1756 } 1757 nv_grbm_select(adev, 0, 0, 0, 0); 1758 1759 mutex_unlock(&adev->srbm_mutex); 1760 1761 gfx_v10_0_init_compute_vmid(adev); 1762 gfx_v10_0_init_gds_vmid(adev); 1763 1764 } 1765 1766 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1767 bool enable) 1768 { 1769 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1770 1771 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1772 enable ? 1 : 0); 1773 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1774 enable ? 1 : 0); 1775 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1776 enable ? 1 : 0); 1777 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1778 enable ? 1 : 0); 1779 1780 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1781 } 1782 1783 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 1784 { 1785 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1786 1787 /* csib */ 1788 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 1789 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1790 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 1791 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1792 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1793 1794 return 0; 1795 } 1796 1797 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1798 { 1799 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1800 1801 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1802 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1803 } 1804 1805 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1806 { 1807 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1808 udelay(50); 1809 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1810 udelay(50); 1811 } 1812 1813 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1814 bool enable) 1815 { 1816 uint32_t rlc_pg_cntl; 1817 1818 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1819 1820 if (!enable) { 1821 /* RLC_PG_CNTL[23] = 0 (default) 1822 * RLC will wait for handshake acks with SMU 1823 * GFXOFF will be enabled 1824 * RLC_PG_CNTL[23] = 1 1825 * RLC will not issue any message to SMU 1826 * hence no handshake between SMU & RLC 1827 * GFXOFF will be disabled 1828 */ 1829 rlc_pg_cntl |= 0x800000; 1830 } else 1831 rlc_pg_cntl &= ~0x800000; 1832 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1833 } 1834 1835 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1836 { 1837 /* TODO: enable rlc & smu handshake until smu 1838 * and gfxoff feature works as expected */ 1839 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1840 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1841 1842 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1843 udelay(50); 1844 } 1845 1846 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1847 { 1848 uint32_t tmp; 1849 1850 /* enable Save Restore Machine */ 1851 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1852 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1853 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1854 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1855 } 1856 1857 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1858 { 1859 const struct rlc_firmware_header_v2_0 *hdr; 1860 const __le32 *fw_data; 1861 unsigned i, fw_size; 1862 1863 if (!adev->gfx.rlc_fw) 1864 return -EINVAL; 1865 1866 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1867 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1868 1869 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1870 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1871 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1872 1873 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1874 RLCG_UCODE_LOADING_START_ADDRESS); 1875 1876 for (i = 0; i < fw_size; i++) 1877 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1878 le32_to_cpup(fw_data++)); 1879 1880 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1881 1882 return 0; 1883 } 1884 1885 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1886 { 1887 int r; 1888 1889 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1890 1891 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1892 if (r) 1893 return r; 1894 1895 gfx_v10_0_init_csb(adev); 1896 1897 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1898 gfx_v10_0_rlc_enable_srm(adev); 1899 } else { 1900 adev->gfx.rlc.funcs->stop(adev); 1901 1902 /* disable CG */ 1903 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1904 1905 /* disable PG */ 1906 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1907 1908 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1909 /* legacy rlc firmware loading */ 1910 r = gfx_v10_0_rlc_load_microcode(adev); 1911 if (r) 1912 return r; 1913 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1914 /* rlc backdoor autoload firmware */ 1915 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1916 if (r) 1917 return r; 1918 } 1919 1920 gfx_v10_0_init_csb(adev); 1921 1922 adev->gfx.rlc.funcs->start(adev); 1923 1924 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1925 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1926 if (r) 1927 return r; 1928 } 1929 } 1930 return 0; 1931 } 1932 1933 static struct { 1934 FIRMWARE_ID id; 1935 unsigned int offset; 1936 unsigned int size; 1937 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1938 1939 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1940 { 1941 int ret; 1942 RLC_TABLE_OF_CONTENT *rlc_toc; 1943 1944 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 1945 AMDGPU_GEM_DOMAIN_GTT, 1946 &adev->gfx.rlc.rlc_toc_bo, 1947 &adev->gfx.rlc.rlc_toc_gpu_addr, 1948 (void **)&adev->gfx.rlc.rlc_toc_buf); 1949 if (ret) { 1950 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 1951 return ret; 1952 } 1953 1954 /* Copy toc from psp sos fw to rlc toc buffer */ 1955 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 1956 1957 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 1958 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 1959 (rlc_toc->id < FIRMWARE_ID_MAX)) { 1960 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 1961 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 1962 /* Offset needs 4KB alignment */ 1963 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 1964 } 1965 1966 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 1967 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 1968 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 1969 1970 rlc_toc++; 1971 } 1972 1973 return 0; 1974 } 1975 1976 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 1977 { 1978 uint32_t total_size = 0; 1979 FIRMWARE_ID id; 1980 int ret; 1981 1982 ret = gfx_v10_0_parse_rlc_toc(adev); 1983 if (ret) { 1984 dev_err(adev->dev, "failed to parse rlc toc\n"); 1985 return 0; 1986 } 1987 1988 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 1989 total_size += rlc_autoload_info[id].size; 1990 1991 /* In case the offset in rlc toc ucode is aligned */ 1992 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 1993 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 1994 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 1995 1996 return total_size; 1997 } 1998 1999 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 2000 { 2001 int r; 2002 uint32_t total_size; 2003 2004 total_size = gfx_v10_0_calc_toc_total_size(adev); 2005 2006 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 2007 AMDGPU_GEM_DOMAIN_GTT, 2008 &adev->gfx.rlc.rlc_autoload_bo, 2009 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2010 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2011 if (r) { 2012 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 2013 return r; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 2020 { 2021 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 2022 &adev->gfx.rlc.rlc_toc_gpu_addr, 2023 (void **)&adev->gfx.rlc.rlc_toc_buf); 2024 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 2025 &adev->gfx.rlc.rlc_autoload_gpu_addr, 2026 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 2027 } 2028 2029 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 2030 FIRMWARE_ID id, 2031 const void *fw_data, 2032 uint32_t fw_size) 2033 { 2034 uint32_t toc_offset; 2035 uint32_t toc_fw_size; 2036 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 2037 2038 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 2039 return; 2040 2041 toc_offset = rlc_autoload_info[id].offset; 2042 toc_fw_size = rlc_autoload_info[id].size; 2043 2044 if (fw_size == 0) 2045 fw_size = toc_fw_size; 2046 2047 if (fw_size > toc_fw_size) 2048 fw_size = toc_fw_size; 2049 2050 memcpy(ptr + toc_offset, fw_data, fw_size); 2051 2052 if (fw_size < toc_fw_size) 2053 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 2054 } 2055 2056 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 2057 { 2058 void *data; 2059 uint32_t size; 2060 2061 data = adev->gfx.rlc.rlc_toc_buf; 2062 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 2063 2064 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2065 FIRMWARE_ID_RLC_TOC, 2066 data, size); 2067 } 2068 2069 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 2070 { 2071 const __le32 *fw_data; 2072 uint32_t fw_size; 2073 const struct gfx_firmware_header_v1_0 *cp_hdr; 2074 const struct rlc_firmware_header_v2_0 *rlc_hdr; 2075 2076 /* pfp ucode */ 2077 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2078 adev->gfx.pfp_fw->data; 2079 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2080 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2081 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2082 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2083 FIRMWARE_ID_CP_PFP, 2084 fw_data, fw_size); 2085 2086 /* ce ucode */ 2087 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2088 adev->gfx.ce_fw->data; 2089 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2090 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2091 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2092 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2093 FIRMWARE_ID_CP_CE, 2094 fw_data, fw_size); 2095 2096 /* me ucode */ 2097 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2098 adev->gfx.me_fw->data; 2099 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2100 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2101 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 2102 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2103 FIRMWARE_ID_CP_ME, 2104 fw_data, fw_size); 2105 2106 /* rlc ucode */ 2107 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 2108 adev->gfx.rlc_fw->data; 2109 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2110 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 2111 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 2112 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2113 FIRMWARE_ID_RLC_G_UCODE, 2114 fw_data, fw_size); 2115 2116 /* mec1 ucode */ 2117 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2118 adev->gfx.mec_fw->data; 2119 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2120 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2121 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 2122 cp_hdr->jt_size * 4; 2123 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2124 FIRMWARE_ID_CP_MEC, 2125 fw_data, fw_size); 2126 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 2127 } 2128 2129 /* Temporarily put sdma part here */ 2130 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 2131 { 2132 const __le32 *fw_data; 2133 uint32_t fw_size; 2134 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2135 int i; 2136 2137 for (i = 0; i < adev->sdma.num_instances; i++) { 2138 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2139 adev->sdma.instance[i].fw->data; 2140 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2141 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2142 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2143 2144 if (i == 0) { 2145 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2146 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2147 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2148 FIRMWARE_ID_SDMA0_JT, 2149 (uint32_t *)fw_data + 2150 sdma_hdr->jt_offset, 2151 sdma_hdr->jt_size * 4); 2152 } else if (i == 1) { 2153 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2154 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2155 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2156 FIRMWARE_ID_SDMA1_JT, 2157 (uint32_t *)fw_data + 2158 sdma_hdr->jt_offset, 2159 sdma_hdr->jt_size * 4); 2160 } 2161 } 2162 } 2163 2164 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2165 { 2166 uint32_t rlc_g_offset, rlc_g_size, tmp; 2167 uint64_t gpu_addr; 2168 2169 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2170 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2171 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2172 2173 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2174 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2175 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2176 2177 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2178 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2179 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2180 2181 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2182 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2183 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2184 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2185 return -EINVAL; 2186 } 2187 2188 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2189 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2190 DRM_ERROR("RLC ROM should halt itself\n"); 2191 return -EINVAL; 2192 } 2193 2194 return 0; 2195 } 2196 2197 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2198 { 2199 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2200 uint32_t tmp; 2201 int i; 2202 uint64_t addr; 2203 2204 /* Trigger an invalidation of the L1 instruction caches */ 2205 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2206 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2207 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2208 2209 /* Wait for invalidation complete */ 2210 for (i = 0; i < usec_timeout; i++) { 2211 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2212 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2213 INVALIDATE_CACHE_COMPLETE)) 2214 break; 2215 udelay(1); 2216 } 2217 2218 if (i >= usec_timeout) { 2219 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2220 return -EINVAL; 2221 } 2222 2223 /* Program me ucode address into intruction cache address register */ 2224 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2225 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2226 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2227 lower_32_bits(addr) & 0xFFFFF000); 2228 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2229 upper_32_bits(addr)); 2230 2231 return 0; 2232 } 2233 2234 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2235 { 2236 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2237 uint32_t tmp; 2238 int i; 2239 uint64_t addr; 2240 2241 /* Trigger an invalidation of the L1 instruction caches */ 2242 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2243 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2244 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2245 2246 /* Wait for invalidation complete */ 2247 for (i = 0; i < usec_timeout; i++) { 2248 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2249 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2250 INVALIDATE_CACHE_COMPLETE)) 2251 break; 2252 udelay(1); 2253 } 2254 2255 if (i >= usec_timeout) { 2256 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2257 return -EINVAL; 2258 } 2259 2260 /* Program ce ucode address into intruction cache address register */ 2261 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2262 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2263 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2264 lower_32_bits(addr) & 0xFFFFF000); 2265 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2266 upper_32_bits(addr)); 2267 2268 return 0; 2269 } 2270 2271 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2272 { 2273 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2274 uint32_t tmp; 2275 int i; 2276 uint64_t addr; 2277 2278 /* Trigger an invalidation of the L1 instruction caches */ 2279 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2280 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2281 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2282 2283 /* Wait for invalidation complete */ 2284 for (i = 0; i < usec_timeout; i++) { 2285 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2286 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2287 INVALIDATE_CACHE_COMPLETE)) 2288 break; 2289 udelay(1); 2290 } 2291 2292 if (i >= usec_timeout) { 2293 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2294 return -EINVAL; 2295 } 2296 2297 /* Program pfp ucode address into intruction cache address register */ 2298 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2299 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2300 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2301 lower_32_bits(addr) & 0xFFFFF000); 2302 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2303 upper_32_bits(addr)); 2304 2305 return 0; 2306 } 2307 2308 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2309 { 2310 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2311 uint32_t tmp; 2312 int i; 2313 uint64_t addr; 2314 2315 /* Trigger an invalidation of the L1 instruction caches */ 2316 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2317 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2318 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2319 2320 /* Wait for invalidation complete */ 2321 for (i = 0; i < usec_timeout; i++) { 2322 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2323 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2324 INVALIDATE_CACHE_COMPLETE)) 2325 break; 2326 udelay(1); 2327 } 2328 2329 if (i >= usec_timeout) { 2330 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2331 return -EINVAL; 2332 } 2333 2334 /* Program mec1 ucode address into intruction cache address register */ 2335 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2336 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2337 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2338 lower_32_bits(addr) & 0xFFFFF000); 2339 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2340 upper_32_bits(addr)); 2341 2342 return 0; 2343 } 2344 2345 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2346 { 2347 uint32_t cp_status; 2348 uint32_t bootload_status; 2349 int i, r; 2350 2351 for (i = 0; i < adev->usec_timeout; i++) { 2352 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2353 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2354 if ((cp_status == 0) && 2355 (REG_GET_FIELD(bootload_status, 2356 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2357 break; 2358 } 2359 udelay(1); 2360 } 2361 2362 if (i >= adev->usec_timeout) { 2363 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2364 return -ETIMEDOUT; 2365 } 2366 2367 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2368 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2369 if (r) 2370 return r; 2371 2372 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2373 if (r) 2374 return r; 2375 2376 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2377 if (r) 2378 return r; 2379 2380 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2381 if (r) 2382 return r; 2383 } 2384 2385 return 0; 2386 } 2387 2388 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2389 { 2390 int i; 2391 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2392 2393 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2394 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2395 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2396 if (!enable) { 2397 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2398 adev->gfx.gfx_ring[i].sched.ready = false; 2399 } 2400 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 2401 2402 for (i = 0; i < adev->usec_timeout; i++) { 2403 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 2404 break; 2405 udelay(1); 2406 } 2407 2408 if (i >= adev->usec_timeout) 2409 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 2410 2411 return 0; 2412 } 2413 2414 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2415 { 2416 int r; 2417 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2418 const __le32 *fw_data; 2419 unsigned i, fw_size; 2420 uint32_t tmp; 2421 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2422 2423 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2424 adev->gfx.pfp_fw->data; 2425 2426 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2427 2428 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2429 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2430 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2431 2432 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2433 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2434 &adev->gfx.pfp.pfp_fw_obj, 2435 &adev->gfx.pfp.pfp_fw_gpu_addr, 2436 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2437 if (r) { 2438 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2439 gfx_v10_0_pfp_fini(adev); 2440 return r; 2441 } 2442 2443 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2444 2445 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2446 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2447 2448 /* Trigger an invalidation of the L1 instruction caches */ 2449 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2450 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2451 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2452 2453 /* Wait for invalidation complete */ 2454 for (i = 0; i < usec_timeout; i++) { 2455 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2456 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2457 INVALIDATE_CACHE_COMPLETE)) 2458 break; 2459 udelay(1); 2460 } 2461 2462 if (i >= usec_timeout) { 2463 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2464 return -EINVAL; 2465 } 2466 2467 if (amdgpu_emu_mode == 1) 2468 adev->nbio.funcs->hdp_flush(adev, NULL); 2469 2470 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2471 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2472 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2473 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2474 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2475 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2476 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2477 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2478 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2479 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2480 2481 return 0; 2482 } 2483 2484 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2485 { 2486 int r; 2487 const struct gfx_firmware_header_v1_0 *ce_hdr; 2488 const __le32 *fw_data; 2489 unsigned i, fw_size; 2490 uint32_t tmp; 2491 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2492 2493 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2494 adev->gfx.ce_fw->data; 2495 2496 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2497 2498 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2499 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2500 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2501 2502 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2503 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2504 &adev->gfx.ce.ce_fw_obj, 2505 &adev->gfx.ce.ce_fw_gpu_addr, 2506 (void **)&adev->gfx.ce.ce_fw_ptr); 2507 if (r) { 2508 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2509 gfx_v10_0_ce_fini(adev); 2510 return r; 2511 } 2512 2513 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2514 2515 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2516 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2517 2518 /* Trigger an invalidation of the L1 instruction caches */ 2519 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2520 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2521 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2522 2523 /* Wait for invalidation complete */ 2524 for (i = 0; i < usec_timeout; i++) { 2525 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2526 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2527 INVALIDATE_CACHE_COMPLETE)) 2528 break; 2529 udelay(1); 2530 } 2531 2532 if (i >= usec_timeout) { 2533 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2534 return -EINVAL; 2535 } 2536 2537 if (amdgpu_emu_mode == 1) 2538 adev->nbio.funcs->hdp_flush(adev, NULL); 2539 2540 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2541 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2542 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2543 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2544 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2545 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2546 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2547 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2548 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2549 2550 return 0; 2551 } 2552 2553 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2554 { 2555 int r; 2556 const struct gfx_firmware_header_v1_0 *me_hdr; 2557 const __le32 *fw_data; 2558 unsigned i, fw_size; 2559 uint32_t tmp; 2560 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2561 2562 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2563 adev->gfx.me_fw->data; 2564 2565 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2566 2567 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2568 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2569 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2570 2571 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2572 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2573 &adev->gfx.me.me_fw_obj, 2574 &adev->gfx.me.me_fw_gpu_addr, 2575 (void **)&adev->gfx.me.me_fw_ptr); 2576 if (r) { 2577 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2578 gfx_v10_0_me_fini(adev); 2579 return r; 2580 } 2581 2582 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2583 2584 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2585 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2586 2587 /* Trigger an invalidation of the L1 instruction caches */ 2588 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2589 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2590 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2591 2592 /* Wait for invalidation complete */ 2593 for (i = 0; i < usec_timeout; i++) { 2594 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2595 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2596 INVALIDATE_CACHE_COMPLETE)) 2597 break; 2598 udelay(1); 2599 } 2600 2601 if (i >= usec_timeout) { 2602 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2603 return -EINVAL; 2604 } 2605 2606 if (amdgpu_emu_mode == 1) 2607 adev->nbio.funcs->hdp_flush(adev, NULL); 2608 2609 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2610 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2611 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2612 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2613 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2614 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2615 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2616 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2617 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2618 2619 return 0; 2620 } 2621 2622 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2623 { 2624 int r; 2625 2626 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2627 return -EINVAL; 2628 2629 gfx_v10_0_cp_gfx_enable(adev, false); 2630 2631 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2632 if (r) { 2633 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2634 return r; 2635 } 2636 2637 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2638 if (r) { 2639 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2640 return r; 2641 } 2642 2643 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2644 if (r) { 2645 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2646 return r; 2647 } 2648 2649 return 0; 2650 } 2651 2652 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2653 { 2654 struct amdgpu_ring *ring; 2655 const struct cs_section_def *sect = NULL; 2656 const struct cs_extent_def *ext = NULL; 2657 int r, i; 2658 int ctx_reg_offset; 2659 2660 /* init the CP */ 2661 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2662 adev->gfx.config.max_hw_contexts - 1); 2663 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2664 2665 gfx_v10_0_cp_gfx_enable(adev, true); 2666 2667 ring = &adev->gfx.gfx_ring[0]; 2668 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2669 if (r) { 2670 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2671 return r; 2672 } 2673 2674 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2675 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2676 2677 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2678 amdgpu_ring_write(ring, 0x80000000); 2679 amdgpu_ring_write(ring, 0x80000000); 2680 2681 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2682 for (ext = sect->section; ext->extent != NULL; ++ext) { 2683 if (sect->id == SECT_CONTEXT) { 2684 amdgpu_ring_write(ring, 2685 PACKET3(PACKET3_SET_CONTEXT_REG, 2686 ext->reg_count)); 2687 amdgpu_ring_write(ring, ext->reg_index - 2688 PACKET3_SET_CONTEXT_REG_START); 2689 for (i = 0; i < ext->reg_count; i++) 2690 amdgpu_ring_write(ring, ext->extent[i]); 2691 } 2692 } 2693 } 2694 2695 ctx_reg_offset = 2696 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2697 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2698 amdgpu_ring_write(ring, ctx_reg_offset); 2699 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2700 2701 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2702 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2703 2704 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2705 amdgpu_ring_write(ring, 0); 2706 2707 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2708 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2709 amdgpu_ring_write(ring, 0x8000); 2710 amdgpu_ring_write(ring, 0x8000); 2711 2712 amdgpu_ring_commit(ring); 2713 2714 /* submit cs packet to copy state 0 to next available state */ 2715 if (adev->gfx.num_gfx_rings > 1) { 2716 /* maximum supported gfx ring is 2 */ 2717 ring = &adev->gfx.gfx_ring[1]; 2718 r = amdgpu_ring_alloc(ring, 2); 2719 if (r) { 2720 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2721 return r; 2722 } 2723 2724 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2725 amdgpu_ring_write(ring, 0); 2726 2727 amdgpu_ring_commit(ring); 2728 } 2729 return 0; 2730 } 2731 2732 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2733 CP_PIPE_ID pipe) 2734 { 2735 u32 tmp; 2736 2737 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2738 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2739 2740 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2741 } 2742 2743 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2744 struct amdgpu_ring *ring) 2745 { 2746 u32 tmp; 2747 2748 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2749 if (ring->use_doorbell) { 2750 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2751 DOORBELL_OFFSET, ring->doorbell_index); 2752 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2753 DOORBELL_EN, 1); 2754 } else { 2755 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2756 DOORBELL_EN, 0); 2757 } 2758 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2759 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2760 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2761 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2762 2763 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2764 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2765 } 2766 2767 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2768 { 2769 struct amdgpu_ring *ring; 2770 u32 tmp; 2771 u32 rb_bufsz; 2772 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2773 u32 i; 2774 2775 /* Set the write pointer delay */ 2776 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2777 2778 /* set the RB to use vmid 0 */ 2779 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2780 2781 /* Init gfx ring 0 for pipe 0 */ 2782 mutex_lock(&adev->srbm_mutex); 2783 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2784 2785 /* Set ring buffer size */ 2786 ring = &adev->gfx.gfx_ring[0]; 2787 rb_bufsz = order_base_2(ring->ring_size / 8); 2788 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2789 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2790 #ifdef __BIG_ENDIAN 2791 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2792 #endif 2793 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2794 2795 /* Initialize the ring buffer's write pointers */ 2796 ring->wptr = 0; 2797 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2798 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2799 2800 /* set the wb address wether it's enabled or not */ 2801 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2802 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2803 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2804 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2805 2806 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2807 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2808 lower_32_bits(wptr_gpu_addr)); 2809 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2810 upper_32_bits(wptr_gpu_addr)); 2811 2812 mdelay(1); 2813 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2814 2815 rb_addr = ring->gpu_addr >> 8; 2816 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2817 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2818 2819 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2820 2821 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2822 mutex_unlock(&adev->srbm_mutex); 2823 2824 /* Init gfx ring 1 for pipe 1 */ 2825 if (adev->gfx.num_gfx_rings > 1) { 2826 mutex_lock(&adev->srbm_mutex); 2827 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2828 /* maximum supported gfx ring is 2 */ 2829 ring = &adev->gfx.gfx_ring[1]; 2830 rb_bufsz = order_base_2(ring->ring_size / 8); 2831 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2832 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2833 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2834 /* Initialize the ring buffer's write pointers */ 2835 ring->wptr = 0; 2836 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2837 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2838 /* Set the wb address wether it's enabled or not */ 2839 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2840 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2841 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2842 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2843 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2844 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2845 lower_32_bits(wptr_gpu_addr)); 2846 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2847 upper_32_bits(wptr_gpu_addr)); 2848 2849 mdelay(1); 2850 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2851 2852 rb_addr = ring->gpu_addr >> 8; 2853 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2854 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2855 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2856 2857 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2858 mutex_unlock(&adev->srbm_mutex); 2859 } 2860 /* Switch to pipe 0 */ 2861 mutex_lock(&adev->srbm_mutex); 2862 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2863 mutex_unlock(&adev->srbm_mutex); 2864 2865 /* start the ring */ 2866 gfx_v10_0_cp_gfx_start(adev); 2867 2868 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2869 ring = &adev->gfx.gfx_ring[i]; 2870 ring->sched.ready = true; 2871 } 2872 2873 return 0; 2874 } 2875 2876 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2877 { 2878 int i; 2879 2880 if (enable) { 2881 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2882 } else { 2883 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2884 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2885 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2886 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2887 adev->gfx.compute_ring[i].sched.ready = false; 2888 adev->gfx.kiq.ring.sched.ready = false; 2889 } 2890 udelay(50); 2891 } 2892 2893 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2894 { 2895 const struct gfx_firmware_header_v1_0 *mec_hdr; 2896 const __le32 *fw_data; 2897 unsigned i; 2898 u32 tmp; 2899 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2900 2901 if (!adev->gfx.mec_fw) 2902 return -EINVAL; 2903 2904 gfx_v10_0_cp_compute_enable(adev, false); 2905 2906 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2907 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2908 2909 fw_data = (const __le32 *) 2910 (adev->gfx.mec_fw->data + 2911 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2912 2913 /* Trigger an invalidation of the L1 instruction caches */ 2914 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2915 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2916 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2917 2918 /* Wait for invalidation complete */ 2919 for (i = 0; i < usec_timeout; i++) { 2920 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2921 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2922 INVALIDATE_CACHE_COMPLETE)) 2923 break; 2924 udelay(1); 2925 } 2926 2927 if (i >= usec_timeout) { 2928 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2929 return -EINVAL; 2930 } 2931 2932 if (amdgpu_emu_mode == 1) 2933 adev->nbio.funcs->hdp_flush(adev, NULL); 2934 2935 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2936 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2937 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2938 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2939 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2940 2941 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 2942 0xFFFFF000); 2943 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2944 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2945 2946 /* MEC1 */ 2947 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 2948 2949 for (i = 0; i < mec_hdr->jt_size; i++) 2950 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2951 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2952 2953 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2954 2955 /* 2956 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 2957 * different microcode than MEC1. 2958 */ 2959 2960 return 0; 2961 } 2962 2963 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 2964 { 2965 uint32_t tmp; 2966 struct amdgpu_device *adev = ring->adev; 2967 2968 /* tell RLC which is KIQ queue */ 2969 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2970 tmp &= 0xffffff00; 2971 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2972 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2973 tmp |= 0x80; 2974 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2975 } 2976 2977 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 2978 { 2979 struct amdgpu_device *adev = ring->adev; 2980 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2981 uint64_t hqd_gpu_addr, wb_gpu_addr; 2982 uint32_t tmp; 2983 uint32_t rb_bufsz; 2984 2985 /* set up gfx hqd wptr */ 2986 mqd->cp_gfx_hqd_wptr = 0; 2987 mqd->cp_gfx_hqd_wptr_hi = 0; 2988 2989 /* set the pointer to the MQD */ 2990 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 2991 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2992 2993 /* set up mqd control */ 2994 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 2995 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2996 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2997 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2998 mqd->cp_gfx_mqd_control = tmp; 2999 3000 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 3001 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 3002 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 3003 mqd->cp_gfx_hqd_vmid = 0; 3004 3005 /* set up default queue priority level 3006 * 0x0 = low priority, 0x1 = high priority */ 3007 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 3008 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 3009 mqd->cp_gfx_hqd_queue_priority = tmp; 3010 3011 /* set up time quantum */ 3012 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 3013 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 3014 mqd->cp_gfx_hqd_quantum = tmp; 3015 3016 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 3017 hqd_gpu_addr = ring->gpu_addr >> 8; 3018 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 3019 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 3020 3021 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 3022 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3023 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 3024 mqd->cp_gfx_hqd_rptr_addr_hi = 3025 upper_32_bits(wb_gpu_addr) & 0xffff; 3026 3027 /* set up rb_wptr_poll addr */ 3028 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3029 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3030 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3031 3032 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 3033 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 3034 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 3035 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 3036 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 3037 #ifdef __BIG_ENDIAN 3038 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 3039 #endif 3040 mqd->cp_gfx_hqd_cntl = tmp; 3041 3042 /* set up cp_doorbell_control */ 3043 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 3044 if (ring->use_doorbell) { 3045 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3046 DOORBELL_OFFSET, ring->doorbell_index); 3047 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3048 DOORBELL_EN, 1); 3049 } else 3050 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 3051 DOORBELL_EN, 0); 3052 mqd->cp_rb_doorbell_control = tmp; 3053 3054 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3055 ring->wptr = 0; 3056 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 3057 3058 /* active the queue */ 3059 mqd->cp_gfx_hqd_active = 1; 3060 3061 return 0; 3062 } 3063 3064 #ifdef BRING_UP_DEBUG 3065 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 3066 { 3067 struct amdgpu_device *adev = ring->adev; 3068 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3069 3070 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 3071 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 3072 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 3073 3074 /* set GFX_MQD_BASE */ 3075 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 3076 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 3077 3078 /* set GFX_MQD_CONTROL */ 3079 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 3080 3081 /* set GFX_HQD_VMID to 0 */ 3082 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 3083 3084 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 3085 mqd->cp_gfx_hqd_queue_priority); 3086 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 3087 3088 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 3089 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 3090 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 3091 3092 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 3093 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 3094 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 3095 3096 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 3097 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 3098 3099 /* set RB_WPTR_POLL_ADDR */ 3100 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 3101 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 3102 3103 /* set RB_DOORBELL_CONTROL */ 3104 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 3105 3106 /* active the queue */ 3107 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 3108 3109 return 0; 3110 } 3111 #endif 3112 3113 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 3114 { 3115 struct amdgpu_device *adev = ring->adev; 3116 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 3117 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 3118 3119 if (!adev->in_gpu_reset && !adev->in_suspend) { 3120 memset((void *)mqd, 0, sizeof(*mqd)); 3121 mutex_lock(&adev->srbm_mutex); 3122 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3123 gfx_v10_0_gfx_mqd_init(ring); 3124 #ifdef BRING_UP_DEBUG 3125 gfx_v10_0_gfx_queue_init_register(ring); 3126 #endif 3127 nv_grbm_select(adev, 0, 0, 0, 0); 3128 mutex_unlock(&adev->srbm_mutex); 3129 if (adev->gfx.me.mqd_backup[mqd_idx]) 3130 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3131 } else if (adev->in_gpu_reset) { 3132 /* reset mqd with the backup copy */ 3133 if (adev->gfx.me.mqd_backup[mqd_idx]) 3134 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 3135 /* reset the ring */ 3136 ring->wptr = 0; 3137 adev->wb.wb[ring->wptr_offs] = 0; 3138 amdgpu_ring_clear_ring(ring); 3139 #ifdef BRING_UP_DEBUG 3140 mutex_lock(&adev->srbm_mutex); 3141 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3142 gfx_v10_0_gfx_queue_init_register(ring); 3143 nv_grbm_select(adev, 0, 0, 0, 0); 3144 mutex_unlock(&adev->srbm_mutex); 3145 #endif 3146 } else { 3147 amdgpu_ring_clear_ring(ring); 3148 } 3149 3150 return 0; 3151 } 3152 3153 #ifndef BRING_UP_DEBUG 3154 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3155 { 3156 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3157 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3158 int r, i; 3159 3160 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3161 return -EINVAL; 3162 3163 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3164 adev->gfx.num_gfx_rings); 3165 if (r) { 3166 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3167 return r; 3168 } 3169 3170 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3171 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3172 3173 return amdgpu_ring_test_helper(kiq_ring); 3174 } 3175 #endif 3176 3177 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3178 { 3179 int r, i; 3180 struct amdgpu_ring *ring; 3181 3182 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3183 ring = &adev->gfx.gfx_ring[i]; 3184 3185 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3186 if (unlikely(r != 0)) 3187 goto done; 3188 3189 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3190 if (!r) { 3191 r = gfx_v10_0_gfx_init_queue(ring); 3192 amdgpu_bo_kunmap(ring->mqd_obj); 3193 ring->mqd_ptr = NULL; 3194 } 3195 amdgpu_bo_unreserve(ring->mqd_obj); 3196 if (r) 3197 goto done; 3198 } 3199 #ifndef BRING_UP_DEBUG 3200 r = gfx_v10_0_kiq_enable_kgq(adev); 3201 if (r) 3202 goto done; 3203 #endif 3204 r = gfx_v10_0_cp_gfx_start(adev); 3205 if (r) 3206 goto done; 3207 3208 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3209 ring = &adev->gfx.gfx_ring[i]; 3210 ring->sched.ready = true; 3211 } 3212 done: 3213 return r; 3214 } 3215 3216 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3217 { 3218 struct amdgpu_device *adev = ring->adev; 3219 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3220 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3221 uint32_t tmp; 3222 3223 mqd->header = 0xC0310800; 3224 mqd->compute_pipelinestat_enable = 0x00000001; 3225 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3226 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3227 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3228 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3229 mqd->compute_misc_reserved = 0x00000003; 3230 3231 eop_base_addr = ring->eop_gpu_addr >> 8; 3232 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3233 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3234 3235 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3236 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3237 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3238 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3239 3240 mqd->cp_hqd_eop_control = tmp; 3241 3242 /* enable doorbell? */ 3243 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3244 3245 if (ring->use_doorbell) { 3246 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3247 DOORBELL_OFFSET, ring->doorbell_index); 3248 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3249 DOORBELL_EN, 1); 3250 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3251 DOORBELL_SOURCE, 0); 3252 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3253 DOORBELL_HIT, 0); 3254 } else { 3255 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3256 DOORBELL_EN, 0); 3257 } 3258 3259 mqd->cp_hqd_pq_doorbell_control = tmp; 3260 3261 /* disable the queue if it's active */ 3262 ring->wptr = 0; 3263 mqd->cp_hqd_dequeue_request = 0; 3264 mqd->cp_hqd_pq_rptr = 0; 3265 mqd->cp_hqd_pq_wptr_lo = 0; 3266 mqd->cp_hqd_pq_wptr_hi = 0; 3267 3268 /* set the pointer to the MQD */ 3269 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3270 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3271 3272 /* set MQD vmid to 0 */ 3273 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3274 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3275 mqd->cp_mqd_control = tmp; 3276 3277 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3278 hqd_gpu_addr = ring->gpu_addr >> 8; 3279 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3280 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3281 3282 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3283 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3284 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3285 (order_base_2(ring->ring_size / 4) - 1)); 3286 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3287 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3288 #ifdef __BIG_ENDIAN 3289 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3290 #endif 3291 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3292 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3293 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3294 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3295 mqd->cp_hqd_pq_control = tmp; 3296 3297 /* set the wb address whether it's enabled or not */ 3298 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3299 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3300 mqd->cp_hqd_pq_rptr_report_addr_hi = 3301 upper_32_bits(wb_gpu_addr) & 0xffff; 3302 3303 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3304 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3305 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3306 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3307 3308 tmp = 0; 3309 /* enable the doorbell if requested */ 3310 if (ring->use_doorbell) { 3311 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3312 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3313 DOORBELL_OFFSET, ring->doorbell_index); 3314 3315 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3316 DOORBELL_EN, 1); 3317 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3318 DOORBELL_SOURCE, 0); 3319 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3320 DOORBELL_HIT, 0); 3321 } 3322 3323 mqd->cp_hqd_pq_doorbell_control = tmp; 3324 3325 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3326 ring->wptr = 0; 3327 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3328 3329 /* set the vmid for the queue */ 3330 mqd->cp_hqd_vmid = 0; 3331 3332 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3333 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3334 mqd->cp_hqd_persistent_state = tmp; 3335 3336 /* set MIN_IB_AVAIL_SIZE */ 3337 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3338 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3339 mqd->cp_hqd_ib_control = tmp; 3340 3341 /* map_queues packet doesn't need activate the queue, 3342 * so only kiq need set this field. 3343 */ 3344 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) 3345 mqd->cp_hqd_active = 1; 3346 3347 return 0; 3348 } 3349 3350 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3351 { 3352 struct amdgpu_device *adev = ring->adev; 3353 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3354 int j; 3355 3356 /* disable wptr polling */ 3357 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3358 3359 /* write the EOP addr */ 3360 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3361 mqd->cp_hqd_eop_base_addr_lo); 3362 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3363 mqd->cp_hqd_eop_base_addr_hi); 3364 3365 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3366 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3367 mqd->cp_hqd_eop_control); 3368 3369 /* enable doorbell? */ 3370 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3371 mqd->cp_hqd_pq_doorbell_control); 3372 3373 /* disable the queue if it's active */ 3374 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3375 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3376 for (j = 0; j < adev->usec_timeout; j++) { 3377 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3378 break; 3379 udelay(1); 3380 } 3381 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3382 mqd->cp_hqd_dequeue_request); 3383 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3384 mqd->cp_hqd_pq_rptr); 3385 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3386 mqd->cp_hqd_pq_wptr_lo); 3387 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3388 mqd->cp_hqd_pq_wptr_hi); 3389 } 3390 3391 /* set the pointer to the MQD */ 3392 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3393 mqd->cp_mqd_base_addr_lo); 3394 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3395 mqd->cp_mqd_base_addr_hi); 3396 3397 /* set MQD vmid to 0 */ 3398 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3399 mqd->cp_mqd_control); 3400 3401 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3402 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3403 mqd->cp_hqd_pq_base_lo); 3404 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3405 mqd->cp_hqd_pq_base_hi); 3406 3407 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3408 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3409 mqd->cp_hqd_pq_control); 3410 3411 /* set the wb address whether it's enabled or not */ 3412 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3413 mqd->cp_hqd_pq_rptr_report_addr_lo); 3414 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3415 mqd->cp_hqd_pq_rptr_report_addr_hi); 3416 3417 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3418 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3419 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3420 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3421 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3422 3423 /* enable the doorbell if requested */ 3424 if (ring->use_doorbell) { 3425 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3426 (adev->doorbell_index.kiq * 2) << 2); 3427 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3428 (adev->doorbell_index.userqueue_end * 2) << 2); 3429 } 3430 3431 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3432 mqd->cp_hqd_pq_doorbell_control); 3433 3434 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3435 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3436 mqd->cp_hqd_pq_wptr_lo); 3437 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3438 mqd->cp_hqd_pq_wptr_hi); 3439 3440 /* set the vmid for the queue */ 3441 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3442 3443 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3444 mqd->cp_hqd_persistent_state); 3445 3446 /* activate the queue */ 3447 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3448 mqd->cp_hqd_active); 3449 3450 if (ring->use_doorbell) 3451 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3452 3453 return 0; 3454 } 3455 3456 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3457 { 3458 struct amdgpu_device *adev = ring->adev; 3459 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3460 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3461 3462 gfx_v10_0_kiq_setting(ring); 3463 3464 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3465 /* reset MQD to a clean status */ 3466 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3467 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3468 3469 /* reset ring buffer */ 3470 ring->wptr = 0; 3471 amdgpu_ring_clear_ring(ring); 3472 3473 mutex_lock(&adev->srbm_mutex); 3474 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3475 gfx_v10_0_kiq_init_register(ring); 3476 nv_grbm_select(adev, 0, 0, 0, 0); 3477 mutex_unlock(&adev->srbm_mutex); 3478 } else { 3479 memset((void *)mqd, 0, sizeof(*mqd)); 3480 mutex_lock(&adev->srbm_mutex); 3481 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3482 gfx_v10_0_compute_mqd_init(ring); 3483 gfx_v10_0_kiq_init_register(ring); 3484 nv_grbm_select(adev, 0, 0, 0, 0); 3485 mutex_unlock(&adev->srbm_mutex); 3486 3487 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3488 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3489 } 3490 3491 return 0; 3492 } 3493 3494 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3495 { 3496 struct amdgpu_device *adev = ring->adev; 3497 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3498 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3499 3500 if (!adev->in_gpu_reset && !adev->in_suspend) { 3501 memset((void *)mqd, 0, sizeof(*mqd)); 3502 mutex_lock(&adev->srbm_mutex); 3503 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3504 gfx_v10_0_compute_mqd_init(ring); 3505 nv_grbm_select(adev, 0, 0, 0, 0); 3506 mutex_unlock(&adev->srbm_mutex); 3507 3508 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3509 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3510 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3511 /* reset MQD to a clean status */ 3512 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3513 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3514 3515 /* reset ring buffer */ 3516 ring->wptr = 0; 3517 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0); 3518 amdgpu_ring_clear_ring(ring); 3519 } else { 3520 amdgpu_ring_clear_ring(ring); 3521 } 3522 3523 return 0; 3524 } 3525 3526 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3527 { 3528 struct amdgpu_ring *ring; 3529 int r; 3530 3531 ring = &adev->gfx.kiq.ring; 3532 3533 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3534 if (unlikely(r != 0)) 3535 return r; 3536 3537 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3538 if (unlikely(r != 0)) 3539 return r; 3540 3541 gfx_v10_0_kiq_init_queue(ring); 3542 amdgpu_bo_kunmap(ring->mqd_obj); 3543 ring->mqd_ptr = NULL; 3544 amdgpu_bo_unreserve(ring->mqd_obj); 3545 ring->sched.ready = true; 3546 return 0; 3547 } 3548 3549 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3550 { 3551 struct amdgpu_ring *ring = NULL; 3552 int r = 0, i; 3553 3554 gfx_v10_0_cp_compute_enable(adev, true); 3555 3556 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3557 ring = &adev->gfx.compute_ring[i]; 3558 3559 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3560 if (unlikely(r != 0)) 3561 goto done; 3562 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3563 if (!r) { 3564 r = gfx_v10_0_kcq_init_queue(ring); 3565 amdgpu_bo_kunmap(ring->mqd_obj); 3566 ring->mqd_ptr = NULL; 3567 } 3568 amdgpu_bo_unreserve(ring->mqd_obj); 3569 if (r) 3570 goto done; 3571 } 3572 3573 r = amdgpu_gfx_enable_kcq(adev); 3574 done: 3575 return r; 3576 } 3577 3578 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3579 { 3580 int r, i; 3581 struct amdgpu_ring *ring; 3582 3583 if (!(adev->flags & AMD_IS_APU)) 3584 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3585 3586 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3587 /* legacy firmware loading */ 3588 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3589 if (r) 3590 return r; 3591 3592 r = gfx_v10_0_cp_compute_load_microcode(adev); 3593 if (r) 3594 return r; 3595 } 3596 3597 r = gfx_v10_0_kiq_resume(adev); 3598 if (r) 3599 return r; 3600 3601 r = gfx_v10_0_kcq_resume(adev); 3602 if (r) 3603 return r; 3604 3605 if (!amdgpu_async_gfx_ring) { 3606 r = gfx_v10_0_cp_gfx_resume(adev); 3607 if (r) 3608 return r; 3609 } else { 3610 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3611 if (r) 3612 return r; 3613 } 3614 3615 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3616 ring = &adev->gfx.gfx_ring[i]; 3617 r = amdgpu_ring_test_helper(ring); 3618 if (r) 3619 return r; 3620 } 3621 3622 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3623 ring = &adev->gfx.compute_ring[i]; 3624 r = amdgpu_ring_test_helper(ring); 3625 if (r) 3626 return r; 3627 } 3628 3629 return 0; 3630 } 3631 3632 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3633 { 3634 gfx_v10_0_cp_gfx_enable(adev, enable); 3635 gfx_v10_0_cp_compute_enable(adev, enable); 3636 } 3637 3638 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3639 { 3640 uint32_t data, pattern = 0xDEADBEEF; 3641 3642 /* check if mmVGT_ESGS_RING_SIZE_UMD 3643 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3644 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3645 3646 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3647 3648 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3649 3650 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3651 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3652 return true; 3653 } else { 3654 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3655 return false; 3656 } 3657 } 3658 3659 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3660 { 3661 uint32_t data; 3662 3663 /* initialize cam_index to 0 3664 * index will auto-inc after each data writting */ 3665 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3666 3667 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3668 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3669 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3670 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3671 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3672 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3673 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3674 3675 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3676 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3677 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3678 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3679 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3680 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3681 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3682 3683 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3684 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3685 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3686 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3687 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3688 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3689 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3690 3691 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3692 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3693 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3694 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3695 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3696 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3697 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3698 3699 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3700 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3701 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3702 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3703 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3704 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3705 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3706 3707 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3708 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3709 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3710 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3711 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3712 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3713 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3714 3715 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3716 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3717 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3718 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3719 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3720 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3721 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3722 } 3723 3724 static int gfx_v10_0_hw_init(void *handle) 3725 { 3726 int r; 3727 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3728 3729 if (!amdgpu_emu_mode) 3730 gfx_v10_0_init_golden_registers(adev); 3731 3732 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3733 /** 3734 * For gfx 10, rlc firmware loading relies on smu firmware is 3735 * loaded firstly, so in direct type, it has to load smc ucode 3736 * here before rlc. 3737 */ 3738 r = smu_load_microcode(&adev->smu); 3739 if (r) 3740 return r; 3741 3742 r = smu_check_fw_status(&adev->smu); 3743 if (r) { 3744 pr_err("SMC firmware status is not correct\n"); 3745 return r; 3746 } 3747 } 3748 3749 /* if GRBM CAM not remapped, set up the remapping */ 3750 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3751 gfx_v10_0_setup_grbm_cam_remapping(adev); 3752 3753 gfx_v10_0_constants_init(adev); 3754 3755 r = gfx_v10_0_rlc_resume(adev); 3756 if (r) 3757 return r; 3758 3759 /* 3760 * init golden registers and rlc resume may override some registers, 3761 * reconfig them here 3762 */ 3763 gfx_v10_0_tcp_harvest(adev); 3764 3765 r = gfx_v10_0_cp_resume(adev); 3766 if (r) 3767 return r; 3768 3769 return r; 3770 } 3771 3772 #ifndef BRING_UP_DEBUG 3773 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3774 { 3775 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3776 struct amdgpu_ring *kiq_ring = &kiq->ring; 3777 int i; 3778 3779 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3780 return -EINVAL; 3781 3782 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3783 adev->gfx.num_gfx_rings)) 3784 return -ENOMEM; 3785 3786 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3787 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3788 PREEMPT_QUEUES, 0, 0); 3789 3790 return amdgpu_ring_test_helper(kiq_ring); 3791 } 3792 #endif 3793 3794 static int gfx_v10_0_hw_fini(void *handle) 3795 { 3796 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3797 int r; 3798 3799 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3800 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3801 #ifndef BRING_UP_DEBUG 3802 if (amdgpu_async_gfx_ring) { 3803 r = gfx_v10_0_kiq_disable_kgq(adev); 3804 if (r) 3805 DRM_ERROR("KGQ disable failed\n"); 3806 } 3807 #endif 3808 if (amdgpu_gfx_disable_kcq(adev)) 3809 DRM_ERROR("KCQ disable failed\n"); 3810 if (amdgpu_sriov_vf(adev)) { 3811 gfx_v10_0_cp_gfx_enable(adev, false); 3812 return 0; 3813 } 3814 gfx_v10_0_cp_enable(adev, false); 3815 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3816 3817 return 0; 3818 } 3819 3820 static int gfx_v10_0_suspend(void *handle) 3821 { 3822 return gfx_v10_0_hw_fini(handle); 3823 } 3824 3825 static int gfx_v10_0_resume(void *handle) 3826 { 3827 return gfx_v10_0_hw_init(handle); 3828 } 3829 3830 static bool gfx_v10_0_is_idle(void *handle) 3831 { 3832 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3833 3834 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3835 GRBM_STATUS, GUI_ACTIVE)) 3836 return false; 3837 else 3838 return true; 3839 } 3840 3841 static int gfx_v10_0_wait_for_idle(void *handle) 3842 { 3843 unsigned i; 3844 u32 tmp; 3845 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3846 3847 for (i = 0; i < adev->usec_timeout; i++) { 3848 /* read MC_STATUS */ 3849 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3850 GRBM_STATUS__GUI_ACTIVE_MASK; 3851 3852 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3853 return 0; 3854 udelay(1); 3855 } 3856 return -ETIMEDOUT; 3857 } 3858 3859 static int gfx_v10_0_soft_reset(void *handle) 3860 { 3861 u32 grbm_soft_reset = 0; 3862 u32 tmp; 3863 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3864 3865 /* GRBM_STATUS */ 3866 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3867 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3868 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3869 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3870 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3871 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3872 | GRBM_STATUS__BCI_BUSY_MASK)) { 3873 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3874 GRBM_SOFT_RESET, SOFT_RESET_CP, 3875 1); 3876 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3877 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3878 1); 3879 } 3880 3881 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3882 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3883 GRBM_SOFT_RESET, SOFT_RESET_CP, 3884 1); 3885 } 3886 3887 /* GRBM_STATUS2 */ 3888 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3889 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3890 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3891 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3892 1); 3893 3894 if (grbm_soft_reset) { 3895 /* stop the rlc */ 3896 gfx_v10_0_rlc_stop(adev); 3897 3898 /* Disable GFX parsing/prefetching */ 3899 gfx_v10_0_cp_gfx_enable(adev, false); 3900 3901 /* Disable MEC parsing/prefetching */ 3902 gfx_v10_0_cp_compute_enable(adev, false); 3903 3904 if (grbm_soft_reset) { 3905 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3906 tmp |= grbm_soft_reset; 3907 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3908 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3909 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3910 3911 udelay(50); 3912 3913 tmp &= ~grbm_soft_reset; 3914 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3915 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3916 } 3917 3918 /* Wait a little for things to settle down */ 3919 udelay(50); 3920 } 3921 return 0; 3922 } 3923 3924 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3925 { 3926 uint64_t clock; 3927 3928 amdgpu_gfx_off_ctrl(adev, false); 3929 mutex_lock(&adev->gfx.gpu_clock_mutex); 3930 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) | 3931 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL); 3932 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3933 amdgpu_gfx_off_ctrl(adev, true); 3934 return clock; 3935 } 3936 3937 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3938 uint32_t vmid, 3939 uint32_t gds_base, uint32_t gds_size, 3940 uint32_t gws_base, uint32_t gws_size, 3941 uint32_t oa_base, uint32_t oa_size) 3942 { 3943 struct amdgpu_device *adev = ring->adev; 3944 3945 /* GDS Base */ 3946 gfx_v10_0_write_data_to_reg(ring, 0, false, 3947 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3948 gds_base); 3949 3950 /* GDS Size */ 3951 gfx_v10_0_write_data_to_reg(ring, 0, false, 3952 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3953 gds_size); 3954 3955 /* GWS */ 3956 gfx_v10_0_write_data_to_reg(ring, 0, false, 3957 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3958 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3959 3960 /* OA */ 3961 gfx_v10_0_write_data_to_reg(ring, 0, false, 3962 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3963 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3964 } 3965 3966 static int gfx_v10_0_early_init(void *handle) 3967 { 3968 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3969 3970 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 3971 3972 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3973 3974 gfx_v10_0_set_kiq_pm4_funcs(adev); 3975 gfx_v10_0_set_ring_funcs(adev); 3976 gfx_v10_0_set_irq_funcs(adev); 3977 gfx_v10_0_set_gds_init(adev); 3978 gfx_v10_0_set_rlc_funcs(adev); 3979 3980 return 0; 3981 } 3982 3983 static int gfx_v10_0_late_init(void *handle) 3984 { 3985 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3986 int r; 3987 3988 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3989 if (r) 3990 return r; 3991 3992 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3993 if (r) 3994 return r; 3995 3996 return 0; 3997 } 3998 3999 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 4000 { 4001 uint32_t rlc_cntl; 4002 4003 /* if RLC is not enabled, do nothing */ 4004 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 4005 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 4006 } 4007 4008 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 4009 { 4010 uint32_t data; 4011 unsigned i; 4012 4013 data = RLC_SAFE_MODE__CMD_MASK; 4014 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 4015 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4016 4017 /* wait for RLC_SAFE_MODE */ 4018 for (i = 0; i < adev->usec_timeout; i++) { 4019 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 4020 break; 4021 udelay(1); 4022 } 4023 } 4024 4025 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 4026 { 4027 uint32_t data; 4028 4029 data = RLC_SAFE_MODE__CMD_MASK; 4030 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 4031 } 4032 4033 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 4034 bool enable) 4035 { 4036 uint32_t data, def; 4037 4038 /* It is disabled by HW by default */ 4039 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 4040 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 4041 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4042 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4043 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4044 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4045 4046 /* only for Vega10 & Raven1 */ 4047 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 4048 4049 if (def != data) 4050 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4051 4052 /* MGLS is a global flag to control all MGLS in GFX */ 4053 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 4054 /* 2 - RLC memory Light sleep */ 4055 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 4056 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4057 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4058 if (def != data) 4059 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4060 } 4061 /* 3 - CP memory Light sleep */ 4062 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 4063 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4064 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4065 if (def != data) 4066 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4067 } 4068 } 4069 } else { 4070 /* 1 - MGCG_OVERRIDE */ 4071 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4072 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 4073 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 4074 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 4075 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 4076 if (def != data) 4077 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4078 4079 /* 2 - disable MGLS in RLC */ 4080 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4081 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 4082 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 4083 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 4084 } 4085 4086 /* 3 - disable MGLS in CP */ 4087 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4088 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 4089 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 4090 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 4091 } 4092 } 4093 } 4094 4095 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 4096 bool enable) 4097 { 4098 uint32_t data, def; 4099 4100 /* Enable 3D CGCG/CGLS */ 4101 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 4102 /* write cmd to clear cgcg/cgls ov */ 4103 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4104 /* unset CGCG override */ 4105 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 4106 /* update CGCG and CGLS override bits */ 4107 if (def != data) 4108 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4109 /* enable 3Dcgcg FSM(0x0000363f) */ 4110 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4111 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4112 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4113 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4114 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4115 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4116 if (def != data) 4117 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4118 4119 /* set IDLE_POLL_COUNT(0x00900100) */ 4120 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4121 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4122 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4123 if (def != data) 4124 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4125 } else { 4126 /* Disable CGCG/CGLS */ 4127 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4128 /* disable cgcg, cgls should be disabled */ 4129 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4130 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4131 /* disable cgcg and cgls in FSM */ 4132 if (def != data) 4133 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4134 } 4135 } 4136 4137 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4138 bool enable) 4139 { 4140 uint32_t def, data; 4141 4142 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4143 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4144 /* unset CGCG override */ 4145 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4146 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4147 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4148 else 4149 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4150 /* update CGCG and CGLS override bits */ 4151 if (def != data) 4152 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4153 4154 /* enable cgcg FSM(0x0000363F) */ 4155 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4156 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4157 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4158 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4159 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4160 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4161 if (def != data) 4162 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4163 4164 /* set IDLE_POLL_COUNT(0x00900100) */ 4165 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4166 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4167 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4168 if (def != data) 4169 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4170 } else { 4171 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4172 /* reset CGCG/CGLS bits */ 4173 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4174 /* disable cgcg and cgls in FSM */ 4175 if (def != data) 4176 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4177 } 4178 } 4179 4180 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4181 bool enable) 4182 { 4183 amdgpu_gfx_rlc_enter_safe_mode(adev); 4184 4185 if (enable) { 4186 /* CGCG/CGLS should be enabled after MGCG/MGLS 4187 * === MGCG + MGLS === 4188 */ 4189 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4190 /* === CGCG /CGLS for GFX 3D Only === */ 4191 gfx_v10_0_update_3d_clock_gating(adev, enable); 4192 /* === CGCG + CGLS === */ 4193 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4194 } else { 4195 /* CGCG/CGLS should be disabled before MGCG/MGLS 4196 * === CGCG + CGLS === 4197 */ 4198 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4199 /* === CGCG /CGLS for GFX 3D Only === */ 4200 gfx_v10_0_update_3d_clock_gating(adev, enable); 4201 /* === MGCG + MGLS === */ 4202 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4203 } 4204 4205 if (adev->cg_flags & 4206 (AMD_CG_SUPPORT_GFX_MGCG | 4207 AMD_CG_SUPPORT_GFX_CGLS | 4208 AMD_CG_SUPPORT_GFX_CGCG | 4209 AMD_CG_SUPPORT_GFX_CGLS | 4210 AMD_CG_SUPPORT_GFX_3D_CGCG | 4211 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4212 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4213 4214 amdgpu_gfx_rlc_exit_safe_mode(adev); 4215 4216 return 0; 4217 } 4218 4219 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 4220 { 4221 u32 data; 4222 4223 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 4224 4225 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 4226 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 4227 4228 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 4229 } 4230 4231 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4232 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4233 .set_safe_mode = gfx_v10_0_set_safe_mode, 4234 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4235 .init = gfx_v10_0_rlc_init, 4236 .get_csb_size = gfx_v10_0_get_csb_size, 4237 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4238 .resume = gfx_v10_0_rlc_resume, 4239 .stop = gfx_v10_0_rlc_stop, 4240 .reset = gfx_v10_0_rlc_reset, 4241 .start = gfx_v10_0_rlc_start, 4242 .update_spm_vmid = gfx_v10_0_update_spm_vmid 4243 }; 4244 4245 static int gfx_v10_0_set_powergating_state(void *handle, 4246 enum amd_powergating_state state) 4247 { 4248 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4249 bool enable = (state == AMD_PG_STATE_GATE); 4250 switch (adev->asic_type) { 4251 case CHIP_NAVI10: 4252 case CHIP_NAVI14: 4253 if (!enable) { 4254 amdgpu_gfx_off_ctrl(adev, false); 4255 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 4256 } else 4257 amdgpu_gfx_off_ctrl(adev, true); 4258 break; 4259 default: 4260 break; 4261 } 4262 return 0; 4263 } 4264 4265 static int gfx_v10_0_set_clockgating_state(void *handle, 4266 enum amd_clockgating_state state) 4267 { 4268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4269 4270 switch (adev->asic_type) { 4271 case CHIP_NAVI10: 4272 case CHIP_NAVI14: 4273 case CHIP_NAVI12: 4274 gfx_v10_0_update_gfx_clock_gating(adev, 4275 state == AMD_CG_STATE_GATE); 4276 break; 4277 default: 4278 break; 4279 } 4280 return 0; 4281 } 4282 4283 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4284 { 4285 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4286 int data; 4287 4288 /* AMD_CG_SUPPORT_GFX_MGCG */ 4289 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4290 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4291 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4292 4293 /* AMD_CG_SUPPORT_GFX_CGCG */ 4294 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4295 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4296 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4297 4298 /* AMD_CG_SUPPORT_GFX_CGLS */ 4299 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4300 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4301 4302 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4303 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4304 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4305 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4306 4307 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4308 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4309 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4310 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4311 4312 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4313 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4314 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4315 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4316 4317 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4318 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4319 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4320 } 4321 4322 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4323 { 4324 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4325 } 4326 4327 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4328 { 4329 struct amdgpu_device *adev = ring->adev; 4330 u64 wptr; 4331 4332 /* XXX check if swapping is necessary on BE */ 4333 if (ring->use_doorbell) { 4334 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4335 } else { 4336 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4337 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4338 } 4339 4340 return wptr; 4341 } 4342 4343 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4344 { 4345 struct amdgpu_device *adev = ring->adev; 4346 4347 if (ring->use_doorbell) { 4348 /* XXX check if swapping is necessary on BE */ 4349 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4350 WDOORBELL64(ring->doorbell_index, ring->wptr); 4351 } else { 4352 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4353 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4354 } 4355 } 4356 4357 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4358 { 4359 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4360 } 4361 4362 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4363 { 4364 u64 wptr; 4365 4366 /* XXX check if swapping is necessary on BE */ 4367 if (ring->use_doorbell) 4368 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4369 else 4370 BUG(); 4371 return wptr; 4372 } 4373 4374 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4375 { 4376 struct amdgpu_device *adev = ring->adev; 4377 4378 /* XXX check if swapping is necessary on BE */ 4379 if (ring->use_doorbell) { 4380 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4381 WDOORBELL64(ring->doorbell_index, ring->wptr); 4382 } else { 4383 BUG(); /* only DOORBELL method supported on gfx10 now */ 4384 } 4385 } 4386 4387 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4388 { 4389 struct amdgpu_device *adev = ring->adev; 4390 u32 ref_and_mask, reg_mem_engine; 4391 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 4392 4393 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4394 switch (ring->me) { 4395 case 1: 4396 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4397 break; 4398 case 2: 4399 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4400 break; 4401 default: 4402 return; 4403 } 4404 reg_mem_engine = 0; 4405 } else { 4406 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4407 reg_mem_engine = 1; /* pfp */ 4408 } 4409 4410 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4411 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 4412 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 4413 ref_and_mask, ref_and_mask, 0x20); 4414 } 4415 4416 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4417 struct amdgpu_job *job, 4418 struct amdgpu_ib *ib, 4419 uint32_t flags) 4420 { 4421 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4422 u32 header, control = 0; 4423 4424 if (ib->flags & AMDGPU_IB_FLAG_CE) 4425 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4426 else 4427 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4428 4429 control |= ib->length_dw | (vmid << 24); 4430 4431 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4432 control |= INDIRECT_BUFFER_PRE_ENB(1); 4433 4434 if (flags & AMDGPU_IB_PREEMPTED) 4435 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4436 4437 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 4438 gfx_v10_0_ring_emit_de_meta(ring, 4439 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 4440 } 4441 4442 amdgpu_ring_write(ring, header); 4443 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4444 amdgpu_ring_write(ring, 4445 #ifdef __BIG_ENDIAN 4446 (2 << 0) | 4447 #endif 4448 lower_32_bits(ib->gpu_addr)); 4449 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4450 amdgpu_ring_write(ring, control); 4451 } 4452 4453 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4454 struct amdgpu_job *job, 4455 struct amdgpu_ib *ib, 4456 uint32_t flags) 4457 { 4458 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4459 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4460 4461 /* Currently, there is a high possibility to get wave ID mismatch 4462 * between ME and GDS, leading to a hw deadlock, because ME generates 4463 * different wave IDs than the GDS expects. This situation happens 4464 * randomly when at least 5 compute pipes use GDS ordered append. 4465 * The wave IDs generated by ME are also wrong after suspend/resume. 4466 * Those are probably bugs somewhere else in the kernel driver. 4467 * 4468 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4469 * GDS to 0 for this ring (me/pipe). 4470 */ 4471 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4472 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4473 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4474 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4475 } 4476 4477 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4478 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4479 amdgpu_ring_write(ring, 4480 #ifdef __BIG_ENDIAN 4481 (2 << 0) | 4482 #endif 4483 lower_32_bits(ib->gpu_addr)); 4484 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4485 amdgpu_ring_write(ring, control); 4486 } 4487 4488 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4489 u64 seq, unsigned flags) 4490 { 4491 struct amdgpu_device *adev = ring->adev; 4492 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4493 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4494 4495 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4496 if (adev->pdev->device == 0x50) 4497 int_sel = false; 4498 4499 /* RELEASE_MEM - flush caches, send int */ 4500 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4501 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4502 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4503 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4504 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4505 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4506 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4507 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4508 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4509 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4510 4511 /* 4512 * the address should be Qword aligned if 64bit write, Dword 4513 * aligned if only send 32bit data low (discard data high) 4514 */ 4515 if (write64bit) 4516 BUG_ON(addr & 0x7); 4517 else 4518 BUG_ON(addr & 0x3); 4519 amdgpu_ring_write(ring, lower_32_bits(addr)); 4520 amdgpu_ring_write(ring, upper_32_bits(addr)); 4521 amdgpu_ring_write(ring, lower_32_bits(seq)); 4522 amdgpu_ring_write(ring, upper_32_bits(seq)); 4523 amdgpu_ring_write(ring, 0); 4524 } 4525 4526 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4527 { 4528 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4529 uint32_t seq = ring->fence_drv.sync_seq; 4530 uint64_t addr = ring->fence_drv.gpu_addr; 4531 4532 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4533 upper_32_bits(addr), seq, 0xffffffff, 4); 4534 } 4535 4536 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4537 unsigned vmid, uint64_t pd_addr) 4538 { 4539 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4540 4541 /* compute doesn't have PFP */ 4542 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4543 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4544 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4545 amdgpu_ring_write(ring, 0x0); 4546 } 4547 } 4548 4549 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4550 u64 seq, unsigned int flags) 4551 { 4552 struct amdgpu_device *adev = ring->adev; 4553 4554 /* we only allocate 32bit for each seq wb address */ 4555 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4556 4557 /* write fence seq to the "addr" */ 4558 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4559 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4560 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4561 amdgpu_ring_write(ring, lower_32_bits(addr)); 4562 amdgpu_ring_write(ring, upper_32_bits(addr)); 4563 amdgpu_ring_write(ring, lower_32_bits(seq)); 4564 4565 if (flags & AMDGPU_FENCE_FLAG_INT) { 4566 /* set register to trigger INT */ 4567 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4568 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4569 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4570 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4571 amdgpu_ring_write(ring, 0); 4572 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4573 } 4574 } 4575 4576 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4577 { 4578 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4579 amdgpu_ring_write(ring, 0); 4580 } 4581 4582 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4583 { 4584 uint32_t dw2 = 0; 4585 4586 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev)) 4587 gfx_v10_0_ring_emit_ce_meta(ring, 4588 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 4589 4590 gfx_v10_0_ring_emit_tmz(ring, true); 4591 4592 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4593 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4594 /* set load_global_config & load_global_uconfig */ 4595 dw2 |= 0x8001; 4596 /* set load_cs_sh_regs */ 4597 dw2 |= 0x01000000; 4598 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4599 dw2 |= 0x10002; 4600 4601 /* set load_ce_ram if preamble presented */ 4602 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4603 dw2 |= 0x10000000; 4604 } else { 4605 /* still load_ce_ram if this is the first time preamble presented 4606 * although there is no context switch happens. 4607 */ 4608 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4609 dw2 |= 0x10000000; 4610 } 4611 4612 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4613 amdgpu_ring_write(ring, dw2); 4614 amdgpu_ring_write(ring, 0); 4615 } 4616 4617 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4618 { 4619 unsigned ret; 4620 4621 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4622 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4623 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4624 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4625 ret = ring->wptr & ring->buf_mask; 4626 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4627 4628 return ret; 4629 } 4630 4631 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4632 { 4633 unsigned cur; 4634 BUG_ON(offset > ring->buf_mask); 4635 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4636 4637 cur = (ring->wptr - 1) & ring->buf_mask; 4638 if (likely(cur > offset)) 4639 ring->ring[offset] = cur - offset; 4640 else 4641 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4642 } 4643 4644 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4645 { 4646 int i, r = 0; 4647 struct amdgpu_device *adev = ring->adev; 4648 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4649 struct amdgpu_ring *kiq_ring = &kiq->ring; 4650 4651 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4652 return -EINVAL; 4653 4654 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) 4655 return -ENOMEM; 4656 4657 /* assert preemption condition */ 4658 amdgpu_ring_set_preempt_cond_exec(ring, false); 4659 4660 /* assert IB preemption, emit the trailing fence */ 4661 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4662 ring->trail_fence_gpu_addr, 4663 ++ring->trail_seq); 4664 amdgpu_ring_commit(kiq_ring); 4665 4666 /* poll the trailing fence */ 4667 for (i = 0; i < adev->usec_timeout; i++) { 4668 if (ring->trail_seq == 4669 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4670 break; 4671 udelay(1); 4672 } 4673 4674 if (i >= adev->usec_timeout) { 4675 r = -EINVAL; 4676 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4677 } 4678 4679 /* deassert preemption condition */ 4680 amdgpu_ring_set_preempt_cond_exec(ring, true); 4681 return r; 4682 } 4683 4684 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4685 { 4686 struct amdgpu_device *adev = ring->adev; 4687 struct v10_ce_ib_state ce_payload = {0}; 4688 uint64_t csa_addr; 4689 int cnt; 4690 4691 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4692 csa_addr = amdgpu_csa_vaddr(ring->adev); 4693 4694 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4695 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4696 WRITE_DATA_DST_SEL(8) | 4697 WR_CONFIRM) | 4698 WRITE_DATA_CACHE_POLICY(0)); 4699 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4700 offsetof(struct v10_gfx_meta_data, ce_payload))); 4701 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4702 offsetof(struct v10_gfx_meta_data, ce_payload))); 4703 4704 if (resume) 4705 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4706 offsetof(struct v10_gfx_meta_data, 4707 ce_payload), 4708 sizeof(ce_payload) >> 2); 4709 else 4710 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4711 sizeof(ce_payload) >> 2); 4712 } 4713 4714 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4715 { 4716 struct amdgpu_device *adev = ring->adev; 4717 struct v10_de_ib_state de_payload = {0}; 4718 uint64_t csa_addr, gds_addr; 4719 int cnt; 4720 4721 csa_addr = amdgpu_csa_vaddr(ring->adev); 4722 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4723 PAGE_SIZE); 4724 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4725 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4726 4727 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4728 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4729 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4730 WRITE_DATA_DST_SEL(8) | 4731 WR_CONFIRM) | 4732 WRITE_DATA_CACHE_POLICY(0)); 4733 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4734 offsetof(struct v10_gfx_meta_data, de_payload))); 4735 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4736 offsetof(struct v10_gfx_meta_data, de_payload))); 4737 4738 if (resume) 4739 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4740 offsetof(struct v10_gfx_meta_data, 4741 de_payload), 4742 sizeof(de_payload) >> 2); 4743 else 4744 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4745 sizeof(de_payload) >> 2); 4746 } 4747 4748 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4749 { 4750 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4751 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4752 } 4753 4754 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4755 { 4756 struct amdgpu_device *adev = ring->adev; 4757 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4758 4759 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4760 amdgpu_ring_write(ring, 0 | /* src: register*/ 4761 (5 << 8) | /* dst: memory */ 4762 (1 << 20)); /* write confirm */ 4763 amdgpu_ring_write(ring, reg); 4764 amdgpu_ring_write(ring, 0); 4765 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4766 kiq->reg_val_offs * 4)); 4767 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4768 kiq->reg_val_offs * 4)); 4769 } 4770 4771 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4772 uint32_t val) 4773 { 4774 uint32_t cmd = 0; 4775 4776 switch (ring->funcs->type) { 4777 case AMDGPU_RING_TYPE_GFX: 4778 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4779 break; 4780 case AMDGPU_RING_TYPE_KIQ: 4781 cmd = (1 << 16); /* no inc addr */ 4782 break; 4783 default: 4784 cmd = WR_CONFIRM; 4785 break; 4786 } 4787 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4788 amdgpu_ring_write(ring, cmd); 4789 amdgpu_ring_write(ring, reg); 4790 amdgpu_ring_write(ring, 0); 4791 amdgpu_ring_write(ring, val); 4792 } 4793 4794 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4795 uint32_t val, uint32_t mask) 4796 { 4797 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4798 } 4799 4800 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 4801 uint32_t reg0, uint32_t reg1, 4802 uint32_t ref, uint32_t mask) 4803 { 4804 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4805 struct amdgpu_device *adev = ring->adev; 4806 bool fw_version_ok = false; 4807 4808 fw_version_ok = adev->gfx.cp_fw_write_wait; 4809 4810 if (fw_version_ok) 4811 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 4812 ref, mask, 0x20); 4813 else 4814 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 4815 ref, mask); 4816 } 4817 4818 static void 4819 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4820 uint32_t me, uint32_t pipe, 4821 enum amdgpu_interrupt_state state) 4822 { 4823 uint32_t cp_int_cntl, cp_int_cntl_reg; 4824 4825 if (!me) { 4826 switch (pipe) { 4827 case 0: 4828 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4829 break; 4830 case 1: 4831 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4832 break; 4833 default: 4834 DRM_DEBUG("invalid pipe %d\n", pipe); 4835 return; 4836 } 4837 } else { 4838 DRM_DEBUG("invalid me %d\n", me); 4839 return; 4840 } 4841 4842 switch (state) { 4843 case AMDGPU_IRQ_STATE_DISABLE: 4844 cp_int_cntl = RREG32(cp_int_cntl_reg); 4845 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4846 TIME_STAMP_INT_ENABLE, 0); 4847 WREG32(cp_int_cntl_reg, cp_int_cntl); 4848 break; 4849 case AMDGPU_IRQ_STATE_ENABLE: 4850 cp_int_cntl = RREG32(cp_int_cntl_reg); 4851 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4852 TIME_STAMP_INT_ENABLE, 1); 4853 WREG32(cp_int_cntl_reg, cp_int_cntl); 4854 break; 4855 default: 4856 break; 4857 } 4858 } 4859 4860 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4861 int me, int pipe, 4862 enum amdgpu_interrupt_state state) 4863 { 4864 u32 mec_int_cntl, mec_int_cntl_reg; 4865 4866 /* 4867 * amdgpu controls only the first MEC. That's why this function only 4868 * handles the setting of interrupts for this specific MEC. All other 4869 * pipes' interrupts are set by amdkfd. 4870 */ 4871 4872 if (me == 1) { 4873 switch (pipe) { 4874 case 0: 4875 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4876 break; 4877 case 1: 4878 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4879 break; 4880 case 2: 4881 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4882 break; 4883 case 3: 4884 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4885 break; 4886 default: 4887 DRM_DEBUG("invalid pipe %d\n", pipe); 4888 return; 4889 } 4890 } else { 4891 DRM_DEBUG("invalid me %d\n", me); 4892 return; 4893 } 4894 4895 switch (state) { 4896 case AMDGPU_IRQ_STATE_DISABLE: 4897 mec_int_cntl = RREG32(mec_int_cntl_reg); 4898 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4899 TIME_STAMP_INT_ENABLE, 0); 4900 WREG32(mec_int_cntl_reg, mec_int_cntl); 4901 break; 4902 case AMDGPU_IRQ_STATE_ENABLE: 4903 mec_int_cntl = RREG32(mec_int_cntl_reg); 4904 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4905 TIME_STAMP_INT_ENABLE, 1); 4906 WREG32(mec_int_cntl_reg, mec_int_cntl); 4907 break; 4908 default: 4909 break; 4910 } 4911 } 4912 4913 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4914 struct amdgpu_irq_src *src, 4915 unsigned type, 4916 enum amdgpu_interrupt_state state) 4917 { 4918 switch (type) { 4919 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4920 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4921 break; 4922 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4923 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4924 break; 4925 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4926 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4927 break; 4928 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4929 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4930 break; 4931 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4932 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4933 break; 4934 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4935 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4936 break; 4937 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4938 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4939 break; 4940 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4941 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4942 break; 4943 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4944 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4945 break; 4946 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4947 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4948 break; 4949 default: 4950 break; 4951 } 4952 return 0; 4953 } 4954 4955 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 4956 struct amdgpu_irq_src *source, 4957 struct amdgpu_iv_entry *entry) 4958 { 4959 int i; 4960 u8 me_id, pipe_id, queue_id; 4961 struct amdgpu_ring *ring; 4962 4963 DRM_DEBUG("IH: CP EOP\n"); 4964 me_id = (entry->ring_id & 0x0c) >> 2; 4965 pipe_id = (entry->ring_id & 0x03) >> 0; 4966 queue_id = (entry->ring_id & 0x70) >> 4; 4967 4968 switch (me_id) { 4969 case 0: 4970 if (pipe_id == 0) 4971 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4972 else 4973 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4974 break; 4975 case 1: 4976 case 2: 4977 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4978 ring = &adev->gfx.compute_ring[i]; 4979 /* Per-queue interrupt is supported for MEC starting from VI. 4980 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4981 */ 4982 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4983 amdgpu_fence_process(ring); 4984 } 4985 break; 4986 } 4987 return 0; 4988 } 4989 4990 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4991 struct amdgpu_irq_src *source, 4992 unsigned type, 4993 enum amdgpu_interrupt_state state) 4994 { 4995 switch (state) { 4996 case AMDGPU_IRQ_STATE_DISABLE: 4997 case AMDGPU_IRQ_STATE_ENABLE: 4998 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4999 PRIV_REG_INT_ENABLE, 5000 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5001 break; 5002 default: 5003 break; 5004 } 5005 5006 return 0; 5007 } 5008 5009 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 5010 struct amdgpu_irq_src *source, 5011 unsigned type, 5012 enum amdgpu_interrupt_state state) 5013 { 5014 switch (state) { 5015 case AMDGPU_IRQ_STATE_DISABLE: 5016 case AMDGPU_IRQ_STATE_ENABLE: 5017 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 5018 PRIV_INSTR_INT_ENABLE, 5019 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 5020 default: 5021 break; 5022 } 5023 5024 return 0; 5025 } 5026 5027 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 5028 struct amdgpu_iv_entry *entry) 5029 { 5030 u8 me_id, pipe_id, queue_id; 5031 struct amdgpu_ring *ring; 5032 int i; 5033 5034 me_id = (entry->ring_id & 0x0c) >> 2; 5035 pipe_id = (entry->ring_id & 0x03) >> 0; 5036 queue_id = (entry->ring_id & 0x70) >> 4; 5037 5038 switch (me_id) { 5039 case 0: 5040 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 5041 ring = &adev->gfx.gfx_ring[i]; 5042 /* we only enabled 1 gfx queue per pipe for now */ 5043 if (ring->me == me_id && ring->pipe == pipe_id) 5044 drm_sched_fault(&ring->sched); 5045 } 5046 break; 5047 case 1: 5048 case 2: 5049 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 5050 ring = &adev->gfx.compute_ring[i]; 5051 if (ring->me == me_id && ring->pipe == pipe_id && 5052 ring->queue == queue_id) 5053 drm_sched_fault(&ring->sched); 5054 } 5055 break; 5056 default: 5057 BUG(); 5058 } 5059 } 5060 5061 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 5062 struct amdgpu_irq_src *source, 5063 struct amdgpu_iv_entry *entry) 5064 { 5065 DRM_ERROR("Illegal register access in command stream\n"); 5066 gfx_v10_0_handle_priv_fault(adev, entry); 5067 return 0; 5068 } 5069 5070 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 5071 struct amdgpu_irq_src *source, 5072 struct amdgpu_iv_entry *entry) 5073 { 5074 DRM_ERROR("Illegal instruction in command stream\n"); 5075 gfx_v10_0_handle_priv_fault(adev, entry); 5076 return 0; 5077 } 5078 5079 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 5080 struct amdgpu_irq_src *src, 5081 unsigned int type, 5082 enum amdgpu_interrupt_state state) 5083 { 5084 uint32_t tmp, target; 5085 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5086 5087 if (ring->me == 1) 5088 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 5089 else 5090 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 5091 target += ring->pipe; 5092 5093 switch (type) { 5094 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 5095 if (state == AMDGPU_IRQ_STATE_DISABLE) { 5096 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5097 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5098 GENERIC2_INT_ENABLE, 0); 5099 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5100 5101 tmp = RREG32(target); 5102 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5103 GENERIC2_INT_ENABLE, 0); 5104 WREG32(target, tmp); 5105 } else { 5106 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 5107 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 5108 GENERIC2_INT_ENABLE, 1); 5109 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 5110 5111 tmp = RREG32(target); 5112 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 5113 GENERIC2_INT_ENABLE, 1); 5114 WREG32(target, tmp); 5115 } 5116 break; 5117 default: 5118 BUG(); /* kiq only support GENERIC2_INT now */ 5119 break; 5120 } 5121 return 0; 5122 } 5123 5124 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 5125 struct amdgpu_irq_src *source, 5126 struct amdgpu_iv_entry *entry) 5127 { 5128 u8 me_id, pipe_id, queue_id; 5129 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 5130 5131 me_id = (entry->ring_id & 0x0c) >> 2; 5132 pipe_id = (entry->ring_id & 0x03) >> 0; 5133 queue_id = (entry->ring_id & 0x70) >> 4; 5134 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 5135 me_id, pipe_id, queue_id); 5136 5137 amdgpu_fence_process(ring); 5138 return 0; 5139 } 5140 5141 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 5142 .name = "gfx_v10_0", 5143 .early_init = gfx_v10_0_early_init, 5144 .late_init = gfx_v10_0_late_init, 5145 .sw_init = gfx_v10_0_sw_init, 5146 .sw_fini = gfx_v10_0_sw_fini, 5147 .hw_init = gfx_v10_0_hw_init, 5148 .hw_fini = gfx_v10_0_hw_fini, 5149 .suspend = gfx_v10_0_suspend, 5150 .resume = gfx_v10_0_resume, 5151 .is_idle = gfx_v10_0_is_idle, 5152 .wait_for_idle = gfx_v10_0_wait_for_idle, 5153 .soft_reset = gfx_v10_0_soft_reset, 5154 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 5155 .set_powergating_state = gfx_v10_0_set_powergating_state, 5156 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5157 }; 5158 5159 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5160 .type = AMDGPU_RING_TYPE_GFX, 5161 .align_mask = 0xff, 5162 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5163 .support_64bit_ptrs = true, 5164 .vmhub = AMDGPU_GFXHUB_0, 5165 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5166 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5167 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5168 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5169 5 + /* COND_EXEC */ 5170 7 + /* PIPELINE_SYNC */ 5171 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5172 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5173 2 + /* VM_FLUSH */ 5174 8 + /* FENCE for VM_FLUSH */ 5175 20 + /* GDS switch */ 5176 4 + /* double SWITCH_BUFFER, 5177 * the first COND_EXEC jump to the place 5178 * just prior to this double SWITCH_BUFFER 5179 */ 5180 5 + /* COND_EXEC */ 5181 7 + /* HDP_flush */ 5182 4 + /* VGT_flush */ 5183 14 + /* CE_META */ 5184 31 + /* DE_META */ 5185 3 + /* CNTX_CTRL */ 5186 5 + /* HDP_INVL */ 5187 8 + 8 + /* FENCE x2 */ 5188 2, /* SWITCH_BUFFER */ 5189 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 5190 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5191 .emit_fence = gfx_v10_0_ring_emit_fence, 5192 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5193 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5194 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5195 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5196 .test_ring = gfx_v10_0_ring_test_ring, 5197 .test_ib = gfx_v10_0_ring_test_ib, 5198 .insert_nop = amdgpu_ring_insert_nop, 5199 .pad_ib = amdgpu_ring_generic_pad_ib, 5200 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5201 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5202 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5203 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5204 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5205 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5206 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5207 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5208 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5209 }; 5210 5211 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5212 .type = AMDGPU_RING_TYPE_COMPUTE, 5213 .align_mask = 0xff, 5214 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5215 .support_64bit_ptrs = true, 5216 .vmhub = AMDGPU_GFXHUB_0, 5217 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5218 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5219 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5220 .emit_frame_size = 5221 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5222 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5223 5 + /* hdp invalidate */ 5224 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5225 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5226 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5227 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5228 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5229 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5230 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5231 .emit_fence = gfx_v10_0_ring_emit_fence, 5232 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5233 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5234 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5235 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5236 .test_ring = gfx_v10_0_ring_test_ring, 5237 .test_ib = gfx_v10_0_ring_test_ib, 5238 .insert_nop = amdgpu_ring_insert_nop, 5239 .pad_ib = amdgpu_ring_generic_pad_ib, 5240 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5241 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5242 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5243 }; 5244 5245 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5246 .type = AMDGPU_RING_TYPE_KIQ, 5247 .align_mask = 0xff, 5248 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5249 .support_64bit_ptrs = true, 5250 .vmhub = AMDGPU_GFXHUB_0, 5251 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5252 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5253 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5254 .emit_frame_size = 5255 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5256 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5257 5 + /*hdp invalidate */ 5258 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5259 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5260 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5261 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5262 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5263 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5264 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5265 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5266 .test_ring = gfx_v10_0_ring_test_ring, 5267 .test_ib = gfx_v10_0_ring_test_ib, 5268 .insert_nop = amdgpu_ring_insert_nop, 5269 .pad_ib = amdgpu_ring_generic_pad_ib, 5270 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5271 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5272 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5273 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 5274 }; 5275 5276 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5277 { 5278 int i; 5279 5280 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5281 5282 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5283 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5284 5285 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5286 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5287 } 5288 5289 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5290 .set = gfx_v10_0_set_eop_interrupt_state, 5291 .process = gfx_v10_0_eop_irq, 5292 }; 5293 5294 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5295 .set = gfx_v10_0_set_priv_reg_fault_state, 5296 .process = gfx_v10_0_priv_reg_irq, 5297 }; 5298 5299 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5300 .set = gfx_v10_0_set_priv_inst_fault_state, 5301 .process = gfx_v10_0_priv_inst_irq, 5302 }; 5303 5304 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5305 .set = gfx_v10_0_kiq_set_interrupt_state, 5306 .process = gfx_v10_0_kiq_irq, 5307 }; 5308 5309 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5310 { 5311 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5312 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5313 5314 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5315 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5316 5317 adev->gfx.priv_reg_irq.num_types = 1; 5318 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5319 5320 adev->gfx.priv_inst_irq.num_types = 1; 5321 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5322 } 5323 5324 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5325 { 5326 switch (adev->asic_type) { 5327 case CHIP_NAVI10: 5328 case CHIP_NAVI14: 5329 case CHIP_NAVI12: 5330 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5331 break; 5332 default: 5333 break; 5334 } 5335 } 5336 5337 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5338 { 5339 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 5340 adev->gfx.config.max_sh_per_se * 5341 adev->gfx.config.max_shader_engines; 5342 5343 adev->gds.gds_size = 0x10000; 5344 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 5345 adev->gds.gws_size = 64; 5346 adev->gds.oa_size = 16; 5347 } 5348 5349 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5350 u32 bitmap) 5351 { 5352 u32 data; 5353 5354 if (!bitmap) 5355 return; 5356 5357 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5358 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5359 5360 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5361 } 5362 5363 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5364 { 5365 u32 data, wgp_bitmask; 5366 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5367 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5368 5369 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5370 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5371 5372 wgp_bitmask = 5373 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5374 5375 return (~data) & wgp_bitmask; 5376 } 5377 5378 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5379 { 5380 u32 wgp_idx, wgp_active_bitmap; 5381 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5382 5383 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5384 cu_active_bitmap = 0; 5385 5386 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5387 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5388 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5389 if (wgp_active_bitmap & (1 << wgp_idx)) 5390 cu_active_bitmap |= cu_bitmap_per_wgp; 5391 } 5392 5393 return cu_active_bitmap; 5394 } 5395 5396 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5397 struct amdgpu_cu_info *cu_info) 5398 { 5399 int i, j, k, counter, active_cu_number = 0; 5400 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5401 unsigned disable_masks[4 * 2]; 5402 5403 if (!adev || !cu_info) 5404 return -EINVAL; 5405 5406 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5407 5408 mutex_lock(&adev->grbm_idx_mutex); 5409 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5410 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5411 mask = 1; 5412 ao_bitmap = 0; 5413 counter = 0; 5414 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5415 if (i < 4 && j < 2) 5416 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5417 adev, disable_masks[i * 2 + j]); 5418 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5419 cu_info->bitmap[i][j] = bitmap; 5420 5421 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5422 if (bitmap & mask) { 5423 if (counter < adev->gfx.config.max_cu_per_sh) 5424 ao_bitmap |= mask; 5425 counter++; 5426 } 5427 mask <<= 1; 5428 } 5429 active_cu_number += counter; 5430 if (i < 2 && j < 2) 5431 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5432 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5433 } 5434 } 5435 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5436 mutex_unlock(&adev->grbm_idx_mutex); 5437 5438 cu_info->number = active_cu_number; 5439 cu_info->ao_cu_mask = ao_cu_mask; 5440 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5441 5442 return 0; 5443 } 5444 5445 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5446 { 5447 .type = AMD_IP_BLOCK_TYPE_GFX, 5448 .major = 10, 5449 .minor = 0, 5450 .rev = 0, 5451 .funcs = &gfx_v10_0_ip_funcs, 5452 }; 5453