1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 #include "gc/gc_10_1_0_offset.h" 36 #include "gc/gc_10_1_0_sh_mask.h" 37 #include "smuio/smuio_11_0_0_offset.h" 38 #include "smuio/smuio_11_0_0_sh_mask.h" 39 #include "navi10_enum.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "soc15_common.h" 45 #include "clearstate_gfx10.h" 46 #include "v10_structs.h" 47 #include "gfx_v10_0.h" 48 #include "nbio_v2_3.h" 49 50 /* 51 * Navi10 has two graphic rings to share each graphic pipe. 52 * 1. Primary ring 53 * 2. Async ring 54 */ 55 #define GFX10_NUM_GFX_RINGS_NV1X 1 56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2 57 #define GFX10_MEC_HPD_SIZE 2048 58 59 #define F32_CE_PROGRAM_RAM_SIZE 65536 60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 61 62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a 65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1 66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b 67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1 68 69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8 70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L 71 72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006 73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1 74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007 75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1 76 77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55 78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0 79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0 80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1 81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1 82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1 83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec 84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2 88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3 90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0 91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4 92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0 93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5 94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0 95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6 96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0 97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a 98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L 99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2 101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL 102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0 104 105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1 107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1 109 110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d 111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1 112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e 113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1 114 115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441 116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1 117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261 118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1 119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f 120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1 121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e 122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1 123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241 124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1 125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250 126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1 127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240 128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1 129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440 130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1 131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580 132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0 133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL 134 135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814 136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1 137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815 138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1 139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818 140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1 141 #define mmCP_HYP_CE_UCODE_DATA 0x5819 142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1 143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816 144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1 145 #define mmCP_HYP_ME_UCODE_DATA 0x5817 146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1 147 148 #define mmCPG_PSP_DEBUG 0x5c10 149 #define mmCPG_PSP_DEBUG_BASE_IDX 1 150 #define mmCPC_PSP_DEBUG 0x5c11 151 #define mmCPC_PSP_DEBUG_BASE_IDX 1 152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L 154 155 //CC_GC_SA_UNIT_DISABLE 156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9 157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0 158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 160 //GC_USER_SA_UNIT_DISABLE 161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea 162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0 163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8 164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L 165 //PA_SC_ENHANCE_3 166 #define mmPA_SC_ENHANCE_3 0x1085 167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0 168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3 169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L 170 171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c 172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1 173 174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3 175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db 177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0 178 179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030 180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0 181 182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5 183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1 184 185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 187 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 191 192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin"); 193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin"); 194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin"); 195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin"); 196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin"); 197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 199 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 203 204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin"); 205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin"); 206 MODULE_FIRMWARE("amdgpu/navi12_me.bin"); 207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin"); 208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin"); 209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin"); 210 211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin"); 212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin"); 213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin"); 214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin"); 215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin"); 216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin"); 217 218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin"); 219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin"); 220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin"); 221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin"); 222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin"); 223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin"); 224 225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin"); 226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin"); 227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin"); 228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin"); 229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin"); 230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin"); 231 232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin"); 233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin"); 234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin"); 235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin"); 236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin"); 237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin"); 238 239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin"); 240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin"); 241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin"); 242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin"); 243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin"); 244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin"); 245 246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin"); 247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin"); 248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin"); 249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin"); 250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin"); 251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin"); 252 253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin"); 254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin"); 255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin"); 256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin"); 257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin"); 258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin"); 259 260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin"); 261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin"); 262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin"); 263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin"); 264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin"); 265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin"); 266 267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin"); 268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin"); 269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin"); 270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin"); 271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin"); 272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin"); 273 274 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 275 { 276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000) 316 }; 317 318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 319 { 320 /* Pending on emulation bring up */ 321 }; 322 323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] = 324 { 325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0), 326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19), 1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20), 1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5), 1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa), 1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14), 1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19), 1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33), 1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 1377 }; 1378 1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 1380 { 1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), 1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105), 1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000), 1419 }; 1420 1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] = 1422 { 1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014), 1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100), 1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100), 1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100), 1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000), 1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe), 1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02), 1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000), 1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820), 1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104), 1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010), 1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000) 1465 }; 1466 1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 1468 { 1469 /* Pending on emulation bring up */ 1470 }; 1471 1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] = 1473 { 1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0), 1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e), 1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4), 1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0), 2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4), 2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0), 2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4), 2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8), 2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac), 2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8), 2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc), 2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8), 2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc), 2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0), 2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4), 2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20), 2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26), 2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28), 2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf), 2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15), 2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f), 2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25), 2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b), 2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 2094 }; 2095 2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] = 2097 { 2098 /* Pending on emulation bring up */ 2099 }; 2100 2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] = 2102 { 2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0), 2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8), 2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2), 2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1), 2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc), 2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8), 2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c), 2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3), 2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20), 2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c), 2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24), 2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28), 2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38), 2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c), 2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18), 2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18), 2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50), 2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54), 2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58), 2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c), 2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14), 2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48), 2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c), 2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40), 2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44), 2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a), 2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10), 2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60), 2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64), 2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70), 2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74), 2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68), 2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c), 2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78), 2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c), 2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88), 2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c), 2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80), 2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84), 2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90), 2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94), 2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0), 2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4), 2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98), 2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c), 2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4), 2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8), 2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac), 2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8), 2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc), 2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0), 2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4), 2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0), 2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4), 2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0), 2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4), 2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8), 2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc), 2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8), 2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec), 2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16), 2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0), 2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4), 2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8), 2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc), 2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17), 2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100), 2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13), 2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104), 2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0), 2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118), 2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c), 2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120), 2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124), 2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc), 2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110), 2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15), 2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114), 2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14), 2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108), 2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c), 2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19), 2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8), 2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b), 2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128), 2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c), 2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138), 2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c), 2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130), 2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12), 2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134), 2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf), 2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140), 2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144), 2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150), 2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154), 2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148), 2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c), 2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7), 2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158), 2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c), 2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168), 2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa), 2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c), 2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9), 3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160), 3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164), 3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0), 3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170), 3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174), 3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180), 3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184), 3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178), 3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10), 3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c), 3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188), 3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c), 3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5), 3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198), 3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc), 3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c), 3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190), 3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe), 3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194), 3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6), 3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30), 3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd), 3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34), 3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11), 3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0), 3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d), 3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4), 3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f), 3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c), 3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb), 3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f), 3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22), 3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1), 3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6), 3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10), 3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000), 3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15), 3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0), 3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35), 3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000) 3155 }; 3156 3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] = 3158 { 3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3167 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100), 3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088), 3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080), 3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988), 3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3202 }; 3203 3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = 3205 { 3206 /* Pending on emulation bring up */ 3207 }; 3208 3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = 3210 { 3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080), 3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080), 3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400), 3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104), 3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004), 3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000), 3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff), 3252 3253 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */ 3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3255 }; 3256 3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 3258 { 3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100), 3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100), 3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000), 3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142), 3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020), 3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103), 3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000), 3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff), 3283 3284 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */ 3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020), 3286 }; 3287 3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = 3289 { 3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242), 3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3310 }; 3311 3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 3313 { 3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100), 3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100), 3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280), 3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000), 3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500), 3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400), 3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008), 3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988), 3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007), 3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820), 3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070), 3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020), 3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000), 3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000), 3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020) 3350 }; 3351 3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = { 3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100), 3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100), 3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100), 3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000), 3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500), 3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070), 3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000), 3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000), 3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000), 3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000), 3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000), 3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000), 3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000), 3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000), 3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000), 3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000), 3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000), 3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000), 3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000), 3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000), 3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000), 3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000), 3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000), 3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000) 3385 }; 3386 3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = { 3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000), 3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e), 3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100), 3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000), 3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014), 3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8), 3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003), 3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200), 3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000), 3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210), 3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044), 3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500), 3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff), 3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017), 3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8), 3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130), 3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130), 3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f), 3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188), 3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009), 3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02), 3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000), 3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101), 3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000), 3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 3422 }; 3423 3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = 3425 { 3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044), 3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042), 3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044), 3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3), 3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007), 3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3448 }; 3449 3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = { 3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100), 3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4), 3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200), 3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280), 3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000), 3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041), 3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500), 3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4), 3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210), 3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210), 3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff), 3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008), 3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988), 3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020), 3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007), 3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800), 3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820), 3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000), 3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020), 3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000) 3473 }; 3474 3475 #define DEFAULT_SH_MEM_CONFIG \ 3476 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 3477 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 3478 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 3479 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 3480 3481 /* TODO: pending on golden setting value of gb address config */ 3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044 3483 3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev); 3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 3490 struct amdgpu_cu_info *cu_info); 3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 3493 u32 sh_num, u32 instance); 3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 3495 3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure); 3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev); 3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev); 3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev); 3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 3507 uint16_t pasid, uint32_t flush_type, 3508 bool all_hub, uint8_t dst_sel); 3509 3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 3511 { 3512 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 3513 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 3514 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 3515 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 3516 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 3517 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 3518 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 3519 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 3520 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 3521 } 3522 3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 3524 struct amdgpu_ring *ring) 3525 { 3526 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 3527 uint64_t wptr_addr = ring->wptr_gpu_addr; 3528 uint32_t eng_sel = 0; 3529 3530 switch (ring->funcs->type) { 3531 case AMDGPU_RING_TYPE_COMPUTE: 3532 eng_sel = 0; 3533 break; 3534 case AMDGPU_RING_TYPE_GFX: 3535 eng_sel = 4; 3536 break; 3537 case AMDGPU_RING_TYPE_MES: 3538 eng_sel = 5; 3539 break; 3540 default: 3541 WARN_ON(1); 3542 } 3543 3544 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 3545 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 3546 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3547 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 3548 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 3549 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 3550 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 3551 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 3552 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 3553 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 3554 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 3555 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 3556 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 3557 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 3558 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 3559 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 3560 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 3561 } 3562 3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 3564 struct amdgpu_ring *ring, 3565 enum amdgpu_unmap_queues_action action, 3566 u64 gpu_addr, u64 seq) 3567 { 3568 struct amdgpu_device *adev = kiq_ring->adev; 3569 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3570 3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { 3572 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq); 3573 return; 3574 } 3575 3576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 3577 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3578 PACKET3_UNMAP_QUEUES_ACTION(action) | 3579 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 3580 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 3581 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 3582 amdgpu_ring_write(kiq_ring, 3583 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 3584 3585 if (action == PREEMPT_QUEUES_NO_UNMAP) { 3586 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 3587 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 3588 amdgpu_ring_write(kiq_ring, seq); 3589 } else { 3590 amdgpu_ring_write(kiq_ring, 0); 3591 amdgpu_ring_write(kiq_ring, 0); 3592 amdgpu_ring_write(kiq_ring, 0); 3593 } 3594 } 3595 3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 3597 struct amdgpu_ring *ring, 3598 u64 addr, 3599 u64 seq) 3600 { 3601 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 3602 3603 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 3604 amdgpu_ring_write(kiq_ring, 3605 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 3606 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 3607 PACKET3_QUERY_STATUS_COMMAND(2)); 3608 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 3609 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 3610 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 3611 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 3612 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 3613 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 3614 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 3615 } 3616 3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, 3618 uint16_t pasid, uint32_t flush_type, 3619 bool all_hub) 3620 { 3621 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1); 3622 } 3623 3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 3625 .kiq_set_resources = gfx10_kiq_set_resources, 3626 .kiq_map_queues = gfx10_kiq_map_queues, 3627 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 3628 .kiq_query_status = gfx10_kiq_query_status, 3629 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs, 3630 .set_resources_size = 8, 3631 .map_queues_size = 7, 3632 .unmap_queues_size = 6, 3633 .query_status_size = 7, 3634 .invalidate_tlbs_size = 2, 3635 }; 3636 3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 3638 { 3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 3640 } 3641 3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev) 3643 { 3644 switch (adev->ip_versions[GC_HWIP][0]) { 3645 case IP_VERSION(10, 1, 10): 3646 soc15_program_register_sequence(adev, 3647 golden_settings_gc_rlc_spm_10_0_nv10, 3648 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10)); 3649 break; 3650 case IP_VERSION(10, 1, 1): 3651 soc15_program_register_sequence(adev, 3652 golden_settings_gc_rlc_spm_10_1_nv14, 3653 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14)); 3654 break; 3655 case IP_VERSION(10, 1, 2): 3656 soc15_program_register_sequence(adev, 3657 golden_settings_gc_rlc_spm_10_1_2_nv12, 3658 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12)); 3659 break; 3660 default: 3661 break; 3662 } 3663 } 3664 3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 3666 { 3667 switch (adev->ip_versions[GC_HWIP][0]) { 3668 case IP_VERSION(10, 1, 10): 3669 soc15_program_register_sequence(adev, 3670 golden_settings_gc_10_1, 3671 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 3672 soc15_program_register_sequence(adev, 3673 golden_settings_gc_10_0_nv10, 3674 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 3675 break; 3676 case IP_VERSION(10, 1, 1): 3677 soc15_program_register_sequence(adev, 3678 golden_settings_gc_10_1_1, 3679 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 3680 soc15_program_register_sequence(adev, 3681 golden_settings_gc_10_1_nv14, 3682 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 3683 break; 3684 case IP_VERSION(10, 1, 2): 3685 soc15_program_register_sequence(adev, 3686 golden_settings_gc_10_1_2, 3687 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2)); 3688 soc15_program_register_sequence(adev, 3689 golden_settings_gc_10_1_2_nv12, 3690 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12)); 3691 break; 3692 case IP_VERSION(10, 3, 0): 3693 soc15_program_register_sequence(adev, 3694 golden_settings_gc_10_3, 3695 (const u32)ARRAY_SIZE(golden_settings_gc_10_3)); 3696 soc15_program_register_sequence(adev, 3697 golden_settings_gc_10_3_sienna_cichlid, 3698 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid)); 3699 break; 3700 case IP_VERSION(10, 3, 2): 3701 soc15_program_register_sequence(adev, 3702 golden_settings_gc_10_3_2, 3703 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2)); 3704 break; 3705 case IP_VERSION(10, 3, 1): 3706 soc15_program_register_sequence(adev, 3707 golden_settings_gc_10_3_vangogh, 3708 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh)); 3709 break; 3710 case IP_VERSION(10, 3, 3): 3711 soc15_program_register_sequence(adev, 3712 golden_settings_gc_10_3_3, 3713 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3)); 3714 break; 3715 case IP_VERSION(10, 3, 4): 3716 soc15_program_register_sequence(adev, 3717 golden_settings_gc_10_3_4, 3718 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4)); 3719 break; 3720 case IP_VERSION(10, 3, 5): 3721 soc15_program_register_sequence(adev, 3722 golden_settings_gc_10_3_5, 3723 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5)); 3724 break; 3725 case IP_VERSION(10, 1, 3): 3726 case IP_VERSION(10, 1, 4): 3727 soc15_program_register_sequence(adev, 3728 golden_settings_gc_10_0_cyan_skillfish, 3729 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish)); 3730 break; 3731 case IP_VERSION(10, 3, 6): 3732 soc15_program_register_sequence(adev, 3733 golden_settings_gc_10_3_6, 3734 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6)); 3735 break; 3736 case IP_VERSION(10, 3, 7): 3737 soc15_program_register_sequence(adev, 3738 golden_settings_gc_10_3_7, 3739 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7)); 3740 break; 3741 default: 3742 break; 3743 } 3744 gfx_v10_0_init_spm_golden_registers(adev); 3745 } 3746 3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 3748 bool wc, uint32_t reg, uint32_t val) 3749 { 3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3751 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 3753 amdgpu_ring_write(ring, reg); 3754 amdgpu_ring_write(ring, 0); 3755 amdgpu_ring_write(ring, val); 3756 } 3757 3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 3759 int mem_space, int opt, uint32_t addr0, 3760 uint32_t addr1, uint32_t ref, uint32_t mask, 3761 uint32_t inv) 3762 { 3763 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 3764 amdgpu_ring_write(ring, 3765 /* memory (1) or register (0) */ 3766 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 3767 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 3768 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 3769 WAIT_REG_MEM_ENGINE(eng_sel))); 3770 3771 if (mem_space) 3772 BUG_ON(addr0 & 0x3); /* Dword align */ 3773 amdgpu_ring_write(ring, addr0); 3774 amdgpu_ring_write(ring, addr1); 3775 amdgpu_ring_write(ring, ref); 3776 amdgpu_ring_write(ring, mask); 3777 amdgpu_ring_write(ring, inv); /* poll interval */ 3778 } 3779 3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 3781 { 3782 struct amdgpu_device *adev = ring->adev; 3783 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 3784 uint32_t tmp = 0; 3785 unsigned i; 3786 int r; 3787 3788 WREG32(scratch, 0xCAFEDEAD); 3789 r = amdgpu_ring_alloc(ring, 3); 3790 if (r) { 3791 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 3792 ring->idx, r); 3793 return r; 3794 } 3795 3796 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 3797 amdgpu_ring_write(ring, scratch - 3798 PACKET3_SET_UCONFIG_REG_START); 3799 amdgpu_ring_write(ring, 0xDEADBEEF); 3800 amdgpu_ring_commit(ring); 3801 3802 for (i = 0; i < adev->usec_timeout; i++) { 3803 tmp = RREG32(scratch); 3804 if (tmp == 0xDEADBEEF) 3805 break; 3806 if (amdgpu_emu_mode == 1) 3807 msleep(1); 3808 else 3809 udelay(1); 3810 } 3811 3812 if (i >= adev->usec_timeout) 3813 r = -ETIMEDOUT; 3814 3815 return r; 3816 } 3817 3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 3819 { 3820 struct amdgpu_device *adev = ring->adev; 3821 struct amdgpu_ib ib; 3822 struct dma_fence *f = NULL; 3823 unsigned index; 3824 uint64_t gpu_addr; 3825 volatile uint32_t *cpu_ptr; 3826 long r; 3827 3828 memset(&ib, 0, sizeof(ib)); 3829 3830 if (ring->is_mes_queue) { 3831 uint32_t padding, offset; 3832 3833 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS); 3834 padding = amdgpu_mes_ctx_get_offs(ring, 3835 AMDGPU_MES_CTX_PADDING_OFFS); 3836 3837 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 3838 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 3839 3840 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding); 3841 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding); 3842 *cpu_ptr = cpu_to_le32(0xCAFEDEAD); 3843 } else { 3844 r = amdgpu_device_wb_get(adev, &index); 3845 if (r) 3846 return r; 3847 3848 gpu_addr = adev->wb.gpu_addr + (index * 4); 3849 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 3850 cpu_ptr = &adev->wb.wb[index]; 3851 3852 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib); 3853 if (r) { 3854 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 3855 goto err1; 3856 } 3857 } 3858 3859 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; 3861 ib.ptr[2] = lower_32_bits(gpu_addr); 3862 ib.ptr[3] = upper_32_bits(gpu_addr); 3863 ib.ptr[4] = 0xDEADBEEF; 3864 ib.length_dw = 5; 3865 3866 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 3867 if (r) 3868 goto err2; 3869 3870 r = dma_fence_wait_timeout(f, false, timeout); 3871 if (r == 0) { 3872 r = -ETIMEDOUT; 3873 goto err2; 3874 } else if (r < 0) { 3875 goto err2; 3876 } 3877 3878 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 3879 r = 0; 3880 else 3881 r = -EINVAL; 3882 err2: 3883 if (!ring->is_mes_queue) 3884 amdgpu_ib_free(adev, &ib, NULL); 3885 dma_fence_put(f); 3886 err1: 3887 if (!ring->is_mes_queue) 3888 amdgpu_device_wb_free(adev, index); 3889 return r; 3890 } 3891 3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 3893 { 3894 release_firmware(adev->gfx.pfp_fw); 3895 adev->gfx.pfp_fw = NULL; 3896 release_firmware(adev->gfx.me_fw); 3897 adev->gfx.me_fw = NULL; 3898 release_firmware(adev->gfx.ce_fw); 3899 adev->gfx.ce_fw = NULL; 3900 release_firmware(adev->gfx.rlc_fw); 3901 adev->gfx.rlc_fw = NULL; 3902 release_firmware(adev->gfx.mec_fw); 3903 adev->gfx.mec_fw = NULL; 3904 release_firmware(adev->gfx.mec2_fw); 3905 adev->gfx.mec2_fw = NULL; 3906 3907 kfree(adev->gfx.rlc.register_list_format); 3908 } 3909 3910 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev) 3911 { 3912 adev->gfx.cp_fw_write_wait = false; 3913 3914 switch (adev->ip_versions[GC_HWIP][0]) { 3915 case IP_VERSION(10, 1, 10): 3916 case IP_VERSION(10, 1, 2): 3917 case IP_VERSION(10, 1, 1): 3918 case IP_VERSION(10, 1, 3): 3919 case IP_VERSION(10, 1, 4): 3920 if ((adev->gfx.me_fw_version >= 0x00000046) && 3921 (adev->gfx.me_feature_version >= 27) && 3922 (adev->gfx.pfp_fw_version >= 0x00000068) && 3923 (adev->gfx.pfp_feature_version >= 27) && 3924 (adev->gfx.mec_fw_version >= 0x0000005b) && 3925 (adev->gfx.mec_feature_version >= 27)) 3926 adev->gfx.cp_fw_write_wait = true; 3927 break; 3928 case IP_VERSION(10, 3, 0): 3929 case IP_VERSION(10, 3, 2): 3930 case IP_VERSION(10, 3, 1): 3931 case IP_VERSION(10, 3, 4): 3932 case IP_VERSION(10, 3, 5): 3933 case IP_VERSION(10, 3, 6): 3934 case IP_VERSION(10, 3, 3): 3935 case IP_VERSION(10, 3, 7): 3936 adev->gfx.cp_fw_write_wait = true; 3937 break; 3938 default: 3939 break; 3940 } 3941 3942 if (!adev->gfx.cp_fw_write_wait) 3943 DRM_WARN_ONCE("CP firmware version too old, please update!"); 3944 } 3945 3946 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) 3947 { 3948 bool ret = false; 3949 3950 switch (adev->pdev->revision) { 3951 case 0xc2: 3952 case 0xc3: 3953 ret = true; 3954 break; 3955 default: 3956 ret = false; 3957 break; 3958 } 3959 3960 return ret ; 3961 } 3962 3963 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 3964 { 3965 switch (adev->ip_versions[GC_HWIP][0]) { 3966 case IP_VERSION(10, 1, 10): 3967 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) 3968 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 3969 break; 3970 default: 3971 break; 3972 } 3973 } 3974 3975 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 3976 { 3977 const char *chip_name; 3978 char fw_name[40]; 3979 char *wks = ""; 3980 int err; 3981 const struct rlc_firmware_header_v2_0 *rlc_hdr; 3982 uint16_t version_major; 3983 uint16_t version_minor; 3984 3985 DRM_DEBUG("\n"); 3986 3987 switch (adev->ip_versions[GC_HWIP][0]) { 3988 case IP_VERSION(10, 1, 10): 3989 chip_name = "navi10"; 3990 break; 3991 case IP_VERSION(10, 1, 1): 3992 chip_name = "navi14"; 3993 if (!(adev->pdev->device == 0x7340 && 3994 adev->pdev->revision != 0x00)) 3995 wks = "_wks"; 3996 break; 3997 case IP_VERSION(10, 1, 2): 3998 chip_name = "navi12"; 3999 break; 4000 case IP_VERSION(10, 3, 0): 4001 chip_name = "sienna_cichlid"; 4002 break; 4003 case IP_VERSION(10, 3, 2): 4004 chip_name = "navy_flounder"; 4005 break; 4006 case IP_VERSION(10, 3, 1): 4007 chip_name = "vangogh"; 4008 break; 4009 case IP_VERSION(10, 3, 4): 4010 chip_name = "dimgrey_cavefish"; 4011 break; 4012 case IP_VERSION(10, 3, 5): 4013 chip_name = "beige_goby"; 4014 break; 4015 case IP_VERSION(10, 3, 3): 4016 chip_name = "yellow_carp"; 4017 break; 4018 case IP_VERSION(10, 3, 6): 4019 chip_name = "gc_10_3_6"; 4020 break; 4021 case IP_VERSION(10, 1, 3): 4022 case IP_VERSION(10, 1, 4): 4023 chip_name = "cyan_skillfish2"; 4024 break; 4025 case IP_VERSION(10, 3, 7): 4026 chip_name = "gc_10_3_7"; 4027 break; 4028 default: 4029 BUG(); 4030 } 4031 4032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks); 4033 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 4034 if (err) 4035 goto out; 4036 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 4037 if (err) 4038 goto out; 4039 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP); 4040 4041 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks); 4042 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 4043 if (err) 4044 goto out; 4045 err = amdgpu_ucode_validate(adev->gfx.me_fw); 4046 if (err) 4047 goto out; 4048 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME); 4049 4050 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks); 4051 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 4052 if (err) 4053 goto out; 4054 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 4055 if (err) 4056 goto out; 4057 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); 4058 4059 if (!amdgpu_sriov_vf(adev)) { 4060 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 4061 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 4062 if (err) 4063 goto out; 4064 /* don't check this. There are apparently firmwares in the wild with 4065 * incorrect size in the header 4066 */ 4067 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 4068 if (err) 4069 dev_dbg(adev->dev, 4070 "gfx10: amdgpu_ucode_validate() failed \"%s\"\n", 4071 fw_name); 4072 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 4073 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 4074 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 4075 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 4076 if (err) 4077 goto out; 4078 } 4079 4080 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks); 4081 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 4082 if (err) 4083 goto out; 4084 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 4085 if (err) 4086 goto out; 4087 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1); 4088 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT); 4089 4090 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks); 4091 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 4092 if (!err) { 4093 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 4094 if (err) 4095 goto out; 4096 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2); 4097 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT); 4098 } else { 4099 err = 0; 4100 adev->gfx.mec2_fw = NULL; 4101 } 4102 4103 gfx_v10_0_check_fw_write_wait(adev); 4104 out: 4105 if (err) { 4106 dev_err(adev->dev, 4107 "gfx10: Failed to init firmware \"%s\"\n", 4108 fw_name); 4109 release_firmware(adev->gfx.pfp_fw); 4110 adev->gfx.pfp_fw = NULL; 4111 release_firmware(adev->gfx.me_fw); 4112 adev->gfx.me_fw = NULL; 4113 release_firmware(adev->gfx.ce_fw); 4114 adev->gfx.ce_fw = NULL; 4115 release_firmware(adev->gfx.rlc_fw); 4116 adev->gfx.rlc_fw = NULL; 4117 release_firmware(adev->gfx.mec_fw); 4118 adev->gfx.mec_fw = NULL; 4119 release_firmware(adev->gfx.mec2_fw); 4120 adev->gfx.mec2_fw = NULL; 4121 } 4122 4123 gfx_v10_0_check_gfxoff_flag(adev); 4124 4125 return err; 4126 } 4127 4128 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 4129 { 4130 u32 count = 0; 4131 const struct cs_section_def *sect = NULL; 4132 const struct cs_extent_def *ext = NULL; 4133 4134 /* begin clear state */ 4135 count += 2; 4136 /* context control state */ 4137 count += 3; 4138 4139 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 4140 for (ext = sect->section; ext->extent != NULL; ++ext) { 4141 if (sect->id == SECT_CONTEXT) 4142 count += 2 + ext->reg_count; 4143 else 4144 return 0; 4145 } 4146 } 4147 4148 /* set PA_SC_TILE_STEERING_OVERRIDE */ 4149 count += 3; 4150 /* end clear state */ 4151 count += 2; 4152 /* clear state */ 4153 count += 2; 4154 4155 return count; 4156 } 4157 4158 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 4159 volatile u32 *buffer) 4160 { 4161 u32 count = 0, i; 4162 const struct cs_section_def *sect = NULL; 4163 const struct cs_extent_def *ext = NULL; 4164 int ctx_reg_offset; 4165 4166 if (adev->gfx.rlc.cs_data == NULL) 4167 return; 4168 if (buffer == NULL) 4169 return; 4170 4171 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4172 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 4173 4174 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4175 buffer[count++] = cpu_to_le32(0x80000000); 4176 buffer[count++] = cpu_to_le32(0x80000000); 4177 4178 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 4179 for (ext = sect->section; ext->extent != NULL; ++ext) { 4180 if (sect->id == SECT_CONTEXT) { 4181 buffer[count++] = 4182 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 4183 buffer[count++] = cpu_to_le32(ext->reg_index - 4184 PACKET3_SET_CONTEXT_REG_START); 4185 for (i = 0; i < ext->reg_count; i++) 4186 buffer[count++] = cpu_to_le32(ext->extent[i]); 4187 } else { 4188 return; 4189 } 4190 } 4191 } 4192 4193 ctx_reg_offset = 4194 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 4195 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 4196 buffer[count++] = cpu_to_le32(ctx_reg_offset); 4197 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 4198 4199 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 4200 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 4201 4202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 4203 buffer[count++] = cpu_to_le32(0); 4204 } 4205 4206 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 4207 { 4208 /* clear state block */ 4209 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 4210 &adev->gfx.rlc.clear_state_gpu_addr, 4211 (void **)&adev->gfx.rlc.cs_ptr); 4212 4213 /* jump table block */ 4214 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 4215 &adev->gfx.rlc.cp_table_gpu_addr, 4216 (void **)&adev->gfx.rlc.cp_table_ptr); 4217 } 4218 4219 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 4220 { 4221 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 4222 4223 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl; 4224 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 4225 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); 4226 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); 4227 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); 4228 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); 4229 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); 4230 switch (adev->ip_versions[GC_HWIP][0]) { 4231 case IP_VERSION(10, 3, 0): 4232 reg_access_ctrl->spare_int = 4233 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid); 4234 break; 4235 default: 4236 reg_access_ctrl->spare_int = 4237 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); 4238 break; 4239 } 4240 adev->gfx.rlc.rlcg_reg_access_supported = true; 4241 } 4242 4243 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 4244 { 4245 const struct cs_section_def *cs_data; 4246 int r; 4247 4248 adev->gfx.rlc.cs_data = gfx10_cs_data; 4249 4250 cs_data = adev->gfx.rlc.cs_data; 4251 4252 if (cs_data) { 4253 /* init clear state block */ 4254 r = amdgpu_gfx_rlc_init_csb(adev); 4255 if (r) 4256 return r; 4257 } 4258 4259 /* init spm vmid with 0xf */ 4260 if (adev->gfx.rlc.funcs->update_spm_vmid) 4261 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); 4262 4263 4264 return 0; 4265 } 4266 4267 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 4268 { 4269 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 4270 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 4271 } 4272 4273 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 4274 { 4275 int r; 4276 4277 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 4278 4279 amdgpu_gfx_graphics_queue_acquire(adev); 4280 4281 r = gfx_v10_0_init_microcode(adev); 4282 if (r) 4283 DRM_ERROR("Failed to load gfx firmware!\n"); 4284 4285 return r; 4286 } 4287 4288 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 4289 { 4290 int r; 4291 u32 *hpd; 4292 const __le32 *fw_data = NULL; 4293 unsigned fw_size; 4294 u32 *fw = NULL; 4295 size_t mec_hpd_size; 4296 4297 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 4298 4299 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 4300 4301 /* take ownership of the relevant compute queues */ 4302 amdgpu_gfx_compute_queue_acquire(adev); 4303 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 4304 4305 if (mec_hpd_size) { 4306 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 4307 AMDGPU_GEM_DOMAIN_GTT, 4308 &adev->gfx.mec.hpd_eop_obj, 4309 &adev->gfx.mec.hpd_eop_gpu_addr, 4310 (void **)&hpd); 4311 if (r) { 4312 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 4313 gfx_v10_0_mec_fini(adev); 4314 return r; 4315 } 4316 4317 memset(hpd, 0, mec_hpd_size); 4318 4319 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 4320 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 4321 } 4322 4323 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 4324 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 4325 4326 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 4327 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 4328 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 4329 4330 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 4331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 4332 &adev->gfx.mec.mec_fw_obj, 4333 &adev->gfx.mec.mec_fw_gpu_addr, 4334 (void **)&fw); 4335 if (r) { 4336 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 4337 gfx_v10_0_mec_fini(adev); 4338 return r; 4339 } 4340 4341 memcpy(fw, fw_data, fw_size); 4342 4343 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 4344 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 4345 } 4346 4347 return 0; 4348 } 4349 4350 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 4351 { 4352 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4353 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4354 (address << SQ_IND_INDEX__INDEX__SHIFT)); 4355 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4356 } 4357 4358 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 4359 uint32_t thread, uint32_t regno, 4360 uint32_t num, uint32_t *out) 4361 { 4362 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 4363 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 4364 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 4365 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 4366 (SQ_IND_INDEX__AUTO_INCR_MASK)); 4367 while (num--) 4368 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 4369 } 4370 4371 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 4372 { 4373 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 4374 * field when performing a select_se_sh so it should be 4375 * zero here */ 4376 WARN_ON(simd != 0); 4377 4378 /* type 2 wave data */ 4379 dst[(*no_fields)++] = 2; 4380 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 4381 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 4382 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 4383 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 4384 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 4385 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 4386 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 4387 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 4388 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 4389 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 4390 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 4391 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 4392 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 4393 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 4394 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 4395 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE); 4396 } 4397 4398 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 4399 uint32_t wave, uint32_t start, 4400 uint32_t size, uint32_t *dst) 4401 { 4402 WARN_ON(simd != 0); 4403 4404 wave_read_regs( 4405 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 4406 dst); 4407 } 4408 4409 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 4410 uint32_t wave, uint32_t thread, 4411 uint32_t start, uint32_t size, 4412 uint32_t *dst) 4413 { 4414 wave_read_regs( 4415 adev, wave, thread, 4416 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 4417 } 4418 4419 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 4420 u32 me, u32 pipe, u32 q, u32 vm) 4421 { 4422 nv_grbm_select(adev, me, pipe, q, vm); 4423 } 4424 4425 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev, 4426 bool enable) 4427 { 4428 uint32_t data, def; 4429 4430 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL); 4431 4432 if (enable) 4433 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4434 else 4435 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK; 4436 4437 if (data != def) 4438 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data); 4439 } 4440 4441 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 4442 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 4443 .select_se_sh = &gfx_v10_0_select_se_sh, 4444 .read_wave_data = &gfx_v10_0_read_wave_data, 4445 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 4446 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 4447 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 4448 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers, 4449 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg, 4450 }; 4451 4452 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 4453 { 4454 u32 gb_addr_config; 4455 4456 switch (adev->ip_versions[GC_HWIP][0]) { 4457 case IP_VERSION(10, 1, 10): 4458 case IP_VERSION(10, 1, 1): 4459 case IP_VERSION(10, 1, 2): 4460 adev->gfx.config.max_hw_contexts = 8; 4461 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4462 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4463 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4464 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4465 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4466 break; 4467 case IP_VERSION(10, 3, 0): 4468 case IP_VERSION(10, 3, 2): 4469 case IP_VERSION(10, 3, 1): 4470 case IP_VERSION(10, 3, 4): 4471 case IP_VERSION(10, 3, 5): 4472 case IP_VERSION(10, 3, 6): 4473 case IP_VERSION(10, 3, 3): 4474 case IP_VERSION(10, 3, 7): 4475 adev->gfx.config.max_hw_contexts = 8; 4476 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4477 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4478 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 4479 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4480 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 4481 adev->gfx.config.gb_addr_config_fields.num_pkrs = 4482 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS); 4483 break; 4484 case IP_VERSION(10, 1, 3): 4485 case IP_VERSION(10, 1, 4): 4486 adev->gfx.config.max_hw_contexts = 8; 4487 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 4488 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 4489 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; 4490 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 4491 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN; 4492 break; 4493 default: 4494 BUG(); 4495 break; 4496 } 4497 4498 adev->gfx.config.gb_addr_config = gb_addr_config; 4499 4500 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 4501 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4502 GB_ADDR_CONFIG, NUM_PIPES); 4503 4504 adev->gfx.config.max_tile_pipes = 4505 adev->gfx.config.gb_addr_config_fields.num_pipes; 4506 4507 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 4508 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4509 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 4510 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 4511 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4512 GB_ADDR_CONFIG, NUM_RB_PER_SE); 4513 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 4514 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4515 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 4516 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 4517 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 4518 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 4519 } 4520 4521 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 4522 int me, int pipe, int queue) 4523 { 4524 struct amdgpu_ring *ring; 4525 unsigned int irq_type; 4526 unsigned int hw_prio; 4527 4528 ring = &adev->gfx.gfx_ring[ring_id]; 4529 4530 ring->me = me; 4531 ring->pipe = pipe; 4532 ring->queue = queue; 4533 4534 ring->ring_obj = NULL; 4535 ring->use_doorbell = true; 4536 4537 if (!ring_id) 4538 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 4539 else 4540 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 4541 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4542 4543 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 4544 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ? 4545 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 4546 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4547 hw_prio, NULL); 4548 } 4549 4550 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 4551 int mec, int pipe, int queue) 4552 { 4553 unsigned irq_type; 4554 struct amdgpu_ring *ring; 4555 unsigned int hw_prio; 4556 4557 ring = &adev->gfx.compute_ring[ring_id]; 4558 4559 /* mec0 is me1 */ 4560 ring->me = mec + 1; 4561 ring->pipe = pipe; 4562 ring->queue = queue; 4563 4564 ring->ring_obj = NULL; 4565 ring->use_doorbell = true; 4566 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 4567 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 4568 + (ring_id * GFX10_MEC_HPD_SIZE); 4569 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 4570 4571 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 4572 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 4573 + ring->pipe; 4574 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 4575 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT; 4576 /* type-2 packets are deprecated on MEC, use type-3 instead */ 4577 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 4578 hw_prio, NULL); 4579 } 4580 4581 static int gfx_v10_0_sw_init(void *handle) 4582 { 4583 int i, j, k, r, ring_id = 0; 4584 struct amdgpu_kiq *kiq; 4585 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4586 4587 switch (adev->ip_versions[GC_HWIP][0]) { 4588 case IP_VERSION(10, 1, 10): 4589 case IP_VERSION(10, 1, 1): 4590 case IP_VERSION(10, 1, 2): 4591 case IP_VERSION(10, 1, 3): 4592 case IP_VERSION(10, 1, 4): 4593 adev->gfx.me.num_me = 1; 4594 adev->gfx.me.num_pipe_per_me = 1; 4595 adev->gfx.me.num_queue_per_pipe = 1; 4596 adev->gfx.mec.num_mec = 2; 4597 adev->gfx.mec.num_pipe_per_mec = 4; 4598 adev->gfx.mec.num_queue_per_pipe = 8; 4599 break; 4600 case IP_VERSION(10, 3, 0): 4601 case IP_VERSION(10, 3, 2): 4602 case IP_VERSION(10, 3, 1): 4603 case IP_VERSION(10, 3, 4): 4604 case IP_VERSION(10, 3, 5): 4605 case IP_VERSION(10, 3, 6): 4606 case IP_VERSION(10, 3, 3): 4607 case IP_VERSION(10, 3, 7): 4608 adev->gfx.me.num_me = 1; 4609 adev->gfx.me.num_pipe_per_me = 1; 4610 adev->gfx.me.num_queue_per_pipe = 1; 4611 adev->gfx.mec.num_mec = 2; 4612 adev->gfx.mec.num_pipe_per_mec = 4; 4613 adev->gfx.mec.num_queue_per_pipe = 4; 4614 break; 4615 default: 4616 adev->gfx.me.num_me = 1; 4617 adev->gfx.me.num_pipe_per_me = 1; 4618 adev->gfx.me.num_queue_per_pipe = 1; 4619 adev->gfx.mec.num_mec = 1; 4620 adev->gfx.mec.num_pipe_per_mec = 4; 4621 adev->gfx.mec.num_queue_per_pipe = 8; 4622 break; 4623 } 4624 4625 /* KIQ event */ 4626 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4627 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 4628 &adev->gfx.kiq.irq); 4629 if (r) 4630 return r; 4631 4632 /* EOP Event */ 4633 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 4634 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 4635 &adev->gfx.eop_irq); 4636 if (r) 4637 return r; 4638 4639 /* Privileged reg */ 4640 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 4641 &adev->gfx.priv_reg_irq); 4642 if (r) 4643 return r; 4644 4645 /* Privileged inst */ 4646 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 4647 &adev->gfx.priv_inst_irq); 4648 if (r) 4649 return r; 4650 4651 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 4652 4653 r = gfx_v10_0_me_init(adev); 4654 if (r) 4655 return r; 4656 4657 if (adev->gfx.rlc.funcs) { 4658 if (adev->gfx.rlc.funcs->init) { 4659 r = adev->gfx.rlc.funcs->init(adev); 4660 if (r) { 4661 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 4662 return r; 4663 } 4664 } 4665 } 4666 4667 r = gfx_v10_0_mec_init(adev); 4668 if (r) { 4669 DRM_ERROR("Failed to init MEC BOs!\n"); 4670 return r; 4671 } 4672 4673 /* set up the gfx ring */ 4674 for (i = 0; i < adev->gfx.me.num_me; i++) { 4675 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 4676 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 4677 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 4678 continue; 4679 4680 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 4681 i, k, j); 4682 if (r) 4683 return r; 4684 ring_id++; 4685 } 4686 } 4687 } 4688 4689 ring_id = 0; 4690 /* set up the compute queues - allocate horizontally across pipes */ 4691 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 4692 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 4693 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 4694 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 4695 j)) 4696 continue; 4697 4698 r = gfx_v10_0_compute_ring_init(adev, ring_id, 4699 i, k, j); 4700 if (r) 4701 return r; 4702 4703 ring_id++; 4704 } 4705 } 4706 } 4707 4708 if (!adev->enable_mes_kiq) { 4709 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 4710 if (r) { 4711 DRM_ERROR("Failed to init KIQ BOs!\n"); 4712 return r; 4713 } 4714 4715 kiq = &adev->gfx.kiq; 4716 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 4717 if (r) 4718 return r; 4719 } 4720 4721 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 4722 if (r) 4723 return r; 4724 4725 /* allocate visible FB for rlc auto-loading fw */ 4726 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 4727 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 4728 if (r) 4729 return r; 4730 } 4731 4732 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 4733 4734 gfx_v10_0_gpu_early_init(adev); 4735 4736 return 0; 4737 } 4738 4739 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 4740 { 4741 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 4742 &adev->gfx.pfp.pfp_fw_gpu_addr, 4743 (void **)&adev->gfx.pfp.pfp_fw_ptr); 4744 } 4745 4746 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 4747 { 4748 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 4749 &adev->gfx.ce.ce_fw_gpu_addr, 4750 (void **)&adev->gfx.ce.ce_fw_ptr); 4751 } 4752 4753 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 4754 { 4755 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 4756 &adev->gfx.me.me_fw_gpu_addr, 4757 (void **)&adev->gfx.me.me_fw_ptr); 4758 } 4759 4760 static int gfx_v10_0_sw_fini(void *handle) 4761 { 4762 int i; 4763 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4764 4765 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 4766 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 4767 for (i = 0; i < adev->gfx.num_compute_rings; i++) 4768 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 4769 4770 amdgpu_gfx_mqd_sw_fini(adev); 4771 4772 if (!adev->enable_mes_kiq) { 4773 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring); 4774 amdgpu_gfx_kiq_fini(adev); 4775 } 4776 4777 gfx_v10_0_pfp_fini(adev); 4778 gfx_v10_0_ce_fini(adev); 4779 gfx_v10_0_me_fini(adev); 4780 gfx_v10_0_rlc_fini(adev); 4781 gfx_v10_0_mec_fini(adev); 4782 4783 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 4784 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 4785 4786 gfx_v10_0_free_microcode(adev); 4787 4788 return 0; 4789 } 4790 4791 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 4792 u32 sh_num, u32 instance) 4793 { 4794 u32 data; 4795 4796 if (instance == 0xffffffff) 4797 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 4798 INSTANCE_BROADCAST_WRITES, 1); 4799 else 4800 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 4801 instance); 4802 4803 if (se_num == 0xffffffff) 4804 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 4805 1); 4806 else 4807 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 4808 4809 if (sh_num == 0xffffffff) 4810 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 4811 1); 4812 else 4813 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 4814 4815 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 4816 } 4817 4818 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 4819 { 4820 u32 data, mask; 4821 4822 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 4823 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 4824 4825 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 4826 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 4827 4828 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 4829 adev->gfx.config.max_sh_per_se); 4830 4831 return (~data) & mask; 4832 } 4833 4834 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 4835 { 4836 int i, j; 4837 u32 data; 4838 u32 active_rbs = 0; 4839 u32 bitmap; 4840 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 4841 adev->gfx.config.max_sh_per_se; 4842 4843 mutex_lock(&adev->grbm_idx_mutex); 4844 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4845 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4846 bitmap = i * adev->gfx.config.max_sh_per_se + j; 4847 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 4848 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 4849 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) && 4850 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 4851 continue; 4852 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4853 data = gfx_v10_0_get_rb_active_bitmap(adev); 4854 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 4855 rb_bitmap_width_per_sh); 4856 } 4857 } 4858 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 4859 mutex_unlock(&adev->grbm_idx_mutex); 4860 4861 adev->gfx.config.backend_enable_mask = active_rbs; 4862 adev->gfx.config.num_rbs = hweight32(active_rbs); 4863 } 4864 4865 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 4866 { 4867 uint32_t num_sc; 4868 uint32_t enabled_rb_per_sh; 4869 uint32_t active_rb_bitmap; 4870 uint32_t num_rb_per_sc; 4871 uint32_t num_packer_per_sc; 4872 uint32_t pa_sc_tile_steering_override; 4873 4874 /* for ASICs that integrates GFX v10.3 4875 * pa_sc_tile_steering_override should be set to 0 */ 4876 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 4877 return 0; 4878 4879 /* init num_sc */ 4880 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 4881 adev->gfx.config.num_sc_per_sh; 4882 /* init num_rb_per_sc */ 4883 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 4884 enabled_rb_per_sh = hweight32(active_rb_bitmap); 4885 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 4886 /* init num_packer_per_sc */ 4887 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 4888 4889 pa_sc_tile_steering_override = 0; 4890 pa_sc_tile_steering_override |= 4891 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 4892 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 4893 pa_sc_tile_steering_override |= 4894 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 4895 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 4896 pa_sc_tile_steering_override |= 4897 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 4898 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 4899 4900 return pa_sc_tile_steering_override; 4901 } 4902 4903 #define DEFAULT_SH_MEM_BASES (0x6000) 4904 4905 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 4906 { 4907 int i; 4908 uint32_t sh_mem_bases; 4909 4910 /* 4911 * Configure apertures: 4912 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 4913 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 4914 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 4915 */ 4916 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 4917 4918 mutex_lock(&adev->srbm_mutex); 4919 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4920 nv_grbm_select(adev, 0, 0, 0, i); 4921 /* CP and shaders */ 4922 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 4923 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 4924 } 4925 nv_grbm_select(adev, 0, 0, 0, 0); 4926 mutex_unlock(&adev->srbm_mutex); 4927 4928 /* Initialize all compute VMIDs to have no GDS, GWS, or OA 4929 access. These should be enabled by FW for target VMIDs. */ 4930 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 4931 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0); 4932 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0); 4933 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0); 4934 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0); 4935 } 4936 } 4937 4938 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 4939 { 4940 int vmid; 4941 4942 /* 4943 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 4944 * access. Compute VMIDs should be enabled by FW for target VMIDs, 4945 * the driver can enable them for graphics. VMID0 should maintain 4946 * access so that HWS firmware can save/restore entries. 4947 */ 4948 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) { 4949 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 4950 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 4951 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 4952 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 4953 } 4954 } 4955 4956 4957 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 4958 { 4959 int i, j, k; 4960 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 4961 u32 tmp, wgp_active_bitmap = 0; 4962 u32 gcrd_targets_disable_tcp = 0; 4963 u32 utcl_invreq_disable = 0; 4964 /* 4965 * GCRD_TARGETS_DISABLE field contains 4966 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 4967 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 4968 */ 4969 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 4970 2 * max_wgp_per_sh + /* TCP */ 4971 max_wgp_per_sh + /* SQC */ 4972 4); /* GL1C */ 4973 /* 4974 * UTCL1_UTCL0_INVREQ_DISABLE field contains 4975 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 4976 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 4977 */ 4978 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 4979 2 * max_wgp_per_sh + /* TCP */ 4980 2 * max_wgp_per_sh + /* SQC */ 4981 4 + /* RMI */ 4982 1); /* SQG */ 4983 4984 mutex_lock(&adev->grbm_idx_mutex); 4985 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 4986 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 4987 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 4988 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 4989 /* 4990 * Set corresponding TCP bits for the inactive WGPs in 4991 * GCRD_SA_TARGETS_DISABLE 4992 */ 4993 gcrd_targets_disable_tcp = 0; 4994 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 4995 utcl_invreq_disable = 0; 4996 4997 for (k = 0; k < max_wgp_per_sh; k++) { 4998 if (!(wgp_active_bitmap & (1 << k))) { 4999 gcrd_targets_disable_tcp |= 3 << (2 * k); 5000 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2)); 5001 utcl_invreq_disable |= (3 << (2 * k)) | 5002 (3 << (2 * (max_wgp_per_sh + k))); 5003 } 5004 } 5005 5006 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 5007 /* only override TCP & SQC bits */ 5008 tmp &= (0xffffffffU << (4 * max_wgp_per_sh)); 5009 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 5010 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 5011 5012 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 5013 /* only override TCP & SQC bits */ 5014 tmp &= (0xffffffffU << (3 * max_wgp_per_sh)); 5015 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 5016 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 5017 } 5018 } 5019 5020 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5021 mutex_unlock(&adev->grbm_idx_mutex); 5022 } 5023 5024 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev) 5025 { 5026 /* TCCs are global (not instanced). */ 5027 uint32_t tcc_disable; 5028 5029 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 5030 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) | 5031 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3); 5032 } else { 5033 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) | 5034 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE); 5035 } 5036 5037 adev->gfx.config.tcc_disabled_mask = 5038 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) | 5039 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16); 5040 } 5041 5042 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 5043 { 5044 u32 tmp; 5045 int i; 5046 5047 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 5048 5049 gfx_v10_0_setup_rb(adev); 5050 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 5051 gfx_v10_0_get_tcc_info(adev); 5052 adev->gfx.config.pa_sc_tile_steering_override = 5053 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 5054 5055 /* XXX SH_MEM regs */ 5056 /* where to put LDS, scratch, GPUVM in FSA64 space */ 5057 mutex_lock(&adev->srbm_mutex); 5058 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 5059 nv_grbm_select(adev, 0, 0, 0, i); 5060 /* CP and shaders */ 5061 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 5062 if (i != 0) { 5063 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 5064 (adev->gmc.private_aperture_start >> 48)); 5065 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 5066 (adev->gmc.shared_aperture_start >> 48)); 5067 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 5068 } 5069 } 5070 nv_grbm_select(adev, 0, 0, 0, 0); 5071 5072 mutex_unlock(&adev->srbm_mutex); 5073 5074 gfx_v10_0_init_compute_vmid(adev); 5075 gfx_v10_0_init_gds_vmid(adev); 5076 5077 } 5078 5079 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 5080 bool enable) 5081 { 5082 u32 tmp; 5083 5084 if (amdgpu_sriov_vf(adev)) 5085 return; 5086 5087 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 5088 5089 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 5090 enable ? 1 : 0); 5091 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 5092 enable ? 1 : 0); 5093 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 5094 enable ? 1 : 0); 5095 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 5096 enable ? 1 : 0); 5097 5098 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 5099 } 5100 5101 static int gfx_v10_0_init_csb(struct amdgpu_device *adev) 5102 { 5103 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 5104 5105 /* csib */ 5106 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5107 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI, 5108 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5109 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO, 5110 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5111 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5112 } else { 5113 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 5114 adev->gfx.rlc.clear_state_gpu_addr >> 32); 5115 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 5116 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 5117 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 5118 } 5119 return 0; 5120 } 5121 5122 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 5123 { 5124 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5125 5126 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 5127 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 5128 } 5129 5130 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 5131 { 5132 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 5133 udelay(50); 5134 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 5135 udelay(50); 5136 } 5137 5138 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 5139 bool enable) 5140 { 5141 uint32_t rlc_pg_cntl; 5142 5143 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 5144 5145 if (!enable) { 5146 /* RLC_PG_CNTL[23] = 0 (default) 5147 * RLC will wait for handshake acks with SMU 5148 * GFXOFF will be enabled 5149 * RLC_PG_CNTL[23] = 1 5150 * RLC will not issue any message to SMU 5151 * hence no handshake between SMU & RLC 5152 * GFXOFF will be disabled 5153 */ 5154 rlc_pg_cntl |= 0x800000; 5155 } else 5156 rlc_pg_cntl &= ~0x800000; 5157 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 5158 } 5159 5160 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 5161 { 5162 /* TODO: enable rlc & smu handshake until smu 5163 * and gfxoff feature works as expected */ 5164 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 5165 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 5166 5167 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 5168 udelay(50); 5169 } 5170 5171 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 5172 { 5173 uint32_t tmp; 5174 5175 /* enable Save Restore Machine */ 5176 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL); 5177 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 5178 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 5179 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp); 5180 } 5181 5182 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 5183 { 5184 const struct rlc_firmware_header_v2_0 *hdr; 5185 const __le32 *fw_data; 5186 unsigned i, fw_size; 5187 5188 if (!adev->gfx.rlc_fw) 5189 return -EINVAL; 5190 5191 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 5192 amdgpu_ucode_print_rlc_hdr(&hdr->header); 5193 5194 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5195 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 5196 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 5197 5198 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 5199 RLCG_UCODE_LOADING_START_ADDRESS); 5200 5201 for (i = 0; i < fw_size; i++) 5202 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 5203 le32_to_cpup(fw_data++)); 5204 5205 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 5206 5207 return 0; 5208 } 5209 5210 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 5211 { 5212 int r; 5213 5214 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && 5215 adev->psp.autoload_supported) { 5216 5217 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5218 if (r) 5219 return r; 5220 5221 gfx_v10_0_init_csb(adev); 5222 5223 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 5224 gfx_v10_0_rlc_enable_srm(adev); 5225 } else { 5226 if (amdgpu_sriov_vf(adev)) { 5227 gfx_v10_0_init_csb(adev); 5228 return 0; 5229 } 5230 5231 adev->gfx.rlc.funcs->stop(adev); 5232 5233 /* disable CG */ 5234 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 5235 5236 /* disable PG */ 5237 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 5238 5239 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 5240 /* legacy rlc firmware loading */ 5241 r = gfx_v10_0_rlc_load_microcode(adev); 5242 if (r) 5243 return r; 5244 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5245 /* rlc backdoor autoload firmware */ 5246 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 5247 if (r) 5248 return r; 5249 } 5250 5251 gfx_v10_0_init_csb(adev); 5252 5253 adev->gfx.rlc.funcs->start(adev); 5254 5255 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5256 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 5257 if (r) 5258 return r; 5259 } 5260 } 5261 return 0; 5262 } 5263 5264 static struct { 5265 FIRMWARE_ID id; 5266 unsigned int offset; 5267 unsigned int size; 5268 } rlc_autoload_info[FIRMWARE_ID_MAX]; 5269 5270 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 5271 { 5272 int ret; 5273 RLC_TABLE_OF_CONTENT *rlc_toc; 5274 5275 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE, 5276 AMDGPU_GEM_DOMAIN_GTT, 5277 &adev->gfx.rlc.rlc_toc_bo, 5278 &adev->gfx.rlc.rlc_toc_gpu_addr, 5279 (void **)&adev->gfx.rlc.rlc_toc_buf); 5280 if (ret) { 5281 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 5282 return ret; 5283 } 5284 5285 /* Copy toc from psp sos fw to rlc toc buffer */ 5286 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes); 5287 5288 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 5289 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 5290 (rlc_toc->id < FIRMWARE_ID_MAX)) { 5291 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 5292 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 5293 /* Offset needs 4KB alignment */ 5294 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 5295 } 5296 5297 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 5298 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 5299 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 5300 5301 rlc_toc++; 5302 } 5303 5304 return 0; 5305 } 5306 5307 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 5308 { 5309 uint32_t total_size = 0; 5310 FIRMWARE_ID id; 5311 int ret; 5312 5313 ret = gfx_v10_0_parse_rlc_toc(adev); 5314 if (ret) { 5315 dev_err(adev->dev, "failed to parse rlc toc\n"); 5316 return 0; 5317 } 5318 5319 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 5320 total_size += rlc_autoload_info[id].size; 5321 5322 /* In case the offset in rlc toc ucode is aligned */ 5323 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 5324 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 5325 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 5326 5327 return total_size; 5328 } 5329 5330 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 5331 { 5332 int r; 5333 uint32_t total_size; 5334 5335 total_size = gfx_v10_0_calc_toc_total_size(adev); 5336 5337 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 5338 AMDGPU_GEM_DOMAIN_GTT, 5339 &adev->gfx.rlc.rlc_autoload_bo, 5340 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5341 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5342 if (r) { 5343 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 5344 return r; 5345 } 5346 5347 return 0; 5348 } 5349 5350 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 5351 { 5352 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 5353 &adev->gfx.rlc.rlc_toc_gpu_addr, 5354 (void **)&adev->gfx.rlc.rlc_toc_buf); 5355 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 5356 &adev->gfx.rlc.rlc_autoload_gpu_addr, 5357 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 5358 } 5359 5360 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 5361 FIRMWARE_ID id, 5362 const void *fw_data, 5363 uint32_t fw_size) 5364 { 5365 uint32_t toc_offset; 5366 uint32_t toc_fw_size; 5367 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 5368 5369 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 5370 return; 5371 5372 toc_offset = rlc_autoload_info[id].offset; 5373 toc_fw_size = rlc_autoload_info[id].size; 5374 5375 if (fw_size == 0) 5376 fw_size = toc_fw_size; 5377 5378 if (fw_size > toc_fw_size) 5379 fw_size = toc_fw_size; 5380 5381 memcpy(ptr + toc_offset, fw_data, fw_size); 5382 5383 if (fw_size < toc_fw_size) 5384 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 5385 } 5386 5387 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 5388 { 5389 void *data; 5390 uint32_t size; 5391 5392 data = adev->gfx.rlc.rlc_toc_buf; 5393 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 5394 5395 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5396 FIRMWARE_ID_RLC_TOC, 5397 data, size); 5398 } 5399 5400 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 5401 { 5402 const __le32 *fw_data; 5403 uint32_t fw_size; 5404 const struct gfx_firmware_header_v1_0 *cp_hdr; 5405 const struct rlc_firmware_header_v2_0 *rlc_hdr; 5406 5407 /* pfp ucode */ 5408 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5409 adev->gfx.pfp_fw->data; 5410 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5411 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5412 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5413 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5414 FIRMWARE_ID_CP_PFP, 5415 fw_data, fw_size); 5416 5417 /* ce ucode */ 5418 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5419 adev->gfx.ce_fw->data; 5420 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5421 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5422 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5423 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5424 FIRMWARE_ID_CP_CE, 5425 fw_data, fw_size); 5426 5427 /* me ucode */ 5428 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5429 adev->gfx.me_fw->data; 5430 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5431 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5432 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 5433 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5434 FIRMWARE_ID_CP_ME, 5435 fw_data, fw_size); 5436 5437 /* rlc ucode */ 5438 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 5439 adev->gfx.rlc_fw->data; 5440 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 5441 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 5442 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 5443 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5444 FIRMWARE_ID_RLC_G_UCODE, 5445 fw_data, fw_size); 5446 5447 /* mec1 ucode */ 5448 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 5449 adev->gfx.mec_fw->data; 5450 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 5451 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 5452 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 5453 cp_hdr->jt_size * 4; 5454 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5455 FIRMWARE_ID_CP_MEC, 5456 fw_data, fw_size); 5457 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 5458 } 5459 5460 /* Temporarily put sdma part here */ 5461 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 5462 { 5463 const __le32 *fw_data; 5464 uint32_t fw_size; 5465 const struct sdma_firmware_header_v1_0 *sdma_hdr; 5466 int i; 5467 5468 for (i = 0; i < adev->sdma.num_instances; i++) { 5469 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 5470 adev->sdma.instance[i].fw->data; 5471 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 5472 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 5473 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 5474 5475 if (i == 0) { 5476 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5477 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 5478 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5479 FIRMWARE_ID_SDMA0_JT, 5480 (uint32_t *)fw_data + 5481 sdma_hdr->jt_offset, 5482 sdma_hdr->jt_size * 4); 5483 } else if (i == 1) { 5484 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5485 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 5486 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 5487 FIRMWARE_ID_SDMA1_JT, 5488 (uint32_t *)fw_data + 5489 sdma_hdr->jt_offset, 5490 sdma_hdr->jt_size * 4); 5491 } 5492 } 5493 } 5494 5495 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 5496 { 5497 uint32_t rlc_g_offset, rlc_g_size, tmp; 5498 uint64_t gpu_addr; 5499 5500 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 5501 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 5502 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 5503 5504 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 5505 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 5506 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 5507 5508 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 5509 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 5510 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 5511 5512 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 5513 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 5514 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 5515 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 5516 return -EINVAL; 5517 } 5518 5519 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 5520 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 5521 DRM_ERROR("RLC ROM should halt itself\n"); 5522 return -EINVAL; 5523 } 5524 5525 return 0; 5526 } 5527 5528 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 5529 { 5530 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5531 uint32_t tmp; 5532 int i; 5533 uint64_t addr; 5534 5535 /* Trigger an invalidation of the L1 instruction caches */ 5536 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5537 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5538 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5539 5540 /* Wait for invalidation complete */ 5541 for (i = 0; i < usec_timeout; i++) { 5542 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5543 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5544 INVALIDATE_CACHE_COMPLETE)) 5545 break; 5546 udelay(1); 5547 } 5548 5549 if (i >= usec_timeout) { 5550 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5551 return -EINVAL; 5552 } 5553 5554 /* Program me ucode address into intruction cache address register */ 5555 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5556 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 5557 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5558 lower_32_bits(addr) & 0xFFFFF000); 5559 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5560 upper_32_bits(addr)); 5561 5562 return 0; 5563 } 5564 5565 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 5566 { 5567 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5568 uint32_t tmp; 5569 int i; 5570 uint64_t addr; 5571 5572 /* Trigger an invalidation of the L1 instruction caches */ 5573 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5574 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5575 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5576 5577 /* Wait for invalidation complete */ 5578 for (i = 0; i < usec_timeout; i++) { 5579 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5580 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5581 INVALIDATE_CACHE_COMPLETE)) 5582 break; 5583 udelay(1); 5584 } 5585 5586 if (i >= usec_timeout) { 5587 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5588 return -EINVAL; 5589 } 5590 5591 /* Program ce ucode address into intruction cache address register */ 5592 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5593 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 5594 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5595 lower_32_bits(addr) & 0xFFFFF000); 5596 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5597 upper_32_bits(addr)); 5598 5599 return 0; 5600 } 5601 5602 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 5603 { 5604 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5605 uint32_t tmp; 5606 int i; 5607 uint64_t addr; 5608 5609 /* Trigger an invalidation of the L1 instruction caches */ 5610 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5611 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5612 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5613 5614 /* Wait for invalidation complete */ 5615 for (i = 0; i < usec_timeout; i++) { 5616 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5617 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5618 INVALIDATE_CACHE_COMPLETE)) 5619 break; 5620 udelay(1); 5621 } 5622 5623 if (i >= usec_timeout) { 5624 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5625 return -EINVAL; 5626 } 5627 5628 /* Program pfp ucode address into intruction cache address register */ 5629 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5630 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 5631 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5632 lower_32_bits(addr) & 0xFFFFF000); 5633 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5634 upper_32_bits(addr)); 5635 5636 return 0; 5637 } 5638 5639 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 5640 { 5641 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5642 uint32_t tmp; 5643 int i; 5644 uint64_t addr; 5645 5646 /* Trigger an invalidation of the L1 instruction caches */ 5647 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5648 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5649 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 5650 5651 /* Wait for invalidation complete */ 5652 for (i = 0; i < usec_timeout; i++) { 5653 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 5654 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 5655 INVALIDATE_CACHE_COMPLETE)) 5656 break; 5657 udelay(1); 5658 } 5659 5660 if (i >= usec_timeout) { 5661 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5662 return -EINVAL; 5663 } 5664 5665 /* Program mec1 ucode address into intruction cache address register */ 5666 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 5667 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 5668 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 5669 lower_32_bits(addr) & 0xFFFFF000); 5670 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 5671 upper_32_bits(addr)); 5672 5673 return 0; 5674 } 5675 5676 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 5677 { 5678 uint32_t cp_status; 5679 uint32_t bootload_status; 5680 int i, r; 5681 5682 for (i = 0; i < adev->usec_timeout; i++) { 5683 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 5684 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 5685 if ((cp_status == 0) && 5686 (REG_GET_FIELD(bootload_status, 5687 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 5688 break; 5689 } 5690 udelay(1); 5691 } 5692 5693 if (i >= adev->usec_timeout) { 5694 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 5695 return -ETIMEDOUT; 5696 } 5697 5698 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 5699 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 5700 if (r) 5701 return r; 5702 5703 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 5704 if (r) 5705 return r; 5706 5707 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 5708 if (r) 5709 return r; 5710 5711 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 5712 if (r) 5713 return r; 5714 } 5715 5716 return 0; 5717 } 5718 5719 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 5720 { 5721 int i; 5722 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 5723 5724 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 5725 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 5726 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 5727 5728 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 5729 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp); 5730 } else { 5731 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 5732 } 5733 5734 if (adev->job_hang && !enable) 5735 return 0; 5736 5737 for (i = 0; i < adev->usec_timeout; i++) { 5738 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0) 5739 break; 5740 udelay(1); 5741 } 5742 5743 if (i >= adev->usec_timeout) 5744 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt"); 5745 5746 return 0; 5747 } 5748 5749 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 5750 { 5751 int r; 5752 const struct gfx_firmware_header_v1_0 *pfp_hdr; 5753 const __le32 *fw_data; 5754 unsigned i, fw_size; 5755 uint32_t tmp; 5756 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5757 5758 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 5759 adev->gfx.pfp_fw->data; 5760 5761 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 5762 5763 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 5764 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 5765 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 5766 5767 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 5768 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5769 &adev->gfx.pfp.pfp_fw_obj, 5770 &adev->gfx.pfp.pfp_fw_gpu_addr, 5771 (void **)&adev->gfx.pfp.pfp_fw_ptr); 5772 if (r) { 5773 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 5774 gfx_v10_0_pfp_fini(adev); 5775 return r; 5776 } 5777 5778 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 5779 5780 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 5781 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 5782 5783 /* Trigger an invalidation of the L1 instruction caches */ 5784 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5785 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5786 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 5787 5788 /* Wait for invalidation complete */ 5789 for (i = 0; i < usec_timeout; i++) { 5790 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 5791 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 5792 INVALIDATE_CACHE_COMPLETE)) 5793 break; 5794 udelay(1); 5795 } 5796 5797 if (i >= usec_timeout) { 5798 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5799 return -EINVAL; 5800 } 5801 5802 if (amdgpu_emu_mode == 1) 5803 adev->hdp.funcs->flush_hdp(adev, NULL); 5804 5805 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 5806 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 5807 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 5808 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 5809 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5810 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 5811 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 5812 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 5813 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 5814 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 5815 5816 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0); 5817 5818 for (i = 0; i < pfp_hdr->jt_size; i++) 5819 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA, 5820 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i)); 5821 5822 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version); 5823 5824 return 0; 5825 } 5826 5827 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 5828 { 5829 int r; 5830 const struct gfx_firmware_header_v1_0 *ce_hdr; 5831 const __le32 *fw_data; 5832 unsigned i, fw_size; 5833 uint32_t tmp; 5834 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5835 5836 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 5837 adev->gfx.ce_fw->data; 5838 5839 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 5840 5841 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 5842 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 5843 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 5844 5845 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 5846 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5847 &adev->gfx.ce.ce_fw_obj, 5848 &adev->gfx.ce.ce_fw_gpu_addr, 5849 (void **)&adev->gfx.ce.ce_fw_ptr); 5850 if (r) { 5851 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 5852 gfx_v10_0_ce_fini(adev); 5853 return r; 5854 } 5855 5856 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 5857 5858 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 5859 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 5860 5861 /* Trigger an invalidation of the L1 instruction caches */ 5862 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5863 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5864 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 5865 5866 /* Wait for invalidation complete */ 5867 for (i = 0; i < usec_timeout; i++) { 5868 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 5869 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 5870 INVALIDATE_CACHE_COMPLETE)) 5871 break; 5872 udelay(1); 5873 } 5874 5875 if (i >= usec_timeout) { 5876 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5877 return -EINVAL; 5878 } 5879 5880 if (amdgpu_emu_mode == 1) 5881 adev->hdp.funcs->flush_hdp(adev, NULL); 5882 5883 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 5884 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 5885 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 5886 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 5887 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5888 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 5889 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 5890 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 5891 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 5892 5893 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0); 5894 5895 for (i = 0; i < ce_hdr->jt_size; i++) 5896 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA, 5897 le32_to_cpup(fw_data + ce_hdr->jt_offset + i)); 5898 5899 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version); 5900 5901 return 0; 5902 } 5903 5904 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 5905 { 5906 int r; 5907 const struct gfx_firmware_header_v1_0 *me_hdr; 5908 const __le32 *fw_data; 5909 unsigned i, fw_size; 5910 uint32_t tmp; 5911 uint32_t usec_timeout = 50000; /* wait for 50ms */ 5912 5913 me_hdr = (const struct gfx_firmware_header_v1_0 *) 5914 adev->gfx.me_fw->data; 5915 5916 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 5917 5918 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 5919 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 5920 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 5921 5922 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 5923 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 5924 &adev->gfx.me.me_fw_obj, 5925 &adev->gfx.me.me_fw_gpu_addr, 5926 (void **)&adev->gfx.me.me_fw_ptr); 5927 if (r) { 5928 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 5929 gfx_v10_0_me_fini(adev); 5930 return r; 5931 } 5932 5933 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 5934 5935 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 5936 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 5937 5938 /* Trigger an invalidation of the L1 instruction caches */ 5939 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5940 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 5941 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 5942 5943 /* Wait for invalidation complete */ 5944 for (i = 0; i < usec_timeout; i++) { 5945 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 5946 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 5947 INVALIDATE_CACHE_COMPLETE)) 5948 break; 5949 udelay(1); 5950 } 5951 5952 if (i >= usec_timeout) { 5953 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 5954 return -EINVAL; 5955 } 5956 5957 if (amdgpu_emu_mode == 1) 5958 adev->hdp.funcs->flush_hdp(adev, NULL); 5959 5960 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 5961 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 5962 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 5963 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 5964 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 5965 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 5966 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 5967 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 5968 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 5969 5970 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0); 5971 5972 for (i = 0; i < me_hdr->jt_size; i++) 5973 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA, 5974 le32_to_cpup(fw_data + me_hdr->jt_offset + i)); 5975 5976 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version); 5977 5978 return 0; 5979 } 5980 5981 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 5982 { 5983 int r; 5984 5985 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 5986 return -EINVAL; 5987 5988 gfx_v10_0_cp_gfx_enable(adev, false); 5989 5990 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 5991 if (r) { 5992 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 5993 return r; 5994 } 5995 5996 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 5997 if (r) { 5998 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 5999 return r; 6000 } 6001 6002 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 6003 if (r) { 6004 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 6005 return r; 6006 } 6007 6008 return 0; 6009 } 6010 6011 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 6012 { 6013 struct amdgpu_ring *ring; 6014 const struct cs_section_def *sect = NULL; 6015 const struct cs_extent_def *ext = NULL; 6016 int r, i; 6017 int ctx_reg_offset; 6018 6019 /* init the CP */ 6020 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 6021 adev->gfx.config.max_hw_contexts - 1); 6022 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 6023 6024 gfx_v10_0_cp_gfx_enable(adev, true); 6025 6026 ring = &adev->gfx.gfx_ring[0]; 6027 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 6028 if (r) { 6029 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6030 return r; 6031 } 6032 6033 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6034 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 6035 6036 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 6037 amdgpu_ring_write(ring, 0x80000000); 6038 amdgpu_ring_write(ring, 0x80000000); 6039 6040 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 6041 for (ext = sect->section; ext->extent != NULL; ++ext) { 6042 if (sect->id == SECT_CONTEXT) { 6043 amdgpu_ring_write(ring, 6044 PACKET3(PACKET3_SET_CONTEXT_REG, 6045 ext->reg_count)); 6046 amdgpu_ring_write(ring, ext->reg_index - 6047 PACKET3_SET_CONTEXT_REG_START); 6048 for (i = 0; i < ext->reg_count; i++) 6049 amdgpu_ring_write(ring, ext->extent[i]); 6050 } 6051 } 6052 } 6053 6054 ctx_reg_offset = 6055 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 6056 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 6057 amdgpu_ring_write(ring, ctx_reg_offset); 6058 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 6059 6060 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 6061 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 6062 6063 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6064 amdgpu_ring_write(ring, 0); 6065 6066 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 6067 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 6068 amdgpu_ring_write(ring, 0x8000); 6069 amdgpu_ring_write(ring, 0x8000); 6070 6071 amdgpu_ring_commit(ring); 6072 6073 /* submit cs packet to copy state 0 to next available state */ 6074 if (adev->gfx.num_gfx_rings > 1) { 6075 /* maximum supported gfx ring is 2 */ 6076 ring = &adev->gfx.gfx_ring[1]; 6077 r = amdgpu_ring_alloc(ring, 2); 6078 if (r) { 6079 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 6080 return r; 6081 } 6082 6083 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 6084 amdgpu_ring_write(ring, 0); 6085 6086 amdgpu_ring_commit(ring); 6087 } 6088 return 0; 6089 } 6090 6091 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 6092 CP_PIPE_ID pipe) 6093 { 6094 u32 tmp; 6095 6096 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 6097 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 6098 6099 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 6100 } 6101 6102 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 6103 struct amdgpu_ring *ring) 6104 { 6105 u32 tmp; 6106 6107 if (!amdgpu_async_gfx_ring) { 6108 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6109 if (ring->use_doorbell) { 6110 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6111 DOORBELL_OFFSET, ring->doorbell_index); 6112 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6113 DOORBELL_EN, 1); 6114 } else { 6115 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6116 DOORBELL_EN, 0); 6117 } 6118 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 6119 } 6120 switch (adev->ip_versions[GC_HWIP][0]) { 6121 case IP_VERSION(10, 3, 0): 6122 case IP_VERSION(10, 3, 2): 6123 case IP_VERSION(10, 3, 1): 6124 case IP_VERSION(10, 3, 4): 6125 case IP_VERSION(10, 3, 5): 6126 case IP_VERSION(10, 3, 6): 6127 case IP_VERSION(10, 3, 3): 6128 case IP_VERSION(10, 3, 7): 6129 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6130 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index); 6131 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6132 6133 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6134 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK); 6135 break; 6136 default: 6137 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 6138 DOORBELL_RANGE_LOWER, ring->doorbell_index); 6139 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 6140 6141 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 6142 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 6143 break; 6144 } 6145 } 6146 6147 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 6148 { 6149 struct amdgpu_ring *ring; 6150 u32 tmp; 6151 u32 rb_bufsz; 6152 u64 rb_addr, rptr_addr, wptr_gpu_addr; 6153 u32 i; 6154 6155 /* Set the write pointer delay */ 6156 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 6157 6158 /* set the RB to use vmid 0 */ 6159 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 6160 6161 /* Init gfx ring 0 for pipe 0 */ 6162 mutex_lock(&adev->srbm_mutex); 6163 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6164 6165 /* Set ring buffer size */ 6166 ring = &adev->gfx.gfx_ring[0]; 6167 rb_bufsz = order_base_2(ring->ring_size / 8); 6168 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 6169 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 6170 #ifdef __BIG_ENDIAN 6171 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 6172 #endif 6173 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6174 6175 /* Initialize the ring buffer's write pointers */ 6176 ring->wptr = 0; 6177 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 6178 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 6179 6180 /* set the wb address wether it's enabled or not */ 6181 rptr_addr = ring->rptr_gpu_addr; 6182 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 6183 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6184 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6185 6186 wptr_gpu_addr = ring->wptr_gpu_addr; 6187 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6188 lower_32_bits(wptr_gpu_addr)); 6189 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6190 upper_32_bits(wptr_gpu_addr)); 6191 6192 mdelay(1); 6193 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 6194 6195 rb_addr = ring->gpu_addr >> 8; 6196 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 6197 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 6198 6199 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 6200 6201 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6202 mutex_unlock(&adev->srbm_mutex); 6203 6204 /* Init gfx ring 1 for pipe 1 */ 6205 if (adev->gfx.num_gfx_rings > 1) { 6206 mutex_lock(&adev->srbm_mutex); 6207 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 6208 /* maximum supported gfx ring is 2 */ 6209 ring = &adev->gfx.gfx_ring[1]; 6210 rb_bufsz = order_base_2(ring->ring_size / 8); 6211 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 6212 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 6213 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6214 /* Initialize the ring buffer's write pointers */ 6215 ring->wptr = 0; 6216 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 6217 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 6218 /* Set the wb address wether it's enabled or not */ 6219 rptr_addr = ring->rptr_gpu_addr; 6220 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 6221 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 6222 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 6223 wptr_gpu_addr = ring->wptr_gpu_addr; 6224 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 6225 lower_32_bits(wptr_gpu_addr)); 6226 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 6227 upper_32_bits(wptr_gpu_addr)); 6228 6229 mdelay(1); 6230 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 6231 6232 rb_addr = ring->gpu_addr >> 8; 6233 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 6234 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 6235 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 6236 6237 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6238 mutex_unlock(&adev->srbm_mutex); 6239 } 6240 /* Switch to pipe 0 */ 6241 mutex_lock(&adev->srbm_mutex); 6242 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 6243 mutex_unlock(&adev->srbm_mutex); 6244 6245 /* start the ring */ 6246 gfx_v10_0_cp_gfx_start(adev); 6247 6248 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6249 ring = &adev->gfx.gfx_ring[i]; 6250 ring->sched.ready = true; 6251 } 6252 6253 return 0; 6254 } 6255 6256 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 6257 { 6258 if (enable) { 6259 switch (adev->ip_versions[GC_HWIP][0]) { 6260 case IP_VERSION(10, 3, 0): 6261 case IP_VERSION(10, 3, 2): 6262 case IP_VERSION(10, 3, 1): 6263 case IP_VERSION(10, 3, 4): 6264 case IP_VERSION(10, 3, 5): 6265 case IP_VERSION(10, 3, 6): 6266 case IP_VERSION(10, 3, 3): 6267 case IP_VERSION(10, 3, 7): 6268 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0); 6269 break; 6270 default: 6271 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 6272 break; 6273 } 6274 } else { 6275 switch (adev->ip_versions[GC_HWIP][0]) { 6276 case IP_VERSION(10, 3, 0): 6277 case IP_VERSION(10, 3, 2): 6278 case IP_VERSION(10, 3, 1): 6279 case IP_VERSION(10, 3, 4): 6280 case IP_VERSION(10, 3, 5): 6281 case IP_VERSION(10, 3, 6): 6282 case IP_VERSION(10, 3, 3): 6283 case IP_VERSION(10, 3, 7): 6284 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 6285 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6286 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6287 break; 6288 default: 6289 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 6290 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 6291 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 6292 break; 6293 } 6294 adev->gfx.kiq.ring.sched.ready = false; 6295 } 6296 udelay(50); 6297 } 6298 6299 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 6300 { 6301 const struct gfx_firmware_header_v1_0 *mec_hdr; 6302 const __le32 *fw_data; 6303 unsigned i; 6304 u32 tmp; 6305 u32 usec_timeout = 50000; /* Wait for 50 ms */ 6306 6307 if (!adev->gfx.mec_fw) 6308 return -EINVAL; 6309 6310 gfx_v10_0_cp_compute_enable(adev, false); 6311 6312 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 6313 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 6314 6315 fw_data = (const __le32 *) 6316 (adev->gfx.mec_fw->data + 6317 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 6318 6319 /* Trigger an invalidation of the L1 instruction caches */ 6320 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6321 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 6322 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 6323 6324 /* Wait for invalidation complete */ 6325 for (i = 0; i < usec_timeout; i++) { 6326 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 6327 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 6328 INVALIDATE_CACHE_COMPLETE)) 6329 break; 6330 udelay(1); 6331 } 6332 6333 if (i >= usec_timeout) { 6334 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 6335 return -EINVAL; 6336 } 6337 6338 if (amdgpu_emu_mode == 1) 6339 adev->hdp.funcs->flush_hdp(adev, NULL); 6340 6341 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 6342 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 6343 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 6344 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 6345 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 6346 6347 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 6348 0xFFFFF000); 6349 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 6350 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 6351 6352 /* MEC1 */ 6353 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 6354 6355 for (i = 0; i < mec_hdr->jt_size; i++) 6356 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 6357 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 6358 6359 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 6360 6361 /* 6362 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 6363 * different microcode than MEC1. 6364 */ 6365 6366 return 0; 6367 } 6368 6369 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 6370 { 6371 uint32_t tmp; 6372 struct amdgpu_device *adev = ring->adev; 6373 6374 /* tell RLC which is KIQ queue */ 6375 switch (adev->ip_versions[GC_HWIP][0]) { 6376 case IP_VERSION(10, 3, 0): 6377 case IP_VERSION(10, 3, 2): 6378 case IP_VERSION(10, 3, 1): 6379 case IP_VERSION(10, 3, 4): 6380 case IP_VERSION(10, 3, 5): 6381 case IP_VERSION(10, 3, 6): 6382 case IP_VERSION(10, 3, 3): 6383 case IP_VERSION(10, 3, 7): 6384 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 6385 tmp &= 0xffffff00; 6386 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6387 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6388 tmp |= 0x80; 6389 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 6390 break; 6391 default: 6392 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 6393 tmp &= 0xffffff00; 6394 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 6395 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6396 tmp |= 0x80; 6397 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 6398 break; 6399 } 6400 } 6401 6402 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev, 6403 struct v10_gfx_mqd *mqd, 6404 struct amdgpu_mqd_prop *prop) 6405 { 6406 bool priority = 0; 6407 u32 tmp; 6408 6409 /* set up default queue priority level 6410 * 0x0 = low priority, 0x1 = high priority 6411 */ 6412 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH) 6413 priority = 1; 6414 6415 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 6416 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority); 6417 mqd->cp_gfx_hqd_queue_priority = tmp; 6418 } 6419 6420 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, 6421 struct amdgpu_mqd_prop *prop) 6422 { 6423 struct v10_gfx_mqd *mqd = m; 6424 uint64_t hqd_gpu_addr, wb_gpu_addr; 6425 uint32_t tmp; 6426 uint32_t rb_bufsz; 6427 6428 /* set up gfx hqd wptr */ 6429 mqd->cp_gfx_hqd_wptr = 0; 6430 mqd->cp_gfx_hqd_wptr_hi = 0; 6431 6432 /* set the pointer to the MQD */ 6433 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc; 6434 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6435 6436 /* set up mqd control */ 6437 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 6438 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 6439 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 6440 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 6441 mqd->cp_gfx_mqd_control = tmp; 6442 6443 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 6444 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 6445 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 6446 mqd->cp_gfx_hqd_vmid = 0; 6447 6448 /* set up gfx queue priority */ 6449 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop); 6450 6451 /* set up time quantum */ 6452 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 6453 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 6454 mqd->cp_gfx_hqd_quantum = tmp; 6455 6456 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 6457 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6458 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 6459 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 6460 6461 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 6462 wb_gpu_addr = prop->rptr_gpu_addr; 6463 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 6464 mqd->cp_gfx_hqd_rptr_addr_hi = 6465 upper_32_bits(wb_gpu_addr) & 0xffff; 6466 6467 /* set up rb_wptr_poll addr */ 6468 wb_gpu_addr = prop->wptr_gpu_addr; 6469 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6470 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6471 6472 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 6473 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; 6474 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 6475 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 6476 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 6477 #ifdef __BIG_ENDIAN 6478 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 6479 #endif 6480 mqd->cp_gfx_hqd_cntl = tmp; 6481 6482 /* set up cp_doorbell_control */ 6483 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 6484 if (prop->use_doorbell) { 6485 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6486 DOORBELL_OFFSET, prop->doorbell_index); 6487 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6488 DOORBELL_EN, 1); 6489 } else 6490 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 6491 DOORBELL_EN, 0); 6492 mqd->cp_rb_doorbell_control = tmp; 6493 6494 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6495 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 6496 6497 /* active the queue */ 6498 mqd->cp_gfx_hqd_active = 1; 6499 6500 return 0; 6501 } 6502 6503 #ifdef BRING_UP_DEBUG 6504 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 6505 { 6506 struct amdgpu_device *adev = ring->adev; 6507 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6508 6509 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 6510 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 6511 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 6512 6513 /* set GFX_MQD_BASE */ 6514 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 6515 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 6516 6517 /* set GFX_MQD_CONTROL */ 6518 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 6519 6520 /* set GFX_HQD_VMID to 0 */ 6521 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 6522 6523 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 6524 mqd->cp_gfx_hqd_queue_priority); 6525 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 6526 6527 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 6528 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 6529 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 6530 6531 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 6532 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 6533 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 6534 6535 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 6536 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 6537 6538 /* set RB_WPTR_POLL_ADDR */ 6539 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 6540 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 6541 6542 /* set RB_DOORBELL_CONTROL */ 6543 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 6544 6545 /* active the queue */ 6546 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 6547 6548 return 0; 6549 } 6550 #endif 6551 6552 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 6553 { 6554 struct amdgpu_device *adev = ring->adev; 6555 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 6556 int mqd_idx = ring - &adev->gfx.gfx_ring[0]; 6557 6558 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6559 memset((void *)mqd, 0, sizeof(*mqd)); 6560 mutex_lock(&adev->srbm_mutex); 6561 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6562 amdgpu_ring_init_mqd(ring); 6563 6564 /* 6565 * if there are 2 gfx rings, set the lower doorbell 6566 * range of the first ring, otherwise the range of 6567 * the second ring will override the first ring 6568 */ 6569 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1) 6570 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 6571 6572 #ifdef BRING_UP_DEBUG 6573 gfx_v10_0_gfx_queue_init_register(ring); 6574 #endif 6575 nv_grbm_select(adev, 0, 0, 0, 0); 6576 mutex_unlock(&adev->srbm_mutex); 6577 if (adev->gfx.me.mqd_backup[mqd_idx]) 6578 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6579 } else if (amdgpu_in_reset(adev)) { 6580 /* reset mqd with the backup copy */ 6581 if (adev->gfx.me.mqd_backup[mqd_idx]) 6582 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd)); 6583 /* reset the ring */ 6584 ring->wptr = 0; 6585 *ring->wptr_cpu_addr = 0; 6586 amdgpu_ring_clear_ring(ring); 6587 #ifdef BRING_UP_DEBUG 6588 mutex_lock(&adev->srbm_mutex); 6589 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6590 gfx_v10_0_gfx_queue_init_register(ring); 6591 nv_grbm_select(adev, 0, 0, 0, 0); 6592 mutex_unlock(&adev->srbm_mutex); 6593 #endif 6594 } else { 6595 amdgpu_ring_clear_ring(ring); 6596 } 6597 6598 return 0; 6599 } 6600 6601 #ifndef BRING_UP_DEBUG 6602 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 6603 { 6604 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 6605 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 6606 int r, i; 6607 6608 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 6609 return -EINVAL; 6610 6611 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 6612 adev->gfx.num_gfx_rings); 6613 if (r) { 6614 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 6615 return r; 6616 } 6617 6618 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 6619 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 6620 6621 return amdgpu_ring_test_helper(kiq_ring); 6622 } 6623 #endif 6624 6625 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 6626 { 6627 int r, i; 6628 struct amdgpu_ring *ring; 6629 6630 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6631 ring = &adev->gfx.gfx_ring[i]; 6632 6633 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6634 if (unlikely(r != 0)) 6635 goto done; 6636 6637 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6638 if (!r) { 6639 r = gfx_v10_0_gfx_init_queue(ring); 6640 amdgpu_bo_kunmap(ring->mqd_obj); 6641 ring->mqd_ptr = NULL; 6642 } 6643 amdgpu_bo_unreserve(ring->mqd_obj); 6644 if (r) 6645 goto done; 6646 } 6647 #ifndef BRING_UP_DEBUG 6648 r = gfx_v10_0_kiq_enable_kgq(adev); 6649 if (r) 6650 goto done; 6651 #endif 6652 r = gfx_v10_0_cp_gfx_start(adev); 6653 if (r) 6654 goto done; 6655 6656 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 6657 ring = &adev->gfx.gfx_ring[i]; 6658 ring->sched.ready = true; 6659 } 6660 done: 6661 return r; 6662 } 6663 6664 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, 6665 struct amdgpu_mqd_prop *prop) 6666 { 6667 struct v10_compute_mqd *mqd = m; 6668 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 6669 uint32_t tmp; 6670 6671 mqd->header = 0xC0310800; 6672 mqd->compute_pipelinestat_enable = 0x00000001; 6673 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 6674 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 6675 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 6676 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 6677 mqd->compute_misc_reserved = 0x00000003; 6678 6679 eop_base_addr = prop->eop_gpu_addr >> 8; 6680 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 6681 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 6682 6683 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6684 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 6685 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 6686 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 6687 6688 mqd->cp_hqd_eop_control = tmp; 6689 6690 /* enable doorbell? */ 6691 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 6692 6693 if (prop->use_doorbell) { 6694 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6695 DOORBELL_OFFSET, prop->doorbell_index); 6696 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6697 DOORBELL_EN, 1); 6698 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6699 DOORBELL_SOURCE, 0); 6700 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6701 DOORBELL_HIT, 0); 6702 } else { 6703 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 6704 DOORBELL_EN, 0); 6705 } 6706 6707 mqd->cp_hqd_pq_doorbell_control = tmp; 6708 6709 /* disable the queue if it's active */ 6710 mqd->cp_hqd_dequeue_request = 0; 6711 mqd->cp_hqd_pq_rptr = 0; 6712 mqd->cp_hqd_pq_wptr_lo = 0; 6713 mqd->cp_hqd_pq_wptr_hi = 0; 6714 6715 /* set the pointer to the MQD */ 6716 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 6717 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 6718 6719 /* set MQD vmid to 0 */ 6720 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 6721 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 6722 mqd->cp_mqd_control = tmp; 6723 6724 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6725 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 6726 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 6727 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 6728 6729 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6730 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 6731 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 6732 (order_base_2(prop->queue_size / 4) - 1)); 6733 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 6734 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 6735 #ifdef __BIG_ENDIAN 6736 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 6737 #endif 6738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 6739 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 6740 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 6741 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 6742 mqd->cp_hqd_pq_control = tmp; 6743 6744 /* set the wb address whether it's enabled or not */ 6745 wb_gpu_addr = prop->rptr_gpu_addr; 6746 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 6747 mqd->cp_hqd_pq_rptr_report_addr_hi = 6748 upper_32_bits(wb_gpu_addr) & 0xffff; 6749 6750 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6751 wb_gpu_addr = prop->wptr_gpu_addr; 6752 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 6753 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 6754 6755 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6756 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 6757 6758 /* set the vmid for the queue */ 6759 mqd->cp_hqd_vmid = 0; 6760 6761 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 6762 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 6763 mqd->cp_hqd_persistent_state = tmp; 6764 6765 /* set MIN_IB_AVAIL_SIZE */ 6766 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 6767 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 6768 mqd->cp_hqd_ib_control = tmp; 6769 6770 /* set static priority for a compute queue/ring */ 6771 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 6772 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 6773 6774 mqd->cp_hqd_active = prop->hqd_active; 6775 6776 return 0; 6777 } 6778 6779 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 6780 { 6781 struct amdgpu_device *adev = ring->adev; 6782 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6783 int j; 6784 6785 /* inactivate the queue */ 6786 if (amdgpu_sriov_vf(adev)) 6787 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); 6788 6789 /* disable wptr polling */ 6790 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 6791 6792 /* disable the queue if it's active */ 6793 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 6794 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 6795 for (j = 0; j < adev->usec_timeout; j++) { 6796 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 6797 break; 6798 udelay(1); 6799 } 6800 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 6801 mqd->cp_hqd_dequeue_request); 6802 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 6803 mqd->cp_hqd_pq_rptr); 6804 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6805 mqd->cp_hqd_pq_wptr_lo); 6806 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6807 mqd->cp_hqd_pq_wptr_hi); 6808 } 6809 6810 /* disable doorbells */ 6811 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 6812 6813 /* write the EOP addr */ 6814 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 6815 mqd->cp_hqd_eop_base_addr_lo); 6816 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 6817 mqd->cp_hqd_eop_base_addr_hi); 6818 6819 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 6820 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 6821 mqd->cp_hqd_eop_control); 6822 6823 /* set the pointer to the MQD */ 6824 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 6825 mqd->cp_mqd_base_addr_lo); 6826 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 6827 mqd->cp_mqd_base_addr_hi); 6828 6829 /* set MQD vmid to 0 */ 6830 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 6831 mqd->cp_mqd_control); 6832 6833 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 6834 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 6835 mqd->cp_hqd_pq_base_lo); 6836 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 6837 mqd->cp_hqd_pq_base_hi); 6838 6839 /* set up the HQD, this is similar to CP_RB0_CNTL */ 6840 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 6841 mqd->cp_hqd_pq_control); 6842 6843 /* set the wb address whether it's enabled or not */ 6844 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 6845 mqd->cp_hqd_pq_rptr_report_addr_lo); 6846 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 6847 mqd->cp_hqd_pq_rptr_report_addr_hi); 6848 6849 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 6850 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 6851 mqd->cp_hqd_pq_wptr_poll_addr_lo); 6852 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 6853 mqd->cp_hqd_pq_wptr_poll_addr_hi); 6854 6855 /* enable the doorbell if requested */ 6856 if (ring->use_doorbell) { 6857 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 6858 (adev->doorbell_index.kiq * 2) << 2); 6859 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 6860 (adev->doorbell_index.userqueue_end * 2) << 2); 6861 } 6862 6863 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 6864 mqd->cp_hqd_pq_doorbell_control); 6865 6866 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 6867 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 6868 mqd->cp_hqd_pq_wptr_lo); 6869 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 6870 mqd->cp_hqd_pq_wptr_hi); 6871 6872 /* set the vmid for the queue */ 6873 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 6874 6875 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 6876 mqd->cp_hqd_persistent_state); 6877 6878 /* activate the queue */ 6879 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 6880 mqd->cp_hqd_active); 6881 6882 if (ring->use_doorbell) 6883 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 6884 6885 return 0; 6886 } 6887 6888 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 6889 { 6890 struct amdgpu_device *adev = ring->adev; 6891 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6892 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 6893 6894 gfx_v10_0_kiq_setting(ring); 6895 6896 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6897 /* reset MQD to a clean status */ 6898 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6899 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6900 6901 /* reset ring buffer */ 6902 ring->wptr = 0; 6903 amdgpu_ring_clear_ring(ring); 6904 6905 mutex_lock(&adev->srbm_mutex); 6906 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6907 gfx_v10_0_kiq_init_register(ring); 6908 nv_grbm_select(adev, 0, 0, 0, 0); 6909 mutex_unlock(&adev->srbm_mutex); 6910 } else { 6911 memset((void *)mqd, 0, sizeof(*mqd)); 6912 if (amdgpu_sriov_vf(adev) && adev->in_suspend) 6913 amdgpu_ring_clear_ring(ring); 6914 mutex_lock(&adev->srbm_mutex); 6915 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6916 amdgpu_ring_init_mqd(ring); 6917 gfx_v10_0_kiq_init_register(ring); 6918 nv_grbm_select(adev, 0, 0, 0, 0); 6919 mutex_unlock(&adev->srbm_mutex); 6920 6921 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6922 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6923 } 6924 6925 return 0; 6926 } 6927 6928 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 6929 { 6930 struct amdgpu_device *adev = ring->adev; 6931 struct v10_compute_mqd *mqd = ring->mqd_ptr; 6932 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 6933 6934 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 6935 memset((void *)mqd, 0, sizeof(*mqd)); 6936 mutex_lock(&adev->srbm_mutex); 6937 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 6938 amdgpu_ring_init_mqd(ring); 6939 nv_grbm_select(adev, 0, 0, 0, 0); 6940 mutex_unlock(&adev->srbm_mutex); 6941 6942 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6943 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 6944 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */ 6945 /* reset MQD to a clean status */ 6946 if (adev->gfx.mec.mqd_backup[mqd_idx]) 6947 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 6948 6949 /* reset ring buffer */ 6950 ring->wptr = 0; 6951 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 6952 amdgpu_ring_clear_ring(ring); 6953 } else { 6954 amdgpu_ring_clear_ring(ring); 6955 } 6956 6957 return 0; 6958 } 6959 6960 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 6961 { 6962 struct amdgpu_ring *ring; 6963 int r; 6964 6965 ring = &adev->gfx.kiq.ring; 6966 6967 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6968 if (unlikely(r != 0)) 6969 return r; 6970 6971 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6972 if (unlikely(r != 0)) 6973 return r; 6974 6975 gfx_v10_0_kiq_init_queue(ring); 6976 amdgpu_bo_kunmap(ring->mqd_obj); 6977 ring->mqd_ptr = NULL; 6978 amdgpu_bo_unreserve(ring->mqd_obj); 6979 ring->sched.ready = true; 6980 return 0; 6981 } 6982 6983 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 6984 { 6985 struct amdgpu_ring *ring = NULL; 6986 int r = 0, i; 6987 6988 gfx_v10_0_cp_compute_enable(adev, true); 6989 6990 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 6991 ring = &adev->gfx.compute_ring[i]; 6992 6993 r = amdgpu_bo_reserve(ring->mqd_obj, false); 6994 if (unlikely(r != 0)) 6995 goto done; 6996 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 6997 if (!r) { 6998 r = gfx_v10_0_kcq_init_queue(ring); 6999 amdgpu_bo_kunmap(ring->mqd_obj); 7000 ring->mqd_ptr = NULL; 7001 } 7002 amdgpu_bo_unreserve(ring->mqd_obj); 7003 if (r) 7004 goto done; 7005 } 7006 7007 r = amdgpu_gfx_enable_kcq(adev); 7008 done: 7009 return r; 7010 } 7011 7012 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 7013 { 7014 int r, i; 7015 struct amdgpu_ring *ring; 7016 7017 if (!(adev->flags & AMD_IS_APU)) 7018 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7019 7020 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7021 /* legacy firmware loading */ 7022 r = gfx_v10_0_cp_gfx_load_microcode(adev); 7023 if (r) 7024 return r; 7025 7026 r = gfx_v10_0_cp_compute_load_microcode(adev); 7027 if (r) 7028 return r; 7029 } 7030 7031 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init) 7032 r = amdgpu_mes_kiq_hw_init(adev); 7033 else 7034 r = gfx_v10_0_kiq_resume(adev); 7035 if (r) 7036 return r; 7037 7038 r = gfx_v10_0_kcq_resume(adev); 7039 if (r) 7040 return r; 7041 7042 if (!amdgpu_async_gfx_ring) { 7043 r = gfx_v10_0_cp_gfx_resume(adev); 7044 if (r) 7045 return r; 7046 } else { 7047 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 7048 if (r) 7049 return r; 7050 } 7051 7052 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 7053 ring = &adev->gfx.gfx_ring[i]; 7054 r = amdgpu_ring_test_helper(ring); 7055 if (r) 7056 return r; 7057 } 7058 7059 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 7060 ring = &adev->gfx.compute_ring[i]; 7061 r = amdgpu_ring_test_helper(ring); 7062 if (r) 7063 return r; 7064 } 7065 7066 return 0; 7067 } 7068 7069 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 7070 { 7071 gfx_v10_0_cp_gfx_enable(adev, enable); 7072 gfx_v10_0_cp_compute_enable(adev, enable); 7073 } 7074 7075 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 7076 { 7077 uint32_t data, pattern = 0xDEADBEEF; 7078 7079 /* check if mmVGT_ESGS_RING_SIZE_UMD 7080 * has been remapped to mmVGT_ESGS_RING_SIZE */ 7081 switch (adev->ip_versions[GC_HWIP][0]) { 7082 case IP_VERSION(10, 3, 0): 7083 case IP_VERSION(10, 3, 2): 7084 case IP_VERSION(10, 3, 4): 7085 case IP_VERSION(10, 3, 5): 7086 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); 7087 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); 7088 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7089 7090 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { 7091 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data); 7092 return true; 7093 } else { 7094 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); 7095 return false; 7096 } 7097 break; 7098 case IP_VERSION(10, 3, 1): 7099 case IP_VERSION(10, 3, 3): 7100 case IP_VERSION(10, 3, 6): 7101 case IP_VERSION(10, 3, 7): 7102 return true; 7103 default: 7104 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 7105 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 7106 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 7107 7108 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 7109 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 7110 return true; 7111 } else { 7112 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 7113 return false; 7114 } 7115 break; 7116 } 7117 } 7118 7119 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 7120 { 7121 uint32_t data; 7122 7123 if (amdgpu_sriov_vf(adev)) 7124 return; 7125 7126 /* initialize cam_index to 0 7127 * index will auto-inc after each data writting */ 7128 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 7129 7130 switch (adev->ip_versions[GC_HWIP][0]) { 7131 case IP_VERSION(10, 3, 0): 7132 case IP_VERSION(10, 3, 2): 7133 case IP_VERSION(10, 3, 1): 7134 case IP_VERSION(10, 3, 4): 7135 case IP_VERSION(10, 3, 5): 7136 case IP_VERSION(10, 3, 6): 7137 case IP_VERSION(10, 3, 3): 7138 case IP_VERSION(10, 3, 7): 7139 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7140 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7141 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7142 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) << 7143 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7144 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7145 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7146 7147 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7148 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7149 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7150 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) << 7151 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7152 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7153 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7154 7155 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7156 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7157 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7158 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) << 7159 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7160 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7161 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7162 7163 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7164 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7165 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7166 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) << 7167 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7168 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7169 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7170 7171 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7172 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7173 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7174 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << 7175 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7176 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7177 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7178 7179 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7180 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7181 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7182 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) << 7183 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7184 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7185 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7186 7187 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7188 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7189 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7190 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) << 7191 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7192 break; 7193 default: 7194 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 7195 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 7196 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7197 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 7198 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7199 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7200 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7201 7202 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 7203 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 7204 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7205 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 7206 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7207 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7208 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7209 7210 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 7211 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 7212 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7213 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 7214 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7215 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7216 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7217 7218 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 7219 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 7220 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7221 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 7222 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7223 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7224 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7225 7226 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 7227 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 7228 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7229 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 7230 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7231 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7232 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7233 7234 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 7235 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 7236 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7237 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 7238 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7239 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7240 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7241 7242 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 7243 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 7244 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 7245 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 7246 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 7247 break; 7248 } 7249 7250 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 7251 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 7252 } 7253 7254 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) 7255 { 7256 uint32_t data; 7257 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG); 7258 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 7259 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data); 7260 7261 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG); 7262 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 7263 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); 7264 } 7265 7266 static int gfx_v10_0_hw_init(void *handle) 7267 { 7268 int r; 7269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7270 7271 if (!amdgpu_emu_mode) 7272 gfx_v10_0_init_golden_registers(adev); 7273 7274 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 7275 /** 7276 * For gfx 10, rlc firmware loading relies on smu firmware is 7277 * loaded firstly, so in direct type, it has to load smc ucode 7278 * here before rlc. 7279 */ 7280 if (!(adev->flags & AMD_IS_APU)) { 7281 r = amdgpu_pm_load_smu_firmware(adev, NULL); 7282 if (r) 7283 return r; 7284 } 7285 gfx_v10_0_disable_gpa_mode(adev); 7286 } 7287 7288 /* if GRBM CAM not remapped, set up the remapping */ 7289 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 7290 gfx_v10_0_setup_grbm_cam_remapping(adev); 7291 7292 gfx_v10_0_constants_init(adev); 7293 7294 r = gfx_v10_0_rlc_resume(adev); 7295 if (r) 7296 return r; 7297 7298 /* 7299 * init golden registers and rlc resume may override some registers, 7300 * reconfig them here 7301 */ 7302 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) || 7303 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) || 7304 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) 7305 gfx_v10_0_tcp_harvest(adev); 7306 7307 r = gfx_v10_0_cp_resume(adev); 7308 if (r) 7309 return r; 7310 7311 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) 7312 gfx_v10_3_program_pbb_mode(adev); 7313 7314 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) 7315 gfx_v10_3_set_power_brake_sequence(adev); 7316 7317 return r; 7318 } 7319 7320 #ifndef BRING_UP_DEBUG 7321 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 7322 { 7323 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 7324 struct amdgpu_ring *kiq_ring = &kiq->ring; 7325 int i; 7326 7327 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 7328 return -EINVAL; 7329 7330 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 7331 adev->gfx.num_gfx_rings)) 7332 return -ENOMEM; 7333 7334 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 7335 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 7336 PREEMPT_QUEUES, 0, 0); 7337 if (!adev->job_hang) 7338 return amdgpu_ring_test_helper(kiq_ring); 7339 else 7340 return 0; 7341 } 7342 #endif 7343 7344 static int gfx_v10_0_hw_fini(void *handle) 7345 { 7346 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7347 int r; 7348 uint32_t tmp; 7349 7350 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 7351 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 7352 7353 if (!adev->no_hw_access) { 7354 #ifndef BRING_UP_DEBUG 7355 if (amdgpu_async_gfx_ring) { 7356 r = gfx_v10_0_kiq_disable_kgq(adev); 7357 if (r) 7358 DRM_ERROR("KGQ disable failed\n"); 7359 } 7360 #endif 7361 if (amdgpu_gfx_disable_kcq(adev)) 7362 DRM_ERROR("KCQ disable failed\n"); 7363 } 7364 7365 if (amdgpu_sriov_vf(adev)) { 7366 gfx_v10_0_cp_gfx_enable(adev, false); 7367 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 7368 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) { 7369 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid); 7370 tmp &= 0xffffff00; 7371 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp); 7372 } else { 7373 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 7374 tmp &= 0xffffff00; 7375 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 7376 } 7377 7378 return 0; 7379 } 7380 gfx_v10_0_cp_enable(adev, false); 7381 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 7382 7383 return 0; 7384 } 7385 7386 static int gfx_v10_0_suspend(void *handle) 7387 { 7388 return gfx_v10_0_hw_fini(handle); 7389 } 7390 7391 static int gfx_v10_0_resume(void *handle) 7392 { 7393 return gfx_v10_0_hw_init(handle); 7394 } 7395 7396 static bool gfx_v10_0_is_idle(void *handle) 7397 { 7398 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7399 7400 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 7401 GRBM_STATUS, GUI_ACTIVE)) 7402 return false; 7403 else 7404 return true; 7405 } 7406 7407 static int gfx_v10_0_wait_for_idle(void *handle) 7408 { 7409 unsigned i; 7410 u32 tmp; 7411 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7412 7413 for (i = 0; i < adev->usec_timeout; i++) { 7414 /* read MC_STATUS */ 7415 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 7416 GRBM_STATUS__GUI_ACTIVE_MASK; 7417 7418 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 7419 return 0; 7420 udelay(1); 7421 } 7422 return -ETIMEDOUT; 7423 } 7424 7425 static int gfx_v10_0_soft_reset(void *handle) 7426 { 7427 u32 grbm_soft_reset = 0; 7428 u32 tmp; 7429 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7430 7431 /* GRBM_STATUS */ 7432 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 7433 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 7434 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 7435 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 7436 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 7437 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) { 7438 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7439 GRBM_SOFT_RESET, SOFT_RESET_CP, 7440 1); 7441 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7442 GRBM_SOFT_RESET, SOFT_RESET_GFX, 7443 1); 7444 } 7445 7446 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 7447 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7448 GRBM_SOFT_RESET, SOFT_RESET_CP, 7449 1); 7450 } 7451 7452 /* GRBM_STATUS2 */ 7453 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 7454 switch (adev->ip_versions[GC_HWIP][0]) { 7455 case IP_VERSION(10, 3, 0): 7456 case IP_VERSION(10, 3, 2): 7457 case IP_VERSION(10, 3, 1): 7458 case IP_VERSION(10, 3, 4): 7459 case IP_VERSION(10, 3, 5): 7460 case IP_VERSION(10, 3, 6): 7461 case IP_VERSION(10, 3, 3): 7462 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid)) 7463 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7464 GRBM_SOFT_RESET, 7465 SOFT_RESET_RLC, 7466 1); 7467 break; 7468 default: 7469 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 7470 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 7471 GRBM_SOFT_RESET, 7472 SOFT_RESET_RLC, 7473 1); 7474 break; 7475 } 7476 7477 if (grbm_soft_reset) { 7478 /* stop the rlc */ 7479 gfx_v10_0_rlc_stop(adev); 7480 7481 /* Disable GFX parsing/prefetching */ 7482 gfx_v10_0_cp_gfx_enable(adev, false); 7483 7484 /* Disable MEC parsing/prefetching */ 7485 gfx_v10_0_cp_compute_enable(adev, false); 7486 7487 if (grbm_soft_reset) { 7488 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7489 tmp |= grbm_soft_reset; 7490 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 7491 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7492 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7493 7494 udelay(50); 7495 7496 tmp &= ~grbm_soft_reset; 7497 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 7498 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 7499 } 7500 7501 /* Wait a little for things to settle down */ 7502 udelay(50); 7503 } 7504 return 0; 7505 } 7506 7507 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 7508 { 7509 uint64_t clock, clock_lo, clock_hi, hi_check; 7510 7511 switch (adev->ip_versions[GC_HWIP][0]) { 7512 case IP_VERSION(10, 3, 1): 7513 case IP_VERSION(10, 3, 3): 7514 case IP_VERSION(10, 3, 7): 7515 preempt_disable(); 7516 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7517 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7518 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh); 7519 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7520 * roughly every 42 seconds. 7521 */ 7522 if (hi_check != clock_hi) { 7523 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh); 7524 clock_hi = hi_check; 7525 } 7526 preempt_enable(); 7527 clock = clock_lo | (clock_hi << 32ULL); 7528 break; 7529 case IP_VERSION(10, 3, 6): 7530 preempt_disable(); 7531 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7532 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7533 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6); 7534 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7535 * roughly every 42 seconds. 7536 */ 7537 if (hi_check != clock_hi) { 7538 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6); 7539 clock_hi = hi_check; 7540 } 7541 preempt_enable(); 7542 clock = clock_lo | (clock_hi << 32ULL); 7543 break; 7544 default: 7545 preempt_disable(); 7546 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7547 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7548 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER); 7549 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over 7550 * roughly every 42 seconds. 7551 */ 7552 if (hi_check != clock_hi) { 7553 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER); 7554 clock_hi = hi_check; 7555 } 7556 preempt_enable(); 7557 clock = clock_lo | (clock_hi << 32ULL); 7558 break; 7559 } 7560 return clock; 7561 } 7562 7563 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 7564 uint32_t vmid, 7565 uint32_t gds_base, uint32_t gds_size, 7566 uint32_t gws_base, uint32_t gws_size, 7567 uint32_t oa_base, uint32_t oa_size) 7568 { 7569 struct amdgpu_device *adev = ring->adev; 7570 7571 /* GDS Base */ 7572 gfx_v10_0_write_data_to_reg(ring, 0, false, 7573 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 7574 gds_base); 7575 7576 /* GDS Size */ 7577 gfx_v10_0_write_data_to_reg(ring, 0, false, 7578 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 7579 gds_size); 7580 7581 /* GWS */ 7582 gfx_v10_0_write_data_to_reg(ring, 0, false, 7583 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 7584 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 7585 7586 /* OA */ 7587 gfx_v10_0_write_data_to_reg(ring, 0, false, 7588 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 7589 (1 << (oa_size + oa_base)) - (1 << oa_base)); 7590 } 7591 7592 static int gfx_v10_0_early_init(void *handle) 7593 { 7594 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7595 7596 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 7597 7598 switch (adev->ip_versions[GC_HWIP][0]) { 7599 case IP_VERSION(10, 1, 10): 7600 case IP_VERSION(10, 1, 1): 7601 case IP_VERSION(10, 1, 2): 7602 case IP_VERSION(10, 1, 3): 7603 case IP_VERSION(10, 1, 4): 7604 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X; 7605 break; 7606 case IP_VERSION(10, 3, 0): 7607 case IP_VERSION(10, 3, 2): 7608 case IP_VERSION(10, 3, 1): 7609 case IP_VERSION(10, 3, 4): 7610 case IP_VERSION(10, 3, 5): 7611 case IP_VERSION(10, 3, 6): 7612 case IP_VERSION(10, 3, 3): 7613 case IP_VERSION(10, 3, 7): 7614 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid; 7615 break; 7616 default: 7617 break; 7618 } 7619 7620 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 7621 AMDGPU_MAX_COMPUTE_RINGS); 7622 7623 gfx_v10_0_set_kiq_pm4_funcs(adev); 7624 gfx_v10_0_set_ring_funcs(adev); 7625 gfx_v10_0_set_irq_funcs(adev); 7626 gfx_v10_0_set_gds_init(adev); 7627 gfx_v10_0_set_rlc_funcs(adev); 7628 gfx_v10_0_set_mqd_funcs(adev); 7629 7630 /* init rlcg reg access ctrl */ 7631 gfx_v10_0_init_rlcg_reg_access_ctrl(adev); 7632 7633 return 0; 7634 } 7635 7636 static int gfx_v10_0_late_init(void *handle) 7637 { 7638 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 7639 int r; 7640 7641 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 7642 if (r) 7643 return r; 7644 7645 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 7646 if (r) 7647 return r; 7648 7649 return 0; 7650 } 7651 7652 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 7653 { 7654 uint32_t rlc_cntl; 7655 7656 /* if RLC is not enabled, do nothing */ 7657 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 7658 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 7659 } 7660 7661 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 7662 { 7663 uint32_t data; 7664 unsigned i; 7665 7666 data = RLC_SAFE_MODE__CMD_MASK; 7667 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 7668 7669 switch (adev->ip_versions[GC_HWIP][0]) { 7670 case IP_VERSION(10, 3, 0): 7671 case IP_VERSION(10, 3, 2): 7672 case IP_VERSION(10, 3, 1): 7673 case IP_VERSION(10, 3, 4): 7674 case IP_VERSION(10, 3, 5): 7675 case IP_VERSION(10, 3, 6): 7676 case IP_VERSION(10, 3, 3): 7677 case IP_VERSION(10, 3, 7): 7678 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7679 7680 /* wait for RLC_SAFE_MODE */ 7681 for (i = 0; i < adev->usec_timeout; i++) { 7682 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid), 7683 RLC_SAFE_MODE, CMD)) 7684 break; 7685 udelay(1); 7686 } 7687 break; 7688 default: 7689 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7690 7691 /* wait for RLC_SAFE_MODE */ 7692 for (i = 0; i < adev->usec_timeout; i++) { 7693 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), 7694 RLC_SAFE_MODE, CMD)) 7695 break; 7696 udelay(1); 7697 } 7698 break; 7699 } 7700 } 7701 7702 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 7703 { 7704 uint32_t data; 7705 7706 data = RLC_SAFE_MODE__CMD_MASK; 7707 switch (adev->ip_versions[GC_HWIP][0]) { 7708 case IP_VERSION(10, 3, 0): 7709 case IP_VERSION(10, 3, 2): 7710 case IP_VERSION(10, 3, 1): 7711 case IP_VERSION(10, 3, 4): 7712 case IP_VERSION(10, 3, 5): 7713 case IP_VERSION(10, 3, 6): 7714 case IP_VERSION(10, 3, 3): 7715 case IP_VERSION(10, 3, 7): 7716 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data); 7717 break; 7718 default: 7719 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 7720 break; 7721 } 7722 } 7723 7724 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 7725 bool enable) 7726 { 7727 uint32_t data, def; 7728 7729 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS))) 7730 return; 7731 7732 /* It is disabled by HW by default */ 7733 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7734 /* 0 - Disable some blocks' MGCG */ 7735 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); 7736 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000); 7737 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000); 7738 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000); 7739 7740 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 7741 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7742 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7743 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7744 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7745 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7746 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7747 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7748 7749 if (def != data) 7750 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7751 7752 /* MGLS is a global flag to control all MGLS in GFX */ 7753 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 7754 /* 2 - RLC memory Light sleep */ 7755 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 7756 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7757 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7758 if (def != data) 7759 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7760 } 7761 /* 3 - CP memory Light sleep */ 7762 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 7763 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7764 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7765 if (def != data) 7766 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7767 } 7768 } 7769 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 7770 /* 1 - MGCG_OVERRIDE */ 7771 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7772 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 7773 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 7774 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 7775 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK | 7776 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK | 7777 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK); 7778 if (def != data) 7779 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7780 7781 /* 2 - disable MGLS in CP */ 7782 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 7783 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 7784 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 7785 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 7786 } 7787 7788 /* 3 - disable MGLS in RLC */ 7789 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 7790 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 7791 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 7792 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 7793 } 7794 7795 } 7796 } 7797 7798 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 7799 bool enable) 7800 { 7801 uint32_t data, def; 7802 7803 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS))) 7804 return; 7805 7806 /* Enable 3D CGCG/CGLS */ 7807 if (enable) { 7808 /* write cmd to clear cgcg/cgls ov */ 7809 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7810 7811 /* unset CGCG override */ 7812 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7813 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 7814 7815 /* update CGCG and CGLS override bits */ 7816 if (def != data) 7817 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7818 7819 /* enable 3Dcgcg FSM(0x0000363f) */ 7820 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7821 data = 0; 7822 7823 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7824 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7825 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7826 7827 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7828 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7829 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7830 7831 if (def != data) 7832 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7833 7834 /* set IDLE_POLL_COUNT(0x00900100) */ 7835 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7836 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7837 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7838 if (def != data) 7839 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7840 } else { 7841 /* Disable CGCG/CGLS */ 7842 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 7843 7844 /* disable cgcg, cgls should be disabled */ 7845 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) 7846 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 7847 7848 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 7849 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 7850 7851 /* disable cgcg and cgls in FSM */ 7852 if (def != data) 7853 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 7854 } 7855 } 7856 7857 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 7858 bool enable) 7859 { 7860 uint32_t def, data; 7861 7862 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS))) 7863 return; 7864 7865 if (enable) { 7866 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7867 7868 /* unset CGCG override */ 7869 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7870 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 7871 7872 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7873 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 7874 7875 /* update CGCG and CGLS override bits */ 7876 if (def != data) 7877 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7878 7879 /* enable cgcg FSM(0x0000363F) */ 7880 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7881 data = 0; 7882 7883 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7884 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 7885 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7886 7887 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7888 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 7889 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7890 7891 if (def != data) 7892 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7893 7894 /* set IDLE_POLL_COUNT(0x00900100) */ 7895 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 7896 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 7897 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 7898 if (def != data) 7899 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 7900 } else { 7901 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 7902 7903 /* reset CGCG/CGLS bits */ 7904 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 7905 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 7906 7907 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 7908 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 7909 7910 /* disable cgcg and cgls in FSM */ 7911 if (def != data) 7912 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 7913 } 7914 } 7915 7916 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev, 7917 bool enable) 7918 { 7919 uint32_t def, data; 7920 7921 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 7922 return; 7923 7924 if (enable) { 7925 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7926 /* unset FGCG override */ 7927 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7928 /* update FGCG override bits */ 7929 if (def != data) 7930 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7931 7932 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7933 /* unset RLC SRAM CLK GATER override */ 7934 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7935 /* update RLC SRAM CLK GATER override bits */ 7936 if (def != data) 7937 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7938 } else { 7939 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 7940 /* reset FGCG bits */ 7941 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 7942 /* disable FGCG*/ 7943 if (def != data) 7944 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 7945 7946 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL); 7947 /* reset RLC SRAM CLK GATER bits */ 7948 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK; 7949 /* disable RLC SRAM CLK*/ 7950 if (def != data) 7951 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data); 7952 } 7953 } 7954 7955 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev) 7956 { 7957 uint32_t reg_data = 0; 7958 uint32_t reg_idx = 0; 7959 uint32_t i; 7960 7961 const uint32_t tcp_ctrl_regs[] = { 7962 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7963 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7964 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7965 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7966 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7967 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7968 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7969 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7970 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7971 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7972 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG, 7973 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG, 7974 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 7975 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 7976 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 7977 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 7978 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 7979 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 7980 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 7981 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 7982 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 7983 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 7984 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG, 7985 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG 7986 }; 7987 7988 const uint32_t tcp_ctrl_regs_nv12[] = { 7989 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG, 7990 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG, 7991 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG, 7992 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG, 7993 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG, 7994 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG, 7995 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG, 7996 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG, 7997 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG, 7998 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG, 7999 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG, 8000 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG, 8001 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG, 8002 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG, 8003 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG, 8004 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG, 8005 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG, 8006 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG, 8007 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG, 8008 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG, 8009 }; 8010 8011 const uint32_t sm_ctlr_regs[] = { 8012 mmCGTS_SA0_QUAD0_SM_CTRL_REG, 8013 mmCGTS_SA0_QUAD1_SM_CTRL_REG, 8014 mmCGTS_SA1_QUAD0_SM_CTRL_REG, 8015 mmCGTS_SA1_QUAD1_SM_CTRL_REG 8016 }; 8017 8018 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) { 8019 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) { 8020 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8021 tcp_ctrl_regs_nv12[i]; 8022 reg_data = RREG32(reg_idx); 8023 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8024 WREG32(reg_idx, reg_data); 8025 } 8026 } else { 8027 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) { 8028 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] + 8029 tcp_ctrl_regs[i]; 8030 reg_data = RREG32(reg_idx); 8031 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK; 8032 WREG32(reg_idx, reg_data); 8033 } 8034 } 8035 8036 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) { 8037 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + 8038 sm_ctlr_regs[i]; 8039 reg_data = RREG32(reg_idx); 8040 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK; 8041 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT; 8042 WREG32(reg_idx, reg_data); 8043 } 8044 } 8045 8046 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 8047 bool enable) 8048 { 8049 amdgpu_gfx_rlc_enter_safe_mode(adev); 8050 8051 if (enable) { 8052 /* enable FGCG firstly*/ 8053 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8054 /* CGCG/CGLS should be enabled after MGCG/MGLS 8055 * === MGCG + MGLS === 8056 */ 8057 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8058 /* === CGCG /CGLS for GFX 3D Only === */ 8059 gfx_v10_0_update_3d_clock_gating(adev, enable); 8060 /* === CGCG + CGLS === */ 8061 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8062 8063 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) || 8064 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) || 8065 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))) 8066 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev); 8067 } else { 8068 /* CGCG/CGLS should be disabled before MGCG/MGLS 8069 * === CGCG + CGLS === 8070 */ 8071 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 8072 /* === CGCG /CGLS for GFX 3D Only === */ 8073 gfx_v10_0_update_3d_clock_gating(adev, enable); 8074 /* === MGCG + MGLS === */ 8075 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 8076 /* disable fgcg at last*/ 8077 gfx_v10_0_update_fine_grain_clock_gating(adev, enable); 8078 } 8079 8080 if (adev->cg_flags & 8081 (AMD_CG_SUPPORT_GFX_MGCG | 8082 AMD_CG_SUPPORT_GFX_CGLS | 8083 AMD_CG_SUPPORT_GFX_CGCG | 8084 AMD_CG_SUPPORT_GFX_3D_CGCG | 8085 AMD_CG_SUPPORT_GFX_3D_CGLS)) 8086 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 8087 8088 amdgpu_gfx_rlc_exit_safe_mode(adev); 8089 8090 return 0; 8091 } 8092 8093 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 8094 { 8095 u32 reg, data; 8096 8097 amdgpu_gfx_off_ctrl(adev, false); 8098 8099 /* not for *_SOC15 */ 8100 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); 8101 if (amdgpu_sriov_is_pp_one_vf(adev)) 8102 data = RREG32_NO_KIQ(reg); 8103 else 8104 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); 8105 8106 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 8107 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 8108 8109 if (amdgpu_sriov_is_pp_one_vf(adev)) 8110 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); 8111 else 8112 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); 8113 8114 amdgpu_gfx_off_ctrl(adev, true); 8115 } 8116 8117 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev, 8118 uint32_t offset, 8119 struct soc15_reg_rlcg *entries, int arr_size) 8120 { 8121 int i; 8122 uint32_t reg; 8123 8124 if (!entries) 8125 return false; 8126 8127 for (i = 0; i < arr_size; i++) { 8128 const struct soc15_reg_rlcg *entry; 8129 8130 entry = &entries[i]; 8131 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; 8132 if (offset == reg) 8133 return true; 8134 } 8135 8136 return false; 8137 } 8138 8139 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset) 8140 { 8141 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0); 8142 } 8143 8144 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable) 8145 { 8146 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 8147 8148 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) 8149 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8150 else 8151 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK; 8152 8153 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data); 8154 8155 /* 8156 * CGPG enablement required and the register to program the hysteresis value 8157 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value 8158 * in refclk count. Note that RLC FW is modified to take 16 bits from 8159 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits. 8160 * 8161 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part) 8162 * of CGPG enablement starting point. 8163 * Power/performance team will optimize it and might give a new value later. 8164 */ 8165 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) { 8166 switch (adev->ip_versions[GC_HWIP][0]) { 8167 case IP_VERSION(10, 3, 1): 8168 case IP_VERSION(10, 3, 3): 8169 case IP_VERSION(10, 3, 6): 8170 case IP_VERSION(10, 3, 7): 8171 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh; 8172 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data); 8173 break; 8174 default: 8175 break; 8176 } 8177 } 8178 } 8179 8180 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable) 8181 { 8182 amdgpu_gfx_rlc_enter_safe_mode(adev); 8183 8184 gfx_v10_cntl_power_gating(adev, enable); 8185 8186 amdgpu_gfx_rlc_exit_safe_mode(adev); 8187 } 8188 8189 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 8190 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8191 .set_safe_mode = gfx_v10_0_set_safe_mode, 8192 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8193 .init = gfx_v10_0_rlc_init, 8194 .get_csb_size = gfx_v10_0_get_csb_size, 8195 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8196 .resume = gfx_v10_0_rlc_resume, 8197 .stop = gfx_v10_0_rlc_stop, 8198 .reset = gfx_v10_0_rlc_reset, 8199 .start = gfx_v10_0_rlc_start, 8200 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8201 }; 8202 8203 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = { 8204 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 8205 .set_safe_mode = gfx_v10_0_set_safe_mode, 8206 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 8207 .init = gfx_v10_0_rlc_init, 8208 .get_csb_size = gfx_v10_0_get_csb_size, 8209 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 8210 .resume = gfx_v10_0_rlc_resume, 8211 .stop = gfx_v10_0_rlc_stop, 8212 .reset = gfx_v10_0_rlc_reset, 8213 .start = gfx_v10_0_rlc_start, 8214 .update_spm_vmid = gfx_v10_0_update_spm_vmid, 8215 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, 8216 }; 8217 8218 static int gfx_v10_0_set_powergating_state(void *handle, 8219 enum amd_powergating_state state) 8220 { 8221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8222 bool enable = (state == AMD_PG_STATE_GATE); 8223 8224 if (amdgpu_sriov_vf(adev)) 8225 return 0; 8226 8227 switch (adev->ip_versions[GC_HWIP][0]) { 8228 case IP_VERSION(10, 1, 10): 8229 case IP_VERSION(10, 1, 1): 8230 case IP_VERSION(10, 1, 2): 8231 case IP_VERSION(10, 3, 0): 8232 case IP_VERSION(10, 3, 2): 8233 case IP_VERSION(10, 3, 4): 8234 case IP_VERSION(10, 3, 5): 8235 amdgpu_gfx_off_ctrl(adev, enable); 8236 break; 8237 case IP_VERSION(10, 3, 1): 8238 case IP_VERSION(10, 3, 3): 8239 case IP_VERSION(10, 3, 6): 8240 case IP_VERSION(10, 3, 7): 8241 gfx_v10_cntl_pg(adev, enable); 8242 amdgpu_gfx_off_ctrl(adev, enable); 8243 break; 8244 default: 8245 break; 8246 } 8247 return 0; 8248 } 8249 8250 static int gfx_v10_0_set_clockgating_state(void *handle, 8251 enum amd_clockgating_state state) 8252 { 8253 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8254 8255 if (amdgpu_sriov_vf(adev)) 8256 return 0; 8257 8258 switch (adev->ip_versions[GC_HWIP][0]) { 8259 case IP_VERSION(10, 1, 10): 8260 case IP_VERSION(10, 1, 1): 8261 case IP_VERSION(10, 1, 2): 8262 case IP_VERSION(10, 3, 0): 8263 case IP_VERSION(10, 3, 2): 8264 case IP_VERSION(10, 3, 1): 8265 case IP_VERSION(10, 3, 4): 8266 case IP_VERSION(10, 3, 5): 8267 case IP_VERSION(10, 3, 6): 8268 case IP_VERSION(10, 3, 3): 8269 case IP_VERSION(10, 3, 7): 8270 gfx_v10_0_update_gfx_clock_gating(adev, 8271 state == AMD_CG_STATE_GATE); 8272 break; 8273 default: 8274 break; 8275 } 8276 return 0; 8277 } 8278 8279 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags) 8280 { 8281 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 8282 int data; 8283 8284 /* AMD_CG_SUPPORT_GFX_FGCG */ 8285 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8286 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 8287 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 8288 8289 /* AMD_CG_SUPPORT_GFX_MGCG */ 8290 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE)); 8291 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 8292 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 8293 8294 /* AMD_CG_SUPPORT_GFX_CGCG */ 8295 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); 8296 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 8297 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 8298 8299 /* AMD_CG_SUPPORT_GFX_CGLS */ 8300 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 8301 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 8302 8303 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 8304 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL)); 8305 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 8306 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 8307 8308 /* AMD_CG_SUPPORT_GFX_CP_LS */ 8309 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); 8310 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 8311 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 8312 8313 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 8314 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D)); 8315 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 8316 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 8317 8318 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 8319 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 8320 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 8321 } 8322 8323 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 8324 { 8325 /* gfx10 is 32bit rptr*/ 8326 return *(uint32_t *)ring->rptr_cpu_addr; 8327 } 8328 8329 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 8330 { 8331 struct amdgpu_device *adev = ring->adev; 8332 u64 wptr; 8333 8334 /* XXX check if swapping is necessary on BE */ 8335 if (ring->use_doorbell) { 8336 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8337 } else { 8338 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 8339 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 8340 } 8341 8342 return wptr; 8343 } 8344 8345 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 8346 { 8347 struct amdgpu_device *adev = ring->adev; 8348 uint32_t *wptr_saved; 8349 uint32_t *is_queue_unmap; 8350 uint64_t aggregated_db_index; 8351 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size; 8352 uint64_t wptr_tmp; 8353 8354 if (ring->is_mes_queue) { 8355 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8356 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8357 sizeof(uint32_t)); 8358 aggregated_db_index = 8359 amdgpu_mes_get_aggregated_doorbell_index(adev, 8360 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8361 8362 wptr_tmp = ring->wptr & ring->buf_mask; 8363 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8364 *wptr_saved = wptr_tmp; 8365 /* assume doorbell always being used by mes mapped queue */ 8366 if (*is_queue_unmap) { 8367 WDOORBELL64(aggregated_db_index, wptr_tmp); 8368 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8369 } else { 8370 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8371 8372 if (*is_queue_unmap) 8373 WDOORBELL64(aggregated_db_index, wptr_tmp); 8374 } 8375 } else { 8376 if (ring->use_doorbell) { 8377 /* XXX check if swapping is necessary on BE */ 8378 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8379 ring->wptr); 8380 WDOORBELL64(ring->doorbell_index, ring->wptr); 8381 } else { 8382 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, 8383 lower_32_bits(ring->wptr)); 8384 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, 8385 upper_32_bits(ring->wptr)); 8386 } 8387 } 8388 } 8389 8390 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 8391 { 8392 /* gfx10 hardware is 32bit rptr */ 8393 return *(uint32_t *)ring->rptr_cpu_addr; 8394 } 8395 8396 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 8397 { 8398 u64 wptr; 8399 8400 /* XXX check if swapping is necessary on BE */ 8401 if (ring->use_doorbell) 8402 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 8403 else 8404 BUG(); 8405 return wptr; 8406 } 8407 8408 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 8409 { 8410 struct amdgpu_device *adev = ring->adev; 8411 uint32_t *wptr_saved; 8412 uint32_t *is_queue_unmap; 8413 uint64_t aggregated_db_index; 8414 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size; 8415 uint64_t wptr_tmp; 8416 8417 if (ring->is_mes_queue) { 8418 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size); 8419 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size + 8420 sizeof(uint32_t)); 8421 aggregated_db_index = 8422 amdgpu_mes_get_aggregated_doorbell_index(adev, 8423 AMDGPU_MES_PRIORITY_LEVEL_NORMAL); 8424 8425 wptr_tmp = ring->wptr & ring->buf_mask; 8426 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp); 8427 *wptr_saved = wptr_tmp; 8428 /* assume doorbell always used by mes mapped queue */ 8429 if (*is_queue_unmap) { 8430 WDOORBELL64(aggregated_db_index, wptr_tmp); 8431 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8432 } else { 8433 WDOORBELL64(ring->doorbell_index, wptr_tmp); 8434 8435 if (*is_queue_unmap) 8436 WDOORBELL64(aggregated_db_index, wptr_tmp); 8437 } 8438 } else { 8439 /* XXX check if swapping is necessary on BE */ 8440 if (ring->use_doorbell) { 8441 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 8442 ring->wptr); 8443 WDOORBELL64(ring->doorbell_index, ring->wptr); 8444 } else { 8445 BUG(); /* only DOORBELL method supported on gfx10 now */ 8446 } 8447 } 8448 } 8449 8450 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 8451 { 8452 struct amdgpu_device *adev = ring->adev; 8453 u32 ref_and_mask, reg_mem_engine; 8454 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg; 8455 8456 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 8457 switch (ring->me) { 8458 case 1: 8459 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 8460 break; 8461 case 2: 8462 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 8463 break; 8464 default: 8465 return; 8466 } 8467 reg_mem_engine = 0; 8468 } else { 8469 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 8470 reg_mem_engine = 1; /* pfp */ 8471 } 8472 8473 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 8474 adev->nbio.funcs->get_hdp_flush_req_offset(adev), 8475 adev->nbio.funcs->get_hdp_flush_done_offset(adev), 8476 ref_and_mask, ref_and_mask, 0x20); 8477 } 8478 8479 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 8480 struct amdgpu_job *job, 8481 struct amdgpu_ib *ib, 8482 uint32_t flags) 8483 { 8484 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8485 u32 header, control = 0; 8486 8487 if (ib->flags & AMDGPU_IB_FLAG_CE) 8488 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 8489 else 8490 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 8491 8492 control |= ib->length_dw | (vmid << 24); 8493 8494 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 8495 control |= INDIRECT_BUFFER_PRE_ENB(1); 8496 8497 if (flags & AMDGPU_IB_PREEMPTED) 8498 control |= INDIRECT_BUFFER_PRE_RESUME(1); 8499 8500 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid) 8501 gfx_v10_0_ring_emit_de_meta(ring, 8502 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8503 } 8504 8505 if (ring->is_mes_queue) 8506 /* inherit vmid from mqd */ 8507 control |= 0x400000; 8508 8509 amdgpu_ring_write(ring, header); 8510 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8511 amdgpu_ring_write(ring, 8512 #ifdef __BIG_ENDIAN 8513 (2 << 0) | 8514 #endif 8515 lower_32_bits(ib->gpu_addr)); 8516 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8517 amdgpu_ring_write(ring, control); 8518 } 8519 8520 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 8521 struct amdgpu_job *job, 8522 struct amdgpu_ib *ib, 8523 uint32_t flags) 8524 { 8525 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 8526 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 8527 8528 if (ring->is_mes_queue) 8529 /* inherit vmid from mqd */ 8530 control |= 0x40000000; 8531 8532 /* Currently, there is a high possibility to get wave ID mismatch 8533 * between ME and GDS, leading to a hw deadlock, because ME generates 8534 * different wave IDs than the GDS expects. This situation happens 8535 * randomly when at least 5 compute pipes use GDS ordered append. 8536 * The wave IDs generated by ME are also wrong after suspend/resume. 8537 * Those are probably bugs somewhere else in the kernel driver. 8538 * 8539 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 8540 * GDS to 0 for this ring (me/pipe). 8541 */ 8542 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 8543 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 8544 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 8545 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 8546 } 8547 8548 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 8549 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 8550 amdgpu_ring_write(ring, 8551 #ifdef __BIG_ENDIAN 8552 (2 << 0) | 8553 #endif 8554 lower_32_bits(ib->gpu_addr)); 8555 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 8556 amdgpu_ring_write(ring, control); 8557 } 8558 8559 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 8560 u64 seq, unsigned flags) 8561 { 8562 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 8563 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 8564 8565 /* RELEASE_MEM - flush caches, send int */ 8566 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 8567 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 8568 PACKET3_RELEASE_MEM_GCR_GL2_WB | 8569 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 8570 PACKET3_RELEASE_MEM_GCR_GLM_WB | 8571 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 8572 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 8573 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 8574 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 8575 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 8576 8577 /* 8578 * the address should be Qword aligned if 64bit write, Dword 8579 * aligned if only send 32bit data low (discard data high) 8580 */ 8581 if (write64bit) 8582 BUG_ON(addr & 0x7); 8583 else 8584 BUG_ON(addr & 0x3); 8585 amdgpu_ring_write(ring, lower_32_bits(addr)); 8586 amdgpu_ring_write(ring, upper_32_bits(addr)); 8587 amdgpu_ring_write(ring, lower_32_bits(seq)); 8588 amdgpu_ring_write(ring, upper_32_bits(seq)); 8589 amdgpu_ring_write(ring, ring->is_mes_queue ? 8590 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0); 8591 } 8592 8593 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 8594 { 8595 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8596 uint32_t seq = ring->fence_drv.sync_seq; 8597 uint64_t addr = ring->fence_drv.gpu_addr; 8598 8599 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 8600 upper_32_bits(addr), seq, 0xffffffff, 4); 8601 } 8602 8603 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring, 8604 uint16_t pasid, uint32_t flush_type, 8605 bool all_hub, uint8_t dst_sel) 8606 { 8607 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 8608 amdgpu_ring_write(ring, 8609 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) | 8610 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) | 8611 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 8612 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 8613 } 8614 8615 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 8616 unsigned vmid, uint64_t pd_addr) 8617 { 8618 if (ring->is_mes_queue) 8619 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0); 8620 else 8621 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 8622 8623 /* compute doesn't have PFP */ 8624 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 8625 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 8626 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 8627 amdgpu_ring_write(ring, 0x0); 8628 } 8629 } 8630 8631 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 8632 u64 seq, unsigned int flags) 8633 { 8634 struct amdgpu_device *adev = ring->adev; 8635 8636 /* we only allocate 32bit for each seq wb address */ 8637 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 8638 8639 /* write fence seq to the "addr" */ 8640 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8641 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8642 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 8643 amdgpu_ring_write(ring, lower_32_bits(addr)); 8644 amdgpu_ring_write(ring, upper_32_bits(addr)); 8645 amdgpu_ring_write(ring, lower_32_bits(seq)); 8646 8647 if (flags & AMDGPU_FENCE_FLAG_INT) { 8648 /* set register to trigger INT */ 8649 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8650 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 8651 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 8652 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 8653 amdgpu_ring_write(ring, 0); 8654 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 8655 } 8656 } 8657 8658 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 8659 { 8660 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 8661 amdgpu_ring_write(ring, 0); 8662 } 8663 8664 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, 8665 uint32_t flags) 8666 { 8667 uint32_t dw2 = 0; 8668 8669 if (amdgpu_mcbp) 8670 gfx_v10_0_ring_emit_ce_meta(ring, 8671 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false); 8672 8673 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 8674 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 8675 /* set load_global_config & load_global_uconfig */ 8676 dw2 |= 0x8001; 8677 /* set load_cs_sh_regs */ 8678 dw2 |= 0x01000000; 8679 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 8680 dw2 |= 0x10002; 8681 8682 /* set load_ce_ram if preamble presented */ 8683 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 8684 dw2 |= 0x10000000; 8685 } else { 8686 /* still load_ce_ram if this is the first time preamble presented 8687 * although there is no context switch happens. 8688 */ 8689 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 8690 dw2 |= 0x10000000; 8691 } 8692 8693 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 8694 amdgpu_ring_write(ring, dw2); 8695 amdgpu_ring_write(ring, 0); 8696 } 8697 8698 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 8699 { 8700 unsigned ret; 8701 8702 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 8703 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 8704 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 8705 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 8706 ret = ring->wptr & ring->buf_mask; 8707 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 8708 8709 return ret; 8710 } 8711 8712 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 8713 { 8714 unsigned cur; 8715 BUG_ON(offset > ring->buf_mask); 8716 BUG_ON(ring->ring[offset] != 0x55aa55aa); 8717 8718 cur = (ring->wptr - 1) & ring->buf_mask; 8719 if (likely(cur > offset)) 8720 ring->ring[offset] = cur - offset; 8721 else 8722 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 8723 } 8724 8725 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 8726 { 8727 int i, r = 0; 8728 struct amdgpu_device *adev = ring->adev; 8729 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 8730 struct amdgpu_ring *kiq_ring = &kiq->ring; 8731 unsigned long flags; 8732 8733 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 8734 return -EINVAL; 8735 8736 spin_lock_irqsave(&kiq->ring_lock, flags); 8737 8738 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 8739 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8740 return -ENOMEM; 8741 } 8742 8743 /* assert preemption condition */ 8744 amdgpu_ring_set_preempt_cond_exec(ring, false); 8745 8746 /* assert IB preemption, emit the trailing fence */ 8747 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 8748 ring->trail_fence_gpu_addr, 8749 ++ring->trail_seq); 8750 amdgpu_ring_commit(kiq_ring); 8751 8752 spin_unlock_irqrestore(&kiq->ring_lock, flags); 8753 8754 /* poll the trailing fence */ 8755 for (i = 0; i < adev->usec_timeout; i++) { 8756 if (ring->trail_seq == 8757 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 8758 break; 8759 udelay(1); 8760 } 8761 8762 if (i >= adev->usec_timeout) { 8763 r = -EINVAL; 8764 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 8765 } 8766 8767 /* deassert preemption condition */ 8768 amdgpu_ring_set_preempt_cond_exec(ring, true); 8769 return r; 8770 } 8771 8772 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 8773 { 8774 struct amdgpu_device *adev = ring->adev; 8775 struct v10_ce_ib_state ce_payload = {0}; 8776 uint64_t offset, ce_payload_gpu_addr; 8777 void *ce_payload_cpu_addr; 8778 int cnt; 8779 8780 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 8781 8782 if (ring->is_mes_queue) { 8783 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8784 gfx[0].gfx_meta_data) + 8785 offsetof(struct v10_gfx_meta_data, ce_payload); 8786 ce_payload_gpu_addr = 8787 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8788 ce_payload_cpu_addr = 8789 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8790 } else { 8791 offset = offsetof(struct v10_gfx_meta_data, ce_payload); 8792 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8793 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8794 } 8795 8796 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8797 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 8798 WRITE_DATA_DST_SEL(8) | 8799 WR_CONFIRM) | 8800 WRITE_DATA_CACHE_POLICY(0)); 8801 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr)); 8802 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr)); 8803 8804 if (resume) 8805 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr, 8806 sizeof(ce_payload) >> 2); 8807 else 8808 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 8809 sizeof(ce_payload) >> 2); 8810 } 8811 8812 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 8813 { 8814 struct amdgpu_device *adev = ring->adev; 8815 struct v10_de_ib_state de_payload = {0}; 8816 uint64_t offset, gds_addr, de_payload_gpu_addr; 8817 void *de_payload_cpu_addr; 8818 int cnt; 8819 8820 if (ring->is_mes_queue) { 8821 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8822 gfx[0].gfx_meta_data) + 8823 offsetof(struct v10_gfx_meta_data, de_payload); 8824 de_payload_gpu_addr = 8825 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8826 de_payload_cpu_addr = 8827 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset); 8828 8829 offset = offsetof(struct amdgpu_mes_ctx_meta_data, 8830 gfx[0].gds_backup) + 8831 offsetof(struct v10_gfx_meta_data, de_payload); 8832 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset); 8833 } else { 8834 offset = offsetof(struct v10_gfx_meta_data, de_payload); 8835 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset; 8836 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset; 8837 8838 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) + 8839 AMDGPU_CSA_SIZE - adev->gds.gds_size, 8840 PAGE_SIZE); 8841 } 8842 8843 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 8844 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 8845 8846 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 8847 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 8848 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 8849 WRITE_DATA_DST_SEL(8) | 8850 WR_CONFIRM) | 8851 WRITE_DATA_CACHE_POLICY(0)); 8852 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr)); 8853 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr)); 8854 8855 if (resume) 8856 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr, 8857 sizeof(de_payload) >> 2); 8858 else 8859 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 8860 sizeof(de_payload) >> 2); 8861 } 8862 8863 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, 8864 bool secure) 8865 { 8866 uint32_t v = secure ? FRAME_TMZ : 0; 8867 8868 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 8869 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1)); 8870 } 8871 8872 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg, 8873 uint32_t reg_val_offs) 8874 { 8875 struct amdgpu_device *adev = ring->adev; 8876 8877 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 8878 amdgpu_ring_write(ring, 0 | /* src: register*/ 8879 (5 << 8) | /* dst: memory */ 8880 (1 << 20)); /* write confirm */ 8881 amdgpu_ring_write(ring, reg); 8882 amdgpu_ring_write(ring, 0); 8883 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 8884 reg_val_offs * 4)); 8885 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 8886 reg_val_offs * 4)); 8887 } 8888 8889 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 8890 uint32_t val) 8891 { 8892 uint32_t cmd = 0; 8893 8894 switch (ring->funcs->type) { 8895 case AMDGPU_RING_TYPE_GFX: 8896 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 8897 break; 8898 case AMDGPU_RING_TYPE_KIQ: 8899 cmd = (1 << 16); /* no inc addr */ 8900 break; 8901 default: 8902 cmd = WR_CONFIRM; 8903 break; 8904 } 8905 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 8906 amdgpu_ring_write(ring, cmd); 8907 amdgpu_ring_write(ring, reg); 8908 amdgpu_ring_write(ring, 0); 8909 amdgpu_ring_write(ring, val); 8910 } 8911 8912 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 8913 uint32_t val, uint32_t mask) 8914 { 8915 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 8916 } 8917 8918 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 8919 uint32_t reg0, uint32_t reg1, 8920 uint32_t ref, uint32_t mask) 8921 { 8922 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 8923 struct amdgpu_device *adev = ring->adev; 8924 bool fw_version_ok = false; 8925 8926 fw_version_ok = adev->gfx.cp_fw_write_wait; 8927 8928 if (fw_version_ok) 8929 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, 8930 ref, mask, 0x20); 8931 else 8932 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, 8933 ref, mask); 8934 } 8935 8936 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, 8937 unsigned vmid) 8938 { 8939 struct amdgpu_device *adev = ring->adev; 8940 uint32_t value = 0; 8941 8942 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); 8943 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); 8944 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); 8945 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); 8946 WREG32_SOC15(GC, 0, mmSQ_CMD, value); 8947 } 8948 8949 static void 8950 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 8951 uint32_t me, uint32_t pipe, 8952 enum amdgpu_interrupt_state state) 8953 { 8954 uint32_t cp_int_cntl, cp_int_cntl_reg; 8955 8956 if (!me) { 8957 switch (pipe) { 8958 case 0: 8959 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 8960 break; 8961 case 1: 8962 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 8963 break; 8964 default: 8965 DRM_DEBUG("invalid pipe %d\n", pipe); 8966 return; 8967 } 8968 } else { 8969 DRM_DEBUG("invalid me %d\n", me); 8970 return; 8971 } 8972 8973 switch (state) { 8974 case AMDGPU_IRQ_STATE_DISABLE: 8975 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8976 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8977 TIME_STAMP_INT_ENABLE, 0); 8978 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8979 break; 8980 case AMDGPU_IRQ_STATE_ENABLE: 8981 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8982 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8983 TIME_STAMP_INT_ENABLE, 1); 8984 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8985 break; 8986 default: 8987 break; 8988 } 8989 } 8990 8991 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 8992 int me, int pipe, 8993 enum amdgpu_interrupt_state state) 8994 { 8995 u32 mec_int_cntl, mec_int_cntl_reg; 8996 8997 /* 8998 * amdgpu controls only the first MEC. That's why this function only 8999 * handles the setting of interrupts for this specific MEC. All other 9000 * pipes' interrupts are set by amdkfd. 9001 */ 9002 9003 if (me == 1) { 9004 switch (pipe) { 9005 case 0: 9006 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9007 break; 9008 case 1: 9009 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 9010 break; 9011 case 2: 9012 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 9013 break; 9014 case 3: 9015 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 9016 break; 9017 default: 9018 DRM_DEBUG("invalid pipe %d\n", pipe); 9019 return; 9020 } 9021 } else { 9022 DRM_DEBUG("invalid me %d\n", me); 9023 return; 9024 } 9025 9026 switch (state) { 9027 case AMDGPU_IRQ_STATE_DISABLE: 9028 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9029 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9030 TIME_STAMP_INT_ENABLE, 0); 9031 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9032 break; 9033 case AMDGPU_IRQ_STATE_ENABLE: 9034 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg); 9035 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 9036 TIME_STAMP_INT_ENABLE, 1); 9037 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl); 9038 break; 9039 default: 9040 break; 9041 } 9042 } 9043 9044 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 9045 struct amdgpu_irq_src *src, 9046 unsigned type, 9047 enum amdgpu_interrupt_state state) 9048 { 9049 switch (type) { 9050 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 9051 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 9052 break; 9053 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 9054 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 9055 break; 9056 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 9057 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 9058 break; 9059 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 9060 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 9061 break; 9062 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 9063 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 9064 break; 9065 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 9066 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 9067 break; 9068 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 9069 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 9070 break; 9071 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 9072 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 9073 break; 9074 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 9075 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 9076 break; 9077 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 9078 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 9079 break; 9080 default: 9081 break; 9082 } 9083 return 0; 9084 } 9085 9086 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 9087 struct amdgpu_irq_src *source, 9088 struct amdgpu_iv_entry *entry) 9089 { 9090 int i; 9091 u8 me_id, pipe_id, queue_id; 9092 struct amdgpu_ring *ring; 9093 uint32_t mes_queue_id = entry->src_data[0]; 9094 9095 DRM_DEBUG("IH: CP EOP\n"); 9096 9097 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) { 9098 struct amdgpu_mes_queue *queue; 9099 9100 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK; 9101 9102 spin_lock(&adev->mes.queue_id_lock); 9103 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id); 9104 if (queue) { 9105 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id); 9106 amdgpu_fence_process(queue->ring); 9107 } 9108 spin_unlock(&adev->mes.queue_id_lock); 9109 } else { 9110 me_id = (entry->ring_id & 0x0c) >> 2; 9111 pipe_id = (entry->ring_id & 0x03) >> 0; 9112 queue_id = (entry->ring_id & 0x70) >> 4; 9113 9114 switch (me_id) { 9115 case 0: 9116 if (pipe_id == 0) 9117 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 9118 else 9119 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 9120 break; 9121 case 1: 9122 case 2: 9123 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9124 ring = &adev->gfx.compute_ring[i]; 9125 /* Per-queue interrupt is supported for MEC starting from VI. 9126 * The interrupt can only be enabled/disabled per pipe instead 9127 * of per queue. 9128 */ 9129 if ((ring->me == me_id) && 9130 (ring->pipe == pipe_id) && 9131 (ring->queue == queue_id)) 9132 amdgpu_fence_process(ring); 9133 } 9134 break; 9135 } 9136 } 9137 9138 return 0; 9139 } 9140 9141 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 9142 struct amdgpu_irq_src *source, 9143 unsigned type, 9144 enum amdgpu_interrupt_state state) 9145 { 9146 switch (state) { 9147 case AMDGPU_IRQ_STATE_DISABLE: 9148 case AMDGPU_IRQ_STATE_ENABLE: 9149 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9150 PRIV_REG_INT_ENABLE, 9151 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9152 break; 9153 default: 9154 break; 9155 } 9156 9157 return 0; 9158 } 9159 9160 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 9161 struct amdgpu_irq_src *source, 9162 unsigned type, 9163 enum amdgpu_interrupt_state state) 9164 { 9165 switch (state) { 9166 case AMDGPU_IRQ_STATE_DISABLE: 9167 case AMDGPU_IRQ_STATE_ENABLE: 9168 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 9169 PRIV_INSTR_INT_ENABLE, 9170 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 9171 break; 9172 default: 9173 break; 9174 } 9175 9176 return 0; 9177 } 9178 9179 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 9180 struct amdgpu_iv_entry *entry) 9181 { 9182 u8 me_id, pipe_id, queue_id; 9183 struct amdgpu_ring *ring; 9184 int i; 9185 9186 me_id = (entry->ring_id & 0x0c) >> 2; 9187 pipe_id = (entry->ring_id & 0x03) >> 0; 9188 queue_id = (entry->ring_id & 0x70) >> 4; 9189 9190 switch (me_id) { 9191 case 0: 9192 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 9193 ring = &adev->gfx.gfx_ring[i]; 9194 /* we only enabled 1 gfx queue per pipe for now */ 9195 if (ring->me == me_id && ring->pipe == pipe_id) 9196 drm_sched_fault(&ring->sched); 9197 } 9198 break; 9199 case 1: 9200 case 2: 9201 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 9202 ring = &adev->gfx.compute_ring[i]; 9203 if (ring->me == me_id && ring->pipe == pipe_id && 9204 ring->queue == queue_id) 9205 drm_sched_fault(&ring->sched); 9206 } 9207 break; 9208 default: 9209 BUG(); 9210 } 9211 } 9212 9213 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 9214 struct amdgpu_irq_src *source, 9215 struct amdgpu_iv_entry *entry) 9216 { 9217 DRM_ERROR("Illegal register access in command stream\n"); 9218 gfx_v10_0_handle_priv_fault(adev, entry); 9219 return 0; 9220 } 9221 9222 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 9223 struct amdgpu_irq_src *source, 9224 struct amdgpu_iv_entry *entry) 9225 { 9226 DRM_ERROR("Illegal instruction in command stream\n"); 9227 gfx_v10_0_handle_priv_fault(adev, entry); 9228 return 0; 9229 } 9230 9231 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 9232 struct amdgpu_irq_src *src, 9233 unsigned int type, 9234 enum amdgpu_interrupt_state state) 9235 { 9236 uint32_t tmp, target; 9237 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9238 9239 if (ring->me == 1) 9240 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 9241 else 9242 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 9243 target += ring->pipe; 9244 9245 switch (type) { 9246 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 9247 if (state == AMDGPU_IRQ_STATE_DISABLE) { 9248 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9249 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9250 GENERIC2_INT_ENABLE, 0); 9251 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9252 9253 tmp = RREG32_SOC15_IP(GC, target); 9254 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9255 GENERIC2_INT_ENABLE, 0); 9256 WREG32_SOC15_IP(GC, target, tmp); 9257 } else { 9258 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 9259 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 9260 GENERIC2_INT_ENABLE, 1); 9261 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 9262 9263 tmp = RREG32_SOC15_IP(GC, target); 9264 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 9265 GENERIC2_INT_ENABLE, 1); 9266 WREG32_SOC15_IP(GC, target, tmp); 9267 } 9268 break; 9269 default: 9270 BUG(); /* kiq only support GENERIC2_INT now */ 9271 break; 9272 } 9273 return 0; 9274 } 9275 9276 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 9277 struct amdgpu_irq_src *source, 9278 struct amdgpu_iv_entry *entry) 9279 { 9280 u8 me_id, pipe_id, queue_id; 9281 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 9282 9283 me_id = (entry->ring_id & 0x0c) >> 2; 9284 pipe_id = (entry->ring_id & 0x03) >> 0; 9285 queue_id = (entry->ring_id & 0x70) >> 4; 9286 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 9287 me_id, pipe_id, queue_id); 9288 9289 amdgpu_fence_process(ring); 9290 return 0; 9291 } 9292 9293 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring) 9294 { 9295 const unsigned int gcr_cntl = 9296 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) | 9297 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) | 9298 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) | 9299 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) | 9300 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) | 9301 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) | 9302 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) | 9303 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1); 9304 9305 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 9306 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 9307 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 9308 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 9309 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 9310 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 9311 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 9312 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 9313 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 9314 } 9315 9316 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 9317 .name = "gfx_v10_0", 9318 .early_init = gfx_v10_0_early_init, 9319 .late_init = gfx_v10_0_late_init, 9320 .sw_init = gfx_v10_0_sw_init, 9321 .sw_fini = gfx_v10_0_sw_fini, 9322 .hw_init = gfx_v10_0_hw_init, 9323 .hw_fini = gfx_v10_0_hw_fini, 9324 .suspend = gfx_v10_0_suspend, 9325 .resume = gfx_v10_0_resume, 9326 .is_idle = gfx_v10_0_is_idle, 9327 .wait_for_idle = gfx_v10_0_wait_for_idle, 9328 .soft_reset = gfx_v10_0_soft_reset, 9329 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 9330 .set_powergating_state = gfx_v10_0_set_powergating_state, 9331 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 9332 }; 9333 9334 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 9335 .type = AMDGPU_RING_TYPE_GFX, 9336 .align_mask = 0xff, 9337 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9338 .support_64bit_ptrs = true, 9339 .secure_submission_supported = true, 9340 .vmhub = AMDGPU_GFXHUB_0, 9341 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 9342 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 9343 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 9344 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 9345 5 + /* COND_EXEC */ 9346 7 + /* PIPELINE_SYNC */ 9347 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9348 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9349 2 + /* VM_FLUSH */ 9350 8 + /* FENCE for VM_FLUSH */ 9351 20 + /* GDS switch */ 9352 4 + /* double SWITCH_BUFFER, 9353 * the first COND_EXEC jump to the place 9354 * just prior to this double SWITCH_BUFFER 9355 */ 9356 5 + /* COND_EXEC */ 9357 7 + /* HDP_flush */ 9358 4 + /* VGT_flush */ 9359 14 + /* CE_META */ 9360 31 + /* DE_META */ 9361 3 + /* CNTX_CTRL */ 9362 5 + /* HDP_INVL */ 9363 8 + 8 + /* FENCE x2 */ 9364 2 + /* SWITCH_BUFFER */ 9365 8, /* gfx_v10_0_emit_mem_sync */ 9366 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */ 9367 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 9368 .emit_fence = gfx_v10_0_ring_emit_fence, 9369 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9370 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9371 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9372 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9373 .test_ring = gfx_v10_0_ring_test_ring, 9374 .test_ib = gfx_v10_0_ring_test_ib, 9375 .insert_nop = amdgpu_ring_insert_nop, 9376 .pad_ib = amdgpu_ring_generic_pad_ib, 9377 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 9378 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 9379 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 9380 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 9381 .preempt_ib = gfx_v10_0_ring_preempt_ib, 9382 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl, 9383 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9384 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9385 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9386 .soft_recovery = gfx_v10_0_ring_soft_recovery, 9387 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9388 }; 9389 9390 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 9391 .type = AMDGPU_RING_TYPE_COMPUTE, 9392 .align_mask = 0xff, 9393 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9394 .support_64bit_ptrs = true, 9395 .vmhub = AMDGPU_GFXHUB_0, 9396 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9397 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9398 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9399 .emit_frame_size = 9400 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9401 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9402 5 + /* hdp invalidate */ 9403 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9404 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9405 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9406 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9407 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 9408 8, /* gfx_v10_0_emit_mem_sync */ 9409 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9410 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9411 .emit_fence = gfx_v10_0_ring_emit_fence, 9412 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 9413 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 9414 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 9415 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 9416 .test_ring = gfx_v10_0_ring_test_ring, 9417 .test_ib = gfx_v10_0_ring_test_ib, 9418 .insert_nop = amdgpu_ring_insert_nop, 9419 .pad_ib = amdgpu_ring_generic_pad_ib, 9420 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9421 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9422 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9423 .emit_mem_sync = gfx_v10_0_emit_mem_sync, 9424 }; 9425 9426 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 9427 .type = AMDGPU_RING_TYPE_KIQ, 9428 .align_mask = 0xff, 9429 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 9430 .support_64bit_ptrs = true, 9431 .vmhub = AMDGPU_GFXHUB_0, 9432 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 9433 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 9434 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 9435 .emit_frame_size = 9436 20 + /* gfx_v10_0_ring_emit_gds_switch */ 9437 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 9438 5 + /*hdp invalidate */ 9439 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 9440 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 9441 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 9442 2 + /* gfx_v10_0_ring_emit_vm_flush */ 9443 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 9444 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 9445 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 9446 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 9447 .test_ring = gfx_v10_0_ring_test_ring, 9448 .test_ib = gfx_v10_0_ring_test_ib, 9449 .insert_nop = amdgpu_ring_insert_nop, 9450 .pad_ib = amdgpu_ring_generic_pad_ib, 9451 .emit_rreg = gfx_v10_0_ring_emit_rreg, 9452 .emit_wreg = gfx_v10_0_ring_emit_wreg, 9453 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 9454 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, 9455 }; 9456 9457 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 9458 { 9459 int i; 9460 9461 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 9462 9463 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 9464 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 9465 9466 for (i = 0; i < adev->gfx.num_compute_rings; i++) 9467 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 9468 } 9469 9470 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 9471 .set = gfx_v10_0_set_eop_interrupt_state, 9472 .process = gfx_v10_0_eop_irq, 9473 }; 9474 9475 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 9476 .set = gfx_v10_0_set_priv_reg_fault_state, 9477 .process = gfx_v10_0_priv_reg_irq, 9478 }; 9479 9480 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 9481 .set = gfx_v10_0_set_priv_inst_fault_state, 9482 .process = gfx_v10_0_priv_inst_irq, 9483 }; 9484 9485 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 9486 .set = gfx_v10_0_kiq_set_interrupt_state, 9487 .process = gfx_v10_0_kiq_irq, 9488 }; 9489 9490 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 9491 { 9492 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 9493 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 9494 9495 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 9496 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 9497 9498 adev->gfx.priv_reg_irq.num_types = 1; 9499 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 9500 9501 adev->gfx.priv_inst_irq.num_types = 1; 9502 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 9503 } 9504 9505 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 9506 { 9507 switch (adev->ip_versions[GC_HWIP][0]) { 9508 case IP_VERSION(10, 1, 10): 9509 case IP_VERSION(10, 1, 1): 9510 case IP_VERSION(10, 1, 3): 9511 case IP_VERSION(10, 1, 4): 9512 case IP_VERSION(10, 3, 2): 9513 case IP_VERSION(10, 3, 1): 9514 case IP_VERSION(10, 3, 4): 9515 case IP_VERSION(10, 3, 5): 9516 case IP_VERSION(10, 3, 6): 9517 case IP_VERSION(10, 3, 3): 9518 case IP_VERSION(10, 3, 7): 9519 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 9520 break; 9521 case IP_VERSION(10, 1, 2): 9522 case IP_VERSION(10, 3, 0): 9523 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov; 9524 break; 9525 default: 9526 break; 9527 } 9528 } 9529 9530 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 9531 { 9532 unsigned total_cu = adev->gfx.config.max_cu_per_sh * 9533 adev->gfx.config.max_sh_per_se * 9534 adev->gfx.config.max_shader_engines; 9535 9536 adev->gds.gds_size = 0x10000; 9537 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1; 9538 adev->gds.gws_size = 64; 9539 adev->gds.oa_size = 16; 9540 } 9541 9542 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev) 9543 { 9544 /* set gfx eng mqd */ 9545 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size = 9546 sizeof(struct v10_gfx_mqd); 9547 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd = 9548 gfx_v10_0_gfx_mqd_init; 9549 /* set compute eng mqd */ 9550 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 9551 sizeof(struct v10_compute_mqd); 9552 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 9553 gfx_v10_0_compute_mqd_init; 9554 } 9555 9556 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 9557 u32 bitmap) 9558 { 9559 u32 data; 9560 9561 if (!bitmap) 9562 return; 9563 9564 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9565 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9566 9567 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 9568 } 9569 9570 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 9571 { 9572 u32 disabled_mask = 9573 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 9574 u32 efuse_setting = 0; 9575 u32 vbios_setting = 0; 9576 9577 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 9578 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9579 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9580 9581 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 9582 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 9583 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 9584 9585 disabled_mask |= efuse_setting | vbios_setting; 9586 9587 return (~disabled_mask); 9588 } 9589 9590 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 9591 { 9592 u32 wgp_idx, wgp_active_bitmap; 9593 u32 cu_bitmap_per_wgp, cu_active_bitmap; 9594 9595 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 9596 cu_active_bitmap = 0; 9597 9598 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 9599 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 9600 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 9601 if (wgp_active_bitmap & (1 << wgp_idx)) 9602 cu_active_bitmap |= cu_bitmap_per_wgp; 9603 } 9604 9605 return cu_active_bitmap; 9606 } 9607 9608 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 9609 struct amdgpu_cu_info *cu_info) 9610 { 9611 int i, j, k, counter, active_cu_number = 0; 9612 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 9613 unsigned disable_masks[4 * 2]; 9614 9615 if (!adev || !cu_info) 9616 return -EINVAL; 9617 9618 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 9619 9620 mutex_lock(&adev->grbm_idx_mutex); 9621 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 9622 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 9623 bitmap = i * adev->gfx.config.max_sh_per_se + j; 9624 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) || 9625 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) || 9626 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) || 9627 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) && 9628 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1)) 9629 continue; 9630 mask = 1; 9631 ao_bitmap = 0; 9632 counter = 0; 9633 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 9634 if (i < 4 && j < 2) 9635 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 9636 adev, disable_masks[i * 2 + j]); 9637 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 9638 cu_info->bitmap[i][j] = bitmap; 9639 9640 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 9641 if (bitmap & mask) { 9642 if (counter < adev->gfx.config.max_cu_per_sh) 9643 ao_bitmap |= mask; 9644 counter++; 9645 } 9646 mask <<= 1; 9647 } 9648 active_cu_number += counter; 9649 if (i < 2 && j < 2) 9650 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 9651 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 9652 } 9653 } 9654 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 9655 mutex_unlock(&adev->grbm_idx_mutex); 9656 9657 cu_info->number = active_cu_number; 9658 cu_info->ao_cu_mask = ao_cu_mask; 9659 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 9660 9661 return 0; 9662 } 9663 9664 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev) 9665 { 9666 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask; 9667 9668 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE); 9669 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9670 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9671 9672 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE); 9673 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK; 9674 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT; 9675 9676 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 9677 adev->gfx.config.max_shader_engines); 9678 disabled_sa = efuse_setting | vbios_setting; 9679 disabled_sa &= max_sa_mask; 9680 9681 return disabled_sa; 9682 } 9683 9684 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev) 9685 { 9686 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines; 9687 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se; 9688 9689 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev); 9690 9691 max_sa_per_se = adev->gfx.config.max_sh_per_se; 9692 max_sa_per_se_mask = (1 << max_sa_per_se) - 1; 9693 max_shader_engines = adev->gfx.config.max_shader_engines; 9694 9695 for (se_index = 0; max_shader_engines > se_index; se_index++) { 9696 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se); 9697 disabled_sa_per_se &= max_sa_per_se_mask; 9698 if (disabled_sa_per_se == max_sa_per_se_mask) { 9699 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1); 9700 break; 9701 } 9702 } 9703 } 9704 9705 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev) 9706 { 9707 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 9708 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) | 9709 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) | 9710 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); 9711 9712 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL); 9713 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, 9714 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) | 9715 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) | 9716 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) | 9717 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT)); 9718 9719 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid, 9720 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) | 9721 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) | 9722 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT)); 9723 9724 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL); 9725 9726 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA, 9727 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT)); 9728 } 9729 9730 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 9731 { 9732 .type = AMD_IP_BLOCK_TYPE_GFX, 9733 .major = 10, 9734 .minor = 0, 9735 .rev = 0, 9736 .funcs = &gfx_v10_0_ip_funcs, 9737 }; 9738