xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c (revision 06ff634c0dae791c17ceeeb60c74e14470d76898) 
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "amdgpu_smu.h"
33 #include "nv.h"
34 #include "nvd.h"
35 
36 #include "gc/gc_10_1_0_offset.h"
37 #include "gc/gc_10_1_0_sh_mask.h"
38 #include "smuio/smuio_11_0_0_offset.h"
39 #include "smuio/smuio_11_0_0_sh_mask.h"
40 #include "navi10_enum.h"
41 #include "hdp/hdp_5_0_0_offset.h"
42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
43 
44 #include "soc15.h"
45 #include "soc15d.h"
46 #include "soc15_common.h"
47 #include "clearstate_gfx10.h"
48 #include "v10_structs.h"
49 #include "gfx_v10_0.h"
50 #include "nbio_v2_3.h"
51 
52 /**
53  * Navi10 has two graphic rings to share each graphic pipe.
54  * 1. Primary ring
55  * 2. Async ring
56  */
57 #define GFX10_NUM_GFX_RINGS_NV1X	1
58 #define GFX10_MEC_HPD_SIZE	2048
59 
60 #define F32_CE_PROGRAM_RAM_SIZE		65536
61 #define RLCG_UCODE_LOADING_START_ADDRESS	0x00002000L
62 
63 #define mmCGTT_GS_NGG_CLK_CTRL	0x5087
64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX	1
65 
66 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
67 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
68 
69 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
70 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
71 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
72 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
73 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
74 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
75 
76 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
77 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
78 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
79 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
80 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
81 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
82 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
83 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
84 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
85 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
86 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
87 
88 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
89 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
90 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
91 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
92 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
93 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
94 
95 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
96 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
97 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
98 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
99 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
100 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
101 
102 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
103 {
104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
144 };
145 
146 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
147 {
148 	/* Pending on emulation bring up */
149 };
150 
151 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
152 {
153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1205 };
1206 
1207 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1208 {
1209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1247 };
1248 
1249 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1250 {
1251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1291 };
1292 
1293 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1294 {
1295 	static void *scratch_reg0;
1296 	static void *scratch_reg1;
1297 	static void *scratch_reg2;
1298 	static void *scratch_reg3;
1299 	static void *spare_int;
1300 	static uint32_t grbm_cntl;
1301 	static uint32_t grbm_idx;
1302 	uint32_t i = 0;
1303 	uint32_t retries = 50000;
1304 
1305 	scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1306 	scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1307 	scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1308 	scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1309 	spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1310 
1311 	grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1312 	grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1313 
1314 	if (amdgpu_sriov_runtime(adev)) {
1315 		pr_err("shouldn't call rlcg write register during runtime\n");
1316 		return;
1317 	}
1318 
1319 	writel(v, scratch_reg0);
1320 	writel(offset | 0x80000000, scratch_reg1);
1321 	writel(1, spare_int);
1322 	for (i = 0; i < retries; i++) {
1323 		u32 tmp;
1324 
1325 		tmp = readl(scratch_reg1);
1326 		if (!(tmp & 0x80000000))
1327 			break;
1328 
1329 		udelay(10);
1330 	}
1331 
1332 	if (i >= retries)
1333 		pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1334 }
1335 
1336 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1337 {
1338 	/* Pending on emulation bring up */
1339 };
1340 
1341 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1342 {
1343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
1950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
1952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
1954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
1956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
1958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
1960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
1962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1963 };
1964 
1965 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
1966 {
1967 	/* Pending on emulation bring up */
1968 };
1969 
1970 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
1971 {
1972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
1973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2025 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2027 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2029 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2030 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2031 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2032 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2033 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2035 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2037 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2039 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2041 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2043 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2045 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2047 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2049 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2051 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2053 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2055 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2057 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2059 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2061 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2063 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2065 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2067 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2069 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2071 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2073 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2075 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2077 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2079 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2081 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2083 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2085 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2086 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2087 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2089 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2090 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2091 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2093 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2095 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2097 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2099 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2101 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2102 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2103 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2104 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2105 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2107 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2109 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2111 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2113 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2115 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2117 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2119 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2121 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2123 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2125 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2127 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2129 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2131 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2133 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2135 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2137 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2139 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2141 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2143 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2145 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2147 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2149 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2150 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2151 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2152 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2153 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2155 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2157 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2159 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2161 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2163 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2165 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2167 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2169 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2171 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2173 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2175 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2177 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2179 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2181 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2183 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2185 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2187 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2189 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2191 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2193 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2195 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2197 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2199 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2201 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2202 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2203 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2204 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2205 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2207 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2209 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2210 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2211 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2212 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2213 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2215 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2217 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2218 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2219 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2220 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2221 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2223 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2225 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2226 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2227 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2228 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2229 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2231 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2233 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2234 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2235 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2236 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2237 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2239 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2241 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2242 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2243 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2244 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2245 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2247 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2249 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2250 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2251 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2252 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2253 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2255 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2257 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2258 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2259 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2260 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2261 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2263 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2265 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2266 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2267 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2268 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2269 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2271 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2273 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2274 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2275 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2276 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2277 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2279 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2281 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2282 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2283 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2284 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2285 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2287 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2289 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2290 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2291 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2292 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2293 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2295 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2297 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2298 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2299 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2300 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2301 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2303 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2305 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2306 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2307 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2308 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2309 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2311 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2313 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2314 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2315 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2316 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2317 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2319 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2321 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2323 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2325 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2327 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2329 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2331 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2333 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2335 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2337 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2339 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2341 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2343 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2345 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2347 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2349 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2351 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2353 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2355 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2357 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2359 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2361 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2363 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2365 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2367 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2369 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2371 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2373 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2375 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2377 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2379 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2381 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2383 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2385 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2387 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2389 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2391 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2393 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2395 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2397 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2399 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2401 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2403 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2405 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2407 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2409 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2411 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2413 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2415 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2417 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2419 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2421 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2423 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2425 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2427 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2429 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2431 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2433 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2435 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2437 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2439 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2441 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2443 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2445 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2447 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2449 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2451 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2453 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2455 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2457 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2459 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2461 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2463 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2465 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2467 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2469 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2471 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2473 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2475 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2477 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2479 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2481 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2483 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2485 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2487 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2489 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2491 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2493 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2495 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2497 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2499 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2501 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2503 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2505 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2507 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2509 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2511 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2513 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2515 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2517 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2519 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2521 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2523 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2525 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2527 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2529 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2531 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2533 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2535 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2537 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2539 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2541 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2543 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2545 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2547 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2549 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2551 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2553 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2555 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2557 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2559 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2561 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2563 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2565 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2567 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2569 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2571 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2573 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2575 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2577 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2579 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2581 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2583 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2585 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2587 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2589 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2591 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2593 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2595 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2597 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2599 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2601 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2603 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2605 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2607 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2609 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2611 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2613 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2615 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2617 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2619 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2621 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2623 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2625 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2627 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2629 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2631 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2633 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2635 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2637 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2639 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2641 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2643 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2645 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2647 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2649 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2651 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2653 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2655 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2657 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2659 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2661 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2663 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2665 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2667 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2669 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2671 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2673 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2675 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2677 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2679 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2681 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2683 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2685 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2687 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2689 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2691 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2693 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2695 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2697 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2699 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2701 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2703 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2705 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2707 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2709 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2711 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2713 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2715 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2717 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2719 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2721 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2723 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2725 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2727 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2729 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2731 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2733 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2735 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2737 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2739 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2741 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2743 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2745 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2747 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2749 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2751 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2753 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2755 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2757 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2759 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2761 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2763 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2765 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2767 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2769 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2771 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2773 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2775 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2777 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2779 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2781 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2783 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2785 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2787 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2789 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2791 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2793 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2795 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2797 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2799 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2801 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2803 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2805 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2807 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2809 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2811 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2813 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2815 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2817 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2819 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2821 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2823 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2825 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2827 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2829 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2831 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2833 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2835 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2837 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2839 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2841 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2843 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2845 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2847 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2849 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2851 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2853 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2855 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2857 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2859 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2861 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2863 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2865 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2867 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2869 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2871 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2873 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2875 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2877 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2879 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2881 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2883 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2885 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2887 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2889 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2891 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2893 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2895 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2897 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2899 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2901 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2903 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2905 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2907 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2909 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2911 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2913 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2915 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2917 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2919 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2921 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2923 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2925 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2927 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2929 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2931 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2933 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2935 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2937 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2939 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2941 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2943 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2945 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2947 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2949 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2951 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2953 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
2955 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2957 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2959 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2961 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2963 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2965 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2967 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2969 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2971 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2973 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2975 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2977 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2979 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2981 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2983 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2985 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2986 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2987 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2988 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2989 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2991 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2993 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2995 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2997 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2999 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3001 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3003 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3005 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3007 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3009 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3010 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3011 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3012 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3013 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3015 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3016 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3017 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3018 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3019 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3021 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3023 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3024 };
3025 
3026 #define DEFAULT_SH_MEM_CONFIG \
3027 	((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3028 	 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3029 	 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3030 	 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3031 
3032 
3033 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3034 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3035 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3036 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3037 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3038                                  struct amdgpu_cu_info *cu_info);
3039 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3040 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3041 				   u32 sh_num, u32 instance);
3042 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3043 
3044 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3045 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3046 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3047 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3048 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3049 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3050 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3051 
3052 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3053 {
3054 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3055 	amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3056 			  PACKET3_SET_RESOURCES_QUEUE_TYPE(0));	/* vmid_mask:0 queue_type:0 (KIQ) */
3057 	amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask));	/* queue mask lo */
3058 	amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask));	/* queue mask hi */
3059 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask lo */
3060 	amdgpu_ring_write(kiq_ring, 0);	/* gws mask hi */
3061 	amdgpu_ring_write(kiq_ring, 0);	/* oac mask */
3062 	amdgpu_ring_write(kiq_ring, 0);	/* gds heap base:0, gds heap size:0 */
3063 }
3064 
3065 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3066 				 struct amdgpu_ring *ring)
3067 {
3068 	struct amdgpu_device *adev = kiq_ring->adev;
3069 	uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3070 	uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3071 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3072 
3073 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3074 	/* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3075 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3076 			  PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3077 			  PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3078 			  PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3079 			  PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3080 			  PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3081 			  PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3082 			  PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3083 			  PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3084 			  PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3085 	amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3086 	amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3087 	amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3088 	amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3089 	amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3090 }
3091 
3092 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3093 				   struct amdgpu_ring *ring,
3094 				   enum amdgpu_unmap_queues_action action,
3095 				   u64 gpu_addr, u64 seq)
3096 {
3097 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3098 
3099 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3100 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3101 			  PACKET3_UNMAP_QUEUES_ACTION(action) |
3102 			  PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3103 			  PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3104 			  PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3105 	amdgpu_ring_write(kiq_ring,
3106 		  PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3107 
3108 	if (action == PREEMPT_QUEUES_NO_UNMAP) {
3109 		amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3110 		amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3111 		amdgpu_ring_write(kiq_ring, seq);
3112 	} else {
3113 		amdgpu_ring_write(kiq_ring, 0);
3114 		amdgpu_ring_write(kiq_ring, 0);
3115 		amdgpu_ring_write(kiq_ring, 0);
3116 	}
3117 }
3118 
3119 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3120 				   struct amdgpu_ring *ring,
3121 				   u64 addr,
3122 				   u64 seq)
3123 {
3124 	uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3125 
3126 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3127 	amdgpu_ring_write(kiq_ring,
3128 			  PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3129 			  PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3130 			  PACKET3_QUERY_STATUS_COMMAND(2));
3131 	amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3132 			  PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3133 			  PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3134 	amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3135 	amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3136 	amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3137 	amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3138 }
3139 
3140 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3141 				uint16_t pasid, uint32_t flush_type,
3142 				bool all_hub)
3143 {
3144 	amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3145 	amdgpu_ring_write(kiq_ring,
3146 			PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3147 			PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3148 			PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3149 			PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3150 }
3151 
3152 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3153 	.kiq_set_resources = gfx10_kiq_set_resources,
3154 	.kiq_map_queues = gfx10_kiq_map_queues,
3155 	.kiq_unmap_queues = gfx10_kiq_unmap_queues,
3156 	.kiq_query_status = gfx10_kiq_query_status,
3157 	.kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3158 	.set_resources_size = 8,
3159 	.map_queues_size = 7,
3160 	.unmap_queues_size = 6,
3161 	.query_status_size = 7,
3162 	.invalidate_tlbs_size = 2,
3163 };
3164 
3165 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3166 {
3167 	adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3168 }
3169 
3170 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3171 {
3172 	switch (adev->asic_type) {
3173 	case CHIP_NAVI10:
3174 		soc15_program_register_sequence(adev,
3175 						golden_settings_gc_10_1,
3176 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3177 		soc15_program_register_sequence(adev,
3178 						golden_settings_gc_10_0_nv10,
3179 						(const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3180 		soc15_program_register_sequence(adev,
3181 						golden_settings_gc_rlc_spm_10_0_nv10,
3182 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3183 		break;
3184 	case CHIP_NAVI14:
3185 		soc15_program_register_sequence(adev,
3186 						golden_settings_gc_10_1_1,
3187 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3188 		soc15_program_register_sequence(adev,
3189 						golden_settings_gc_10_1_nv14,
3190 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3191 		soc15_program_register_sequence(adev,
3192 						golden_settings_gc_rlc_spm_10_1_nv14,
3193 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3194 		break;
3195 	case CHIP_NAVI12:
3196 		soc15_program_register_sequence(adev,
3197 						golden_settings_gc_10_1_2,
3198 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3199 		soc15_program_register_sequence(adev,
3200 						golden_settings_gc_10_1_2_nv12,
3201 						(const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3202 		soc15_program_register_sequence(adev,
3203 						golden_settings_gc_rlc_spm_10_1_2_nv12,
3204 						(const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3205 		break;
3206 	default:
3207 		break;
3208 	}
3209 }
3210 
3211 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3212 {
3213 	adev->gfx.scratch.num_reg = 8;
3214 	adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3215 	adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3216 }
3217 
3218 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3219 				       bool wc, uint32_t reg, uint32_t val)
3220 {
3221 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3222 	amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3223 			  WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3224 	amdgpu_ring_write(ring, reg);
3225 	amdgpu_ring_write(ring, 0);
3226 	amdgpu_ring_write(ring, val);
3227 }
3228 
3229 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3230 				  int mem_space, int opt, uint32_t addr0,
3231 				  uint32_t addr1, uint32_t ref, uint32_t mask,
3232 				  uint32_t inv)
3233 {
3234 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3235 	amdgpu_ring_write(ring,
3236 			  /* memory (1) or register (0) */
3237 			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3238 			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
3239 			   WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3240 			   WAIT_REG_MEM_ENGINE(eng_sel)));
3241 
3242 	if (mem_space)
3243 		BUG_ON(addr0 & 0x3); /* Dword align */
3244 	amdgpu_ring_write(ring, addr0);
3245 	amdgpu_ring_write(ring, addr1);
3246 	amdgpu_ring_write(ring, ref);
3247 	amdgpu_ring_write(ring, mask);
3248 	amdgpu_ring_write(ring, inv); /* poll interval */
3249 }
3250 
3251 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3252 {
3253 	struct amdgpu_device *adev = ring->adev;
3254 	uint32_t scratch;
3255 	uint32_t tmp = 0;
3256 	unsigned i;
3257 	int r;
3258 
3259 	r = amdgpu_gfx_scratch_get(adev, &scratch);
3260 	if (r) {
3261 		DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3262 		return r;
3263 	}
3264 
3265 	WREG32(scratch, 0xCAFEDEAD);
3266 
3267 	r = amdgpu_ring_alloc(ring, 3);
3268 	if (r) {
3269 		DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3270 			  ring->idx, r);
3271 		amdgpu_gfx_scratch_free(adev, scratch);
3272 		return r;
3273 	}
3274 
3275 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3276 	amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3277 	amdgpu_ring_write(ring, 0xDEADBEEF);
3278 	amdgpu_ring_commit(ring);
3279 
3280 	for (i = 0; i < adev->usec_timeout; i++) {
3281 		tmp = RREG32(scratch);
3282 		if (tmp == 0xDEADBEEF)
3283 			break;
3284 		if (amdgpu_emu_mode == 1)
3285 			msleep(1);
3286 		else
3287 			udelay(1);
3288 	}
3289 
3290 	if (i >= adev->usec_timeout)
3291 		r = -ETIMEDOUT;
3292 
3293 	amdgpu_gfx_scratch_free(adev, scratch);
3294 
3295 	return r;
3296 }
3297 
3298 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3299 {
3300 	struct amdgpu_device *adev = ring->adev;
3301 	struct amdgpu_ib ib;
3302 	struct dma_fence *f = NULL;
3303 	unsigned index;
3304 	uint64_t gpu_addr;
3305 	uint32_t tmp;
3306 	long r;
3307 
3308 	r = amdgpu_device_wb_get(adev, &index);
3309 	if (r)
3310 		return r;
3311 
3312 	gpu_addr = adev->wb.gpu_addr + (index * 4);
3313 	adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3314 	memset(&ib, 0, sizeof(ib));
3315 	r = amdgpu_ib_get(adev, NULL, 16,
3316 					AMDGPU_IB_POOL_DIRECT, &ib);
3317 	if (r)
3318 		goto err1;
3319 
3320 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3321 	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3322 	ib.ptr[2] = lower_32_bits(gpu_addr);
3323 	ib.ptr[3] = upper_32_bits(gpu_addr);
3324 	ib.ptr[4] = 0xDEADBEEF;
3325 	ib.length_dw = 5;
3326 
3327 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3328 	if (r)
3329 		goto err2;
3330 
3331 	r = dma_fence_wait_timeout(f, false, timeout);
3332 	if (r == 0) {
3333 		r = -ETIMEDOUT;
3334 		goto err2;
3335 	} else if (r < 0) {
3336 		goto err2;
3337 	}
3338 
3339 	tmp = adev->wb.wb[index];
3340 	if (tmp == 0xDEADBEEF)
3341 		r = 0;
3342 	else
3343 		r = -EINVAL;
3344 err2:
3345 	amdgpu_ib_free(adev, &ib, NULL);
3346 	dma_fence_put(f);
3347 err1:
3348 	amdgpu_device_wb_free(adev, index);
3349 	return r;
3350 }
3351 
3352 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3353 {
3354 	release_firmware(adev->gfx.pfp_fw);
3355 	adev->gfx.pfp_fw = NULL;
3356 	release_firmware(adev->gfx.me_fw);
3357 	adev->gfx.me_fw = NULL;
3358 	release_firmware(adev->gfx.ce_fw);
3359 	adev->gfx.ce_fw = NULL;
3360 	release_firmware(adev->gfx.rlc_fw);
3361 	adev->gfx.rlc_fw = NULL;
3362 	release_firmware(adev->gfx.mec_fw);
3363 	adev->gfx.mec_fw = NULL;
3364 	release_firmware(adev->gfx.mec2_fw);
3365 	adev->gfx.mec2_fw = NULL;
3366 
3367 	kfree(adev->gfx.rlc.register_list_format);
3368 }
3369 
3370 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3371 {
3372 	adev->gfx.cp_fw_write_wait = false;
3373 
3374 	switch (adev->asic_type) {
3375 	case CHIP_NAVI10:
3376 	case CHIP_NAVI12:
3377 	case CHIP_NAVI14:
3378 		if ((adev->gfx.me_fw_version >= 0x00000046) &&
3379 		    (adev->gfx.me_feature_version >= 27) &&
3380 		    (adev->gfx.pfp_fw_version >= 0x00000068) &&
3381 		    (adev->gfx.pfp_feature_version >= 27) &&
3382 		    (adev->gfx.mec_fw_version >= 0x0000005b) &&
3383 		    (adev->gfx.mec_feature_version >= 27))
3384 			adev->gfx.cp_fw_write_wait = true;
3385 		break;
3386 	default:
3387 		break;
3388 	}
3389 
3390 	if (adev->gfx.cp_fw_write_wait == false)
3391 		DRM_WARN_ONCE("CP firmware version too old, please update!");
3392 }
3393 
3394 
3395 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3396 {
3397 	const struct rlc_firmware_header_v2_1 *rlc_hdr;
3398 
3399 	rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3400 	adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3401 	adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3402 	adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3403 	adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3404 	adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3405 	adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3406 	adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3407 	adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3408 	adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3409 	adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3410 	adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3411 	adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3412 	adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3413 			le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3414 }
3415 
3416 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3417 {
3418 	bool ret = false;
3419 
3420 	switch (adev->pdev->revision) {
3421 	case 0xc2:
3422 	case 0xc3:
3423 		ret = true;
3424 		break;
3425 	default:
3426 		ret = false;
3427 		break;
3428 	}
3429 
3430 	return ret ;
3431 }
3432 
3433 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3434 {
3435 	switch (adev->asic_type) {
3436 	case CHIP_NAVI10:
3437 		if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3438 			adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3439 		break;
3440 	default:
3441 		break;
3442 	}
3443 }
3444 
3445 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3446 {
3447 	const char *chip_name;
3448 	char fw_name[40];
3449 	char wks[10];
3450 	int err;
3451 	struct amdgpu_firmware_info *info = NULL;
3452 	const struct common_firmware_header *header = NULL;
3453 	const struct gfx_firmware_header_v1_0 *cp_hdr;
3454 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
3455 	unsigned int *tmp = NULL;
3456 	unsigned int i = 0;
3457 	uint16_t version_major;
3458 	uint16_t version_minor;
3459 
3460 	DRM_DEBUG("\n");
3461 
3462 	memset(wks, 0, sizeof(wks));
3463 	switch (adev->asic_type) {
3464 	case CHIP_NAVI10:
3465 		chip_name = "navi10";
3466 		break;
3467 	case CHIP_NAVI14:
3468 		chip_name = "navi14";
3469 		if (!(adev->pdev->device == 0x7340 &&
3470 		      adev->pdev->revision != 0x00))
3471 			snprintf(wks, sizeof(wks), "_wks");
3472 		break;
3473 	case CHIP_NAVI12:
3474 		chip_name = "navi12";
3475 		break;
3476 	case CHIP_SIENNA_CICHLID:
3477 		chip_name = "sienna_cichlid";
3478 		break;
3479 	default:
3480 		BUG();
3481 	}
3482 
3483 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3484 	err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3485 	if (err)
3486 		goto out;
3487 	err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3488 	if (err)
3489 		goto out;
3490 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3491 	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3492 	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3493 
3494 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3495 	err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3496 	if (err)
3497 		goto out;
3498 	err = amdgpu_ucode_validate(adev->gfx.me_fw);
3499 	if (err)
3500 		goto out;
3501 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3502 	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3503 	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3504 
3505 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3506 	err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3507 	if (err)
3508 		goto out;
3509 	err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3510 	if (err)
3511 		goto out;
3512 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3513 	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3514 	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3515 
3516 	if (!amdgpu_sriov_vf(adev)) {
3517 		snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3518 		err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3519 		if (err)
3520 			goto out;
3521 		err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3522 		rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3523 		version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3524 		version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3525 		if (version_major == 2 && version_minor == 1)
3526 			adev->gfx.rlc.is_rlc_v2_1 = true;
3527 
3528 		adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3529 		adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3530 		adev->gfx.rlc.save_and_restore_offset =
3531 			le32_to_cpu(rlc_hdr->save_and_restore_offset);
3532 		adev->gfx.rlc.clear_state_descriptor_offset =
3533 			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3534 		adev->gfx.rlc.avail_scratch_ram_locations =
3535 			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3536 		adev->gfx.rlc.reg_restore_list_size =
3537 			le32_to_cpu(rlc_hdr->reg_restore_list_size);
3538 		adev->gfx.rlc.reg_list_format_start =
3539 			le32_to_cpu(rlc_hdr->reg_list_format_start);
3540 		adev->gfx.rlc.reg_list_format_separate_start =
3541 			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3542 		adev->gfx.rlc.starting_offsets_start =
3543 			le32_to_cpu(rlc_hdr->starting_offsets_start);
3544 		adev->gfx.rlc.reg_list_format_size_bytes =
3545 			le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3546 		adev->gfx.rlc.reg_list_size_bytes =
3547 			le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3548 		adev->gfx.rlc.register_list_format =
3549 			kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3550 					adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3551 		if (!adev->gfx.rlc.register_list_format) {
3552 			err = -ENOMEM;
3553 			goto out;
3554 		}
3555 
3556 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3557 							   le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3558 		for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3559 			adev->gfx.rlc.register_list_format[i] =	le32_to_cpu(tmp[i]);
3560 
3561 		adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3562 
3563 		tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3564 							   le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3565 		for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3566 			adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3567 
3568 		if (adev->gfx.rlc.is_rlc_v2_1)
3569 			gfx_v10_0_init_rlc_ext_microcode(adev);
3570 	}
3571 
3572 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3573 	err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3574 	if (err)
3575 		goto out;
3576 	err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3577 	if (err)
3578 		goto out;
3579 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3580 	adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3581 	adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3582 
3583 	snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3584 	err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3585 	if (!err) {
3586 		err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3587 		if (err)
3588 			goto out;
3589 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3590 		adev->gfx.mec2_fw->data;
3591 		adev->gfx.mec2_fw_version =
3592 		le32_to_cpu(cp_hdr->header.ucode_version);
3593 		adev->gfx.mec2_feature_version =
3594 		le32_to_cpu(cp_hdr->ucode_feature_version);
3595 	} else {
3596 		err = 0;
3597 		adev->gfx.mec2_fw = NULL;
3598 	}
3599 
3600 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3601 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3602 		info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3603 		info->fw = adev->gfx.pfp_fw;
3604 		header = (const struct common_firmware_header *)info->fw->data;
3605 		adev->firmware.fw_size +=
3606 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3607 
3608 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3609 		info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3610 		info->fw = adev->gfx.me_fw;
3611 		header = (const struct common_firmware_header *)info->fw->data;
3612 		adev->firmware.fw_size +=
3613 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3614 
3615 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3616 		info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3617 		info->fw = adev->gfx.ce_fw;
3618 		header = (const struct common_firmware_header *)info->fw->data;
3619 		adev->firmware.fw_size +=
3620 			ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3621 
3622 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3623 		info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3624 		info->fw = adev->gfx.rlc_fw;
3625 		if (info->fw) {
3626 			header = (const struct common_firmware_header *)info->fw->data;
3627 			adev->firmware.fw_size +=
3628 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3629 		}
3630 		if (adev->gfx.rlc.is_rlc_v2_1 &&
3631 		    adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3632 		    adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3633 		    adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3634 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3635 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3636 			info->fw = adev->gfx.rlc_fw;
3637 			adev->firmware.fw_size +=
3638 				ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3639 
3640 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3641 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3642 			info->fw = adev->gfx.rlc_fw;
3643 			adev->firmware.fw_size +=
3644 				ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3645 
3646 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3647 			info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3648 			info->fw = adev->gfx.rlc_fw;
3649 			adev->firmware.fw_size +=
3650 				ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3651 		}
3652 
3653 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3654 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3655 		info->fw = adev->gfx.mec_fw;
3656 		header = (const struct common_firmware_header *)info->fw->data;
3657 		cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3658 		adev->firmware.fw_size +=
3659 			ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3660 			      le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3661 
3662 		info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3663 		info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3664 		info->fw = adev->gfx.mec_fw;
3665 		adev->firmware.fw_size +=
3666 			ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3667 
3668 		if (adev->gfx.mec2_fw) {
3669 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3670 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3671 			info->fw = adev->gfx.mec2_fw;
3672 			header = (const struct common_firmware_header *)info->fw->data;
3673 			cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3674 			adev->firmware.fw_size +=
3675 				ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3676 				      le32_to_cpu(cp_hdr->jt_size) * 4,
3677 				      PAGE_SIZE);
3678 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3679 			info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3680 			info->fw = adev->gfx.mec2_fw;
3681 			adev->firmware.fw_size +=
3682 				ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3683 				      PAGE_SIZE);
3684 		}
3685 	}
3686 
3687 	gfx_v10_0_check_fw_write_wait(adev);
3688 out:
3689 	if (err) {
3690 		dev_err(adev->dev,
3691 			"gfx10: Failed to load firmware \"%s\"\n",
3692 			fw_name);
3693 		release_firmware(adev->gfx.pfp_fw);
3694 		adev->gfx.pfp_fw = NULL;
3695 		release_firmware(adev->gfx.me_fw);
3696 		adev->gfx.me_fw = NULL;
3697 		release_firmware(adev->gfx.ce_fw);
3698 		adev->gfx.ce_fw = NULL;
3699 		release_firmware(adev->gfx.rlc_fw);
3700 		adev->gfx.rlc_fw = NULL;
3701 		release_firmware(adev->gfx.mec_fw);
3702 		adev->gfx.mec_fw = NULL;
3703 		release_firmware(adev->gfx.mec2_fw);
3704 		adev->gfx.mec2_fw = NULL;
3705 	}
3706 
3707 	gfx_v10_0_check_gfxoff_flag(adev);
3708 
3709 	return err;
3710 }
3711 
3712 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3713 {
3714 	u32 count = 0;
3715 	const struct cs_section_def *sect = NULL;
3716 	const struct cs_extent_def *ext = NULL;
3717 
3718 	/* begin clear state */
3719 	count += 2;
3720 	/* context control state */
3721 	count += 3;
3722 
3723 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3724 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3725 			if (sect->id == SECT_CONTEXT)
3726 				count += 2 + ext->reg_count;
3727 			else
3728 				return 0;
3729 		}
3730 	}
3731 
3732 	/* set PA_SC_TILE_STEERING_OVERRIDE */
3733 	count += 3;
3734 	/* end clear state */
3735 	count += 2;
3736 	/* clear state */
3737 	count += 2;
3738 
3739 	return count;
3740 }
3741 
3742 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3743 				    volatile u32 *buffer)
3744 {
3745 	u32 count = 0, i;
3746 	const struct cs_section_def *sect = NULL;
3747 	const struct cs_extent_def *ext = NULL;
3748 	int ctx_reg_offset;
3749 
3750 	if (adev->gfx.rlc.cs_data == NULL)
3751 		return;
3752 	if (buffer == NULL)
3753 		return;
3754 
3755 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3756 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3757 
3758 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3759 	buffer[count++] = cpu_to_le32(0x80000000);
3760 	buffer[count++] = cpu_to_le32(0x80000000);
3761 
3762 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3763 		for (ext = sect->section; ext->extent != NULL; ++ext) {
3764 			if (sect->id == SECT_CONTEXT) {
3765 				buffer[count++] =
3766 					cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3767 				buffer[count++] = cpu_to_le32(ext->reg_index -
3768 						PACKET3_SET_CONTEXT_REG_START);
3769 				for (i = 0; i < ext->reg_count; i++)
3770 					buffer[count++] = cpu_to_le32(ext->extent[i]);
3771 			} else {
3772 				return;
3773 			}
3774 		}
3775 	}
3776 
3777 	ctx_reg_offset =
3778 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3779 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3780 	buffer[count++] = cpu_to_le32(ctx_reg_offset);
3781 	buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3782 
3783 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3784 	buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3785 
3786 	buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3787 	buffer[count++] = cpu_to_le32(0);
3788 }
3789 
3790 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3791 {
3792 	/* clear state block */
3793 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3794 			&adev->gfx.rlc.clear_state_gpu_addr,
3795 			(void **)&adev->gfx.rlc.cs_ptr);
3796 
3797 	/* jump table block */
3798 	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3799 			&adev->gfx.rlc.cp_table_gpu_addr,
3800 			(void **)&adev->gfx.rlc.cp_table_ptr);
3801 }
3802 
3803 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3804 {
3805 	const struct cs_section_def *cs_data;
3806 	int r;
3807 
3808 	adev->gfx.rlc.cs_data = gfx10_cs_data;
3809 
3810 	cs_data = adev->gfx.rlc.cs_data;
3811 
3812 	if (cs_data) {
3813 		/* init clear state block */
3814 		r = amdgpu_gfx_rlc_init_csb(adev);
3815 		if (r)
3816 			return r;
3817 	}
3818 
3819 	/* init spm vmid with 0xf */
3820 	if (adev->gfx.rlc.funcs->update_spm_vmid)
3821 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
3822 
3823 	return 0;
3824 }
3825 
3826 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
3827 {
3828 	amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
3829 	amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
3830 }
3831 
3832 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
3833 {
3834 	int r;
3835 
3836 	bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
3837 
3838 	amdgpu_gfx_graphics_queue_acquire(adev);
3839 
3840 	r = gfx_v10_0_init_microcode(adev);
3841 	if (r)
3842 		DRM_ERROR("Failed to load gfx firmware!\n");
3843 
3844 	return r;
3845 }
3846 
3847 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
3848 {
3849 	int r;
3850 	u32 *hpd;
3851 	const __le32 *fw_data = NULL;
3852 	unsigned fw_size;
3853 	u32 *fw = NULL;
3854 	size_t mec_hpd_size;
3855 
3856 	const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
3857 
3858 	bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
3859 
3860 	/* take ownership of the relevant compute queues */
3861 	amdgpu_gfx_compute_queue_acquire(adev);
3862 	mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
3863 
3864 	r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
3865 				      AMDGPU_GEM_DOMAIN_GTT,
3866 				      &adev->gfx.mec.hpd_eop_obj,
3867 				      &adev->gfx.mec.hpd_eop_gpu_addr,
3868 				      (void **)&hpd);
3869 	if (r) {
3870 		dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
3871 		gfx_v10_0_mec_fini(adev);
3872 		return r;
3873 	}
3874 
3875 	memset(hpd, 0, mec_hpd_size);
3876 
3877 	amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
3878 	amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
3879 
3880 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
3881 		mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3882 
3883 		fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3884 			 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3885 		fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3886 
3887 		r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3888 					      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3889 					      &adev->gfx.mec.mec_fw_obj,
3890 					      &adev->gfx.mec.mec_fw_gpu_addr,
3891 					      (void **)&fw);
3892 		if (r) {
3893 			dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3894 			gfx_v10_0_mec_fini(adev);
3895 			return r;
3896 		}
3897 
3898 		memcpy(fw, fw_data, fw_size);
3899 
3900 		amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3901 		amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3902 	}
3903 
3904 	return 0;
3905 }
3906 
3907 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
3908 {
3909 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
3910 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3911 		(address << SQ_IND_INDEX__INDEX__SHIFT));
3912 	return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
3913 }
3914 
3915 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
3916 			   uint32_t thread, uint32_t regno,
3917 			   uint32_t num, uint32_t *out)
3918 {
3919 	WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
3920 		(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3921 		(regno << SQ_IND_INDEX__INDEX__SHIFT) |
3922 		(thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
3923 		(SQ_IND_INDEX__AUTO_INCR_MASK));
3924 	while (num--)
3925 		*(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
3926 }
3927 
3928 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3929 {
3930 	/* in gfx10 the SIMD_ID is specified as part of the INSTANCE
3931 	 * field when performing a select_se_sh so it should be
3932 	 * zero here */
3933 	WARN_ON(simd != 0);
3934 
3935 	/* type 2 wave data */
3936 	dst[(*no_fields)++] = 2;
3937 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
3938 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
3939 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
3940 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
3941 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
3942 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
3943 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
3944 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
3945 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
3946 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
3947 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
3948 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
3949 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
3950 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
3951 	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
3952 }
3953 
3954 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3955 				     uint32_t wave, uint32_t start,
3956 				     uint32_t size, uint32_t *dst)
3957 {
3958 	WARN_ON(simd != 0);
3959 
3960 	wave_read_regs(
3961 		adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
3962 		dst);
3963 }
3964 
3965 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
3966 				      uint32_t wave, uint32_t thread,
3967 				      uint32_t start, uint32_t size,
3968 				      uint32_t *dst)
3969 {
3970 	wave_read_regs(
3971 		adev, wave, thread,
3972 		start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
3973 }
3974 
3975 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
3976 									  u32 me, u32 pipe, u32 q, u32 vm)
3977  {
3978        nv_grbm_select(adev, me, pipe, q, vm);
3979  }
3980 
3981 
3982 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
3983 	.get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
3984 	.select_se_sh = &gfx_v10_0_select_se_sh,
3985 	.read_wave_data = &gfx_v10_0_read_wave_data,
3986 	.read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
3987 	.read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
3988 	.select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
3989 };
3990 
3991 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
3992 {
3993 	u32 gb_addr_config;
3994 
3995 	adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
3996 
3997 	switch (adev->asic_type) {
3998 	case CHIP_NAVI10:
3999 	case CHIP_NAVI14:
4000 	case CHIP_NAVI12:
4001 		adev->gfx.config.max_hw_contexts = 8;
4002 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4003 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4004 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4005 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4006 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4007 		break;
4008 	case CHIP_SIENNA_CICHLID:
4009 		adev->gfx.config.max_hw_contexts = 8;
4010 		adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4011 		adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4012 		adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4013 		adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4014 		gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4015 		adev->gfx.config.gb_addr_config_fields.num_pkrs =
4016 			1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4017 		break;
4018 	default:
4019 		BUG();
4020 		break;
4021 	}
4022 
4023 	adev->gfx.config.gb_addr_config = gb_addr_config;
4024 
4025 	adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4026 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4027 				      GB_ADDR_CONFIG, NUM_PIPES);
4028 
4029 	adev->gfx.config.max_tile_pipes =
4030 		adev->gfx.config.gb_addr_config_fields.num_pipes;
4031 
4032 	adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4033 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4034 				      GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4035 	adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4036 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4037 				      GB_ADDR_CONFIG, NUM_RB_PER_SE);
4038 	adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4039 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4040 				      GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4041 	adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4042 			REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4043 				      GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4044 }
4045 
4046 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4047 				   int me, int pipe, int queue)
4048 {
4049 	int r;
4050 	struct amdgpu_ring *ring;
4051 	unsigned int irq_type;
4052 
4053 	ring = &adev->gfx.gfx_ring[ring_id];
4054 
4055 	ring->me = me;
4056 	ring->pipe = pipe;
4057 	ring->queue = queue;
4058 
4059 	ring->ring_obj = NULL;
4060 	ring->use_doorbell = true;
4061 
4062 	if (!ring_id)
4063 		ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4064 	else
4065 		ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4066 	sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4067 
4068 	irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4069 	r = amdgpu_ring_init(adev, ring, 1024,
4070 			     &adev->gfx.eop_irq, irq_type,
4071 			     AMDGPU_RING_PRIO_DEFAULT);
4072 	if (r)
4073 		return r;
4074 	return 0;
4075 }
4076 
4077 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4078 				       int mec, int pipe, int queue)
4079 {
4080 	int r;
4081 	unsigned irq_type;
4082 	struct amdgpu_ring *ring;
4083 	unsigned int hw_prio;
4084 
4085 	ring = &adev->gfx.compute_ring[ring_id];
4086 
4087 	/* mec0 is me1 */
4088 	ring->me = mec + 1;
4089 	ring->pipe = pipe;
4090 	ring->queue = queue;
4091 
4092 	ring->ring_obj = NULL;
4093 	ring->use_doorbell = true;
4094 	ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4095 	ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4096 				+ (ring_id * GFX10_MEC_HPD_SIZE);
4097 	sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4098 
4099 	irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4100 		+ ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4101 		+ ring->pipe;
4102 	hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4103 			AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4104 	/* type-2 packets are deprecated on MEC, use type-3 instead */
4105 	r = amdgpu_ring_init(adev, ring, 1024,
4106 			     &adev->gfx.eop_irq, irq_type, hw_prio);
4107 	if (r)
4108 		return r;
4109 
4110 	return 0;
4111 }
4112 
4113 static int gfx_v10_0_sw_init(void *handle)
4114 {
4115 	int i, j, k, r, ring_id = 0;
4116 	struct amdgpu_kiq *kiq;
4117 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4118 
4119 	switch (adev->asic_type) {
4120 	case CHIP_NAVI10:
4121 	case CHIP_NAVI14:
4122 	case CHIP_NAVI12:
4123 	case CHIP_SIENNA_CICHLID:
4124 		adev->gfx.me.num_me = 1;
4125 		adev->gfx.me.num_pipe_per_me = 1;
4126 		adev->gfx.me.num_queue_per_pipe = 1;
4127 		adev->gfx.mec.num_mec = 2;
4128 		adev->gfx.mec.num_pipe_per_mec = 4;
4129 		adev->gfx.mec.num_queue_per_pipe = 8;
4130 		break;
4131 	default:
4132 		adev->gfx.me.num_me = 1;
4133 		adev->gfx.me.num_pipe_per_me = 1;
4134 		adev->gfx.me.num_queue_per_pipe = 1;
4135 		adev->gfx.mec.num_mec = 1;
4136 		adev->gfx.mec.num_pipe_per_mec = 4;
4137 		adev->gfx.mec.num_queue_per_pipe = 8;
4138 		break;
4139 	}
4140 
4141 	/* KIQ event */
4142 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4143 			      GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4144 			      &adev->gfx.kiq.irq);
4145 	if (r)
4146 		return r;
4147 
4148 	/* EOP Event */
4149 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4150 			      GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4151 			      &adev->gfx.eop_irq);
4152 	if (r)
4153 		return r;
4154 
4155 	/* Privileged reg */
4156 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4157 			      &adev->gfx.priv_reg_irq);
4158 	if (r)
4159 		return r;
4160 
4161 	/* Privileged inst */
4162 	r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4163 			      &adev->gfx.priv_inst_irq);
4164 	if (r)
4165 		return r;
4166 
4167 	adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4168 
4169 	gfx_v10_0_scratch_init(adev);
4170 
4171 	r = gfx_v10_0_me_init(adev);
4172 	if (r)
4173 		return r;
4174 
4175 	r = gfx_v10_0_rlc_init(adev);
4176 	if (r) {
4177 		DRM_ERROR("Failed to init rlc BOs!\n");
4178 		return r;
4179 	}
4180 
4181 	r = gfx_v10_0_mec_init(adev);
4182 	if (r) {
4183 		DRM_ERROR("Failed to init MEC BOs!\n");
4184 		return r;
4185 	}
4186 
4187 	/* set up the gfx ring */
4188 	for (i = 0; i < adev->gfx.me.num_me; i++) {
4189 		for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4190 			for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4191 				if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4192 					continue;
4193 
4194 				r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4195 							    i, k, j);
4196 				if (r)
4197 					return r;
4198 				ring_id++;
4199 			}
4200 		}
4201 	}
4202 
4203 	ring_id = 0;
4204 	/* set up the compute queues - allocate horizontally across pipes */
4205 	for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4206 		for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4207 			for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4208 				if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4209 								     j))
4210 					continue;
4211 
4212 				r = gfx_v10_0_compute_ring_init(adev, ring_id,
4213 								i, k, j);
4214 				if (r)
4215 					return r;
4216 
4217 				ring_id++;
4218 			}
4219 		}
4220 	}
4221 
4222 	r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4223 	if (r) {
4224 		DRM_ERROR("Failed to init KIQ BOs!\n");
4225 		return r;
4226 	}
4227 
4228 	kiq = &adev->gfx.kiq;
4229 	r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4230 	if (r)
4231 		return r;
4232 
4233 	r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4234 	if (r)
4235 		return r;
4236 
4237 	/* allocate visible FB for rlc auto-loading fw */
4238 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4239 		r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4240 		if (r)
4241 			return r;
4242 	}
4243 
4244 	adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4245 
4246 	gfx_v10_0_gpu_early_init(adev);
4247 
4248 	return 0;
4249 }
4250 
4251 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4252 {
4253 	amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4254 			      &adev->gfx.pfp.pfp_fw_gpu_addr,
4255 			      (void **)&adev->gfx.pfp.pfp_fw_ptr);
4256 }
4257 
4258 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4259 {
4260 	amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4261 			      &adev->gfx.ce.ce_fw_gpu_addr,
4262 			      (void **)&adev->gfx.ce.ce_fw_ptr);
4263 }
4264 
4265 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4266 {
4267 	amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4268 			      &adev->gfx.me.me_fw_gpu_addr,
4269 			      (void **)&adev->gfx.me.me_fw_ptr);
4270 }
4271 
4272 static int gfx_v10_0_sw_fini(void *handle)
4273 {
4274 	int i;
4275 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4276 
4277 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4278 		amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4279 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
4280 		amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4281 
4282 	amdgpu_gfx_mqd_sw_fini(adev);
4283 	amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4284 	amdgpu_gfx_kiq_fini(adev);
4285 
4286 	gfx_v10_0_pfp_fini(adev);
4287 	gfx_v10_0_ce_fini(adev);
4288 	gfx_v10_0_me_fini(adev);
4289 	gfx_v10_0_rlc_fini(adev);
4290 	gfx_v10_0_mec_fini(adev);
4291 
4292 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4293 		gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4294 
4295 	gfx_v10_0_free_microcode(adev);
4296 
4297 	return 0;
4298 }
4299 
4300 
4301 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev)
4302 {
4303 	/* TODO */
4304 }
4305 
4306 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4307 				   u32 sh_num, u32 instance)
4308 {
4309 	u32 data;
4310 
4311 	if (instance == 0xffffffff)
4312 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4313 				     INSTANCE_BROADCAST_WRITES, 1);
4314 	else
4315 		data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4316 				     instance);
4317 
4318 	if (se_num == 0xffffffff)
4319 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4320 				     1);
4321 	else
4322 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4323 
4324 	if (sh_num == 0xffffffff)
4325 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4326 				     1);
4327 	else
4328 		data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4329 
4330 	WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4331 }
4332 
4333 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4334 {
4335 	u32 data, mask;
4336 
4337 	data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4338 	data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4339 
4340 	data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4341 	data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4342 
4343 	mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4344 					 adev->gfx.config.max_sh_per_se);
4345 
4346 	return (~data) & mask;
4347 }
4348 
4349 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4350 {
4351 	int i, j;
4352 	u32 data;
4353 	u32 active_rbs = 0;
4354 	u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4355 					adev->gfx.config.max_sh_per_se;
4356 
4357 	mutex_lock(&adev->grbm_idx_mutex);
4358 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4359 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4360 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4361 			data = gfx_v10_0_get_rb_active_bitmap(adev);
4362 			active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4363 					       rb_bitmap_width_per_sh);
4364 		}
4365 	}
4366 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4367 	mutex_unlock(&adev->grbm_idx_mutex);
4368 
4369 	adev->gfx.config.backend_enable_mask = active_rbs;
4370 	adev->gfx.config.num_rbs = hweight32(active_rbs);
4371 }
4372 
4373 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4374 {
4375 	uint32_t num_sc;
4376 	uint32_t enabled_rb_per_sh;
4377 	uint32_t active_rb_bitmap;
4378 	uint32_t num_rb_per_sc;
4379 	uint32_t num_packer_per_sc;
4380 	uint32_t pa_sc_tile_steering_override;
4381 
4382 	/* init num_sc */
4383 	num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4384 			adev->gfx.config.num_sc_per_sh;
4385 	/* init num_rb_per_sc */
4386 	active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4387 	enabled_rb_per_sh = hweight32(active_rb_bitmap);
4388 	num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4389 	/* init num_packer_per_sc */
4390 	num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4391 
4392 	pa_sc_tile_steering_override = 0;
4393 	pa_sc_tile_steering_override |=
4394 		(order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4395 		PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4396 	pa_sc_tile_steering_override |=
4397 		(order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4398 		PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4399 	pa_sc_tile_steering_override |=
4400 		(order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4401 		PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4402 
4403 	return pa_sc_tile_steering_override;
4404 }
4405 
4406 #define DEFAULT_SH_MEM_BASES	(0x6000)
4407 #define FIRST_COMPUTE_VMID	(8)
4408 #define LAST_COMPUTE_VMID	(16)
4409 
4410 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4411 {
4412 	int i;
4413 	uint32_t sh_mem_bases;
4414 
4415 	/*
4416 	 * Configure apertures:
4417 	 * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4418 	 * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4419 	 * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4420 	 */
4421 	sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4422 
4423 	mutex_lock(&adev->srbm_mutex);
4424 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
4425 		nv_grbm_select(adev, 0, 0, 0, i);
4426 		/* CP and shaders */
4427 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4428 		WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4429 	}
4430 	nv_grbm_select(adev, 0, 0, 0, 0);
4431 	mutex_unlock(&adev->srbm_mutex);
4432 
4433 	/* Initialize all compute VMIDs to have no GDS, GWS, or OA
4434 	   acccess. These should be enabled by FW for target VMIDs. */
4435 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
4436 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4437 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4438 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4439 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4440 	}
4441 }
4442 
4443 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4444 {
4445 	int vmid;
4446 
4447 	/*
4448 	 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4449 	 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4450 	 * the driver can enable them for graphics. VMID0 should maintain
4451 	 * access so that HWS firmware can save/restore entries.
4452 	 */
4453 	for (vmid = 1; vmid < 16; vmid++) {
4454 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4455 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4456 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4457 		WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4458 	}
4459 }
4460 
4461 
4462 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4463 {
4464 	int i, j, k;
4465 	int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4466 	u32 tmp, wgp_active_bitmap = 0;
4467 	u32 gcrd_targets_disable_tcp = 0;
4468 	u32 utcl_invreq_disable = 0;
4469 	/*
4470 	 * GCRD_TARGETS_DISABLE field contains
4471 	 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4472 	 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4473 	 */
4474 	u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4475 		2 * max_wgp_per_sh + /* TCP */
4476 		max_wgp_per_sh + /* SQC */
4477 		4); /* GL1C */
4478 	/*
4479 	 * UTCL1_UTCL0_INVREQ_DISABLE field contains
4480 	 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4481 	 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4482 	 */
4483 	u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4484 		2 * max_wgp_per_sh + /* TCP */
4485 		2 * max_wgp_per_sh + /* SQC */
4486 		4 + /* RMI */
4487 		1); /* SQG */
4488 
4489 	if (adev->asic_type == CHIP_NAVI10 ||
4490 	    adev->asic_type == CHIP_NAVI14 ||
4491 	    adev->asic_type == CHIP_NAVI12) {
4492 		mutex_lock(&adev->grbm_idx_mutex);
4493 		for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4494 			for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4495 				gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4496 				wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4497 				/*
4498 				 * Set corresponding TCP bits for the inactive WGPs in
4499 				 * GCRD_SA_TARGETS_DISABLE
4500 				 */
4501 				gcrd_targets_disable_tcp = 0;
4502 				/* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4503 				utcl_invreq_disable = 0;
4504 
4505 				for (k = 0; k < max_wgp_per_sh; k++) {
4506 					if (!(wgp_active_bitmap & (1 << k))) {
4507 						gcrd_targets_disable_tcp |= 3 << (2 * k);
4508 						utcl_invreq_disable |= (3 << (2 * k)) |
4509 							(3 << (2 * (max_wgp_per_sh + k)));
4510 					}
4511 				}
4512 
4513 				tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4514 				/* only override TCP & SQC bits */
4515 				tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4516 				tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4517 				WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4518 
4519 				tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4520 				/* only override TCP bits */
4521 				tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4522 				tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4523 				WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4524 			}
4525 		}
4526 
4527 		gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4528 		mutex_unlock(&adev->grbm_idx_mutex);
4529 	}
4530 }
4531 
4532 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4533 {
4534 	/* TCCs are global (not instanced). */
4535 	uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4536 			       RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4537 
4538 	adev->gfx.config.tcc_disabled_mask =
4539 		REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4540 		(REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4541 }
4542 
4543 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4544 {
4545 	u32 tmp;
4546 	int i;
4547 
4548 	WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4549 
4550 	gfx_v10_0_tiling_mode_table_init(adev);
4551 
4552 	gfx_v10_0_setup_rb(adev);
4553 	gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4554 	gfx_v10_0_get_tcc_info(adev);
4555 	adev->gfx.config.pa_sc_tile_steering_override =
4556 		gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4557 
4558 	/* XXX SH_MEM regs */
4559 	/* where to put LDS, scratch, GPUVM in FSA64 space */
4560 	mutex_lock(&adev->srbm_mutex);
4561 	for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4562 		nv_grbm_select(adev, 0, 0, 0, i);
4563 		/* CP and shaders */
4564 		WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4565 		if (i != 0) {
4566 			tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4567 				(adev->gmc.private_aperture_start >> 48));
4568 			tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4569 				(adev->gmc.shared_aperture_start >> 48));
4570 			WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4571 		}
4572 	}
4573 	nv_grbm_select(adev, 0, 0, 0, 0);
4574 
4575 	mutex_unlock(&adev->srbm_mutex);
4576 
4577 	gfx_v10_0_init_compute_vmid(adev);
4578 	gfx_v10_0_init_gds_vmid(adev);
4579 
4580 }
4581 
4582 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4583 					       bool enable)
4584 {
4585 	u32 tmp;
4586 
4587 	if (amdgpu_sriov_vf(adev))
4588 		return;
4589 
4590 	tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4591 
4592 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4593 			    enable ? 1 : 0);
4594 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4595 			    enable ? 1 : 0);
4596 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4597 			    enable ? 1 : 0);
4598 	tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4599 			    enable ? 1 : 0);
4600 
4601 	WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4602 }
4603 
4604 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4605 {
4606 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4607 
4608 	/* csib */
4609 	WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4610 			 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4611 	WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4612 			 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4613 	WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4614 
4615 	return 0;
4616 }
4617 
4618 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4619 {
4620 	u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4621 
4622 	tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4623 	WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4624 }
4625 
4626 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4627 {
4628 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4629 	udelay(50);
4630 	WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4631 	udelay(50);
4632 }
4633 
4634 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4635 					     bool enable)
4636 {
4637 	uint32_t rlc_pg_cntl;
4638 
4639 	rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4640 
4641 	if (!enable) {
4642 		/* RLC_PG_CNTL[23] = 0 (default)
4643 		 * RLC will wait for handshake acks with SMU
4644 		 * GFXOFF will be enabled
4645 		 * RLC_PG_CNTL[23] = 1
4646 		 * RLC will not issue any message to SMU
4647 		 * hence no handshake between SMU & RLC
4648 		 * GFXOFF will be disabled
4649 		 */
4650 		rlc_pg_cntl |= 0x800000;
4651 	} else
4652 		rlc_pg_cntl &= ~0x800000;
4653 	WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4654 }
4655 
4656 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4657 {
4658 	/* TODO: enable rlc & smu handshake until smu
4659 	 * and gfxoff feature works as expected */
4660 	if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4661 		gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4662 
4663 	WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4664 	udelay(50);
4665 }
4666 
4667 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4668 {
4669 	uint32_t tmp;
4670 
4671 	/* enable Save Restore Machine */
4672 	tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4673 	tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4674 	tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4675 	WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4676 }
4677 
4678 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4679 {
4680 	const struct rlc_firmware_header_v2_0 *hdr;
4681 	const __le32 *fw_data;
4682 	unsigned i, fw_size;
4683 
4684 	if (!adev->gfx.rlc_fw)
4685 		return -EINVAL;
4686 
4687 	hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4688 	amdgpu_ucode_print_rlc_hdr(&hdr->header);
4689 
4690 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4691 			   le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4692 	fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4693 
4694 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4695 		     RLCG_UCODE_LOADING_START_ADDRESS);
4696 
4697 	for (i = 0; i < fw_size; i++)
4698 		WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4699 			     le32_to_cpup(fw_data++));
4700 
4701 	WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4702 
4703 	return 0;
4704 }
4705 
4706 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4707 {
4708 	int r;
4709 
4710 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4711 
4712 		r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4713 		if (r)
4714 			return r;
4715 
4716 		gfx_v10_0_init_csb(adev);
4717 
4718 		if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4719 			gfx_v10_0_rlc_enable_srm(adev);
4720 	} else {
4721 		if (amdgpu_sriov_vf(adev)) {
4722 			gfx_v10_0_init_csb(adev);
4723 			return 0;
4724 		}
4725 
4726 		adev->gfx.rlc.funcs->stop(adev);
4727 
4728 		/* disable CG */
4729 		WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4730 
4731 		/* disable PG */
4732 		WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4733 
4734 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4735 			/* legacy rlc firmware loading */
4736 			r = gfx_v10_0_rlc_load_microcode(adev);
4737 			if (r)
4738 				return r;
4739 		} else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4740 			/* rlc backdoor autoload firmware */
4741 			r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4742 			if (r)
4743 				return r;
4744 		}
4745 
4746 		gfx_v10_0_init_csb(adev);
4747 
4748 		adev->gfx.rlc.funcs->start(adev);
4749 
4750 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4751 			r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4752 			if (r)
4753 				return r;
4754 		}
4755 	}
4756 	return 0;
4757 }
4758 
4759 static struct {
4760 	FIRMWARE_ID	id;
4761 	unsigned int	offset;
4762 	unsigned int	size;
4763 } rlc_autoload_info[FIRMWARE_ID_MAX];
4764 
4765 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4766 {
4767 	int ret;
4768 	RLC_TABLE_OF_CONTENT *rlc_toc;
4769 
4770 	ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4771 					AMDGPU_GEM_DOMAIN_GTT,
4772 					&adev->gfx.rlc.rlc_toc_bo,
4773 					&adev->gfx.rlc.rlc_toc_gpu_addr,
4774 					(void **)&adev->gfx.rlc.rlc_toc_buf);
4775 	if (ret) {
4776 		dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4777 		return ret;
4778 	}
4779 
4780 	/* Copy toc from psp sos fw to rlc toc buffer */
4781 	memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4782 
4783 	rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4784 	while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4785 		(rlc_toc->id < FIRMWARE_ID_MAX)) {
4786 		if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4787 		    (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4788 			/* Offset needs 4KB alignment */
4789 			rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4790 		}
4791 
4792 		rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4793 		rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4794 		rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4795 
4796 		rlc_toc++;
4797 	}
4798 
4799 	return 0;
4800 }
4801 
4802 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4803 {
4804 	uint32_t total_size = 0;
4805 	FIRMWARE_ID id;
4806 	int ret;
4807 
4808 	ret = gfx_v10_0_parse_rlc_toc(adev);
4809 	if (ret) {
4810 		dev_err(adev->dev, "failed to parse rlc toc\n");
4811 		return 0;
4812 	}
4813 
4814 	for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
4815 		total_size += rlc_autoload_info[id].size;
4816 
4817 	/* In case the offset in rlc toc ucode is aligned */
4818 	if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
4819 		total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
4820 				rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
4821 
4822 	return total_size;
4823 }
4824 
4825 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
4826 {
4827 	int r;
4828 	uint32_t total_size;
4829 
4830 	total_size = gfx_v10_0_calc_toc_total_size(adev);
4831 
4832 	r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
4833 				      AMDGPU_GEM_DOMAIN_GTT,
4834 				      &adev->gfx.rlc.rlc_autoload_bo,
4835 				      &adev->gfx.rlc.rlc_autoload_gpu_addr,
4836 				      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
4837 	if (r) {
4838 		dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
4839 		return r;
4840 	}
4841 
4842 	return 0;
4843 }
4844 
4845 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
4846 {
4847 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
4848 			      &adev->gfx.rlc.rlc_toc_gpu_addr,
4849 			      (void **)&adev->gfx.rlc.rlc_toc_buf);
4850 	amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
4851 			      &adev->gfx.rlc.rlc_autoload_gpu_addr,
4852 			      (void **)&adev->gfx.rlc.rlc_autoload_ptr);
4853 }
4854 
4855 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
4856 						       FIRMWARE_ID id,
4857 						       const void *fw_data,
4858 						       uint32_t fw_size)
4859 {
4860 	uint32_t toc_offset;
4861 	uint32_t toc_fw_size;
4862 	char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
4863 
4864 	if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
4865 		return;
4866 
4867 	toc_offset = rlc_autoload_info[id].offset;
4868 	toc_fw_size = rlc_autoload_info[id].size;
4869 
4870 	if (fw_size == 0)
4871 		fw_size = toc_fw_size;
4872 
4873 	if (fw_size > toc_fw_size)
4874 		fw_size = toc_fw_size;
4875 
4876 	memcpy(ptr + toc_offset, fw_data, fw_size);
4877 
4878 	if (fw_size < toc_fw_size)
4879 		memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
4880 }
4881 
4882 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
4883 {
4884 	void *data;
4885 	uint32_t size;
4886 
4887 	data = adev->gfx.rlc.rlc_toc_buf;
4888 	size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
4889 
4890 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4891 						   FIRMWARE_ID_RLC_TOC,
4892 						   data, size);
4893 }
4894 
4895 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
4896 {
4897 	const __le32 *fw_data;
4898 	uint32_t fw_size;
4899 	const struct gfx_firmware_header_v1_0 *cp_hdr;
4900 	const struct rlc_firmware_header_v2_0 *rlc_hdr;
4901 
4902 	/* pfp ucode */
4903 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4904 		adev->gfx.pfp_fw->data;
4905 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
4906 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4907 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
4908 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4909 						   FIRMWARE_ID_CP_PFP,
4910 						   fw_data, fw_size);
4911 
4912 	/* ce ucode */
4913 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4914 		adev->gfx.ce_fw->data;
4915 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
4916 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4917 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
4918 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4919 						   FIRMWARE_ID_CP_CE,
4920 						   fw_data, fw_size);
4921 
4922 	/* me ucode */
4923 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4924 		adev->gfx.me_fw->data;
4925 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
4926 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4927 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
4928 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4929 						   FIRMWARE_ID_CP_ME,
4930 						   fw_data, fw_size);
4931 
4932 	/* rlc ucode */
4933 	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
4934 		adev->gfx.rlc_fw->data;
4935 	fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4936 		le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
4937 	fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
4938 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4939 						   FIRMWARE_ID_RLC_G_UCODE,
4940 						   fw_data, fw_size);
4941 
4942 	/* mec1 ucode */
4943 	cp_hdr = (const struct gfx_firmware_header_v1_0 *)
4944 		adev->gfx.mec_fw->data;
4945 	fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4946 		le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
4947 	fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
4948 		cp_hdr->jt_size * 4;
4949 	gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4950 						   FIRMWARE_ID_CP_MEC,
4951 						   fw_data, fw_size);
4952 	/* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
4953 }
4954 
4955 /* Temporarily put sdma part here */
4956 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
4957 {
4958 	const __le32 *fw_data;
4959 	uint32_t fw_size;
4960 	const struct sdma_firmware_header_v1_0 *sdma_hdr;
4961 	int i;
4962 
4963 	for (i = 0; i < adev->sdma.num_instances; i++) {
4964 		sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
4965 			adev->sdma.instance[i].fw->data;
4966 		fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
4967 			le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
4968 		fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
4969 
4970 		if (i == 0) {
4971 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4972 				FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
4973 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4974 				FIRMWARE_ID_SDMA0_JT,
4975 				(uint32_t *)fw_data +
4976 				sdma_hdr->jt_offset,
4977 				sdma_hdr->jt_size * 4);
4978 		} else if (i == 1) {
4979 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4980 				FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
4981 			gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
4982 				FIRMWARE_ID_SDMA1_JT,
4983 				(uint32_t *)fw_data +
4984 				sdma_hdr->jt_offset,
4985 				sdma_hdr->jt_size * 4);
4986 		}
4987 	}
4988 }
4989 
4990 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
4991 {
4992 	uint32_t rlc_g_offset, rlc_g_size, tmp;
4993 	uint64_t gpu_addr;
4994 
4995 	gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
4996 	gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
4997 	gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
4998 
4999 	rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5000 	rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5001 	gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5002 
5003 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5004 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5005 	WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5006 
5007 	tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5008 	if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5009 		   RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5010 		DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5011 		return -EINVAL;
5012 	}
5013 
5014 	tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5015 	if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5016 		DRM_ERROR("RLC ROM should halt itself\n");
5017 		return -EINVAL;
5018 	}
5019 
5020 	return 0;
5021 }
5022 
5023 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5024 {
5025 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5026 	uint32_t tmp;
5027 	int i;
5028 	uint64_t addr;
5029 
5030 	/* Trigger an invalidation of the L1 instruction caches */
5031 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5032 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5033 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5034 
5035 	/* Wait for invalidation complete */
5036 	for (i = 0; i < usec_timeout; i++) {
5037 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5038 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5039 			INVALIDATE_CACHE_COMPLETE))
5040 			break;
5041 		udelay(1);
5042 	}
5043 
5044 	if (i >= usec_timeout) {
5045 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5046 		return -EINVAL;
5047 	}
5048 
5049 	/* Program me ucode address into intruction cache address register */
5050 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5051 		rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5052 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5053 			lower_32_bits(addr) & 0xFFFFF000);
5054 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5055 			upper_32_bits(addr));
5056 
5057 	return 0;
5058 }
5059 
5060 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5061 {
5062 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5063 	uint32_t tmp;
5064 	int i;
5065 	uint64_t addr;
5066 
5067 	/* Trigger an invalidation of the L1 instruction caches */
5068 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5069 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5070 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5071 
5072 	/* Wait for invalidation complete */
5073 	for (i = 0; i < usec_timeout; i++) {
5074 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5075 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5076 			INVALIDATE_CACHE_COMPLETE))
5077 			break;
5078 		udelay(1);
5079 	}
5080 
5081 	if (i >= usec_timeout) {
5082 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5083 		return -EINVAL;
5084 	}
5085 
5086 	/* Program ce ucode address into intruction cache address register */
5087 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5088 		rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5089 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5090 			lower_32_bits(addr) & 0xFFFFF000);
5091 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5092 			upper_32_bits(addr));
5093 
5094 	return 0;
5095 }
5096 
5097 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5098 {
5099 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5100 	uint32_t tmp;
5101 	int i;
5102 	uint64_t addr;
5103 
5104 	/* Trigger an invalidation of the L1 instruction caches */
5105 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5106 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5107 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5108 
5109 	/* Wait for invalidation complete */
5110 	for (i = 0; i < usec_timeout; i++) {
5111 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5112 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5113 			INVALIDATE_CACHE_COMPLETE))
5114 			break;
5115 		udelay(1);
5116 	}
5117 
5118 	if (i >= usec_timeout) {
5119 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5120 		return -EINVAL;
5121 	}
5122 
5123 	/* Program pfp ucode address into intruction cache address register */
5124 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5125 		rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5126 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5127 			lower_32_bits(addr) & 0xFFFFF000);
5128 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5129 			upper_32_bits(addr));
5130 
5131 	return 0;
5132 }
5133 
5134 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5135 {
5136 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5137 	uint32_t tmp;
5138 	int i;
5139 	uint64_t addr;
5140 
5141 	/* Trigger an invalidation of the L1 instruction caches */
5142 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5143 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5144 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5145 
5146 	/* Wait for invalidation complete */
5147 	for (i = 0; i < usec_timeout; i++) {
5148 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5149 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5150 			INVALIDATE_CACHE_COMPLETE))
5151 			break;
5152 		udelay(1);
5153 	}
5154 
5155 	if (i >= usec_timeout) {
5156 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5157 		return -EINVAL;
5158 	}
5159 
5160 	/* Program mec1 ucode address into intruction cache address register */
5161 	addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5162 		rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5163 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5164 			lower_32_bits(addr) & 0xFFFFF000);
5165 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5166 			upper_32_bits(addr));
5167 
5168 	return 0;
5169 }
5170 
5171 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5172 {
5173 	uint32_t cp_status;
5174 	uint32_t bootload_status;
5175 	int i, r;
5176 
5177 	for (i = 0; i < adev->usec_timeout; i++) {
5178 		cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5179 		bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5180 		if ((cp_status == 0) &&
5181 		    (REG_GET_FIELD(bootload_status,
5182 			RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5183 			break;
5184 		}
5185 		udelay(1);
5186 	}
5187 
5188 	if (i >= adev->usec_timeout) {
5189 		dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5190 		return -ETIMEDOUT;
5191 	}
5192 
5193 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5194 		r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5195 		if (r)
5196 			return r;
5197 
5198 		r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5199 		if (r)
5200 			return r;
5201 
5202 		r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5203 		if (r)
5204 			return r;
5205 
5206 		r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5207 		if (r)
5208 			return r;
5209 	}
5210 
5211 	return 0;
5212 }
5213 
5214 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5215 {
5216 	int i;
5217 	u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5218 
5219 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5220 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5221 	tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5222 	WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5223 
5224 	for (i = 0; i < adev->usec_timeout; i++) {
5225 		if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5226 			break;
5227 		udelay(1);
5228 	}
5229 
5230 	if (i >= adev->usec_timeout)
5231 		DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5232 
5233 	return 0;
5234 }
5235 
5236 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5237 {
5238 	int r;
5239 	const struct gfx_firmware_header_v1_0 *pfp_hdr;
5240 	const __le32 *fw_data;
5241 	unsigned i, fw_size;
5242 	uint32_t tmp;
5243 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5244 
5245 	pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5246 		adev->gfx.pfp_fw->data;
5247 
5248 	amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5249 
5250 	fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5251 		le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5252 	fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5253 
5254 	r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5255 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5256 				      &adev->gfx.pfp.pfp_fw_obj,
5257 				      &adev->gfx.pfp.pfp_fw_gpu_addr,
5258 				      (void **)&adev->gfx.pfp.pfp_fw_ptr);
5259 	if (r) {
5260 		dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5261 		gfx_v10_0_pfp_fini(adev);
5262 		return r;
5263 	}
5264 
5265 	memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5266 
5267 	amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5268 	amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5269 
5270 	/* Trigger an invalidation of the L1 instruction caches */
5271 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5272 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5273 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5274 
5275 	/* Wait for invalidation complete */
5276 	for (i = 0; i < usec_timeout; i++) {
5277 		tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5278 		if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5279 			INVALIDATE_CACHE_COMPLETE))
5280 			break;
5281 		udelay(1);
5282 	}
5283 
5284 	if (i >= usec_timeout) {
5285 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5286 		return -EINVAL;
5287 	}
5288 
5289 	if (amdgpu_emu_mode == 1)
5290 		adev->nbio.funcs->hdp_flush(adev, NULL);
5291 
5292 	tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5293 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5294 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5295 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5296 	tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5297 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5298 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5299 		adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5300 	WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5301 		upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5302 
5303 	return 0;
5304 }
5305 
5306 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5307 {
5308 	int r;
5309 	const struct gfx_firmware_header_v1_0 *ce_hdr;
5310 	const __le32 *fw_data;
5311 	unsigned i, fw_size;
5312 	uint32_t tmp;
5313 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5314 
5315 	ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5316 		adev->gfx.ce_fw->data;
5317 
5318 	amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5319 
5320 	fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5321 		le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5322 	fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5323 
5324 	r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5325 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5326 				      &adev->gfx.ce.ce_fw_obj,
5327 				      &adev->gfx.ce.ce_fw_gpu_addr,
5328 				      (void **)&adev->gfx.ce.ce_fw_ptr);
5329 	if (r) {
5330 		dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5331 		gfx_v10_0_ce_fini(adev);
5332 		return r;
5333 	}
5334 
5335 	memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5336 
5337 	amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5338 	amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5339 
5340 	/* Trigger an invalidation of the L1 instruction caches */
5341 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5342 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5343 	WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5344 
5345 	/* Wait for invalidation complete */
5346 	for (i = 0; i < usec_timeout; i++) {
5347 		tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5348 		if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5349 			INVALIDATE_CACHE_COMPLETE))
5350 			break;
5351 		udelay(1);
5352 	}
5353 
5354 	if (i >= usec_timeout) {
5355 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5356 		return -EINVAL;
5357 	}
5358 
5359 	if (amdgpu_emu_mode == 1)
5360 		adev->nbio.funcs->hdp_flush(adev, NULL);
5361 
5362 	tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5363 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5364 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5365 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5366 	tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5367 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5368 		adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5369 	WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5370 		upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5371 
5372 	return 0;
5373 }
5374 
5375 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5376 {
5377 	int r;
5378 	const struct gfx_firmware_header_v1_0 *me_hdr;
5379 	const __le32 *fw_data;
5380 	unsigned i, fw_size;
5381 	uint32_t tmp;
5382 	uint32_t usec_timeout = 50000;  /* wait for 50ms */
5383 
5384 	me_hdr = (const struct gfx_firmware_header_v1_0 *)
5385 		adev->gfx.me_fw->data;
5386 
5387 	amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5388 
5389 	fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5390 		le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5391 	fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5392 
5393 	r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5394 				      PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5395 				      &adev->gfx.me.me_fw_obj,
5396 				      &adev->gfx.me.me_fw_gpu_addr,
5397 				      (void **)&adev->gfx.me.me_fw_ptr);
5398 	if (r) {
5399 		dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5400 		gfx_v10_0_me_fini(adev);
5401 		return r;
5402 	}
5403 
5404 	memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5405 
5406 	amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5407 	amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5408 
5409 	/* Trigger an invalidation of the L1 instruction caches */
5410 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5411 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5412 	WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5413 
5414 	/* Wait for invalidation complete */
5415 	for (i = 0; i < usec_timeout; i++) {
5416 		tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5417 		if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5418 			INVALIDATE_CACHE_COMPLETE))
5419 			break;
5420 		udelay(1);
5421 	}
5422 
5423 	if (i >= usec_timeout) {
5424 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5425 		return -EINVAL;
5426 	}
5427 
5428 	if (amdgpu_emu_mode == 1)
5429 		adev->nbio.funcs->hdp_flush(adev, NULL);
5430 
5431 	tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5432 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5433 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5434 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5435 	tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5436 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5437 		adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5438 	WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5439 		upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5440 
5441 	return 0;
5442 }
5443 
5444 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5445 {
5446 	int r;
5447 
5448 	if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5449 		return -EINVAL;
5450 
5451 	gfx_v10_0_cp_gfx_enable(adev, false);
5452 
5453 	r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5454 	if (r) {
5455 		dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5456 		return r;
5457 	}
5458 
5459 	r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5460 	if (r) {
5461 		dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5462 		return r;
5463 	}
5464 
5465 	r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5466 	if (r) {
5467 		dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5468 		return r;
5469 	}
5470 
5471 	return 0;
5472 }
5473 
5474 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5475 {
5476 	struct amdgpu_ring *ring;
5477 	const struct cs_section_def *sect = NULL;
5478 	const struct cs_extent_def *ext = NULL;
5479 	int r, i;
5480 	int ctx_reg_offset;
5481 
5482 	/* init the CP */
5483 	WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5484 		     adev->gfx.config.max_hw_contexts - 1);
5485 	WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5486 
5487 	gfx_v10_0_cp_gfx_enable(adev, true);
5488 
5489 	ring = &adev->gfx.gfx_ring[0];
5490 	r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5491 	if (r) {
5492 		DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5493 		return r;
5494 	}
5495 
5496 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5497 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5498 
5499 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5500 	amdgpu_ring_write(ring, 0x80000000);
5501 	amdgpu_ring_write(ring, 0x80000000);
5502 
5503 	for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5504 		for (ext = sect->section; ext->extent != NULL; ++ext) {
5505 			if (sect->id == SECT_CONTEXT) {
5506 				amdgpu_ring_write(ring,
5507 						  PACKET3(PACKET3_SET_CONTEXT_REG,
5508 							  ext->reg_count));
5509 				amdgpu_ring_write(ring, ext->reg_index -
5510 						  PACKET3_SET_CONTEXT_REG_START);
5511 				for (i = 0; i < ext->reg_count; i++)
5512 					amdgpu_ring_write(ring, ext->extent[i]);
5513 			}
5514 		}
5515 	}
5516 
5517 	ctx_reg_offset =
5518 		SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5519 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5520 	amdgpu_ring_write(ring, ctx_reg_offset);
5521 	amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5522 
5523 	amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5524 	amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5525 
5526 	amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5527 	amdgpu_ring_write(ring, 0);
5528 
5529 	amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5530 	amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5531 	amdgpu_ring_write(ring, 0x8000);
5532 	amdgpu_ring_write(ring, 0x8000);
5533 
5534 	amdgpu_ring_commit(ring);
5535 
5536 	/* submit cs packet to copy state 0 to next available state */
5537 	if (adev->gfx.num_gfx_rings > 1) {
5538 		/* maximum supported gfx ring is 2 */
5539 		ring = &adev->gfx.gfx_ring[1];
5540 		r = amdgpu_ring_alloc(ring, 2);
5541 		if (r) {
5542 			DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5543 			return r;
5544 		}
5545 
5546 		amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5547 		amdgpu_ring_write(ring, 0);
5548 
5549 		amdgpu_ring_commit(ring);
5550 	}
5551 	return 0;
5552 }
5553 
5554 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5555 					 CP_PIPE_ID pipe)
5556 {
5557 	u32 tmp;
5558 
5559 	tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5560 	tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5561 
5562 	WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5563 }
5564 
5565 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5566 					  struct amdgpu_ring *ring)
5567 {
5568 	u32 tmp;
5569 
5570 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5571 	if (ring->use_doorbell) {
5572 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5573 				    DOORBELL_OFFSET, ring->doorbell_index);
5574 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5575 				    DOORBELL_EN, 1);
5576 	} else {
5577 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5578 				    DOORBELL_EN, 0);
5579 	}
5580 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5581 	tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5582 			    DOORBELL_RANGE_LOWER, ring->doorbell_index);
5583 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5584 
5585 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5586 		     CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5587 }
5588 
5589 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5590 {
5591 	struct amdgpu_ring *ring;
5592 	u32 tmp;
5593 	u32 rb_bufsz;
5594 	u64 rb_addr, rptr_addr, wptr_gpu_addr;
5595 	u32 i;
5596 
5597 	/* Set the write pointer delay */
5598 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5599 
5600 	/* set the RB to use vmid 0 */
5601 	WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5602 
5603 	/* Init gfx ring 0 for pipe 0 */
5604 	mutex_lock(&adev->srbm_mutex);
5605 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5606 
5607 	/* Set ring buffer size */
5608 	ring = &adev->gfx.gfx_ring[0];
5609 	rb_bufsz = order_base_2(ring->ring_size / 8);
5610 	tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5611 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5612 #ifdef __BIG_ENDIAN
5613 	tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5614 #endif
5615 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5616 
5617 	/* Initialize the ring buffer's write pointers */
5618 	ring->wptr = 0;
5619 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5620 	WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5621 
5622 	/* set the wb address wether it's enabled or not */
5623 	rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5624 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5625 	WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5626 		     CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5627 
5628 	wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5629 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5630 		     lower_32_bits(wptr_gpu_addr));
5631 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5632 		     upper_32_bits(wptr_gpu_addr));
5633 
5634 	mdelay(1);
5635 	WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5636 
5637 	rb_addr = ring->gpu_addr >> 8;
5638 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5639 	WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5640 
5641 	WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5642 
5643 	gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5644 	mutex_unlock(&adev->srbm_mutex);
5645 
5646 	/* Init gfx ring 1 for pipe 1 */
5647 	if (adev->gfx.num_gfx_rings > 1) {
5648 		mutex_lock(&adev->srbm_mutex);
5649 		gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5650 		/* maximum supported gfx ring is 2 */
5651 		ring = &adev->gfx.gfx_ring[1];
5652 		rb_bufsz = order_base_2(ring->ring_size / 8);
5653 		tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5654 		tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5655 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5656 		/* Initialize the ring buffer's write pointers */
5657 		ring->wptr = 0;
5658 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5659 		WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5660 		/* Set the wb address wether it's enabled or not */
5661 		rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5662 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5663 		WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5664 			     CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5665 		wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5666 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5667 			     lower_32_bits(wptr_gpu_addr));
5668 		WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5669 			     upper_32_bits(wptr_gpu_addr));
5670 
5671 		mdelay(1);
5672 		WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5673 
5674 		rb_addr = ring->gpu_addr >> 8;
5675 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5676 		WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5677 		WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5678 
5679 		gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5680 		mutex_unlock(&adev->srbm_mutex);
5681 	}
5682 	/* Switch to pipe 0 */
5683 	mutex_lock(&adev->srbm_mutex);
5684 	gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5685 	mutex_unlock(&adev->srbm_mutex);
5686 
5687 	/* start the ring */
5688 	gfx_v10_0_cp_gfx_start(adev);
5689 
5690 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5691 		ring = &adev->gfx.gfx_ring[i];
5692 		ring->sched.ready = true;
5693 	}
5694 
5695 	return 0;
5696 }
5697 
5698 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5699 {
5700 	if (enable) {
5701 		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5702 	} else {
5703 		WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5704 			     (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5705 			      CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5706 		adev->gfx.kiq.ring.sched.ready = false;
5707 	}
5708 	udelay(50);
5709 }
5710 
5711 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5712 {
5713 	const struct gfx_firmware_header_v1_0 *mec_hdr;
5714 	const __le32 *fw_data;
5715 	unsigned i;
5716 	u32 tmp;
5717 	u32 usec_timeout = 50000; /* Wait for 50 ms */
5718 
5719 	if (!adev->gfx.mec_fw)
5720 		return -EINVAL;
5721 
5722 	gfx_v10_0_cp_compute_enable(adev, false);
5723 
5724 	mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5725 	amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5726 
5727 	fw_data = (const __le32 *)
5728 		(adev->gfx.mec_fw->data +
5729 		 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5730 
5731 	/* Trigger an invalidation of the L1 instruction caches */
5732 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5733 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5734 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5735 
5736 	/* Wait for invalidation complete */
5737 	for (i = 0; i < usec_timeout; i++) {
5738 		tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5739 		if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5740 				       INVALIDATE_CACHE_COMPLETE))
5741 			break;
5742 		udelay(1);
5743 	}
5744 
5745 	if (i >= usec_timeout) {
5746 		dev_err(adev->dev, "failed to invalidate instruction cache\n");
5747 		return -EINVAL;
5748 	}
5749 
5750 	if (amdgpu_emu_mode == 1)
5751 		adev->nbio.funcs->hdp_flush(adev, NULL);
5752 
5753 	tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
5754 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
5755 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
5756 	tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5757 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
5758 
5759 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
5760 		     0xFFFFF000);
5761 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5762 		     upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
5763 
5764 	/* MEC1 */
5765 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
5766 
5767 	for (i = 0; i < mec_hdr->jt_size; i++)
5768 		WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
5769 			     le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
5770 
5771 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
5772 
5773 	/*
5774 	 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
5775 	 * different microcode than MEC1.
5776 	 */
5777 
5778 	return 0;
5779 }
5780 
5781 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
5782 {
5783 	uint32_t tmp;
5784 	struct amdgpu_device *adev = ring->adev;
5785 
5786 	/* tell RLC which is KIQ queue */
5787 	tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
5788 	tmp &= 0xffffff00;
5789 	tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
5790 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
5791 	tmp |= 0x80;
5792 	WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
5793 }
5794 
5795 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
5796 {
5797 	struct amdgpu_device *adev = ring->adev;
5798 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5799 	uint64_t hqd_gpu_addr, wb_gpu_addr;
5800 	uint32_t tmp;
5801 	uint32_t rb_bufsz;
5802 
5803 	/* set up gfx hqd wptr */
5804 	mqd->cp_gfx_hqd_wptr = 0;
5805 	mqd->cp_gfx_hqd_wptr_hi = 0;
5806 
5807 	/* set the pointer to the MQD */
5808 	mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
5809 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
5810 
5811 	/* set up mqd control */
5812 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
5813 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
5814 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
5815 	tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
5816 	mqd->cp_gfx_mqd_control = tmp;
5817 
5818 	/* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
5819 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
5820 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
5821 	mqd->cp_gfx_hqd_vmid = 0;
5822 
5823 	/* set up default queue priority level
5824 	 * 0x0 = low priority, 0x1 = high priority */
5825 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
5826 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
5827 	mqd->cp_gfx_hqd_queue_priority = tmp;
5828 
5829 	/* set up time quantum */
5830 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
5831 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
5832 	mqd->cp_gfx_hqd_quantum = tmp;
5833 
5834 	/* set up gfx hqd base. this is similar as CP_RB_BASE */
5835 	hqd_gpu_addr = ring->gpu_addr >> 8;
5836 	mqd->cp_gfx_hqd_base = hqd_gpu_addr;
5837 	mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
5838 
5839 	/* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
5840 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5841 	mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
5842 	mqd->cp_gfx_hqd_rptr_addr_hi =
5843 		upper_32_bits(wb_gpu_addr) & 0xffff;
5844 
5845 	/* set up rb_wptr_poll addr */
5846 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5847 	mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
5848 	mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
5849 
5850 	/* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
5851 	rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
5852 	tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
5853 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
5854 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
5855 #ifdef __BIG_ENDIAN
5856 	tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
5857 #endif
5858 	mqd->cp_gfx_hqd_cntl = tmp;
5859 
5860 	/* set up cp_doorbell_control */
5861 	tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5862 	if (ring->use_doorbell) {
5863 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5864 				    DOORBELL_OFFSET, ring->doorbell_index);
5865 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5866 				    DOORBELL_EN, 1);
5867 	} else
5868 		tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5869 				    DOORBELL_EN, 0);
5870 	mqd->cp_rb_doorbell_control = tmp;
5871 
5872 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
5873 	ring->wptr = 0;
5874 	mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
5875 
5876 	/* active the queue */
5877 	mqd->cp_gfx_hqd_active = 1;
5878 
5879 	return 0;
5880 }
5881 
5882 #ifdef BRING_UP_DEBUG
5883 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
5884 {
5885 	struct amdgpu_device *adev = ring->adev;
5886 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5887 
5888 	/* set mmCP_GFX_HQD_WPTR/_HI to 0 */
5889 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
5890 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
5891 
5892 	/* set GFX_MQD_BASE */
5893 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
5894 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
5895 
5896 	/* set GFX_MQD_CONTROL */
5897 	WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
5898 
5899 	/* set GFX_HQD_VMID to 0 */
5900 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
5901 
5902 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
5903 			mqd->cp_gfx_hqd_queue_priority);
5904 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
5905 
5906 	/* set GFX_HQD_BASE, similar as CP_RB_BASE */
5907 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
5908 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
5909 
5910 	/* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
5911 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
5912 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
5913 
5914 	/* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
5915 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
5916 
5917 	/* set RB_WPTR_POLL_ADDR */
5918 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
5919 	WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
5920 
5921 	/* set RB_DOORBELL_CONTROL */
5922 	WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
5923 
5924 	/* active the queue */
5925 	WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
5926 
5927 	return 0;
5928 }
5929 #endif
5930 
5931 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
5932 {
5933 	struct amdgpu_device *adev = ring->adev;
5934 	struct v10_gfx_mqd *mqd = ring->mqd_ptr;
5935 	int mqd_idx = ring - &adev->gfx.gfx_ring[0];
5936 
5937 	if (!adev->in_gpu_reset && !adev->in_suspend) {
5938 		memset((void *)mqd, 0, sizeof(*mqd));
5939 		mutex_lock(&adev->srbm_mutex);
5940 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5941 		gfx_v10_0_gfx_mqd_init(ring);
5942 #ifdef BRING_UP_DEBUG
5943 		gfx_v10_0_gfx_queue_init_register(ring);
5944 #endif
5945 		nv_grbm_select(adev, 0, 0, 0, 0);
5946 		mutex_unlock(&adev->srbm_mutex);
5947 		if (adev->gfx.me.mqd_backup[mqd_idx])
5948 			memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
5949 	} else if (adev->in_gpu_reset) {
5950 		/* reset mqd with the backup copy */
5951 		if (adev->gfx.me.mqd_backup[mqd_idx])
5952 			memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
5953 		/* reset the ring */
5954 		ring->wptr = 0;
5955 		adev->wb.wb[ring->wptr_offs] = 0;
5956 		amdgpu_ring_clear_ring(ring);
5957 #ifdef BRING_UP_DEBUG
5958 		mutex_lock(&adev->srbm_mutex);
5959 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
5960 		gfx_v10_0_gfx_queue_init_register(ring);
5961 		nv_grbm_select(adev, 0, 0, 0, 0);
5962 		mutex_unlock(&adev->srbm_mutex);
5963 #endif
5964 	} else {
5965 		amdgpu_ring_clear_ring(ring);
5966 	}
5967 
5968 	return 0;
5969 }
5970 
5971 #ifndef BRING_UP_DEBUG
5972 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
5973 {
5974 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
5975 	struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
5976 	int r, i;
5977 
5978 	if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
5979 		return -EINVAL;
5980 
5981 	r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
5982 					adev->gfx.num_gfx_rings);
5983 	if (r) {
5984 		DRM_ERROR("Failed to lock KIQ (%d).\n", r);
5985 		return r;
5986 	}
5987 
5988 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
5989 		kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
5990 
5991 	return amdgpu_ring_test_helper(kiq_ring);
5992 }
5993 #endif
5994 
5995 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
5996 {
5997 	int r, i;
5998 	struct amdgpu_ring *ring;
5999 
6000 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6001 		ring = &adev->gfx.gfx_ring[i];
6002 
6003 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6004 		if (unlikely(r != 0))
6005 			goto done;
6006 
6007 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6008 		if (!r) {
6009 			r = gfx_v10_0_gfx_init_queue(ring);
6010 			amdgpu_bo_kunmap(ring->mqd_obj);
6011 			ring->mqd_ptr = NULL;
6012 		}
6013 		amdgpu_bo_unreserve(ring->mqd_obj);
6014 		if (r)
6015 			goto done;
6016 	}
6017 #ifndef BRING_UP_DEBUG
6018 	r = gfx_v10_0_kiq_enable_kgq(adev);
6019 	if (r)
6020 		goto done;
6021 #endif
6022 	r = gfx_v10_0_cp_gfx_start(adev);
6023 	if (r)
6024 		goto done;
6025 
6026 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6027 		ring = &adev->gfx.gfx_ring[i];
6028 		ring->sched.ready = true;
6029 	}
6030 done:
6031 	return r;
6032 }
6033 
6034 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6035 {
6036 	struct amdgpu_device *adev = ring->adev;
6037 
6038 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6039 		if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6040 			mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6041 			mqd->cp_hqd_queue_priority =
6042 				AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6043 		}
6044 	}
6045 }
6046 
6047 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6048 {
6049 	struct amdgpu_device *adev = ring->adev;
6050 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6051 	uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6052 	uint32_t tmp;
6053 
6054 	mqd->header = 0xC0310800;
6055 	mqd->compute_pipelinestat_enable = 0x00000001;
6056 	mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6057 	mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6058 	mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6059 	mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6060 	mqd->compute_misc_reserved = 0x00000003;
6061 
6062 	eop_base_addr = ring->eop_gpu_addr >> 8;
6063 	mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6064 	mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6065 
6066 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6067 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6068 	tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6069 			(order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6070 
6071 	mqd->cp_hqd_eop_control = tmp;
6072 
6073 	/* enable doorbell? */
6074 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6075 
6076 	if (ring->use_doorbell) {
6077 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6078 				    DOORBELL_OFFSET, ring->doorbell_index);
6079 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6080 				    DOORBELL_EN, 1);
6081 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6082 				    DOORBELL_SOURCE, 0);
6083 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6084 				    DOORBELL_HIT, 0);
6085 	} else {
6086 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6087 				    DOORBELL_EN, 0);
6088 	}
6089 
6090 	mqd->cp_hqd_pq_doorbell_control = tmp;
6091 
6092 	/* disable the queue if it's active */
6093 	ring->wptr = 0;
6094 	mqd->cp_hqd_dequeue_request = 0;
6095 	mqd->cp_hqd_pq_rptr = 0;
6096 	mqd->cp_hqd_pq_wptr_lo = 0;
6097 	mqd->cp_hqd_pq_wptr_hi = 0;
6098 
6099 	/* set the pointer to the MQD */
6100 	mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6101 	mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6102 
6103 	/* set MQD vmid to 0 */
6104 	tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6105 	tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6106 	mqd->cp_mqd_control = tmp;
6107 
6108 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6109 	hqd_gpu_addr = ring->gpu_addr >> 8;
6110 	mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6111 	mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6112 
6113 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6114 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6115 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6116 			    (order_base_2(ring->ring_size / 4) - 1));
6117 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6118 			    ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6119 #ifdef __BIG_ENDIAN
6120 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6121 #endif
6122 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6123 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6124 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6125 	tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6126 	mqd->cp_hqd_pq_control = tmp;
6127 
6128 	/* set the wb address whether it's enabled or not */
6129 	wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6130 	mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6131 	mqd->cp_hqd_pq_rptr_report_addr_hi =
6132 		upper_32_bits(wb_gpu_addr) & 0xffff;
6133 
6134 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6135 	wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6136 	mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6137 	mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6138 
6139 	tmp = 0;
6140 	/* enable the doorbell if requested */
6141 	if (ring->use_doorbell) {
6142 		tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6143 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6144 				DOORBELL_OFFSET, ring->doorbell_index);
6145 
6146 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6147 				    DOORBELL_EN, 1);
6148 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6149 				    DOORBELL_SOURCE, 0);
6150 		tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6151 				    DOORBELL_HIT, 0);
6152 	}
6153 
6154 	mqd->cp_hqd_pq_doorbell_control = tmp;
6155 
6156 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6157 	ring->wptr = 0;
6158 	mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6159 
6160 	/* set the vmid for the queue */
6161 	mqd->cp_hqd_vmid = 0;
6162 
6163 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6164 	tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6165 	mqd->cp_hqd_persistent_state = tmp;
6166 
6167 	/* set MIN_IB_AVAIL_SIZE */
6168 	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6169 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6170 	mqd->cp_hqd_ib_control = tmp;
6171 
6172 	/* set static priority for a compute queue/ring */
6173 	gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6174 
6175 	/* map_queues packet doesn't need activate the queue,
6176 	 * so only kiq need set this field.
6177 	 */
6178 	if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6179 		mqd->cp_hqd_active = 1;
6180 
6181 	return 0;
6182 }
6183 
6184 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6185 {
6186 	struct amdgpu_device *adev = ring->adev;
6187 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6188 	int j;
6189 
6190 	/* disable wptr polling */
6191 	WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6192 
6193 	/* write the EOP addr */
6194 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6195 	       mqd->cp_hqd_eop_base_addr_lo);
6196 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6197 	       mqd->cp_hqd_eop_base_addr_hi);
6198 
6199 	/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6200 	WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6201 	       mqd->cp_hqd_eop_control);
6202 
6203 	/* enable doorbell? */
6204 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6205 	       mqd->cp_hqd_pq_doorbell_control);
6206 
6207 	/* disable the queue if it's active */
6208 	if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6209 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6210 		for (j = 0; j < adev->usec_timeout; j++) {
6211 			if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6212 				break;
6213 			udelay(1);
6214 		}
6215 		WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6216 		       mqd->cp_hqd_dequeue_request);
6217 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6218 		       mqd->cp_hqd_pq_rptr);
6219 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6220 		       mqd->cp_hqd_pq_wptr_lo);
6221 		WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6222 		       mqd->cp_hqd_pq_wptr_hi);
6223 	}
6224 
6225 	/* set the pointer to the MQD */
6226 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6227 	       mqd->cp_mqd_base_addr_lo);
6228 	WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6229 	       mqd->cp_mqd_base_addr_hi);
6230 
6231 	/* set MQD vmid to 0 */
6232 	WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6233 	       mqd->cp_mqd_control);
6234 
6235 	/* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6236 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6237 	       mqd->cp_hqd_pq_base_lo);
6238 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6239 	       mqd->cp_hqd_pq_base_hi);
6240 
6241 	/* set up the HQD, this is similar to CP_RB0_CNTL */
6242 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6243 	       mqd->cp_hqd_pq_control);
6244 
6245 	/* set the wb address whether it's enabled or not */
6246 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6247 		mqd->cp_hqd_pq_rptr_report_addr_lo);
6248 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6249 		mqd->cp_hqd_pq_rptr_report_addr_hi);
6250 
6251 	/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6252 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6253 	       mqd->cp_hqd_pq_wptr_poll_addr_lo);
6254 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6255 	       mqd->cp_hqd_pq_wptr_poll_addr_hi);
6256 
6257 	/* enable the doorbell if requested */
6258 	if (ring->use_doorbell) {
6259 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6260 			(adev->doorbell_index.kiq * 2) << 2);
6261 		WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6262 			(adev->doorbell_index.userqueue_end * 2) << 2);
6263 	}
6264 
6265 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6266 	       mqd->cp_hqd_pq_doorbell_control);
6267 
6268 	/* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6269 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6270 	       mqd->cp_hqd_pq_wptr_lo);
6271 	WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6272 	       mqd->cp_hqd_pq_wptr_hi);
6273 
6274 	/* set the vmid for the queue */
6275 	WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6276 
6277 	WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6278 	       mqd->cp_hqd_persistent_state);
6279 
6280 	/* activate the queue */
6281 	WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6282 	       mqd->cp_hqd_active);
6283 
6284 	if (ring->use_doorbell)
6285 		WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6286 
6287 	return 0;
6288 }
6289 
6290 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6291 {
6292 	struct amdgpu_device *adev = ring->adev;
6293 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6294 	int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6295 
6296 	gfx_v10_0_kiq_setting(ring);
6297 
6298 	if (adev->in_gpu_reset) { /* for GPU_RESET case */
6299 		/* reset MQD to a clean status */
6300 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6301 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6302 
6303 		/* reset ring buffer */
6304 		ring->wptr = 0;
6305 		amdgpu_ring_clear_ring(ring);
6306 
6307 		mutex_lock(&adev->srbm_mutex);
6308 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6309 		gfx_v10_0_kiq_init_register(ring);
6310 		nv_grbm_select(adev, 0, 0, 0, 0);
6311 		mutex_unlock(&adev->srbm_mutex);
6312 	} else {
6313 		memset((void *)mqd, 0, sizeof(*mqd));
6314 		mutex_lock(&adev->srbm_mutex);
6315 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6316 		gfx_v10_0_compute_mqd_init(ring);
6317 		gfx_v10_0_kiq_init_register(ring);
6318 		nv_grbm_select(adev, 0, 0, 0, 0);
6319 		mutex_unlock(&adev->srbm_mutex);
6320 
6321 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6322 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6323 	}
6324 
6325 	return 0;
6326 }
6327 
6328 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6329 {
6330 	struct amdgpu_device *adev = ring->adev;
6331 	struct v10_compute_mqd *mqd = ring->mqd_ptr;
6332 	int mqd_idx = ring - &adev->gfx.compute_ring[0];
6333 
6334 	if (!adev->in_gpu_reset && !adev->in_suspend) {
6335 		memset((void *)mqd, 0, sizeof(*mqd));
6336 		mutex_lock(&adev->srbm_mutex);
6337 		nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6338 		gfx_v10_0_compute_mqd_init(ring);
6339 		nv_grbm_select(adev, 0, 0, 0, 0);
6340 		mutex_unlock(&adev->srbm_mutex);
6341 
6342 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6343 			memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6344 	} else if (adev->in_gpu_reset) { /* for GPU_RESET case */
6345 		/* reset MQD to a clean status */
6346 		if (adev->gfx.mec.mqd_backup[mqd_idx])
6347 			memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6348 
6349 		/* reset ring buffer */
6350 		ring->wptr = 0;
6351 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6352 		amdgpu_ring_clear_ring(ring);
6353 	} else {
6354 		amdgpu_ring_clear_ring(ring);
6355 	}
6356 
6357 	return 0;
6358 }
6359 
6360 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6361 {
6362 	struct amdgpu_ring *ring;
6363 	int r;
6364 
6365 	ring = &adev->gfx.kiq.ring;
6366 
6367 	r = amdgpu_bo_reserve(ring->mqd_obj, false);
6368 	if (unlikely(r != 0))
6369 		return r;
6370 
6371 	r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6372 	if (unlikely(r != 0))
6373 		return r;
6374 
6375 	gfx_v10_0_kiq_init_queue(ring);
6376 	amdgpu_bo_kunmap(ring->mqd_obj);
6377 	ring->mqd_ptr = NULL;
6378 	amdgpu_bo_unreserve(ring->mqd_obj);
6379 	ring->sched.ready = true;
6380 	return 0;
6381 }
6382 
6383 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6384 {
6385 	struct amdgpu_ring *ring = NULL;
6386 	int r = 0, i;
6387 
6388 	gfx_v10_0_cp_compute_enable(adev, true);
6389 
6390 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6391 		ring = &adev->gfx.compute_ring[i];
6392 
6393 		r = amdgpu_bo_reserve(ring->mqd_obj, false);
6394 		if (unlikely(r != 0))
6395 			goto done;
6396 		r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6397 		if (!r) {
6398 			r = gfx_v10_0_kcq_init_queue(ring);
6399 			amdgpu_bo_kunmap(ring->mqd_obj);
6400 			ring->mqd_ptr = NULL;
6401 		}
6402 		amdgpu_bo_unreserve(ring->mqd_obj);
6403 		if (r)
6404 			goto done;
6405 	}
6406 
6407 	r = amdgpu_gfx_enable_kcq(adev);
6408 done:
6409 	return r;
6410 }
6411 
6412 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6413 {
6414 	int r, i;
6415 	struct amdgpu_ring *ring;
6416 
6417 	if (!(adev->flags & AMD_IS_APU))
6418 		gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6419 
6420 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6421 		/* legacy firmware loading */
6422 		r = gfx_v10_0_cp_gfx_load_microcode(adev);
6423 		if (r)
6424 			return r;
6425 
6426 		r = gfx_v10_0_cp_compute_load_microcode(adev);
6427 		if (r)
6428 			return r;
6429 	}
6430 
6431 	r = gfx_v10_0_kiq_resume(adev);
6432 	if (r)
6433 		return r;
6434 
6435 	r = gfx_v10_0_kcq_resume(adev);
6436 	if (r)
6437 		return r;
6438 
6439 	if (!amdgpu_async_gfx_ring) {
6440 		r = gfx_v10_0_cp_gfx_resume(adev);
6441 		if (r)
6442 			return r;
6443 	} else {
6444 		r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6445 		if (r)
6446 			return r;
6447 	}
6448 
6449 	for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6450 		ring = &adev->gfx.gfx_ring[i];
6451 		r = amdgpu_ring_test_helper(ring);
6452 		if (r)
6453 			return r;
6454 	}
6455 
6456 	for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6457 		ring = &adev->gfx.compute_ring[i];
6458 		r = amdgpu_ring_test_helper(ring);
6459 		if (r)
6460 			return r;
6461 	}
6462 
6463 	return 0;
6464 }
6465 
6466 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6467 {
6468 	gfx_v10_0_cp_gfx_enable(adev, enable);
6469 	gfx_v10_0_cp_compute_enable(adev, enable);
6470 }
6471 
6472 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6473 {
6474 	uint32_t data, pattern = 0xDEADBEEF;
6475 
6476 	/* check if mmVGT_ESGS_RING_SIZE_UMD
6477 	 * has been remapped to mmVGT_ESGS_RING_SIZE */
6478 	data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6479 
6480 	WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6481 
6482 	WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6483 
6484 	if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6485 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6486 		return true;
6487 	} else {
6488 		WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6489 		return false;
6490 	}
6491 }
6492 
6493 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6494 {
6495 	uint32_t data;
6496 
6497 	/* initialize cam_index to 0
6498 	 * index will auto-inc after each data writting */
6499 	WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6500 
6501 	/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6502 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6503 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6504 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6505 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6506 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6507 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6508 
6509 	/* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6510 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6511 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6512 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6513 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6514 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6515 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6516 
6517 	/* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6518 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6519 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6520 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6521 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6522 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6523 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6524 
6525 	/* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6526 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6527 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6528 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6529 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6530 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6531 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6532 
6533 	/* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6534 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6535 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6536 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6537 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6538 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6539 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6540 
6541 	/* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6542 	data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6543 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6544 	       (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6545 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6546 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6547 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6548 
6549 	/* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6550 	data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6551 		GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6552 	       (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6553 		GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6554 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6555 	WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6556 }
6557 
6558 static int gfx_v10_0_hw_init(void *handle)
6559 {
6560 	int r;
6561 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6562 
6563 	if (!amdgpu_emu_mode)
6564 		gfx_v10_0_init_golden_registers(adev);
6565 
6566 	if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6567 		/**
6568 		 * For gfx 10, rlc firmware loading relies on smu firmware is
6569 		 * loaded firstly, so in direct type, it has to load smc ucode
6570 		 * here before rlc.
6571 		 */
6572 		if (adev->smu.ppt_funcs != NULL) {
6573 			r = smu_load_microcode(&adev->smu);
6574 			if (r)
6575 				return r;
6576 
6577 			r = smu_check_fw_status(&adev->smu);
6578 			if (r) {
6579 				pr_err("SMC firmware status is not correct\n");
6580 				return r;
6581 			}
6582 		}
6583 	}
6584 
6585 	/* if GRBM CAM not remapped, set up the remapping */
6586 	if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6587 		gfx_v10_0_setup_grbm_cam_remapping(adev);
6588 
6589 	gfx_v10_0_constants_init(adev);
6590 
6591 	r = gfx_v10_0_rlc_resume(adev);
6592 	if (r)
6593 		return r;
6594 
6595 	/*
6596 	 * init golden registers and rlc resume may override some registers,
6597 	 * reconfig them here
6598 	 */
6599 	gfx_v10_0_tcp_harvest(adev);
6600 
6601 	r = gfx_v10_0_cp_resume(adev);
6602 	if (r)
6603 		return r;
6604 
6605 	return r;
6606 }
6607 
6608 #ifndef BRING_UP_DEBUG
6609 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6610 {
6611 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6612 	struct amdgpu_ring *kiq_ring = &kiq->ring;
6613 	int i;
6614 
6615 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6616 		return -EINVAL;
6617 
6618 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6619 					adev->gfx.num_gfx_rings))
6620 		return -ENOMEM;
6621 
6622 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6623 		kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6624 					   PREEMPT_QUEUES, 0, 0);
6625 
6626 	return amdgpu_ring_test_helper(kiq_ring);
6627 }
6628 #endif
6629 
6630 static int gfx_v10_0_hw_fini(void *handle)
6631 {
6632 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6633 	int r;
6634 
6635 	amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6636 	amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6637 #ifndef BRING_UP_DEBUG
6638 	if (amdgpu_async_gfx_ring) {
6639 		r = gfx_v10_0_kiq_disable_kgq(adev);
6640 		if (r)
6641 			DRM_ERROR("KGQ disable failed\n");
6642 	}
6643 #endif
6644 	if (amdgpu_gfx_disable_kcq(adev))
6645 		DRM_ERROR("KCQ disable failed\n");
6646 	if (amdgpu_sriov_vf(adev)) {
6647 		gfx_v10_0_cp_gfx_enable(adev, false);
6648 		return 0;
6649 	}
6650 	gfx_v10_0_cp_enable(adev, false);
6651 	gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6652 
6653 	return 0;
6654 }
6655 
6656 static int gfx_v10_0_suspend(void *handle)
6657 {
6658 	return gfx_v10_0_hw_fini(handle);
6659 }
6660 
6661 static int gfx_v10_0_resume(void *handle)
6662 {
6663 	return gfx_v10_0_hw_init(handle);
6664 }
6665 
6666 static bool gfx_v10_0_is_idle(void *handle)
6667 {
6668 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6669 
6670 	if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
6671 				GRBM_STATUS, GUI_ACTIVE))
6672 		return false;
6673 	else
6674 		return true;
6675 }
6676 
6677 static int gfx_v10_0_wait_for_idle(void *handle)
6678 {
6679 	unsigned i;
6680 	u32 tmp;
6681 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6682 
6683 	for (i = 0; i < adev->usec_timeout; i++) {
6684 		/* read MC_STATUS */
6685 		tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
6686 			GRBM_STATUS__GUI_ACTIVE_MASK;
6687 
6688 		if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
6689 			return 0;
6690 		udelay(1);
6691 	}
6692 	return -ETIMEDOUT;
6693 }
6694 
6695 static int gfx_v10_0_soft_reset(void *handle)
6696 {
6697 	u32 grbm_soft_reset = 0;
6698 	u32 tmp;
6699 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6700 
6701 	/* GRBM_STATUS */
6702 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
6703 	if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
6704 		   GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
6705 		   GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
6706 		   GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
6707 		   GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK
6708 		   | GRBM_STATUS__BCI_BUSY_MASK)) {
6709 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6710 						GRBM_SOFT_RESET, SOFT_RESET_CP,
6711 						1);
6712 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6713 						GRBM_SOFT_RESET, SOFT_RESET_GFX,
6714 						1);
6715 	}
6716 
6717 	if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
6718 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6719 						GRBM_SOFT_RESET, SOFT_RESET_CP,
6720 						1);
6721 	}
6722 
6723 	/* GRBM_STATUS2 */
6724 	tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
6725 	if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
6726 		grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
6727 						GRBM_SOFT_RESET, SOFT_RESET_RLC,
6728 						1);
6729 
6730 	if (grbm_soft_reset) {
6731 		/* stop the rlc */
6732 		gfx_v10_0_rlc_stop(adev);
6733 
6734 		/* Disable GFX parsing/prefetching */
6735 		gfx_v10_0_cp_gfx_enable(adev, false);
6736 
6737 		/* Disable MEC parsing/prefetching */
6738 		gfx_v10_0_cp_compute_enable(adev, false);
6739 
6740 		if (grbm_soft_reset) {
6741 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
6742 			tmp |= grbm_soft_reset;
6743 			dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
6744 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
6745 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
6746 
6747 			udelay(50);
6748 
6749 			tmp &= ~grbm_soft_reset;
6750 			WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
6751 			tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
6752 		}
6753 
6754 		/* Wait a little for things to settle down */
6755 		udelay(50);
6756 	}
6757 	return 0;
6758 }
6759 
6760 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
6761 {
6762 	uint64_t clock;
6763 
6764 	amdgpu_gfx_off_ctrl(adev, false);
6765 	mutex_lock(&adev->gfx.gpu_clock_mutex);
6766 	clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
6767 		((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
6768 	mutex_unlock(&adev->gfx.gpu_clock_mutex);
6769 	amdgpu_gfx_off_ctrl(adev, true);
6770 	return clock;
6771 }
6772 
6773 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
6774 					   uint32_t vmid,
6775 					   uint32_t gds_base, uint32_t gds_size,
6776 					   uint32_t gws_base, uint32_t gws_size,
6777 					   uint32_t oa_base, uint32_t oa_size)
6778 {
6779 	struct amdgpu_device *adev = ring->adev;
6780 
6781 	/* GDS Base */
6782 	gfx_v10_0_write_data_to_reg(ring, 0, false,
6783 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
6784 				    gds_base);
6785 
6786 	/* GDS Size */
6787 	gfx_v10_0_write_data_to_reg(ring, 0, false,
6788 				    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
6789 				    gds_size);
6790 
6791 	/* GWS */
6792 	gfx_v10_0_write_data_to_reg(ring, 0, false,
6793 				    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
6794 				    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
6795 
6796 	/* OA */
6797 	gfx_v10_0_write_data_to_reg(ring, 0, false,
6798 				    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
6799 				    (1 << (oa_size + oa_base)) - (1 << oa_base));
6800 }
6801 
6802 static int gfx_v10_0_early_init(void *handle)
6803 {
6804 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6805 
6806 	adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
6807 
6808 	adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
6809 
6810 	gfx_v10_0_set_kiq_pm4_funcs(adev);
6811 	gfx_v10_0_set_ring_funcs(adev);
6812 	gfx_v10_0_set_irq_funcs(adev);
6813 	gfx_v10_0_set_gds_init(adev);
6814 	gfx_v10_0_set_rlc_funcs(adev);
6815 
6816 	return 0;
6817 }
6818 
6819 static int gfx_v10_0_late_init(void *handle)
6820 {
6821 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6822 	int r;
6823 
6824 	r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
6825 	if (r)
6826 		return r;
6827 
6828 	r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
6829 	if (r)
6830 		return r;
6831 
6832 	return 0;
6833 }
6834 
6835 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
6836 {
6837 	uint32_t rlc_cntl;
6838 
6839 	/* if RLC is not enabled, do nothing */
6840 	rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
6841 	return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
6842 }
6843 
6844 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
6845 {
6846 	uint32_t data;
6847 	unsigned i;
6848 
6849 	data = RLC_SAFE_MODE__CMD_MASK;
6850 	data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
6851 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
6852 
6853 	/* wait for RLC_SAFE_MODE */
6854 	for (i = 0; i < adev->usec_timeout; i++) {
6855 		if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
6856 			break;
6857 		udelay(1);
6858 	}
6859 }
6860 
6861 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
6862 {
6863 	uint32_t data;
6864 
6865 	data = RLC_SAFE_MODE__CMD_MASK;
6866 	WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
6867 }
6868 
6869 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
6870 						      bool enable)
6871 {
6872 	uint32_t data, def;
6873 
6874 	/* It is disabled by HW by default */
6875 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
6876 		/* 0 - Disable some blocks' MGCG */
6877 		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
6878 		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
6879 		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
6880 		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
6881 
6882 		/* 1 - RLC_CGTT_MGCG_OVERRIDE */
6883 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6884 		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
6885 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
6886 			  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
6887 
6888 		/* only for Vega10 & Raven1 */
6889 		data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
6890 
6891 		if (def != data)
6892 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6893 
6894 		/* MGLS is a global flag to control all MGLS in GFX */
6895 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
6896 			/* 2 - RLC memory Light sleep */
6897 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
6898 				def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
6899 				data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
6900 				if (def != data)
6901 					WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
6902 			}
6903 			/* 3 - CP memory Light sleep */
6904 			if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
6905 				def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
6906 				data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
6907 				if (def != data)
6908 					WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
6909 			}
6910 		}
6911 	} else {
6912 		/* 1 - MGCG_OVERRIDE */
6913 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6914 		data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
6915 			 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
6916 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
6917 			 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
6918 		if (def != data)
6919 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6920 
6921 		/* 2 - disable MGLS in CP */
6922 		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
6923 		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
6924 			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
6925 			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
6926 		}
6927 
6928 		/* 3 - disable MGLS in RLC */
6929 		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
6930 		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
6931 			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
6932 			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
6933 		}
6934 
6935 	}
6936 }
6937 
6938 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
6939 					   bool enable)
6940 {
6941 	uint32_t data, def;
6942 
6943 	/* Enable 3D CGCG/CGLS */
6944 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
6945 		/* write cmd to clear cgcg/cgls ov */
6946 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6947 		/* unset CGCG override */
6948 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
6949 		/* update CGCG and CGLS override bits */
6950 		if (def != data)
6951 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6952 		/* enable 3Dcgcg FSM(0x0000363f) */
6953 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
6954 		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
6955 			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
6956 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
6957 			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
6958 				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
6959 		if (def != data)
6960 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
6961 
6962 		/* set IDLE_POLL_COUNT(0x00900100) */
6963 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
6964 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
6965 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
6966 		if (def != data)
6967 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
6968 	} else {
6969 		/* Disable CGCG/CGLS */
6970 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
6971 		/* disable cgcg, cgls should be disabled */
6972 		data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
6973 			  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
6974 		/* disable cgcg and cgls in FSM */
6975 		if (def != data)
6976 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
6977 	}
6978 }
6979 
6980 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
6981 						      bool enable)
6982 {
6983 	uint32_t def, data;
6984 
6985 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
6986 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
6987 		/* unset CGCG override */
6988 		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
6989 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
6990 			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
6991 		else
6992 			data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
6993 		/* update CGCG and CGLS override bits */
6994 		if (def != data)
6995 			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
6996 
6997 		/* enable cgcg FSM(0x0000363F) */
6998 		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
6999 		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7000 			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7001 		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7002 			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7003 				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7004 		if (def != data)
7005 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7006 
7007 		/* set IDLE_POLL_COUNT(0x00900100) */
7008 		def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7009 		data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7010 			(0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7011 		if (def != data)
7012 			WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7013 	} else {
7014 		def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7015 		/* reset CGCG/CGLS bits */
7016 		data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7017 		/* disable cgcg and cgls in FSM */
7018 		if (def != data)
7019 			WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7020 	}
7021 }
7022 
7023 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7024 					    bool enable)
7025 {
7026 	amdgpu_gfx_rlc_enter_safe_mode(adev);
7027 
7028 	if (enable) {
7029 		/* CGCG/CGLS should be enabled after MGCG/MGLS
7030 		 * ===  MGCG + MGLS ===
7031 		 */
7032 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7033 		/* ===  CGCG /CGLS for GFX 3D Only === */
7034 		gfx_v10_0_update_3d_clock_gating(adev, enable);
7035 		/* ===  CGCG + CGLS === */
7036 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7037 	} else {
7038 		/* CGCG/CGLS should be disabled before MGCG/MGLS
7039 		 * ===  CGCG + CGLS ===
7040 		 */
7041 		gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7042 		/* ===  CGCG /CGLS for GFX 3D Only === */
7043 		gfx_v10_0_update_3d_clock_gating(adev, enable);
7044 		/* ===  MGCG + MGLS === */
7045 		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7046 	}
7047 
7048 	if (adev->cg_flags &
7049 	    (AMD_CG_SUPPORT_GFX_MGCG |
7050 	     AMD_CG_SUPPORT_GFX_CGLS |
7051 	     AMD_CG_SUPPORT_GFX_CGCG |
7052 	     AMD_CG_SUPPORT_GFX_CGLS |
7053 	     AMD_CG_SUPPORT_GFX_3D_CGCG |
7054 	     AMD_CG_SUPPORT_GFX_3D_CGLS))
7055 		gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7056 
7057 	amdgpu_gfx_rlc_exit_safe_mode(adev);
7058 
7059 	return 0;
7060 }
7061 
7062 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7063 {
7064 	u32 reg, data;
7065 
7066 	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7067 	if (amdgpu_sriov_is_pp_one_vf(adev))
7068 		data = RREG32_NO_KIQ(reg);
7069 	else
7070 		data = RREG32(reg);
7071 
7072 	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7073 	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7074 
7075 	if (amdgpu_sriov_is_pp_one_vf(adev))
7076 		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7077 	else
7078 		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7079 }
7080 
7081 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7082 					uint32_t offset,
7083 					struct soc15_reg_rlcg *entries, int arr_size)
7084 {
7085 	int i;
7086 	uint32_t reg;
7087 
7088 	if (!entries)
7089 		return false;
7090 
7091 	for (i = 0; i < arr_size; i++) {
7092 		const struct soc15_reg_rlcg *entry;
7093 
7094 		entry = &entries[i];
7095 		reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7096 		if (offset == reg)
7097 			return true;
7098 	}
7099 
7100 	return false;
7101 }
7102 
7103 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7104 {
7105 	return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7106 }
7107 
7108 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7109 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7110 	.set_safe_mode = gfx_v10_0_set_safe_mode,
7111 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
7112 	.init = gfx_v10_0_rlc_init,
7113 	.get_csb_size = gfx_v10_0_get_csb_size,
7114 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
7115 	.resume = gfx_v10_0_rlc_resume,
7116 	.stop = gfx_v10_0_rlc_stop,
7117 	.reset = gfx_v10_0_rlc_reset,
7118 	.start = gfx_v10_0_rlc_start,
7119 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
7120 };
7121 
7122 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7123 	.is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7124 	.set_safe_mode = gfx_v10_0_set_safe_mode,
7125 	.unset_safe_mode = gfx_v10_0_unset_safe_mode,
7126 	.init = gfx_v10_0_rlc_init,
7127 	.get_csb_size = gfx_v10_0_get_csb_size,
7128 	.get_csb_buffer = gfx_v10_0_get_csb_buffer,
7129 	.resume = gfx_v10_0_rlc_resume,
7130 	.stop = gfx_v10_0_rlc_stop,
7131 	.reset = gfx_v10_0_rlc_reset,
7132 	.start = gfx_v10_0_rlc_start,
7133 	.update_spm_vmid = gfx_v10_0_update_spm_vmid,
7134 	.rlcg_wreg = gfx_v10_rlcg_wreg,
7135 	.is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7136 };
7137 
7138 static int gfx_v10_0_set_powergating_state(void *handle,
7139 					  enum amd_powergating_state state)
7140 {
7141 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7142 	bool enable = (state == AMD_PG_STATE_GATE);
7143 
7144 	if (amdgpu_sriov_vf(adev))
7145 		return 0;
7146 
7147 	switch (adev->asic_type) {
7148 	case CHIP_NAVI10:
7149 	case CHIP_NAVI14:
7150 	case CHIP_NAVI12:
7151 		amdgpu_gfx_off_ctrl(adev, enable);
7152 		break;
7153 	default:
7154 		break;
7155 	}
7156 	return 0;
7157 }
7158 
7159 static int gfx_v10_0_set_clockgating_state(void *handle,
7160 					  enum amd_clockgating_state state)
7161 {
7162 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7163 
7164 	if (amdgpu_sriov_vf(adev))
7165 		return 0;
7166 
7167 	switch (adev->asic_type) {
7168 	case CHIP_NAVI10:
7169 	case CHIP_NAVI14:
7170 	case CHIP_NAVI12:
7171 	case CHIP_SIENNA_CICHLID:
7172 		gfx_v10_0_update_gfx_clock_gating(adev,
7173 						 state == AMD_CG_STATE_GATE);
7174 		break;
7175 	default:
7176 		break;
7177 	}
7178 	return 0;
7179 }
7180 
7181 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7182 {
7183 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7184 	int data;
7185 
7186 	/* AMD_CG_SUPPORT_GFX_MGCG */
7187 	data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7188 	if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7189 		*flags |= AMD_CG_SUPPORT_GFX_MGCG;
7190 
7191 	/* AMD_CG_SUPPORT_GFX_CGCG */
7192 	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7193 	if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7194 		*flags |= AMD_CG_SUPPORT_GFX_CGCG;
7195 
7196 	/* AMD_CG_SUPPORT_GFX_CGLS */
7197 	if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7198 		*flags |= AMD_CG_SUPPORT_GFX_CGLS;
7199 
7200 	/* AMD_CG_SUPPORT_GFX_RLC_LS */
7201 	data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7202 	if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7203 		*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7204 
7205 	/* AMD_CG_SUPPORT_GFX_CP_LS */
7206 	data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7207 	if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7208 		*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7209 
7210 	/* AMD_CG_SUPPORT_GFX_3D_CGCG */
7211 	data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7212 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7213 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7214 
7215 	/* AMD_CG_SUPPORT_GFX_3D_CGLS */
7216 	if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7217 		*flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7218 }
7219 
7220 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7221 {
7222 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7223 }
7224 
7225 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7226 {
7227 	struct amdgpu_device *adev = ring->adev;
7228 	u64 wptr;
7229 
7230 	/* XXX check if swapping is necessary on BE */
7231 	if (ring->use_doorbell) {
7232 		wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7233 	} else {
7234 		wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7235 		wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7236 	}
7237 
7238 	return wptr;
7239 }
7240 
7241 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7242 {
7243 	struct amdgpu_device *adev = ring->adev;
7244 
7245 	if (ring->use_doorbell) {
7246 		/* XXX check if swapping is necessary on BE */
7247 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7248 		WDOORBELL64(ring->doorbell_index, ring->wptr);
7249 	} else {
7250 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7251 		WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7252 	}
7253 }
7254 
7255 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7256 {
7257 	return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7258 }
7259 
7260 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7261 {
7262 	u64 wptr;
7263 
7264 	/* XXX check if swapping is necessary on BE */
7265 	if (ring->use_doorbell)
7266 		wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7267 	else
7268 		BUG();
7269 	return wptr;
7270 }
7271 
7272 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7273 {
7274 	struct amdgpu_device *adev = ring->adev;
7275 
7276 	/* XXX check if swapping is necessary on BE */
7277 	if (ring->use_doorbell) {
7278 		atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7279 		WDOORBELL64(ring->doorbell_index, ring->wptr);
7280 	} else {
7281 		BUG(); /* only DOORBELL method supported on gfx10 now */
7282 	}
7283 }
7284 
7285 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7286 {
7287 	struct amdgpu_device *adev = ring->adev;
7288 	u32 ref_and_mask, reg_mem_engine;
7289 	const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7290 
7291 	if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7292 		switch (ring->me) {
7293 		case 1:
7294 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7295 			break;
7296 		case 2:
7297 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7298 			break;
7299 		default:
7300 			return;
7301 		}
7302 		reg_mem_engine = 0;
7303 	} else {
7304 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7305 		reg_mem_engine = 1; /* pfp */
7306 	}
7307 
7308 	gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7309 			       adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7310 			       adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7311 			       ref_and_mask, ref_and_mask, 0x20);
7312 }
7313 
7314 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7315 				       struct amdgpu_job *job,
7316 				       struct amdgpu_ib *ib,
7317 				       uint32_t flags)
7318 {
7319 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7320 	u32 header, control = 0;
7321 
7322 	if (ib->flags & AMDGPU_IB_FLAG_CE)
7323 		header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7324 	else
7325 		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7326 
7327 	control |= ib->length_dw | (vmid << 24);
7328 
7329 	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7330 		control |= INDIRECT_BUFFER_PRE_ENB(1);
7331 
7332 		if (flags & AMDGPU_IB_PREEMPTED)
7333 			control |= INDIRECT_BUFFER_PRE_RESUME(1);
7334 
7335 		if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7336 			gfx_v10_0_ring_emit_de_meta(ring,
7337 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7338 	}
7339 
7340 	amdgpu_ring_write(ring, header);
7341 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7342 	amdgpu_ring_write(ring,
7343 #ifdef __BIG_ENDIAN
7344 		(2 << 0) |
7345 #endif
7346 		lower_32_bits(ib->gpu_addr));
7347 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7348 	amdgpu_ring_write(ring, control);
7349 }
7350 
7351 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7352 					   struct amdgpu_job *job,
7353 					   struct amdgpu_ib *ib,
7354 					   uint32_t flags)
7355 {
7356 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7357 	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7358 
7359 	/* Currently, there is a high possibility to get wave ID mismatch
7360 	 * between ME and GDS, leading to a hw deadlock, because ME generates
7361 	 * different wave IDs than the GDS expects. This situation happens
7362 	 * randomly when at least 5 compute pipes use GDS ordered append.
7363 	 * The wave IDs generated by ME are also wrong after suspend/resume.
7364 	 * Those are probably bugs somewhere else in the kernel driver.
7365 	 *
7366 	 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7367 	 * GDS to 0 for this ring (me/pipe).
7368 	 */
7369 	if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7370 		amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7371 		amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7372 		amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7373 	}
7374 
7375 	amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7376 	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7377 	amdgpu_ring_write(ring,
7378 #ifdef __BIG_ENDIAN
7379 				(2 << 0) |
7380 #endif
7381 				lower_32_bits(ib->gpu_addr));
7382 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7383 	amdgpu_ring_write(ring, control);
7384 }
7385 
7386 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7387 				     u64 seq, unsigned flags)
7388 {
7389 	struct amdgpu_device *adev = ring->adev;
7390 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7391 	bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7392 
7393 	/* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */
7394 	if (adev->pdev->device == 0x50)
7395 		int_sel = false;
7396 
7397 	/* RELEASE_MEM - flush caches, send int */
7398 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7399 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7400 				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
7401 				 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7402 				 PACKET3_RELEASE_MEM_GCR_GLM_WB |
7403 				 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7404 				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7405 				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7406 	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7407 				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7408 
7409 	/*
7410 	 * the address should be Qword aligned if 64bit write, Dword
7411 	 * aligned if only send 32bit data low (discard data high)
7412 	 */
7413 	if (write64bit)
7414 		BUG_ON(addr & 0x7);
7415 	else
7416 		BUG_ON(addr & 0x3);
7417 	amdgpu_ring_write(ring, lower_32_bits(addr));
7418 	amdgpu_ring_write(ring, upper_32_bits(addr));
7419 	amdgpu_ring_write(ring, lower_32_bits(seq));
7420 	amdgpu_ring_write(ring, upper_32_bits(seq));
7421 	amdgpu_ring_write(ring, 0);
7422 }
7423 
7424 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7425 {
7426 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7427 	uint32_t seq = ring->fence_drv.sync_seq;
7428 	uint64_t addr = ring->fence_drv.gpu_addr;
7429 
7430 	gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7431 			       upper_32_bits(addr), seq, 0xffffffff, 4);
7432 }
7433 
7434 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7435 					 unsigned vmid, uint64_t pd_addr)
7436 {
7437 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7438 
7439 	/* compute doesn't have PFP */
7440 	if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7441 		/* sync PFP to ME, otherwise we might get invalid PFP reads */
7442 		amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7443 		amdgpu_ring_write(ring, 0x0);
7444 	}
7445 }
7446 
7447 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7448 					  u64 seq, unsigned int flags)
7449 {
7450 	struct amdgpu_device *adev = ring->adev;
7451 
7452 	/* we only allocate 32bit for each seq wb address */
7453 	BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7454 
7455 	/* write fence seq to the "addr" */
7456 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7457 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7458 				 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7459 	amdgpu_ring_write(ring, lower_32_bits(addr));
7460 	amdgpu_ring_write(ring, upper_32_bits(addr));
7461 	amdgpu_ring_write(ring, lower_32_bits(seq));
7462 
7463 	if (flags & AMDGPU_FENCE_FLAG_INT) {
7464 		/* set register to trigger INT */
7465 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7466 		amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7467 					 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7468 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7469 		amdgpu_ring_write(ring, 0);
7470 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7471 	}
7472 }
7473 
7474 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7475 {
7476 	amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7477 	amdgpu_ring_write(ring, 0);
7478 }
7479 
7480 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7481 					 uint32_t flags)
7482 {
7483 	uint32_t dw2 = 0;
7484 
7485 	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7486 		gfx_v10_0_ring_emit_ce_meta(ring,
7487 				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7488 
7489 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7490 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7491 		/* set load_global_config & load_global_uconfig */
7492 		dw2 |= 0x8001;
7493 		/* set load_cs_sh_regs */
7494 		dw2 |= 0x01000000;
7495 		/* set load_per_context_state & load_gfx_sh_regs for GFX */
7496 		dw2 |= 0x10002;
7497 
7498 		/* set load_ce_ram if preamble presented */
7499 		if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7500 			dw2 |= 0x10000000;
7501 	} else {
7502 		/* still load_ce_ram if this is the first time preamble presented
7503 		 * although there is no context switch happens.
7504 		 */
7505 		if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7506 			dw2 |= 0x10000000;
7507 	}
7508 
7509 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7510 	amdgpu_ring_write(ring, dw2);
7511 	amdgpu_ring_write(ring, 0);
7512 }
7513 
7514 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7515 {
7516 	unsigned ret;
7517 
7518 	amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7519 	amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7520 	amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7521 	amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7522 	ret = ring->wptr & ring->buf_mask;
7523 	amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7524 
7525 	return ret;
7526 }
7527 
7528 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7529 {
7530 	unsigned cur;
7531 	BUG_ON(offset > ring->buf_mask);
7532 	BUG_ON(ring->ring[offset] != 0x55aa55aa);
7533 
7534 	cur = (ring->wptr - 1) & ring->buf_mask;
7535 	if (likely(cur > offset))
7536 		ring->ring[offset] = cur - offset;
7537 	else
7538 		ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7539 }
7540 
7541 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7542 {
7543 	int i, r = 0;
7544 	struct amdgpu_device *adev = ring->adev;
7545 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7546 	struct amdgpu_ring *kiq_ring = &kiq->ring;
7547 
7548 	if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7549 		return -EINVAL;
7550 
7551 	if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size))
7552 		return -ENOMEM;
7553 
7554 	/* assert preemption condition */
7555 	amdgpu_ring_set_preempt_cond_exec(ring, false);
7556 
7557 	/* assert IB preemption, emit the trailing fence */
7558 	kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7559 				   ring->trail_fence_gpu_addr,
7560 				   ++ring->trail_seq);
7561 	amdgpu_ring_commit(kiq_ring);
7562 
7563 	/* poll the trailing fence */
7564 	for (i = 0; i < adev->usec_timeout; i++) {
7565 		if (ring->trail_seq ==
7566 		    le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7567 			break;
7568 		udelay(1);
7569 	}
7570 
7571 	if (i >= adev->usec_timeout) {
7572 		r = -EINVAL;
7573 		DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7574 	}
7575 
7576 	/* deassert preemption condition */
7577 	amdgpu_ring_set_preempt_cond_exec(ring, true);
7578 	return r;
7579 }
7580 
7581 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7582 {
7583 	struct amdgpu_device *adev = ring->adev;
7584 	struct v10_ce_ib_state ce_payload = {0};
7585 	uint64_t csa_addr;
7586 	int cnt;
7587 
7588 	cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7589 	csa_addr = amdgpu_csa_vaddr(ring->adev);
7590 
7591 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7592 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
7593 				 WRITE_DATA_DST_SEL(8) |
7594 				 WR_CONFIRM) |
7595 				 WRITE_DATA_CACHE_POLICY(0));
7596 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7597 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
7598 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7599 			      offsetof(struct v10_gfx_meta_data, ce_payload)));
7600 
7601 	if (resume)
7602 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7603 					   offsetof(struct v10_gfx_meta_data,
7604 						    ce_payload),
7605 					   sizeof(ce_payload) >> 2);
7606 	else
7607 		amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
7608 					   sizeof(ce_payload) >> 2);
7609 }
7610 
7611 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
7612 {
7613 	struct amdgpu_device *adev = ring->adev;
7614 	struct v10_de_ib_state de_payload = {0};
7615 	uint64_t csa_addr, gds_addr;
7616 	int cnt;
7617 
7618 	csa_addr = amdgpu_csa_vaddr(ring->adev);
7619 	gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
7620 			 PAGE_SIZE);
7621 	de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
7622 	de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
7623 
7624 	cnt = (sizeof(de_payload) >> 2) + 4 - 2;
7625 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
7626 	amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
7627 				 WRITE_DATA_DST_SEL(8) |
7628 				 WR_CONFIRM) |
7629 				 WRITE_DATA_CACHE_POLICY(0));
7630 	amdgpu_ring_write(ring, lower_32_bits(csa_addr +
7631 			      offsetof(struct v10_gfx_meta_data, de_payload)));
7632 	amdgpu_ring_write(ring, upper_32_bits(csa_addr +
7633 			      offsetof(struct v10_gfx_meta_data, de_payload)));
7634 
7635 	if (resume)
7636 		amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
7637 					   offsetof(struct v10_gfx_meta_data,
7638 						    de_payload),
7639 					   sizeof(de_payload) >> 2);
7640 	else
7641 		amdgpu_ring_write_multiple(ring, (void *)&de_payload,
7642 					   sizeof(de_payload) >> 2);
7643 }
7644 
7645 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
7646 				    bool secure)
7647 {
7648 	uint32_t v = secure ? FRAME_TMZ : 0;
7649 
7650 	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
7651 	amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
7652 }
7653 
7654 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
7655 				     uint32_t reg_val_offs)
7656 {
7657 	struct amdgpu_device *adev = ring->adev;
7658 
7659 	amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
7660 	amdgpu_ring_write(ring, 0 |	/* src: register*/
7661 				(5 << 8) |	/* dst: memory */
7662 				(1 << 20));	/* write confirm */
7663 	amdgpu_ring_write(ring, reg);
7664 	amdgpu_ring_write(ring, 0);
7665 	amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
7666 				reg_val_offs * 4));
7667 	amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
7668 				reg_val_offs * 4));
7669 }
7670 
7671 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
7672 				   uint32_t val)
7673 {
7674 	uint32_t cmd = 0;
7675 
7676 	switch (ring->funcs->type) {
7677 	case AMDGPU_RING_TYPE_GFX:
7678 		cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
7679 		break;
7680 	case AMDGPU_RING_TYPE_KIQ:
7681 		cmd = (1 << 16); /* no inc addr */
7682 		break;
7683 	default:
7684 		cmd = WR_CONFIRM;
7685 		break;
7686 	}
7687 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7688 	amdgpu_ring_write(ring, cmd);
7689 	amdgpu_ring_write(ring, reg);
7690 	amdgpu_ring_write(ring, 0);
7691 	amdgpu_ring_write(ring, val);
7692 }
7693 
7694 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
7695 					uint32_t val, uint32_t mask)
7696 {
7697 	gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
7698 }
7699 
7700 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
7701 						   uint32_t reg0, uint32_t reg1,
7702 						   uint32_t ref, uint32_t mask)
7703 {
7704 	int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7705 	struct amdgpu_device *adev = ring->adev;
7706 	bool fw_version_ok = false;
7707 
7708 	fw_version_ok = adev->gfx.cp_fw_write_wait;
7709 
7710 	if (fw_version_ok)
7711 		gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
7712 				       ref, mask, 0x20);
7713 	else
7714 		amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
7715 							   ref, mask);
7716 }
7717 
7718 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
7719 					 unsigned vmid)
7720 {
7721 	struct amdgpu_device *adev = ring->adev;
7722 	uint32_t value = 0;
7723 
7724 	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
7725 	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
7726 	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
7727 	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
7728 	WREG32_SOC15(GC, 0, mmSQ_CMD, value);
7729 }
7730 
7731 static void
7732 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
7733 				      uint32_t me, uint32_t pipe,
7734 				      enum amdgpu_interrupt_state state)
7735 {
7736 	uint32_t cp_int_cntl, cp_int_cntl_reg;
7737 
7738 	if (!me) {
7739 		switch (pipe) {
7740 		case 0:
7741 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
7742 			break;
7743 		case 1:
7744 			cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
7745 			break;
7746 		default:
7747 			DRM_DEBUG("invalid pipe %d\n", pipe);
7748 			return;
7749 		}
7750 	} else {
7751 		DRM_DEBUG("invalid me %d\n", me);
7752 		return;
7753 	}
7754 
7755 	switch (state) {
7756 	case AMDGPU_IRQ_STATE_DISABLE:
7757 		cp_int_cntl = RREG32(cp_int_cntl_reg);
7758 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
7759 					    TIME_STAMP_INT_ENABLE, 0);
7760 		WREG32(cp_int_cntl_reg, cp_int_cntl);
7761 		break;
7762 	case AMDGPU_IRQ_STATE_ENABLE:
7763 		cp_int_cntl = RREG32(cp_int_cntl_reg);
7764 		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
7765 					    TIME_STAMP_INT_ENABLE, 1);
7766 		WREG32(cp_int_cntl_reg, cp_int_cntl);
7767 		break;
7768 	default:
7769 		break;
7770 	}
7771 }
7772 
7773 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
7774 						     int me, int pipe,
7775 						     enum amdgpu_interrupt_state state)
7776 {
7777 	u32 mec_int_cntl, mec_int_cntl_reg;
7778 
7779 	/*
7780 	 * amdgpu controls only the first MEC. That's why this function only
7781 	 * handles the setting of interrupts for this specific MEC. All other
7782 	 * pipes' interrupts are set by amdkfd.
7783 	 */
7784 
7785 	if (me == 1) {
7786 		switch (pipe) {
7787 		case 0:
7788 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
7789 			break;
7790 		case 1:
7791 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
7792 			break;
7793 		case 2:
7794 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
7795 			break;
7796 		case 3:
7797 			mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
7798 			break;
7799 		default:
7800 			DRM_DEBUG("invalid pipe %d\n", pipe);
7801 			return;
7802 		}
7803 	} else {
7804 		DRM_DEBUG("invalid me %d\n", me);
7805 		return;
7806 	}
7807 
7808 	switch (state) {
7809 	case AMDGPU_IRQ_STATE_DISABLE:
7810 		mec_int_cntl = RREG32(mec_int_cntl_reg);
7811 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
7812 					     TIME_STAMP_INT_ENABLE, 0);
7813 		WREG32(mec_int_cntl_reg, mec_int_cntl);
7814 		break;
7815 	case AMDGPU_IRQ_STATE_ENABLE:
7816 		mec_int_cntl = RREG32(mec_int_cntl_reg);
7817 		mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
7818 					     TIME_STAMP_INT_ENABLE, 1);
7819 		WREG32(mec_int_cntl_reg, mec_int_cntl);
7820 		break;
7821 	default:
7822 		break;
7823 	}
7824 }
7825 
7826 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
7827 					    struct amdgpu_irq_src *src,
7828 					    unsigned type,
7829 					    enum amdgpu_interrupt_state state)
7830 {
7831 	switch (type) {
7832 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
7833 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
7834 		break;
7835 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
7836 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
7837 		break;
7838 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
7839 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
7840 		break;
7841 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
7842 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
7843 		break;
7844 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
7845 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
7846 		break;
7847 	case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
7848 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
7849 		break;
7850 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
7851 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
7852 		break;
7853 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
7854 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
7855 		break;
7856 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
7857 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
7858 		break;
7859 	case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
7860 		gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
7861 		break;
7862 	default:
7863 		break;
7864 	}
7865 	return 0;
7866 }
7867 
7868 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
7869 			     struct amdgpu_irq_src *source,
7870 			     struct amdgpu_iv_entry *entry)
7871 {
7872 	int i;
7873 	u8 me_id, pipe_id, queue_id;
7874 	struct amdgpu_ring *ring;
7875 
7876 	DRM_DEBUG("IH: CP EOP\n");
7877 	me_id = (entry->ring_id & 0x0c) >> 2;
7878 	pipe_id = (entry->ring_id & 0x03) >> 0;
7879 	queue_id = (entry->ring_id & 0x70) >> 4;
7880 
7881 	switch (me_id) {
7882 	case 0:
7883 		if (pipe_id == 0)
7884 			amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
7885 		else
7886 			amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
7887 		break;
7888 	case 1:
7889 	case 2:
7890 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7891 			ring = &adev->gfx.compute_ring[i];
7892 			/* Per-queue interrupt is supported for MEC starting from VI.
7893 			  * The interrupt can only be enabled/disabled per pipe instead of per queue.
7894 			  */
7895 			if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
7896 				amdgpu_fence_process(ring);
7897 		}
7898 		break;
7899 	}
7900 	return 0;
7901 }
7902 
7903 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
7904 					      struct amdgpu_irq_src *source,
7905 					      unsigned type,
7906 					      enum amdgpu_interrupt_state state)
7907 {
7908 	switch (state) {
7909 	case AMDGPU_IRQ_STATE_DISABLE:
7910 	case AMDGPU_IRQ_STATE_ENABLE:
7911 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
7912 			       PRIV_REG_INT_ENABLE,
7913 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
7914 		break;
7915 	default:
7916 		break;
7917 	}
7918 
7919 	return 0;
7920 }
7921 
7922 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
7923 					       struct amdgpu_irq_src *source,
7924 					       unsigned type,
7925 					       enum amdgpu_interrupt_state state)
7926 {
7927 	switch (state) {
7928 	case AMDGPU_IRQ_STATE_DISABLE:
7929 	case AMDGPU_IRQ_STATE_ENABLE:
7930 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
7931 			       PRIV_INSTR_INT_ENABLE,
7932 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
7933 	default:
7934 		break;
7935 	}
7936 
7937 	return 0;
7938 }
7939 
7940 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
7941 					struct amdgpu_iv_entry *entry)
7942 {
7943 	u8 me_id, pipe_id, queue_id;
7944 	struct amdgpu_ring *ring;
7945 	int i;
7946 
7947 	me_id = (entry->ring_id & 0x0c) >> 2;
7948 	pipe_id = (entry->ring_id & 0x03) >> 0;
7949 	queue_id = (entry->ring_id & 0x70) >> 4;
7950 
7951 	switch (me_id) {
7952 	case 0:
7953 		for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7954 			ring = &adev->gfx.gfx_ring[i];
7955 			/* we only enabled 1 gfx queue per pipe for now */
7956 			if (ring->me == me_id && ring->pipe == pipe_id)
7957 				drm_sched_fault(&ring->sched);
7958 		}
7959 		break;
7960 	case 1:
7961 	case 2:
7962 		for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7963 			ring = &adev->gfx.compute_ring[i];
7964 			if (ring->me == me_id && ring->pipe == pipe_id &&
7965 			    ring->queue == queue_id)
7966 				drm_sched_fault(&ring->sched);
7967 		}
7968 		break;
7969 	default:
7970 		BUG();
7971 	}
7972 }
7973 
7974 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
7975 				  struct amdgpu_irq_src *source,
7976 				  struct amdgpu_iv_entry *entry)
7977 {
7978 	DRM_ERROR("Illegal register access in command stream\n");
7979 	gfx_v10_0_handle_priv_fault(adev, entry);
7980 	return 0;
7981 }
7982 
7983 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
7984 				   struct amdgpu_irq_src *source,
7985 				   struct amdgpu_iv_entry *entry)
7986 {
7987 	DRM_ERROR("Illegal instruction in command stream\n");
7988 	gfx_v10_0_handle_priv_fault(adev, entry);
7989 	return 0;
7990 }
7991 
7992 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
7993 					     struct amdgpu_irq_src *src,
7994 					     unsigned int type,
7995 					     enum amdgpu_interrupt_state state)
7996 {
7997 	uint32_t tmp, target;
7998 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
7999 
8000 	if (ring->me == 1)
8001 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8002 	else
8003 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8004 	target += ring->pipe;
8005 
8006 	switch (type) {
8007 	case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8008 		if (state == AMDGPU_IRQ_STATE_DISABLE) {
8009 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8010 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8011 					    GENERIC2_INT_ENABLE, 0);
8012 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8013 
8014 			tmp = RREG32(target);
8015 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8016 					    GENERIC2_INT_ENABLE, 0);
8017 			WREG32(target, tmp);
8018 		} else {
8019 			tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8020 			tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8021 					    GENERIC2_INT_ENABLE, 1);
8022 			WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8023 
8024 			tmp = RREG32(target);
8025 			tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8026 					    GENERIC2_INT_ENABLE, 1);
8027 			WREG32(target, tmp);
8028 		}
8029 		break;
8030 	default:
8031 		BUG(); /* kiq only support GENERIC2_INT now */
8032 		break;
8033 	}
8034 	return 0;
8035 }
8036 
8037 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8038 			     struct amdgpu_irq_src *source,
8039 			     struct amdgpu_iv_entry *entry)
8040 {
8041 	u8 me_id, pipe_id, queue_id;
8042 	struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8043 
8044 	me_id = (entry->ring_id & 0x0c) >> 2;
8045 	pipe_id = (entry->ring_id & 0x03) >> 0;
8046 	queue_id = (entry->ring_id & 0x70) >> 4;
8047 	DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8048 		   me_id, pipe_id, queue_id);
8049 
8050 	amdgpu_fence_process(ring);
8051 	return 0;
8052 }
8053 
8054 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8055 {
8056 	const unsigned int gcr_cntl =
8057 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8058 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8059 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8060 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8061 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8062 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8063 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8064 			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8065 
8066 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8067 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8068 	amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8069 	amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8070 	amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8071 	amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8072 	amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8073 	amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8074 	amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8075 }
8076 
8077 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8078 	.name = "gfx_v10_0",
8079 	.early_init = gfx_v10_0_early_init,
8080 	.late_init = gfx_v10_0_late_init,
8081 	.sw_init = gfx_v10_0_sw_init,
8082 	.sw_fini = gfx_v10_0_sw_fini,
8083 	.hw_init = gfx_v10_0_hw_init,
8084 	.hw_fini = gfx_v10_0_hw_fini,
8085 	.suspend = gfx_v10_0_suspend,
8086 	.resume = gfx_v10_0_resume,
8087 	.is_idle = gfx_v10_0_is_idle,
8088 	.wait_for_idle = gfx_v10_0_wait_for_idle,
8089 	.soft_reset = gfx_v10_0_soft_reset,
8090 	.set_clockgating_state = gfx_v10_0_set_clockgating_state,
8091 	.set_powergating_state = gfx_v10_0_set_powergating_state,
8092 	.get_clockgating_state = gfx_v10_0_get_clockgating_state,
8093 };
8094 
8095 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8096 	.type = AMDGPU_RING_TYPE_GFX,
8097 	.align_mask = 0xff,
8098 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8099 	.support_64bit_ptrs = true,
8100 	.vmhub = AMDGPU_GFXHUB_0,
8101 	.get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8102 	.get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8103 	.set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8104 	.emit_frame_size = /* totally 242 maximum if 16 IBs */
8105 		5 + /* COND_EXEC */
8106 		7 + /* PIPELINE_SYNC */
8107 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8108 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8109 		2 + /* VM_FLUSH */
8110 		8 + /* FENCE for VM_FLUSH */
8111 		20 + /* GDS switch */
8112 		4 + /* double SWITCH_BUFFER,
8113 		     * the first COND_EXEC jump to the place
8114 		     * just prior to this double SWITCH_BUFFER
8115 		     */
8116 		5 + /* COND_EXEC */
8117 		7 + /* HDP_flush */
8118 		4 + /* VGT_flush */
8119 		14 + /*	CE_META */
8120 		31 + /*	DE_META */
8121 		3 + /* CNTX_CTRL */
8122 		5 + /* HDP_INVL */
8123 		8 + 8 + /* FENCE x2 */
8124 		2 + /* SWITCH_BUFFER */
8125 		8, /* gfx_v10_0_emit_mem_sync */
8126 	.emit_ib_size =	4, /* gfx_v10_0_ring_emit_ib_gfx */
8127 	.emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8128 	.emit_fence = gfx_v10_0_ring_emit_fence,
8129 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8130 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8131 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8132 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8133 	.test_ring = gfx_v10_0_ring_test_ring,
8134 	.test_ib = gfx_v10_0_ring_test_ib,
8135 	.insert_nop = amdgpu_ring_insert_nop,
8136 	.pad_ib = amdgpu_ring_generic_pad_ib,
8137 	.emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8138 	.emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8139 	.init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8140 	.patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8141 	.preempt_ib = gfx_v10_0_ring_preempt_ib,
8142 	.emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8143 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8144 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8145 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8146 	.soft_recovery = gfx_v10_0_ring_soft_recovery,
8147 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
8148 };
8149 
8150 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8151 	.type = AMDGPU_RING_TYPE_COMPUTE,
8152 	.align_mask = 0xff,
8153 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8154 	.support_64bit_ptrs = true,
8155 	.vmhub = AMDGPU_GFXHUB_0,
8156 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
8157 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
8158 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
8159 	.emit_frame_size =
8160 		20 + /* gfx_v10_0_ring_emit_gds_switch */
8161 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
8162 		5 + /* hdp invalidate */
8163 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8164 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8165 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8166 		2 + /* gfx_v10_0_ring_emit_vm_flush */
8167 		8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8168 		8, /* gfx_v10_0_emit_mem_sync */
8169 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
8170 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
8171 	.emit_fence = gfx_v10_0_ring_emit_fence,
8172 	.emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8173 	.emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8174 	.emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8175 	.emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8176 	.test_ring = gfx_v10_0_ring_test_ring,
8177 	.test_ib = gfx_v10_0_ring_test_ib,
8178 	.insert_nop = amdgpu_ring_insert_nop,
8179 	.pad_ib = amdgpu_ring_generic_pad_ib,
8180 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8181 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8182 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8183 	.emit_mem_sync = gfx_v10_0_emit_mem_sync,
8184 };
8185 
8186 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8187 	.type = AMDGPU_RING_TYPE_KIQ,
8188 	.align_mask = 0xff,
8189 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
8190 	.support_64bit_ptrs = true,
8191 	.vmhub = AMDGPU_GFXHUB_0,
8192 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
8193 	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
8194 	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
8195 	.emit_frame_size =
8196 		20 + /* gfx_v10_0_ring_emit_gds_switch */
8197 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
8198 		5 + /*hdp invalidate */
8199 		7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8200 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8201 		SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8202 		2 + /* gfx_v10_0_ring_emit_vm_flush */
8203 		8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8204 	.emit_ib_size =	7, /* gfx_v10_0_ring_emit_ib_compute */
8205 	.emit_ib = gfx_v10_0_ring_emit_ib_compute,
8206 	.emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8207 	.test_ring = gfx_v10_0_ring_test_ring,
8208 	.test_ib = gfx_v10_0_ring_test_ib,
8209 	.insert_nop = amdgpu_ring_insert_nop,
8210 	.pad_ib = amdgpu_ring_generic_pad_ib,
8211 	.emit_rreg = gfx_v10_0_ring_emit_rreg,
8212 	.emit_wreg = gfx_v10_0_ring_emit_wreg,
8213 	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8214 	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8215 };
8216 
8217 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8218 {
8219 	int i;
8220 
8221 	adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8222 
8223 	for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8224 		adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8225 
8226 	for (i = 0; i < adev->gfx.num_compute_rings; i++)
8227 		adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8228 }
8229 
8230 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8231 	.set = gfx_v10_0_set_eop_interrupt_state,
8232 	.process = gfx_v10_0_eop_irq,
8233 };
8234 
8235 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8236 	.set = gfx_v10_0_set_priv_reg_fault_state,
8237 	.process = gfx_v10_0_priv_reg_irq,
8238 };
8239 
8240 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8241 	.set = gfx_v10_0_set_priv_inst_fault_state,
8242 	.process = gfx_v10_0_priv_inst_irq,
8243 };
8244 
8245 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8246 	.set = gfx_v10_0_kiq_set_interrupt_state,
8247 	.process = gfx_v10_0_kiq_irq,
8248 };
8249 
8250 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8251 {
8252 	adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8253 	adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8254 
8255 	adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8256 	adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8257 
8258 	adev->gfx.priv_reg_irq.num_types = 1;
8259 	adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8260 
8261 	adev->gfx.priv_inst_irq.num_types = 1;
8262 	adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8263 }
8264 
8265 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8266 {
8267 	switch (adev->asic_type) {
8268 	case CHIP_NAVI10:
8269 	case CHIP_NAVI14:
8270 	case CHIP_SIENNA_CICHLID:
8271 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8272 		break;
8273 	case CHIP_NAVI12:
8274 		adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8275 		break;
8276 	default:
8277 		break;
8278 	}
8279 }
8280 
8281 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8282 {
8283 	unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8284 			    adev->gfx.config.max_sh_per_se *
8285 			    adev->gfx.config.max_shader_engines;
8286 
8287 	adev->gds.gds_size = 0x10000;
8288 	adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8289 	adev->gds.gws_size = 64;
8290 	adev->gds.oa_size = 16;
8291 }
8292 
8293 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8294 							  u32 bitmap)
8295 {
8296 	u32 data;
8297 
8298 	if (!bitmap)
8299 		return;
8300 
8301 	data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8302 	data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8303 
8304 	WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8305 }
8306 
8307 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8308 {
8309 	u32 data, wgp_bitmask;
8310 	data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8311 	data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8312 
8313 	data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8314 	data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8315 
8316 	wgp_bitmask =
8317 		amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8318 
8319 	return (~data) & wgp_bitmask;
8320 }
8321 
8322 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8323 {
8324 	u32 wgp_idx, wgp_active_bitmap;
8325 	u32 cu_bitmap_per_wgp, cu_active_bitmap;
8326 
8327 	wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8328 	cu_active_bitmap = 0;
8329 
8330 	for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8331 		/* if there is one WGP enabled, it means 2 CUs will be enabled */
8332 		cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8333 		if (wgp_active_bitmap & (1 << wgp_idx))
8334 			cu_active_bitmap |= cu_bitmap_per_wgp;
8335 	}
8336 
8337 	return cu_active_bitmap;
8338 }
8339 
8340 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8341 				 struct amdgpu_cu_info *cu_info)
8342 {
8343 	int i, j, k, counter, active_cu_number = 0;
8344 	u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8345 	unsigned disable_masks[4 * 2];
8346 
8347 	if (!adev || !cu_info)
8348 		return -EINVAL;
8349 
8350 	amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8351 
8352 	mutex_lock(&adev->grbm_idx_mutex);
8353 	for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8354 		for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8355 			mask = 1;
8356 			ao_bitmap = 0;
8357 			counter = 0;
8358 			gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8359 			if (i < 4 && j < 2)
8360 				gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8361 					adev, disable_masks[i * 2 + j]);
8362 			bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8363 			cu_info->bitmap[i][j] = bitmap;
8364 
8365 			for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8366 				if (bitmap & mask) {
8367 					if (counter < adev->gfx.config.max_cu_per_sh)
8368 						ao_bitmap |= mask;
8369 					counter++;
8370 				}
8371 				mask <<= 1;
8372 			}
8373 			active_cu_number += counter;
8374 			if (i < 2 && j < 2)
8375 				ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8376 			cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8377 		}
8378 	}
8379 	gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8380 	mutex_unlock(&adev->grbm_idx_mutex);
8381 
8382 	cu_info->number = active_cu_number;
8383 	cu_info->ao_cu_mask = ao_cu_mask;
8384 	cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8385 
8386 	return 0;
8387 }
8388 
8389 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8390 {
8391 	.type = AMD_IP_BLOCK_TYPE_GFX,
8392 	.major = 10,
8393 	.minor = 0,
8394 	.rev = 0,
8395 	.funcs = &gfx_v10_0_ip_funcs,
8396 };
8397