1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/delay.h> 25 #include <linux/kernel.h> 26 #include <linux/firmware.h> 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include "amdgpu.h" 30 #include "amdgpu_gfx.h" 31 #include "amdgpu_psp.h" 32 #include "amdgpu_smu.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 #include "gc/gc_10_1_0_offset.h" 37 #include "gc/gc_10_1_0_sh_mask.h" 38 #include "navi10_enum.h" 39 #include "hdp/hdp_5_0_0_offset.h" 40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h" 41 42 #include "soc15.h" 43 #include "soc15_common.h" 44 #include "clearstate_gfx10.h" 45 #include "v10_structs.h" 46 #include "gfx_v10_0.h" 47 #include "nbio_v2_3.h" 48 49 /** 50 * Navi10 has two graphic rings to share each graphic pipe. 51 * 1. Primary ring 52 * 2. Async ring 53 * 54 * In bring-up phase, it just used primary ring so set gfx ring number as 1 at 55 * first. 56 */ 57 #define GFX10_NUM_GFX_RINGS 2 58 #define GFX10_MEC_HPD_SIZE 2048 59 60 #define F32_CE_PROGRAM_RAM_SIZE 65536 61 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 62 63 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087 64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1 65 66 MODULE_FIRMWARE("amdgpu/navi10_ce.bin"); 67 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin"); 68 MODULE_FIRMWARE("amdgpu/navi10_me.bin"); 69 MODULE_FIRMWARE("amdgpu/navi10_mec.bin"); 70 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin"); 71 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin"); 72 73 MODULE_FIRMWARE("amdgpu/navi14_ce.bin"); 74 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin"); 75 MODULE_FIRMWARE("amdgpu/navi14_me.bin"); 76 MODULE_FIRMWARE("amdgpu/navi14_mec.bin"); 77 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin"); 78 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin"); 79 80 static const struct soc15_reg_golden golden_settings_gc_10_1[] = 81 { 82 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), 83 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), 84 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), 85 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), 86 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), 87 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 88 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100), 89 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 90 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 91 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff), 92 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000), 93 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 94 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 95 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000), 96 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 97 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 98 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 99 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032), 102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231), 103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf), 105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100), 106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188), 108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130), 114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100), 118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000) 119 }; 120 121 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] = 122 { 123 /* Pending on emulation bring up */ 124 }; 125 126 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] = 127 { 128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014), 129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100), 130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100), 131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), 132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100), 133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100), 134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), 135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100), 136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000), 138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff), 139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000), 140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420), 141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200), 142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000), 143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f), 144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204), 145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500), 146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe), 147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4), 148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7), 150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100), 151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f), 152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188), 153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009), 154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000), 155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000), 156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101), 157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff), 158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130), 159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff), 160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000), 161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010), 162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000), 163 }; 164 165 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = 166 { 167 /* Pending on emulation bring up */ 168 }; 169 170 #define DEFAULT_SH_MEM_CONFIG \ 171 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 172 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 173 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \ 174 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 175 176 177 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev); 178 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev); 179 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev); 180 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev); 181 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 182 struct amdgpu_cu_info *cu_info); 183 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev); 184 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 185 u32 sh_num, u32 instance); 186 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev); 187 188 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev); 189 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev); 190 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev); 191 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 192 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume); 193 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume); 194 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start); 195 196 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) 197 { 198 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); 199 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | 200 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */ 201 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ 202 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ 203 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ 204 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ 205 amdgpu_ring_write(kiq_ring, 0); /* oac mask */ 206 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ 207 } 208 209 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring, 210 struct amdgpu_ring *ring) 211 { 212 struct amdgpu_device *adev = kiq_ring->adev; 213 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); 214 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 215 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 216 217 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 218 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/ 219 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 220 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 221 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ 222 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | 223 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | 224 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | 225 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 226 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 227 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | 228 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 229 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); 230 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr)); 231 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr)); 232 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr)); 233 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr)); 234 } 235 236 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring, 237 struct amdgpu_ring *ring, 238 enum amdgpu_unmap_queues_action action, 239 u64 gpu_addr, u64 seq) 240 { 241 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 242 243 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4)); 244 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 245 PACKET3_UNMAP_QUEUES_ACTION(action) | 246 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) | 247 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) | 248 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1)); 249 amdgpu_ring_write(kiq_ring, 250 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index)); 251 252 if (action == PREEMPT_QUEUES_NO_UNMAP) { 253 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr)); 254 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr)); 255 amdgpu_ring_write(kiq_ring, seq); 256 } else { 257 amdgpu_ring_write(kiq_ring, 0); 258 amdgpu_ring_write(kiq_ring, 0); 259 amdgpu_ring_write(kiq_ring, 0); 260 } 261 } 262 263 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring, 264 struct amdgpu_ring *ring, 265 u64 addr, 266 u64 seq) 267 { 268 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; 269 270 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5)); 271 amdgpu_ring_write(kiq_ring, 272 PACKET3_QUERY_STATUS_CONTEXT_ID(0) | 273 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) | 274 PACKET3_QUERY_STATUS_COMMAND(2)); 275 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */ 276 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) | 277 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel)); 278 amdgpu_ring_write(kiq_ring, lower_32_bits(addr)); 279 amdgpu_ring_write(kiq_ring, upper_32_bits(addr)); 280 amdgpu_ring_write(kiq_ring, lower_32_bits(seq)); 281 amdgpu_ring_write(kiq_ring, upper_32_bits(seq)); 282 } 283 284 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = { 285 .kiq_set_resources = gfx10_kiq_set_resources, 286 .kiq_map_queues = gfx10_kiq_map_queues, 287 .kiq_unmap_queues = gfx10_kiq_unmap_queues, 288 .kiq_query_status = gfx10_kiq_query_status, 289 .set_resources_size = 8, 290 .map_queues_size = 7, 291 .unmap_queues_size = 6, 292 .query_status_size = 7, 293 }; 294 295 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev) 296 { 297 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; 298 } 299 300 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev) 301 { 302 switch (adev->asic_type) { 303 case CHIP_NAVI10: 304 soc15_program_register_sequence(adev, 305 golden_settings_gc_10_1, 306 (const u32)ARRAY_SIZE(golden_settings_gc_10_1)); 307 soc15_program_register_sequence(adev, 308 golden_settings_gc_10_0_nv10, 309 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10)); 310 break; 311 case CHIP_NAVI14: 312 soc15_program_register_sequence(adev, 313 golden_settings_gc_10_1_1, 314 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1)); 315 soc15_program_register_sequence(adev, 316 golden_settings_gc_10_1_nv14, 317 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14)); 318 break; 319 default: 320 break; 321 } 322 } 323 324 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev) 325 { 326 adev->gfx.scratch.num_reg = 8; 327 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); 328 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1; 329 } 330 331 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, 332 bool wc, uint32_t reg, uint32_t val) 333 { 334 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 335 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | 336 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); 337 amdgpu_ring_write(ring, reg); 338 amdgpu_ring_write(ring, 0); 339 amdgpu_ring_write(ring, val); 340 } 341 342 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 343 int mem_space, int opt, uint32_t addr0, 344 uint32_t addr1, uint32_t ref, uint32_t mask, 345 uint32_t inv) 346 { 347 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 348 amdgpu_ring_write(ring, 349 /* memory (1) or register (0) */ 350 (WAIT_REG_MEM_MEM_SPACE(mem_space) | 351 WAIT_REG_MEM_OPERATION(opt) | /* wait */ 352 WAIT_REG_MEM_FUNCTION(3) | /* equal */ 353 WAIT_REG_MEM_ENGINE(eng_sel))); 354 355 if (mem_space) 356 BUG_ON(addr0 & 0x3); /* Dword align */ 357 amdgpu_ring_write(ring, addr0); 358 amdgpu_ring_write(ring, addr1); 359 amdgpu_ring_write(ring, ref); 360 amdgpu_ring_write(ring, mask); 361 amdgpu_ring_write(ring, inv); /* poll interval */ 362 } 363 364 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring) 365 { 366 struct amdgpu_device *adev = ring->adev; 367 uint32_t scratch; 368 uint32_t tmp = 0; 369 unsigned i; 370 int r; 371 372 r = amdgpu_gfx_scratch_get(adev, &scratch); 373 if (r) { 374 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r); 375 return r; 376 } 377 378 WREG32(scratch, 0xCAFEDEAD); 379 380 r = amdgpu_ring_alloc(ring, 3); 381 if (r) { 382 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", 383 ring->idx, r); 384 amdgpu_gfx_scratch_free(adev, scratch); 385 return r; 386 } 387 388 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 389 amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START)); 390 amdgpu_ring_write(ring, 0xDEADBEEF); 391 amdgpu_ring_commit(ring); 392 393 for (i = 0; i < adev->usec_timeout; i++) { 394 tmp = RREG32(scratch); 395 if (tmp == 0xDEADBEEF) 396 break; 397 if (amdgpu_emu_mode == 1) 398 msleep(1); 399 else 400 udelay(1); 401 } 402 if (i < adev->usec_timeout) { 403 if (amdgpu_emu_mode == 1) 404 DRM_INFO("ring test on %d succeeded in %d msecs\n", 405 ring->idx, i); 406 else 407 DRM_INFO("ring test on %d succeeded in %d usecs\n", 408 ring->idx, i); 409 } else { 410 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n", 411 ring->idx, scratch, tmp); 412 r = -EINVAL; 413 } 414 amdgpu_gfx_scratch_free(adev, scratch); 415 416 return r; 417 } 418 419 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout) 420 { 421 struct amdgpu_device *adev = ring->adev; 422 struct amdgpu_ib ib; 423 struct dma_fence *f = NULL; 424 uint32_t scratch; 425 uint32_t tmp = 0; 426 long r; 427 428 r = amdgpu_gfx_scratch_get(adev, &scratch); 429 if (r) { 430 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); 431 return r; 432 } 433 434 WREG32(scratch, 0xCAFEDEAD); 435 436 memset(&ib, 0, sizeof(ib)); 437 r = amdgpu_ib_get(adev, NULL, 256, &ib); 438 if (r) { 439 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 440 goto err1; 441 } 442 443 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); 444 ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); 445 ib.ptr[2] = 0xDEADBEEF; 446 ib.length_dw = 3; 447 448 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 449 if (r) 450 goto err2; 451 452 r = dma_fence_wait_timeout(f, false, timeout); 453 if (r == 0) { 454 DRM_ERROR("amdgpu: IB test timed out.\n"); 455 r = -ETIMEDOUT; 456 goto err2; 457 } else if (r < 0) { 458 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 459 goto err2; 460 } 461 462 tmp = RREG32(scratch); 463 if (tmp == 0xDEADBEEF) { 464 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 465 r = 0; 466 } else { 467 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", 468 scratch, tmp); 469 r = -EINVAL; 470 } 471 err2: 472 amdgpu_ib_free(adev, &ib, NULL); 473 dma_fence_put(f); 474 err1: 475 amdgpu_gfx_scratch_free(adev, scratch); 476 477 return r; 478 } 479 480 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev) 481 { 482 release_firmware(adev->gfx.pfp_fw); 483 adev->gfx.pfp_fw = NULL; 484 release_firmware(adev->gfx.me_fw); 485 adev->gfx.me_fw = NULL; 486 release_firmware(adev->gfx.ce_fw); 487 adev->gfx.ce_fw = NULL; 488 release_firmware(adev->gfx.rlc_fw); 489 adev->gfx.rlc_fw = NULL; 490 release_firmware(adev->gfx.mec_fw); 491 adev->gfx.mec_fw = NULL; 492 release_firmware(adev->gfx.mec2_fw); 493 adev->gfx.mec2_fw = NULL; 494 495 kfree(adev->gfx.rlc.register_list_format); 496 } 497 498 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev) 499 { 500 const struct rlc_firmware_header_v2_1 *rlc_hdr; 501 502 rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 503 adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver); 504 adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver); 505 adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes); 506 adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes); 507 adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver); 508 adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver); 509 adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes); 510 adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes); 511 adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver); 512 adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver); 513 adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes); 514 adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes); 515 adev->gfx.rlc.reg_list_format_direct_reg_list_length = 516 le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length); 517 } 518 519 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) 520 { 521 switch (adev->asic_type) { 522 case CHIP_NAVI10: 523 adev->pm.pp_feature &= ~PP_GFXOFF_MASK; 524 break; 525 default: 526 break; 527 } 528 } 529 530 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) 531 { 532 const char *chip_name; 533 char fw_name[30]; 534 int err; 535 struct amdgpu_firmware_info *info = NULL; 536 const struct common_firmware_header *header = NULL; 537 const struct gfx_firmware_header_v1_0 *cp_hdr; 538 const struct rlc_firmware_header_v2_0 *rlc_hdr; 539 unsigned int *tmp = NULL; 540 unsigned int i = 0; 541 uint16_t version_major; 542 uint16_t version_minor; 543 544 DRM_DEBUG("\n"); 545 546 switch (adev->asic_type) { 547 case CHIP_NAVI10: 548 chip_name = "navi10"; 549 break; 550 case CHIP_NAVI14: 551 chip_name = "navi14"; 552 break; 553 default: 554 BUG(); 555 } 556 557 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name); 558 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); 559 if (err) 560 goto out; 561 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); 562 if (err) 563 goto out; 564 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; 565 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 566 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 567 568 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name); 569 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); 570 if (err) 571 goto out; 572 err = amdgpu_ucode_validate(adev->gfx.me_fw); 573 if (err) 574 goto out; 575 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; 576 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 577 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 578 579 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name); 580 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); 581 if (err) 582 goto out; 583 err = amdgpu_ucode_validate(adev->gfx.ce_fw); 584 if (err) 585 goto out; 586 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data; 587 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 588 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 589 590 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name); 591 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); 592 if (err) 593 goto out; 594 err = amdgpu_ucode_validate(adev->gfx.rlc_fw); 595 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 596 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 597 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 598 if (version_major == 2 && version_minor == 1) 599 adev->gfx.rlc.is_rlc_v2_1 = true; 600 601 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version); 602 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version); 603 adev->gfx.rlc.save_and_restore_offset = 604 le32_to_cpu(rlc_hdr->save_and_restore_offset); 605 adev->gfx.rlc.clear_state_descriptor_offset = 606 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset); 607 adev->gfx.rlc.avail_scratch_ram_locations = 608 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations); 609 adev->gfx.rlc.reg_restore_list_size = 610 le32_to_cpu(rlc_hdr->reg_restore_list_size); 611 adev->gfx.rlc.reg_list_format_start = 612 le32_to_cpu(rlc_hdr->reg_list_format_start); 613 adev->gfx.rlc.reg_list_format_separate_start = 614 le32_to_cpu(rlc_hdr->reg_list_format_separate_start); 615 adev->gfx.rlc.starting_offsets_start = 616 le32_to_cpu(rlc_hdr->starting_offsets_start); 617 adev->gfx.rlc.reg_list_format_size_bytes = 618 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes); 619 adev->gfx.rlc.reg_list_size_bytes = 620 le32_to_cpu(rlc_hdr->reg_list_size_bytes); 621 adev->gfx.rlc.register_list_format = 622 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes + 623 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL); 624 if (!adev->gfx.rlc.register_list_format) { 625 err = -ENOMEM; 626 goto out; 627 } 628 629 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 630 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 631 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++) 632 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]); 633 634 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i; 635 636 tmp = (unsigned int *)((uintptr_t)rlc_hdr + 637 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 638 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++) 639 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]); 640 641 if (adev->gfx.rlc.is_rlc_v2_1) 642 gfx_v10_0_init_rlc_ext_microcode(adev); 643 644 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name); 645 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); 646 if (err) 647 goto out; 648 err = amdgpu_ucode_validate(adev->gfx.mec_fw); 649 if (err) 650 goto out; 651 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 652 adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); 653 adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); 654 655 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name); 656 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); 657 if (!err) { 658 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); 659 if (err) 660 goto out; 661 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 662 adev->gfx.mec2_fw->data; 663 adev->gfx.mec2_fw_version = 664 le32_to_cpu(cp_hdr->header.ucode_version); 665 adev->gfx.mec2_feature_version = 666 le32_to_cpu(cp_hdr->ucode_feature_version); 667 } else { 668 err = 0; 669 adev->gfx.mec2_fw = NULL; 670 } 671 672 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 673 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP]; 674 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP; 675 info->fw = adev->gfx.pfp_fw; 676 header = (const struct common_firmware_header *)info->fw->data; 677 adev->firmware.fw_size += 678 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 679 680 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME]; 681 info->ucode_id = AMDGPU_UCODE_ID_CP_ME; 682 info->fw = adev->gfx.me_fw; 683 header = (const struct common_firmware_header *)info->fw->data; 684 adev->firmware.fw_size += 685 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 686 687 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE]; 688 info->ucode_id = AMDGPU_UCODE_ID_CP_CE; 689 info->fw = adev->gfx.ce_fw; 690 header = (const struct common_firmware_header *)info->fw->data; 691 adev->firmware.fw_size += 692 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 693 694 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G]; 695 info->ucode_id = AMDGPU_UCODE_ID_RLC_G; 696 info->fw = adev->gfx.rlc_fw; 697 header = (const struct common_firmware_header *)info->fw->data; 698 adev->firmware.fw_size += 699 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE); 700 701 if (adev->gfx.rlc.is_rlc_v2_1 && 702 adev->gfx.rlc.save_restore_list_cntl_size_bytes && 703 adev->gfx.rlc.save_restore_list_gpm_size_bytes && 704 adev->gfx.rlc.save_restore_list_srm_size_bytes) { 705 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL]; 706 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL; 707 info->fw = adev->gfx.rlc_fw; 708 adev->firmware.fw_size += 709 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE); 710 711 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM]; 712 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM; 713 info->fw = adev->gfx.rlc_fw; 714 adev->firmware.fw_size += 715 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE); 716 717 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM]; 718 info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM; 719 info->fw = adev->gfx.rlc_fw; 720 adev->firmware.fw_size += 721 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE); 722 } 723 724 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1]; 725 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1; 726 info->fw = adev->gfx.mec_fw; 727 header = (const struct common_firmware_header *)info->fw->data; 728 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 729 adev->firmware.fw_size += 730 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 731 le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 732 733 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT]; 734 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT; 735 info->fw = adev->gfx.mec_fw; 736 adev->firmware.fw_size += 737 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE); 738 739 if (adev->gfx.mec2_fw) { 740 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2]; 741 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2; 742 info->fw = adev->gfx.mec2_fw; 743 header = (const struct common_firmware_header *)info->fw->data; 744 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data; 745 adev->firmware.fw_size += 746 ALIGN(le32_to_cpu(header->ucode_size_bytes) - 747 le32_to_cpu(cp_hdr->jt_size) * 4, 748 PAGE_SIZE); 749 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT]; 750 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT; 751 info->fw = adev->gfx.mec2_fw; 752 adev->firmware.fw_size += 753 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, 754 PAGE_SIZE); 755 } 756 } 757 758 out: 759 if (err) { 760 dev_err(adev->dev, 761 "gfx10: Failed to load firmware \"%s\"\n", 762 fw_name); 763 release_firmware(adev->gfx.pfp_fw); 764 adev->gfx.pfp_fw = NULL; 765 release_firmware(adev->gfx.me_fw); 766 adev->gfx.me_fw = NULL; 767 release_firmware(adev->gfx.ce_fw); 768 adev->gfx.ce_fw = NULL; 769 release_firmware(adev->gfx.rlc_fw); 770 adev->gfx.rlc_fw = NULL; 771 release_firmware(adev->gfx.mec_fw); 772 adev->gfx.mec_fw = NULL; 773 release_firmware(adev->gfx.mec2_fw); 774 adev->gfx.mec2_fw = NULL; 775 } 776 777 gfx_v10_0_check_gfxoff_flag(adev); 778 779 return err; 780 } 781 782 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev) 783 { 784 u32 count = 0; 785 const struct cs_section_def *sect = NULL; 786 const struct cs_extent_def *ext = NULL; 787 788 /* begin clear state */ 789 count += 2; 790 /* context control state */ 791 count += 3; 792 793 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 794 for (ext = sect->section; ext->extent != NULL; ++ext) { 795 if (sect->id == SECT_CONTEXT) 796 count += 2 + ext->reg_count; 797 else 798 return 0; 799 } 800 } 801 802 /* set PA_SC_TILE_STEERING_OVERRIDE */ 803 count += 3; 804 /* end clear state */ 805 count += 2; 806 /* clear state */ 807 count += 2; 808 809 return count; 810 } 811 812 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev, 813 volatile u32 *buffer) 814 { 815 u32 count = 0, i; 816 const struct cs_section_def *sect = NULL; 817 const struct cs_extent_def *ext = NULL; 818 int ctx_reg_offset; 819 820 if (adev->gfx.rlc.cs_data == NULL) 821 return; 822 if (buffer == NULL) 823 return; 824 825 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 826 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 827 828 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 829 buffer[count++] = cpu_to_le32(0x80000000); 830 buffer[count++] = cpu_to_le32(0x80000000); 831 832 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 833 for (ext = sect->section; ext->extent != NULL; ++ext) { 834 if (sect->id == SECT_CONTEXT) { 835 buffer[count++] = 836 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); 837 buffer[count++] = cpu_to_le32(ext->reg_index - 838 PACKET3_SET_CONTEXT_REG_START); 839 for (i = 0; i < ext->reg_count; i++) 840 buffer[count++] = cpu_to_le32(ext->extent[i]); 841 } else { 842 return; 843 } 844 } 845 } 846 847 ctx_reg_offset = 848 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 849 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 850 buffer[count++] = cpu_to_le32(ctx_reg_offset); 851 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override); 852 853 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 854 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); 855 856 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0)); 857 buffer[count++] = cpu_to_le32(0); 858 } 859 860 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev) 861 { 862 /* clear state block */ 863 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 864 &adev->gfx.rlc.clear_state_gpu_addr, 865 (void **)&adev->gfx.rlc.cs_ptr); 866 867 /* jump table block */ 868 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 869 &adev->gfx.rlc.cp_table_gpu_addr, 870 (void **)&adev->gfx.rlc.cp_table_ptr); 871 } 872 873 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev) 874 { 875 const struct cs_section_def *cs_data; 876 int r; 877 878 adev->gfx.rlc.cs_data = gfx10_cs_data; 879 880 cs_data = adev->gfx.rlc.cs_data; 881 882 if (cs_data) { 883 /* init clear state block */ 884 r = amdgpu_gfx_rlc_init_csb(adev); 885 if (r) 886 return r; 887 } 888 889 return 0; 890 } 891 892 static int gfx_v10_0_csb_vram_pin(struct amdgpu_device *adev) 893 { 894 int r; 895 896 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false); 897 if (unlikely(r != 0)) 898 return r; 899 900 r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj, 901 AMDGPU_GEM_DOMAIN_VRAM); 902 if (!r) 903 adev->gfx.rlc.clear_state_gpu_addr = 904 amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj); 905 906 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 907 908 return r; 909 } 910 911 static void gfx_v10_0_csb_vram_unpin(struct amdgpu_device *adev) 912 { 913 int r; 914 915 if (!adev->gfx.rlc.clear_state_obj) 916 return; 917 918 r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true); 919 if (likely(r == 0)) { 920 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj); 921 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj); 922 } 923 } 924 925 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev) 926 { 927 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 928 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 929 } 930 931 static int gfx_v10_0_me_init(struct amdgpu_device *adev) 932 { 933 int r; 934 935 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); 936 937 amdgpu_gfx_graphics_queue_acquire(adev); 938 939 r = gfx_v10_0_init_microcode(adev); 940 if (r) 941 DRM_ERROR("Failed to load gfx firmware!\n"); 942 943 return r; 944 } 945 946 static int gfx_v10_0_mec_init(struct amdgpu_device *adev) 947 { 948 int r; 949 u32 *hpd; 950 const __le32 *fw_data = NULL; 951 unsigned fw_size; 952 u32 *fw = NULL; 953 size_t mec_hpd_size; 954 955 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL; 956 957 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 958 959 /* take ownership of the relevant compute queues */ 960 amdgpu_gfx_compute_queue_acquire(adev); 961 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; 962 963 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 964 AMDGPU_GEM_DOMAIN_GTT, 965 &adev->gfx.mec.hpd_eop_obj, 966 &adev->gfx.mec.hpd_eop_gpu_addr, 967 (void **)&hpd); 968 if (r) { 969 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 970 gfx_v10_0_mec_fini(adev); 971 return r; 972 } 973 974 memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size); 975 976 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 977 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 978 979 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 980 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 981 982 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 983 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 984 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes); 985 986 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes, 987 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 988 &adev->gfx.mec.mec_fw_obj, 989 &adev->gfx.mec.mec_fw_gpu_addr, 990 (void **)&fw); 991 if (r) { 992 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r); 993 gfx_v10_0_mec_fini(adev); 994 return r; 995 } 996 997 memcpy(fw, fw_data, fw_size); 998 999 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 1000 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 1001 } 1002 1003 return 0; 1004 } 1005 1006 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address) 1007 { 1008 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1009 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1010 (address << SQ_IND_INDEX__INDEX__SHIFT)); 1011 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1012 } 1013 1014 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave, 1015 uint32_t thread, uint32_t regno, 1016 uint32_t num, uint32_t *out) 1017 { 1018 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX, 1019 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 1020 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 1021 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 1022 (SQ_IND_INDEX__AUTO_INCR_MASK)); 1023 while (num--) 1024 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA); 1025 } 1026 1027 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields) 1028 { 1029 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE 1030 * field when performing a select_se_sh so it should be 1031 * zero here */ 1032 WARN_ON(simd != 0); 1033 1034 /* type 2 wave data */ 1035 dst[(*no_fields)++] = 2; 1036 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS); 1037 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO); 1038 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI); 1039 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO); 1040 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI); 1041 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1); 1042 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2); 1043 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0); 1044 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC); 1045 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC); 1046 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS); 1047 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS); 1048 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2); 1049 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1); 1050 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0); 1051 } 1052 1053 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd, 1054 uint32_t wave, uint32_t start, 1055 uint32_t size, uint32_t *dst) 1056 { 1057 WARN_ON(simd != 0); 1058 1059 wave_read_regs( 1060 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size, 1061 dst); 1062 } 1063 1064 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd, 1065 uint32_t wave, uint32_t thread, 1066 uint32_t start, uint32_t size, 1067 uint32_t *dst) 1068 { 1069 wave_read_regs( 1070 adev, wave, thread, 1071 start + SQIND_WAVE_VGPRS_OFFSET, size, dst); 1072 } 1073 1074 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev, 1075 u32 me, u32 pipe, u32 q, u32 vm) 1076 { 1077 nv_grbm_select(adev, me, pipe, q, vm); 1078 } 1079 1080 1081 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = { 1082 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter, 1083 .select_se_sh = &gfx_v10_0_select_se_sh, 1084 .read_wave_data = &gfx_v10_0_read_wave_data, 1085 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs, 1086 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs, 1087 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q, 1088 }; 1089 1090 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) 1091 { 1092 u32 gb_addr_config; 1093 1094 adev->gfx.funcs = &gfx_v10_0_gfx_funcs; 1095 1096 switch (adev->asic_type) { 1097 case CHIP_NAVI10: 1098 adev->gfx.config.max_hw_contexts = 8; 1099 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1100 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1101 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 1102 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1103 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1104 break; 1105 case CHIP_NAVI14: 1106 adev->gfx.config.max_hw_contexts = 8; 1107 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 1108 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 1109 adev->gfx.config.sc_hiz_tile_fifo_size = 0x0; 1110 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 1111 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); 1112 break; 1113 default: 1114 BUG(); 1115 break; 1116 } 1117 1118 adev->gfx.config.gb_addr_config = gb_addr_config; 1119 1120 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << 1121 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1122 GB_ADDR_CONFIG, NUM_PIPES); 1123 1124 adev->gfx.config.max_tile_pipes = 1125 adev->gfx.config.gb_addr_config_fields.num_pipes; 1126 1127 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << 1128 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1129 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS); 1130 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << 1131 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1132 GB_ADDR_CONFIG, NUM_RB_PER_SE); 1133 adev->gfx.config.gb_addr_config_fields.num_se = 1 << 1134 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1135 GB_ADDR_CONFIG, NUM_SHADER_ENGINES); 1136 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + 1137 REG_GET_FIELD(adev->gfx.config.gb_addr_config, 1138 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE)); 1139 } 1140 1141 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id, 1142 int me, int pipe, int queue) 1143 { 1144 int r; 1145 struct amdgpu_ring *ring; 1146 unsigned int irq_type; 1147 1148 ring = &adev->gfx.gfx_ring[ring_id]; 1149 1150 ring->me = me; 1151 ring->pipe = pipe; 1152 ring->queue = queue; 1153 1154 ring->ring_obj = NULL; 1155 ring->use_doorbell = true; 1156 1157 if (!ring_id) 1158 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1; 1159 else 1160 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1; 1161 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1162 1163 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe; 1164 r = amdgpu_ring_init(adev, ring, 1024, 1165 &adev->gfx.eop_irq, irq_type); 1166 if (r) 1167 return r; 1168 return 0; 1169 } 1170 1171 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, 1172 int mec, int pipe, int queue) 1173 { 1174 int r; 1175 unsigned irq_type; 1176 struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id]; 1177 1178 ring = &adev->gfx.compute_ring[ring_id]; 1179 1180 /* mec0 is me1 */ 1181 ring->me = mec + 1; 1182 ring->pipe = pipe; 1183 ring->queue = queue; 1184 1185 ring->ring_obj = NULL; 1186 ring->use_doorbell = true; 1187 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1; 1188 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr 1189 + (ring_id * GFX10_MEC_HPD_SIZE); 1190 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); 1191 1192 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 1193 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 1194 + ring->pipe; 1195 1196 /* type-2 packets are deprecated on MEC, use type-3 instead */ 1197 r = amdgpu_ring_init(adev, ring, 1024, 1198 &adev->gfx.eop_irq, irq_type); 1199 if (r) 1200 return r; 1201 1202 return 0; 1203 } 1204 1205 static int gfx_v10_0_sw_init(void *handle) 1206 { 1207 int i, j, k, r, ring_id = 0; 1208 struct amdgpu_kiq *kiq; 1209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1210 1211 switch (adev->asic_type) { 1212 case CHIP_NAVI10: 1213 case CHIP_NAVI14: 1214 adev->gfx.me.num_me = 1; 1215 adev->gfx.me.num_pipe_per_me = 2; 1216 adev->gfx.me.num_queue_per_pipe = 1; 1217 adev->gfx.mec.num_mec = 2; 1218 adev->gfx.mec.num_pipe_per_mec = 4; 1219 adev->gfx.mec.num_queue_per_pipe = 8; 1220 break; 1221 default: 1222 adev->gfx.me.num_me = 1; 1223 adev->gfx.me.num_pipe_per_me = 1; 1224 adev->gfx.me.num_queue_per_pipe = 1; 1225 adev->gfx.mec.num_mec = 1; 1226 adev->gfx.mec.num_pipe_per_mec = 4; 1227 adev->gfx.mec.num_queue_per_pipe = 8; 1228 break; 1229 } 1230 1231 /* KIQ event */ 1232 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1233 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT, 1234 &adev->gfx.kiq.irq); 1235 if (r) 1236 return r; 1237 1238 /* EOP Event */ 1239 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, 1240 GFX_10_1__SRCID__CP_EOP_INTERRUPT, 1241 &adev->gfx.eop_irq); 1242 if (r) 1243 return r; 1244 1245 /* Privileged reg */ 1246 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT, 1247 &adev->gfx.priv_reg_irq); 1248 if (r) 1249 return r; 1250 1251 /* Privileged inst */ 1252 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT, 1253 &adev->gfx.priv_inst_irq); 1254 if (r) 1255 return r; 1256 1257 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1258 1259 gfx_v10_0_scratch_init(adev); 1260 1261 r = gfx_v10_0_me_init(adev); 1262 if (r) 1263 return r; 1264 1265 r = gfx_v10_0_rlc_init(adev); 1266 if (r) { 1267 DRM_ERROR("Failed to init rlc BOs!\n"); 1268 return r; 1269 } 1270 1271 r = gfx_v10_0_mec_init(adev); 1272 if (r) { 1273 DRM_ERROR("Failed to init MEC BOs!\n"); 1274 return r; 1275 } 1276 1277 /* set up the gfx ring */ 1278 for (i = 0; i < adev->gfx.me.num_me; i++) { 1279 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) { 1280 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) { 1281 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j)) 1282 continue; 1283 1284 r = gfx_v10_0_gfx_ring_init(adev, ring_id, 1285 i, k, j); 1286 if (r) 1287 return r; 1288 ring_id++; 1289 } 1290 } 1291 } 1292 1293 ring_id = 0; 1294 /* set up the compute queues - allocate horizontally across pipes */ 1295 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1296 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1297 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1298 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, 1299 j)) 1300 continue; 1301 1302 r = gfx_v10_0_compute_ring_init(adev, ring_id, 1303 i, k, j); 1304 if (r) 1305 return r; 1306 1307 ring_id++; 1308 } 1309 } 1310 } 1311 1312 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE); 1313 if (r) { 1314 DRM_ERROR("Failed to init KIQ BOs!\n"); 1315 return r; 1316 } 1317 1318 kiq = &adev->gfx.kiq; 1319 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq); 1320 if (r) 1321 return r; 1322 1323 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd)); 1324 if (r) 1325 return r; 1326 1327 /* allocate visible FB for rlc auto-loading fw */ 1328 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1329 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev); 1330 if (r) 1331 return r; 1332 } 1333 1334 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE; 1335 1336 gfx_v10_0_gpu_early_init(adev); 1337 1338 return 0; 1339 } 1340 1341 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev) 1342 { 1343 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj, 1344 &adev->gfx.pfp.pfp_fw_gpu_addr, 1345 (void **)&adev->gfx.pfp.pfp_fw_ptr); 1346 } 1347 1348 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev) 1349 { 1350 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj, 1351 &adev->gfx.ce.ce_fw_gpu_addr, 1352 (void **)&adev->gfx.ce.ce_fw_ptr); 1353 } 1354 1355 static void gfx_v10_0_me_fini(struct amdgpu_device *adev) 1356 { 1357 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj, 1358 &adev->gfx.me.me_fw_gpu_addr, 1359 (void **)&adev->gfx.me.me_fw_ptr); 1360 } 1361 1362 static int gfx_v10_0_sw_fini(void *handle) 1363 { 1364 int i; 1365 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1366 1367 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 1368 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); 1369 for (i = 0; i < adev->gfx.num_compute_rings; i++) 1370 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1371 1372 amdgpu_gfx_mqd_sw_fini(adev); 1373 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq); 1374 amdgpu_gfx_kiq_fini(adev); 1375 1376 gfx_v10_0_pfp_fini(adev); 1377 gfx_v10_0_ce_fini(adev); 1378 gfx_v10_0_me_fini(adev); 1379 gfx_v10_0_rlc_fini(adev); 1380 gfx_v10_0_mec_fini(adev); 1381 1382 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1383 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev); 1384 1385 gfx_v10_0_free_microcode(adev); 1386 1387 return 0; 1388 } 1389 1390 1391 static void gfx_v10_0_tiling_mode_table_init(struct amdgpu_device *adev) 1392 { 1393 /* TODO */ 1394 } 1395 1396 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1397 u32 sh_num, u32 instance) 1398 { 1399 u32 data; 1400 1401 if (instance == 0xffffffff) 1402 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1403 INSTANCE_BROADCAST_WRITES, 1); 1404 else 1405 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1406 instance); 1407 1408 if (se_num == 0xffffffff) 1409 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1410 1); 1411 else 1412 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1413 1414 if (sh_num == 0xffffffff) 1415 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1416 1); 1417 else 1418 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1419 1420 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1421 } 1422 1423 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev) 1424 { 1425 u32 data, mask; 1426 1427 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE); 1428 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE); 1429 1430 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK; 1431 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT; 1432 1433 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se / 1434 adev->gfx.config.max_sh_per_se); 1435 1436 return (~data) & mask; 1437 } 1438 1439 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev) 1440 { 1441 int i, j; 1442 u32 data; 1443 u32 active_rbs = 0; 1444 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se / 1445 adev->gfx.config.max_sh_per_se; 1446 1447 mutex_lock(&adev->grbm_idx_mutex); 1448 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1449 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1450 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1451 data = gfx_v10_0_get_rb_active_bitmap(adev); 1452 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * 1453 rb_bitmap_width_per_sh); 1454 } 1455 } 1456 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1457 mutex_unlock(&adev->grbm_idx_mutex); 1458 1459 adev->gfx.config.backend_enable_mask = active_rbs; 1460 adev->gfx.config.num_rbs = hweight32(active_rbs); 1461 } 1462 1463 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev) 1464 { 1465 uint32_t num_sc; 1466 uint32_t enabled_rb_per_sh; 1467 uint32_t active_rb_bitmap; 1468 uint32_t num_rb_per_sc; 1469 uint32_t num_packer_per_sc; 1470 uint32_t pa_sc_tile_steering_override; 1471 1472 /* init num_sc */ 1473 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * 1474 adev->gfx.config.num_sc_per_sh; 1475 /* init num_rb_per_sc */ 1476 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev); 1477 enabled_rb_per_sh = hweight32(active_rb_bitmap); 1478 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh; 1479 /* init num_packer_per_sc */ 1480 num_packer_per_sc = adev->gfx.config.num_packer_per_sc; 1481 1482 pa_sc_tile_steering_override = 0; 1483 pa_sc_tile_steering_override |= 1484 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) & 1485 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK; 1486 pa_sc_tile_steering_override |= 1487 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) & 1488 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK; 1489 pa_sc_tile_steering_override |= 1490 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) & 1491 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK; 1492 1493 return pa_sc_tile_steering_override; 1494 } 1495 1496 #define DEFAULT_SH_MEM_BASES (0x6000) 1497 #define FIRST_COMPUTE_VMID (8) 1498 #define LAST_COMPUTE_VMID (16) 1499 1500 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev) 1501 { 1502 int i; 1503 uint32_t sh_mem_bases; 1504 1505 /* 1506 * Configure apertures: 1507 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB) 1508 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB) 1509 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB) 1510 */ 1511 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16); 1512 1513 mutex_lock(&adev->srbm_mutex); 1514 for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { 1515 nv_grbm_select(adev, 0, 0, 0, i); 1516 /* CP and shaders */ 1517 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1518 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 1519 } 1520 nv_grbm_select(adev, 0, 0, 0, 0); 1521 mutex_unlock(&adev->srbm_mutex); 1522 } 1523 1524 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev) 1525 { 1526 int vmid; 1527 1528 /* 1529 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA 1530 * access. Compute VMIDs should be enabled by FW for target VMIDs, 1531 * the driver can enable them for graphics. VMID0 should maintain 1532 * access so that HWS firmware can save/restore entries. 1533 */ 1534 for (vmid = 1; vmid < 16; vmid++) { 1535 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0); 1536 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0); 1537 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0); 1538 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0); 1539 } 1540 } 1541 1542 1543 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev) 1544 { 1545 int i, j, k; 1546 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1; 1547 u32 tmp, wgp_active_bitmap = 0; 1548 u32 gcrd_targets_disable_tcp = 0; 1549 u32 utcl_invreq_disable = 0; 1550 /* 1551 * GCRD_TARGETS_DISABLE field contains 1552 * for Navi10: GL1C=[18:15], SQC=[14:10], TCP=[9:0] 1553 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0] 1554 */ 1555 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask( 1556 2 * max_wgp_per_sh + /* TCP */ 1557 max_wgp_per_sh + /* SQC */ 1558 4); /* GL1C */ 1559 /* 1560 * UTCL1_UTCL0_INVREQ_DISABLE field contains 1561 * for Navi10: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0] 1562 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0] 1563 */ 1564 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask( 1565 2 * max_wgp_per_sh + /* TCP */ 1566 2 * max_wgp_per_sh + /* SQC */ 1567 4 + /* RMI */ 1568 1); /* SQG */ 1569 1570 if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_NAVI14) { 1571 mutex_lock(&adev->grbm_idx_mutex); 1572 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 1573 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 1574 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 1575 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 1576 /* 1577 * Set corresponding TCP bits for the inactive WGPs in 1578 * GCRD_SA_TARGETS_DISABLE 1579 */ 1580 gcrd_targets_disable_tcp = 0; 1581 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */ 1582 utcl_invreq_disable = 0; 1583 1584 for (k = 0; k < max_wgp_per_sh; k++) { 1585 if (!(wgp_active_bitmap & (1 << k))) { 1586 gcrd_targets_disable_tcp |= 3 << (2 * k); 1587 utcl_invreq_disable |= (3 << (2 * k)) | 1588 (3 << (2 * (max_wgp_per_sh + k))); 1589 } 1590 } 1591 1592 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE); 1593 /* only override TCP & SQC bits */ 1594 tmp &= 0xffffffff << (4 * max_wgp_per_sh); 1595 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask); 1596 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp); 1597 1598 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE); 1599 /* only override TCP bits */ 1600 tmp &= 0xffffffff << (2 * max_wgp_per_sh); 1601 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask); 1602 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp); 1603 } 1604 } 1605 1606 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1607 mutex_unlock(&adev->grbm_idx_mutex); 1608 } 1609 } 1610 1611 static void gfx_v10_0_constants_init(struct amdgpu_device *adev) 1612 { 1613 u32 tmp; 1614 int i; 1615 1616 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff); 1617 1618 gfx_v10_0_tiling_mode_table_init(adev); 1619 1620 gfx_v10_0_setup_rb(adev); 1621 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info); 1622 adev->gfx.config.pa_sc_tile_steering_override = 1623 gfx_v10_0_init_pa_sc_tile_steering_override(adev); 1624 1625 /* XXX SH_MEM regs */ 1626 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1627 mutex_lock(&adev->srbm_mutex); 1628 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) { 1629 nv_grbm_select(adev, 0, 0, 0, i); 1630 /* CP and shaders */ 1631 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG); 1632 if (i != 0) { 1633 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1634 (adev->gmc.private_aperture_start >> 48)); 1635 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1636 (adev->gmc.shared_aperture_start >> 48)); 1637 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp); 1638 } 1639 } 1640 nv_grbm_select(adev, 0, 0, 0, 0); 1641 1642 mutex_unlock(&adev->srbm_mutex); 1643 1644 gfx_v10_0_init_compute_vmid(adev); 1645 gfx_v10_0_init_gds_vmid(adev); 1646 1647 } 1648 1649 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1650 bool enable) 1651 { 1652 u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); 1653 1654 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1655 enable ? 1 : 0); 1656 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1657 enable ? 1 : 0); 1658 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1659 enable ? 1 : 0); 1660 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1661 enable ? 1 : 0); 1662 1663 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp); 1664 } 1665 1666 static void gfx_v10_0_init_csb(struct amdgpu_device *adev) 1667 { 1668 /* csib */ 1669 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI, 1670 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1671 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO, 1672 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1673 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1674 } 1675 1676 static void gfx_v10_0_init_pg(struct amdgpu_device *adev) 1677 { 1678 gfx_v10_0_init_csb(adev); 1679 1680 amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); 1681 1682 /* TODO: init power gating */ 1683 return; 1684 } 1685 1686 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev) 1687 { 1688 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 1689 1690 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1691 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp); 1692 } 1693 1694 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev) 1695 { 1696 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1697 udelay(50); 1698 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1699 udelay(50); 1700 } 1701 1702 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1703 bool enable) 1704 { 1705 uint32_t rlc_pg_cntl; 1706 1707 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL); 1708 1709 if (!enable) { 1710 /* RLC_PG_CNTL[23] = 0 (default) 1711 * RLC will wait for handshake acks with SMU 1712 * GFXOFF will be enabled 1713 * RLC_PG_CNTL[23] = 1 1714 * RLC will not issue any message to SMU 1715 * hence no handshake between SMU & RLC 1716 * GFXOFF will be disabled 1717 */ 1718 rlc_pg_cntl |= 0x80000; 1719 } else 1720 rlc_pg_cntl &= ~0x80000; 1721 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl); 1722 } 1723 1724 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev) 1725 { 1726 /* TODO: enable rlc & smu handshake until smu 1727 * and gfxoff feature works as expected */ 1728 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1729 gfx_v10_0_rlc_smu_handshake_cntl(adev, false); 1730 1731 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1); 1732 udelay(50); 1733 } 1734 1735 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev) 1736 { 1737 uint32_t tmp; 1738 1739 /* enable Save Restore Machine */ 1740 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL)); 1741 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1742 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1743 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp); 1744 } 1745 1746 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev) 1747 { 1748 const struct rlc_firmware_header_v2_0 *hdr; 1749 const __le32 *fw_data; 1750 unsigned i, fw_size; 1751 1752 if (!adev->gfx.rlc_fw) 1753 return -EINVAL; 1754 1755 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1756 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1757 1758 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1759 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1760 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1761 1762 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, 1763 RLCG_UCODE_LOADING_START_ADDRESS); 1764 1765 for (i = 0; i < fw_size; i++) 1766 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, 1767 le32_to_cpup(fw_data++)); 1768 1769 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version); 1770 1771 return 0; 1772 } 1773 1774 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev) 1775 { 1776 int r; 1777 1778 if (amdgpu_sriov_vf(adev)) 1779 return 0; 1780 1781 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1782 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1783 if (r) 1784 return r; 1785 gfx_v10_0_init_pg(adev); 1786 1787 /* enable RLC SRM */ 1788 gfx_v10_0_rlc_enable_srm(adev); 1789 1790 } else { 1791 adev->gfx.rlc.funcs->stop(adev); 1792 1793 /* disable CG */ 1794 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); 1795 1796 /* disable PG */ 1797 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); 1798 1799 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1800 /* legacy rlc firmware loading */ 1801 r = gfx_v10_0_rlc_load_microcode(adev); 1802 if (r) 1803 return r; 1804 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1805 /* rlc backdoor autoload firmware */ 1806 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev); 1807 if (r) 1808 return r; 1809 } 1810 1811 gfx_v10_0_init_pg(adev); 1812 adev->gfx.rlc.funcs->start(adev); 1813 1814 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1815 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev); 1816 if (r) 1817 return r; 1818 } 1819 } 1820 return 0; 1821 } 1822 1823 static struct { 1824 FIRMWARE_ID id; 1825 unsigned int offset; 1826 unsigned int size; 1827 } rlc_autoload_info[FIRMWARE_ID_MAX]; 1828 1829 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev) 1830 { 1831 int ret; 1832 RLC_TABLE_OF_CONTENT *rlc_toc; 1833 1834 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE, 1835 AMDGPU_GEM_DOMAIN_GTT, 1836 &adev->gfx.rlc.rlc_toc_bo, 1837 &adev->gfx.rlc.rlc_toc_gpu_addr, 1838 (void **)&adev->gfx.rlc.rlc_toc_buf); 1839 if (ret) { 1840 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret); 1841 return ret; 1842 } 1843 1844 /* Copy toc from psp sos fw to rlc toc buffer */ 1845 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size); 1846 1847 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf; 1848 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) && 1849 (rlc_toc->id < FIRMWARE_ID_MAX)) { 1850 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) && 1851 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) { 1852 /* Offset needs 4KB alignment */ 1853 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE); 1854 } 1855 1856 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id; 1857 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4; 1858 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4; 1859 1860 rlc_toc++; 1861 }; 1862 1863 return 0; 1864 } 1865 1866 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev) 1867 { 1868 uint32_t total_size = 0; 1869 FIRMWARE_ID id; 1870 int ret; 1871 1872 ret = gfx_v10_0_parse_rlc_toc(adev); 1873 if (ret) { 1874 dev_err(adev->dev, "failed to parse rlc toc\n"); 1875 return 0; 1876 } 1877 1878 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++) 1879 total_size += rlc_autoload_info[id].size; 1880 1881 /* In case the offset in rlc toc ucode is aligned */ 1882 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset) 1883 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset + 1884 rlc_autoload_info[FIRMWARE_ID_MAX-1].size; 1885 1886 return total_size; 1887 } 1888 1889 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev) 1890 { 1891 int r; 1892 uint32_t total_size; 1893 1894 total_size = gfx_v10_0_calc_toc_total_size(adev); 1895 1896 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE, 1897 AMDGPU_GEM_DOMAIN_GTT, 1898 &adev->gfx.rlc.rlc_autoload_bo, 1899 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1900 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1901 if (r) { 1902 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 1903 return r; 1904 } 1905 1906 return 0; 1907 } 1908 1909 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev) 1910 { 1911 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo, 1912 &adev->gfx.rlc.rlc_toc_gpu_addr, 1913 (void **)&adev->gfx.rlc.rlc_toc_buf); 1914 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1915 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1916 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1917 } 1918 1919 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 1920 FIRMWARE_ID id, 1921 const void *fw_data, 1922 uint32_t fw_size) 1923 { 1924 uint32_t toc_offset; 1925 uint32_t toc_fw_size; 1926 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 1927 1928 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX) 1929 return; 1930 1931 toc_offset = rlc_autoload_info[id].offset; 1932 toc_fw_size = rlc_autoload_info[id].size; 1933 1934 if (fw_size == 0) 1935 fw_size = toc_fw_size; 1936 1937 if (fw_size > toc_fw_size) 1938 fw_size = toc_fw_size; 1939 1940 memcpy(ptr + toc_offset, fw_data, fw_size); 1941 1942 if (fw_size < toc_fw_size) 1943 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size); 1944 } 1945 1946 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 1947 { 1948 void *data; 1949 uint32_t size; 1950 1951 data = adev->gfx.rlc.rlc_toc_buf; 1952 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size; 1953 1954 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1955 FIRMWARE_ID_RLC_TOC, 1956 data, size); 1957 } 1958 1959 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 1960 { 1961 const __le32 *fw_data; 1962 uint32_t fw_size; 1963 const struct gfx_firmware_header_v1_0 *cp_hdr; 1964 const struct rlc_firmware_header_v2_0 *rlc_hdr; 1965 1966 /* pfp ucode */ 1967 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1968 adev->gfx.pfp_fw->data; 1969 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 1970 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1971 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1972 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1973 FIRMWARE_ID_CP_PFP, 1974 fw_data, fw_size); 1975 1976 /* ce ucode */ 1977 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1978 adev->gfx.ce_fw->data; 1979 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 1980 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1981 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1982 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1983 FIRMWARE_ID_CP_CE, 1984 fw_data, fw_size); 1985 1986 /* me ucode */ 1987 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 1988 adev->gfx.me_fw->data; 1989 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 1990 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 1991 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes); 1992 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 1993 FIRMWARE_ID_CP_ME, 1994 fw_data, fw_size); 1995 1996 /* rlc ucode */ 1997 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 1998 adev->gfx.rlc_fw->data; 1999 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 2000 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 2001 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 2002 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2003 FIRMWARE_ID_RLC_G_UCODE, 2004 fw_data, fw_size); 2005 2006 /* mec1 ucode */ 2007 cp_hdr = (const struct gfx_firmware_header_v1_0 *) 2008 adev->gfx.mec_fw->data; 2009 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2010 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes)); 2011 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) - 2012 cp_hdr->jt_size * 4; 2013 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2014 FIRMWARE_ID_CP_MEC, 2015 fw_data, fw_size); 2016 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */ 2017 } 2018 2019 /* Temporarily put sdma part here */ 2020 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 2021 { 2022 const __le32 *fw_data; 2023 uint32_t fw_size; 2024 const struct sdma_firmware_header_v1_0 *sdma_hdr; 2025 int i; 2026 2027 for (i = 0; i < adev->sdma.num_instances; i++) { 2028 sdma_hdr = (const struct sdma_firmware_header_v1_0 *) 2029 adev->sdma.instance[i].fw->data; 2030 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data + 2031 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes)); 2032 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes); 2033 2034 if (i == 0) { 2035 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2036 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size); 2037 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2038 FIRMWARE_ID_SDMA0_JT, 2039 (uint32_t *)fw_data + 2040 sdma_hdr->jt_offset, 2041 sdma_hdr->jt_size * 4); 2042 } else if (i == 1) { 2043 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2044 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size); 2045 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev, 2046 FIRMWARE_ID_SDMA1_JT, 2047 (uint32_t *)fw_data + 2048 sdma_hdr->jt_offset, 2049 sdma_hdr->jt_size * 4); 2050 } 2051 } 2052 } 2053 2054 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 2055 { 2056 uint32_t rlc_g_offset, rlc_g_size, tmp; 2057 uint64_t gpu_addr; 2058 2059 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev); 2060 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev); 2061 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev); 2062 2063 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset; 2064 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size; 2065 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset; 2066 2067 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr)); 2068 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr)); 2069 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size); 2070 2071 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR); 2072 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK | 2073 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) { 2074 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n"); 2075 return -EINVAL; 2076 } 2077 2078 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL); 2079 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) { 2080 DRM_ERROR("RLC ROM should halt itself\n"); 2081 return -EINVAL; 2082 } 2083 2084 return 0; 2085 } 2086 2087 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev) 2088 { 2089 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2090 uint32_t tmp; 2091 int i; 2092 uint64_t addr; 2093 2094 /* Trigger an invalidation of the L1 instruction caches */ 2095 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2096 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2097 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2098 2099 /* Wait for invalidation complete */ 2100 for (i = 0; i < usec_timeout; i++) { 2101 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2102 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2103 INVALIDATE_CACHE_COMPLETE)) 2104 break; 2105 udelay(1); 2106 } 2107 2108 if (i >= usec_timeout) { 2109 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2110 return -EINVAL; 2111 } 2112 2113 /* Program me ucode address into intruction cache address register */ 2114 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2115 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset; 2116 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2117 lower_32_bits(addr) & 0xFFFFF000); 2118 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2119 upper_32_bits(addr)); 2120 2121 return 0; 2122 } 2123 2124 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev) 2125 { 2126 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2127 uint32_t tmp; 2128 int i; 2129 uint64_t addr; 2130 2131 /* Trigger an invalidation of the L1 instruction caches */ 2132 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2133 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2134 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2135 2136 /* Wait for invalidation complete */ 2137 for (i = 0; i < usec_timeout; i++) { 2138 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2139 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2140 INVALIDATE_CACHE_COMPLETE)) 2141 break; 2142 udelay(1); 2143 } 2144 2145 if (i >= usec_timeout) { 2146 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2147 return -EINVAL; 2148 } 2149 2150 /* Program ce ucode address into intruction cache address register */ 2151 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2152 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset; 2153 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2154 lower_32_bits(addr) & 0xFFFFF000); 2155 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2156 upper_32_bits(addr)); 2157 2158 return 0; 2159 } 2160 2161 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev) 2162 { 2163 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2164 uint32_t tmp; 2165 int i; 2166 uint64_t addr; 2167 2168 /* Trigger an invalidation of the L1 instruction caches */ 2169 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2170 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2171 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2172 2173 /* Wait for invalidation complete */ 2174 for (i = 0; i < usec_timeout; i++) { 2175 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2176 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2177 INVALIDATE_CACHE_COMPLETE)) 2178 break; 2179 udelay(1); 2180 } 2181 2182 if (i >= usec_timeout) { 2183 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2184 return -EINVAL; 2185 } 2186 2187 /* Program pfp ucode address into intruction cache address register */ 2188 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2189 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset; 2190 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2191 lower_32_bits(addr) & 0xFFFFF000); 2192 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2193 upper_32_bits(addr)); 2194 2195 return 0; 2196 } 2197 2198 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev) 2199 { 2200 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2201 uint32_t tmp; 2202 int i; 2203 uint64_t addr; 2204 2205 /* Trigger an invalidation of the L1 instruction caches */ 2206 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2207 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2208 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2209 2210 /* Wait for invalidation complete */ 2211 for (i = 0; i < usec_timeout; i++) { 2212 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2213 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2214 INVALIDATE_CACHE_COMPLETE)) 2215 break; 2216 udelay(1); 2217 } 2218 2219 if (i >= usec_timeout) { 2220 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2221 return -EINVAL; 2222 } 2223 2224 /* Program mec1 ucode address into intruction cache address register */ 2225 addr = adev->gfx.rlc.rlc_autoload_gpu_addr + 2226 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset; 2227 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, 2228 lower_32_bits(addr) & 0xFFFFF000); 2229 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2230 upper_32_bits(addr)); 2231 2232 return 0; 2233 } 2234 2235 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2236 { 2237 uint32_t cp_status; 2238 uint32_t bootload_status; 2239 int i, r; 2240 2241 for (i = 0; i < adev->usec_timeout; i++) { 2242 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT); 2243 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS); 2244 if ((cp_status == 0) && 2245 (REG_GET_FIELD(bootload_status, 2246 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 2247 break; 2248 } 2249 udelay(1); 2250 } 2251 2252 if (i >= adev->usec_timeout) { 2253 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n"); 2254 return -ETIMEDOUT; 2255 } 2256 2257 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2258 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev); 2259 if (r) 2260 return r; 2261 2262 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev); 2263 if (r) 2264 return r; 2265 2266 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev); 2267 if (r) 2268 return r; 2269 2270 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev); 2271 if (r) 2272 return r; 2273 } 2274 2275 return 0; 2276 } 2277 2278 static void gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) 2279 { 2280 int i; 2281 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); 2282 2283 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); 2284 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); 2285 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); 2286 if (!enable) { 2287 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 2288 adev->gfx.gfx_ring[i].sched.ready = false; 2289 } 2290 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp); 2291 udelay(50); 2292 } 2293 2294 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev) 2295 { 2296 int r; 2297 const struct gfx_firmware_header_v1_0 *pfp_hdr; 2298 const __le32 *fw_data; 2299 unsigned i, fw_size; 2300 uint32_t tmp; 2301 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2302 2303 pfp_hdr = (const struct gfx_firmware_header_v1_0 *) 2304 adev->gfx.pfp_fw->data; 2305 2306 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header); 2307 2308 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data + 2309 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes)); 2310 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes); 2311 2312 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes, 2313 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2314 &adev->gfx.pfp.pfp_fw_obj, 2315 &adev->gfx.pfp.pfp_fw_gpu_addr, 2316 (void **)&adev->gfx.pfp.pfp_fw_ptr); 2317 if (r) { 2318 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r); 2319 gfx_v10_0_pfp_fini(adev); 2320 return r; 2321 } 2322 2323 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size); 2324 2325 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj); 2326 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj); 2327 2328 /* Trigger an invalidation of the L1 instruction caches */ 2329 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2330 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2331 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp); 2332 2333 /* Wait for invalidation complete */ 2334 for (i = 0; i < usec_timeout; i++) { 2335 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL); 2336 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL, 2337 INVALIDATE_CACHE_COMPLETE)) 2338 break; 2339 udelay(1); 2340 } 2341 2342 if (i >= usec_timeout) { 2343 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2344 return -EINVAL; 2345 } 2346 2347 if (amdgpu_emu_mode == 1) 2348 adev->nbio_funcs->hdp_flush(adev, NULL); 2349 2350 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL); 2351 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0); 2352 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0); 2353 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0); 2354 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2355 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp); 2356 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO, 2357 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000); 2358 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI, 2359 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr)); 2360 2361 return 0; 2362 } 2363 2364 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev) 2365 { 2366 int r; 2367 const struct gfx_firmware_header_v1_0 *ce_hdr; 2368 const __le32 *fw_data; 2369 unsigned i, fw_size; 2370 uint32_t tmp; 2371 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2372 2373 ce_hdr = (const struct gfx_firmware_header_v1_0 *) 2374 adev->gfx.ce_fw->data; 2375 2376 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header); 2377 2378 fw_data = (const __le32 *)(adev->gfx.ce_fw->data + 2379 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes)); 2380 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes); 2381 2382 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes, 2383 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2384 &adev->gfx.ce.ce_fw_obj, 2385 &adev->gfx.ce.ce_fw_gpu_addr, 2386 (void **)&adev->gfx.ce.ce_fw_ptr); 2387 if (r) { 2388 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r); 2389 gfx_v10_0_ce_fini(adev); 2390 return r; 2391 } 2392 2393 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size); 2394 2395 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj); 2396 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj); 2397 2398 /* Trigger an invalidation of the L1 instruction caches */ 2399 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2400 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2401 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp); 2402 2403 /* Wait for invalidation complete */ 2404 for (i = 0; i < usec_timeout; i++) { 2405 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL); 2406 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL, 2407 INVALIDATE_CACHE_COMPLETE)) 2408 break; 2409 udelay(1); 2410 } 2411 2412 if (i >= usec_timeout) { 2413 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2414 return -EINVAL; 2415 } 2416 2417 if (amdgpu_emu_mode == 1) 2418 adev->nbio_funcs->hdp_flush(adev, NULL); 2419 2420 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL); 2421 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0); 2422 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0); 2423 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0); 2424 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2425 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO, 2426 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000); 2427 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI, 2428 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr)); 2429 2430 return 0; 2431 } 2432 2433 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev) 2434 { 2435 int r; 2436 const struct gfx_firmware_header_v1_0 *me_hdr; 2437 const __le32 *fw_data; 2438 unsigned i, fw_size; 2439 uint32_t tmp; 2440 uint32_t usec_timeout = 50000; /* wait for 50ms */ 2441 2442 me_hdr = (const struct gfx_firmware_header_v1_0 *) 2443 adev->gfx.me_fw->data; 2444 2445 amdgpu_ucode_print_gfx_hdr(&me_hdr->header); 2446 2447 fw_data = (const __le32 *)(adev->gfx.me_fw->data + 2448 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes)); 2449 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes); 2450 2451 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes, 2452 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT, 2453 &adev->gfx.me.me_fw_obj, 2454 &adev->gfx.me.me_fw_gpu_addr, 2455 (void **)&adev->gfx.me.me_fw_ptr); 2456 if (r) { 2457 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r); 2458 gfx_v10_0_me_fini(adev); 2459 return r; 2460 } 2461 2462 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size); 2463 2464 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj); 2465 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj); 2466 2467 /* Trigger an invalidation of the L1 instruction caches */ 2468 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2469 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2470 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp); 2471 2472 /* Wait for invalidation complete */ 2473 for (i = 0; i < usec_timeout; i++) { 2474 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL); 2475 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL, 2476 INVALIDATE_CACHE_COMPLETE)) 2477 break; 2478 udelay(1); 2479 } 2480 2481 if (i >= usec_timeout) { 2482 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2483 return -EINVAL; 2484 } 2485 2486 if (amdgpu_emu_mode == 1) 2487 adev->nbio_funcs->hdp_flush(adev, NULL); 2488 2489 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL); 2490 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0); 2491 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0); 2492 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0); 2493 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2494 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO, 2495 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000); 2496 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI, 2497 upper_32_bits(adev->gfx.me.me_fw_gpu_addr)); 2498 2499 return 0; 2500 } 2501 2502 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev) 2503 { 2504 int r; 2505 2506 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) 2507 return -EINVAL; 2508 2509 gfx_v10_0_cp_gfx_enable(adev, false); 2510 2511 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev); 2512 if (r) { 2513 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r); 2514 return r; 2515 } 2516 2517 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev); 2518 if (r) { 2519 dev_err(adev->dev, "(%d) failed to load ce fw\n", r); 2520 return r; 2521 } 2522 2523 r = gfx_v10_0_cp_gfx_load_me_microcode(adev); 2524 if (r) { 2525 dev_err(adev->dev, "(%d) failed to load me fw\n", r); 2526 return r; 2527 } 2528 2529 return 0; 2530 } 2531 2532 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev) 2533 { 2534 struct amdgpu_ring *ring; 2535 const struct cs_section_def *sect = NULL; 2536 const struct cs_extent_def *ext = NULL; 2537 int r, i; 2538 int ctx_reg_offset; 2539 2540 /* init the CP */ 2541 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, 2542 adev->gfx.config.max_hw_contexts - 1); 2543 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1); 2544 2545 gfx_v10_0_cp_gfx_enable(adev, true); 2546 2547 ring = &adev->gfx.gfx_ring[0]; 2548 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4); 2549 if (r) { 2550 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2551 return r; 2552 } 2553 2554 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2555 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 2556 2557 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 2558 amdgpu_ring_write(ring, 0x80000000); 2559 amdgpu_ring_write(ring, 0x80000000); 2560 2561 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) { 2562 for (ext = sect->section; ext->extent != NULL; ++ext) { 2563 if (sect->id == SECT_CONTEXT) { 2564 amdgpu_ring_write(ring, 2565 PACKET3(PACKET3_SET_CONTEXT_REG, 2566 ext->reg_count)); 2567 amdgpu_ring_write(ring, ext->reg_index - 2568 PACKET3_SET_CONTEXT_REG_START); 2569 for (i = 0; i < ext->reg_count; i++) 2570 amdgpu_ring_write(ring, ext->extent[i]); 2571 } 2572 } 2573 } 2574 2575 ctx_reg_offset = 2576 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; 2577 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 2578 amdgpu_ring_write(ring, ctx_reg_offset); 2579 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override); 2580 2581 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 2582 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); 2583 2584 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2585 amdgpu_ring_write(ring, 0); 2586 2587 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); 2588 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); 2589 amdgpu_ring_write(ring, 0x8000); 2590 amdgpu_ring_write(ring, 0x8000); 2591 2592 amdgpu_ring_commit(ring); 2593 2594 /* submit cs packet to copy state 0 to next available state */ 2595 ring = &adev->gfx.gfx_ring[1]; 2596 r = amdgpu_ring_alloc(ring, 2); 2597 if (r) { 2598 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r); 2599 return r; 2600 } 2601 2602 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); 2603 amdgpu_ring_write(ring, 0); 2604 2605 amdgpu_ring_commit(ring); 2606 2607 return 0; 2608 } 2609 2610 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev, 2611 CP_PIPE_ID pipe) 2612 { 2613 u32 tmp; 2614 2615 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL); 2616 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe); 2617 2618 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp); 2619 } 2620 2621 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev, 2622 struct amdgpu_ring *ring) 2623 { 2624 u32 tmp; 2625 2626 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2627 if (ring->use_doorbell) { 2628 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2629 DOORBELL_OFFSET, ring->doorbell_index); 2630 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2631 DOORBELL_EN, 1); 2632 } else { 2633 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2634 DOORBELL_EN, 0); 2635 } 2636 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp); 2637 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER, 2638 DOORBELL_RANGE_LOWER, ring->doorbell_index); 2639 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp); 2640 2641 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER, 2642 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK); 2643 } 2644 2645 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev) 2646 { 2647 struct amdgpu_ring *ring; 2648 u32 tmp; 2649 u32 rb_bufsz; 2650 u64 rb_addr, rptr_addr, wptr_gpu_addr; 2651 u32 i; 2652 2653 /* Set the write pointer delay */ 2654 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0); 2655 2656 /* set the RB to use vmid 0 */ 2657 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0); 2658 2659 /* Init gfx ring 0 for pipe 0 */ 2660 mutex_lock(&adev->srbm_mutex); 2661 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2662 mutex_unlock(&adev->srbm_mutex); 2663 /* Set ring buffer size */ 2664 ring = &adev->gfx.gfx_ring[0]; 2665 rb_bufsz = order_base_2(ring->ring_size / 8); 2666 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); 2667 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); 2668 #ifdef __BIG_ENDIAN 2669 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1); 2670 #endif 2671 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2672 2673 /* Initialize the ring buffer's write pointers */ 2674 ring->wptr = 0; 2675 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 2676 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 2677 2678 /* set the wb address wether it's enabled or not */ 2679 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2680 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); 2681 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2682 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2683 2684 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2685 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2686 lower_32_bits(wptr_gpu_addr)); 2687 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2688 upper_32_bits(wptr_gpu_addr)); 2689 2690 mdelay(1); 2691 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp); 2692 2693 rb_addr = ring->gpu_addr >> 8; 2694 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr); 2695 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr)); 2696 2697 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1); 2698 2699 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2700 2701 /* Init gfx ring 1 for pipe 1 */ 2702 mutex_lock(&adev->srbm_mutex); 2703 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1); 2704 mutex_unlock(&adev->srbm_mutex); 2705 ring = &adev->gfx.gfx_ring[1]; 2706 rb_bufsz = order_base_2(ring->ring_size / 8); 2707 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); 2708 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); 2709 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2710 /* Initialize the ring buffer's write pointers */ 2711 ring->wptr = 0; 2712 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); 2713 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); 2714 /* Set the wb address wether it's enabled or not */ 2715 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2716 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr)); 2717 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 2718 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK); 2719 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2720 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, 2721 lower_32_bits(wptr_gpu_addr)); 2722 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, 2723 upper_32_bits(wptr_gpu_addr)); 2724 2725 mdelay(1); 2726 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp); 2727 2728 rb_addr = ring->gpu_addr >> 8; 2729 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr); 2730 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr)); 2731 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1); 2732 2733 gfx_v10_0_cp_gfx_set_doorbell(adev, ring); 2734 2735 /* Switch to pipe 0 */ 2736 mutex_lock(&adev->srbm_mutex); 2737 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0); 2738 mutex_unlock(&adev->srbm_mutex); 2739 2740 /* start the ring */ 2741 gfx_v10_0_cp_gfx_start(adev); 2742 2743 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 2744 ring = &adev->gfx.gfx_ring[i]; 2745 ring->sched.ready = true; 2746 } 2747 2748 return 0; 2749 } 2750 2751 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) 2752 { 2753 int i; 2754 2755 if (enable) { 2756 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0); 2757 } else { 2758 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 2759 (CP_MEC_CNTL__MEC_ME1_HALT_MASK | 2760 CP_MEC_CNTL__MEC_ME2_HALT_MASK)); 2761 for (i = 0; i < adev->gfx.num_compute_rings; i++) 2762 adev->gfx.compute_ring[i].sched.ready = false; 2763 adev->gfx.kiq.ring.sched.ready = false; 2764 } 2765 udelay(50); 2766 } 2767 2768 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev) 2769 { 2770 const struct gfx_firmware_header_v1_0 *mec_hdr; 2771 const __le32 *fw_data; 2772 unsigned i; 2773 u32 tmp; 2774 u32 usec_timeout = 50000; /* Wait for 50 ms */ 2775 2776 if (!adev->gfx.mec_fw) 2777 return -EINVAL; 2778 2779 gfx_v10_0_cp_compute_enable(adev, false); 2780 2781 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data; 2782 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2783 2784 fw_data = (const __le32 *) 2785 (adev->gfx.mec_fw->data + 2786 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes)); 2787 2788 /* Trigger an invalidation of the L1 instruction caches */ 2789 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2790 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2791 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp); 2792 2793 /* Wait for invalidation complete */ 2794 for (i = 0; i < usec_timeout; i++) { 2795 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL); 2796 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2797 INVALIDATE_CACHE_COMPLETE)) 2798 break; 2799 udelay(1); 2800 } 2801 2802 if (i >= usec_timeout) { 2803 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2804 return -EINVAL; 2805 } 2806 2807 if (amdgpu_emu_mode == 1) 2808 adev->nbio_funcs->hdp_flush(adev, NULL); 2809 2810 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); 2811 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2812 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2813 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1); 2814 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); 2815 2816 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr & 2817 0xFFFFF000); 2818 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI, 2819 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2820 2821 /* MEC1 */ 2822 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0); 2823 2824 for (i = 0; i < mec_hdr->jt_size; i++) 2825 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA, 2826 le32_to_cpup(fw_data + mec_hdr->jt_offset + i)); 2827 2828 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version); 2829 2830 /* 2831 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run 2832 * different microcode than MEC1. 2833 */ 2834 2835 return 0; 2836 } 2837 2838 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring) 2839 { 2840 uint32_t tmp; 2841 struct amdgpu_device *adev = ring->adev; 2842 2843 /* tell RLC which is KIQ queue */ 2844 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS); 2845 tmp &= 0xffffff00; 2846 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue); 2847 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2848 tmp |= 0x80; 2849 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp); 2850 } 2851 2852 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring) 2853 { 2854 struct amdgpu_device *adev = ring->adev; 2855 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2856 uint64_t hqd_gpu_addr, wb_gpu_addr; 2857 uint32_t tmp; 2858 uint32_t rb_bufsz; 2859 2860 /* set up gfx hqd wptr */ 2861 mqd->cp_gfx_hqd_wptr = 0; 2862 mqd->cp_gfx_hqd_wptr_hi = 0; 2863 2864 /* set the pointer to the MQD */ 2865 mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc; 2866 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 2867 2868 /* set up mqd control */ 2869 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL); 2870 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0); 2871 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); 2872 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0); 2873 mqd->cp_gfx_mqd_control = tmp; 2874 2875 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */ 2876 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID); 2877 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0); 2878 mqd->cp_gfx_hqd_vmid = 0; 2879 2880 /* set up default queue priority level 2881 * 0x0 = low priority, 0x1 = high priority */ 2882 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY); 2883 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0); 2884 mqd->cp_gfx_hqd_queue_priority = tmp; 2885 2886 /* set up time quantum */ 2887 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM); 2888 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1); 2889 mqd->cp_gfx_hqd_quantum = tmp; 2890 2891 /* set up gfx hqd base. this is similar as CP_RB_BASE */ 2892 hqd_gpu_addr = ring->gpu_addr >> 8; 2893 mqd->cp_gfx_hqd_base = hqd_gpu_addr; 2894 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr); 2895 2896 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */ 2897 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 2898 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc; 2899 mqd->cp_gfx_hqd_rptr_addr_hi = 2900 upper_32_bits(wb_gpu_addr) & 0xffff; 2901 2902 /* set up rb_wptr_poll addr */ 2903 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 2904 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2905 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2906 2907 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */ 2908 rb_bufsz = order_base_2(ring->ring_size / 4) - 1; 2909 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL); 2910 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); 2911 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); 2912 #ifdef __BIG_ENDIAN 2913 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1); 2914 #endif 2915 mqd->cp_gfx_hqd_cntl = tmp; 2916 2917 /* set up cp_doorbell_control */ 2918 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL); 2919 if (ring->use_doorbell) { 2920 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2921 DOORBELL_OFFSET, ring->doorbell_index); 2922 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2923 DOORBELL_EN, 1); 2924 } else 2925 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, 2926 DOORBELL_EN, 0); 2927 mqd->cp_rb_doorbell_control = tmp; 2928 2929 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2930 ring->wptr = 0; 2931 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR); 2932 2933 /* active the queue */ 2934 mqd->cp_gfx_hqd_active = 1; 2935 2936 return 0; 2937 } 2938 2939 #ifdef BRING_UP_DEBUG 2940 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring) 2941 { 2942 struct amdgpu_device *adev = ring->adev; 2943 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2944 2945 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */ 2946 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr); 2947 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi); 2948 2949 /* set GFX_MQD_BASE */ 2950 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr); 2951 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); 2952 2953 /* set GFX_MQD_CONTROL */ 2954 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control); 2955 2956 /* set GFX_HQD_VMID to 0 */ 2957 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid); 2958 2959 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY, 2960 mqd->cp_gfx_hqd_queue_priority); 2961 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum); 2962 2963 /* set GFX_HQD_BASE, similar as CP_RB_BASE */ 2964 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base); 2965 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi); 2966 2967 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */ 2968 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr); 2969 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi); 2970 2971 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */ 2972 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl); 2973 2974 /* set RB_WPTR_POLL_ADDR */ 2975 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo); 2976 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi); 2977 2978 /* set RB_DOORBELL_CONTROL */ 2979 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control); 2980 2981 /* active the queue */ 2982 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active); 2983 2984 return 0; 2985 } 2986 #endif 2987 2988 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) 2989 { 2990 struct amdgpu_device *adev = ring->adev; 2991 struct v10_gfx_mqd *mqd = ring->mqd_ptr; 2992 2993 if (!adev->in_gpu_reset && !adev->in_suspend) { 2994 memset((void *)mqd, 0, sizeof(*mqd)); 2995 mutex_lock(&adev->srbm_mutex); 2996 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 2997 gfx_v10_0_gfx_mqd_init(ring); 2998 #ifdef BRING_UP_DEBUG 2999 gfx_v10_0_gfx_queue_init_register(ring); 3000 #endif 3001 nv_grbm_select(adev, 0, 0, 0, 0); 3002 mutex_unlock(&adev->srbm_mutex); 3003 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 3004 memcpy(adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], mqd, sizeof(*mqd)); 3005 } else if (adev->in_gpu_reset) { 3006 /* reset mqd with the backup copy */ 3007 if (adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS]) 3008 memcpy(mqd, adev->gfx.me.mqd_backup[AMDGPU_MAX_GFX_RINGS], sizeof(*mqd)); 3009 /* reset the ring */ 3010 ring->wptr = 0; 3011 amdgpu_ring_clear_ring(ring); 3012 #ifdef BRING_UP_DEBUG 3013 mutex_lock(&adev->srbm_mutex); 3014 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3015 gfx_v10_0_gfx_queue_init_register(ring); 3016 nv_grbm_select(adev, 0, 0, 0, 0); 3017 mutex_unlock(&adev->srbm_mutex); 3018 #endif 3019 } else { 3020 amdgpu_ring_clear_ring(ring); 3021 } 3022 3023 return 0; 3024 } 3025 3026 #ifndef BRING_UP_DEBUG 3027 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev) 3028 { 3029 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3030 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 3031 int r, i; 3032 3033 if (!kiq->pmf || !kiq->pmf->kiq_map_queues) 3034 return -EINVAL; 3035 3036 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size * 3037 adev->gfx.num_gfx_rings); 3038 if (r) { 3039 DRM_ERROR("Failed to lock KIQ (%d).\n", r); 3040 return r; 3041 } 3042 3043 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3044 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]); 3045 3046 r = amdgpu_ring_test_ring(kiq_ring); 3047 if (r) { 3048 DRM_ERROR("kfq enable failed\n"); 3049 kiq_ring->sched.ready = false; 3050 } 3051 return r; 3052 } 3053 #endif 3054 3055 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) 3056 { 3057 int r, i; 3058 struct amdgpu_ring *ring; 3059 3060 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3061 ring = &adev->gfx.gfx_ring[i]; 3062 3063 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3064 if (unlikely(r != 0)) 3065 goto done; 3066 3067 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3068 if (!r) { 3069 r = gfx_v10_0_gfx_init_queue(ring); 3070 amdgpu_bo_kunmap(ring->mqd_obj); 3071 ring->mqd_ptr = NULL; 3072 } 3073 amdgpu_bo_unreserve(ring->mqd_obj); 3074 if (r) 3075 goto done; 3076 } 3077 #ifndef BRING_UP_DEBUG 3078 r = gfx_v10_0_kiq_enable_kgq(adev); 3079 if (r) 3080 goto done; 3081 #endif 3082 r = gfx_v10_0_cp_gfx_start(adev); 3083 if (r) 3084 goto done; 3085 3086 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3087 ring = &adev->gfx.gfx_ring[i]; 3088 ring->sched.ready = true; 3089 } 3090 done: 3091 return r; 3092 } 3093 3094 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring) 3095 { 3096 struct amdgpu_device *adev = ring->adev; 3097 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3098 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 3099 uint32_t tmp; 3100 3101 mqd->header = 0xC0310800; 3102 mqd->compute_pipelinestat_enable = 0x00000001; 3103 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 3104 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 3105 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 3106 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 3107 mqd->compute_misc_reserved = 0x00000003; 3108 3109 eop_base_addr = ring->eop_gpu_addr >> 8; 3110 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 3111 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 3112 3113 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3114 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL); 3115 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 3116 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1)); 3117 3118 mqd->cp_hqd_eop_control = tmp; 3119 3120 /* enable doorbell? */ 3121 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3122 3123 if (ring->use_doorbell) { 3124 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3125 DOORBELL_OFFSET, ring->doorbell_index); 3126 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3127 DOORBELL_EN, 1); 3128 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3129 DOORBELL_SOURCE, 0); 3130 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3131 DOORBELL_HIT, 0); 3132 } else { 3133 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3134 DOORBELL_EN, 0); 3135 } 3136 3137 mqd->cp_hqd_pq_doorbell_control = tmp; 3138 3139 /* disable the queue if it's active */ 3140 ring->wptr = 0; 3141 mqd->cp_hqd_dequeue_request = 0; 3142 mqd->cp_hqd_pq_rptr = 0; 3143 mqd->cp_hqd_pq_wptr_lo = 0; 3144 mqd->cp_hqd_pq_wptr_hi = 0; 3145 3146 /* set the pointer to the MQD */ 3147 mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc; 3148 mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr); 3149 3150 /* set MQD vmid to 0 */ 3151 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL); 3152 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 3153 mqd->cp_mqd_control = tmp; 3154 3155 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3156 hqd_gpu_addr = ring->gpu_addr >> 8; 3157 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 3158 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 3159 3160 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3161 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL); 3162 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 3163 (order_base_2(ring->ring_size / 4) - 1)); 3164 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 3165 ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8)); 3166 #ifdef __BIG_ENDIAN 3167 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); 3168 #endif 3169 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 3170 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 3171 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 3172 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 3173 mqd->cp_hqd_pq_control = tmp; 3174 3175 /* set the wb address whether it's enabled or not */ 3176 wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4); 3177 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 3178 mqd->cp_hqd_pq_rptr_report_addr_hi = 3179 upper_32_bits(wb_gpu_addr) & 0xffff; 3180 3181 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3182 wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); 3183 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 3184 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 3185 3186 tmp = 0; 3187 /* enable the doorbell if requested */ 3188 if (ring->use_doorbell) { 3189 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL); 3190 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3191 DOORBELL_OFFSET, ring->doorbell_index); 3192 3193 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3194 DOORBELL_EN, 1); 3195 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3196 DOORBELL_SOURCE, 0); 3197 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 3198 DOORBELL_HIT, 0); 3199 } 3200 3201 mqd->cp_hqd_pq_doorbell_control = tmp; 3202 3203 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3204 ring->wptr = 0; 3205 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR); 3206 3207 /* set the vmid for the queue */ 3208 mqd->cp_hqd_vmid = 0; 3209 3210 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE); 3211 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53); 3212 mqd->cp_hqd_persistent_state = tmp; 3213 3214 /* set MIN_IB_AVAIL_SIZE */ 3215 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL); 3216 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); 3217 mqd->cp_hqd_ib_control = tmp; 3218 3219 /* activate the queue */ 3220 mqd->cp_hqd_active = 1; 3221 3222 return 0; 3223 } 3224 3225 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring) 3226 { 3227 struct amdgpu_device *adev = ring->adev; 3228 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3229 int j; 3230 3231 /* disable wptr polling */ 3232 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0); 3233 3234 /* write the EOP addr */ 3235 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR, 3236 mqd->cp_hqd_eop_base_addr_lo); 3237 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI, 3238 mqd->cp_hqd_eop_base_addr_hi); 3239 3240 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 3241 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL, 3242 mqd->cp_hqd_eop_control); 3243 3244 /* enable doorbell? */ 3245 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3246 mqd->cp_hqd_pq_doorbell_control); 3247 3248 /* disable the queue if it's active */ 3249 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { 3250 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1); 3251 for (j = 0; j < adev->usec_timeout; j++) { 3252 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) 3253 break; 3254 udelay(1); 3255 } 3256 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 3257 mqd->cp_hqd_dequeue_request); 3258 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 3259 mqd->cp_hqd_pq_rptr); 3260 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3261 mqd->cp_hqd_pq_wptr_lo); 3262 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3263 mqd->cp_hqd_pq_wptr_hi); 3264 } 3265 3266 /* set the pointer to the MQD */ 3267 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, 3268 mqd->cp_mqd_base_addr_lo); 3269 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, 3270 mqd->cp_mqd_base_addr_hi); 3271 3272 /* set MQD vmid to 0 */ 3273 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL, 3274 mqd->cp_mqd_control); 3275 3276 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 3277 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE, 3278 mqd->cp_hqd_pq_base_lo); 3279 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI, 3280 mqd->cp_hqd_pq_base_hi); 3281 3282 /* set up the HQD, this is similar to CP_RB0_CNTL */ 3283 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL, 3284 mqd->cp_hqd_pq_control); 3285 3286 /* set the wb address whether it's enabled or not */ 3287 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR, 3288 mqd->cp_hqd_pq_rptr_report_addr_lo); 3289 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI, 3290 mqd->cp_hqd_pq_rptr_report_addr_hi); 3291 3292 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 3293 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 3294 mqd->cp_hqd_pq_wptr_poll_addr_lo); 3295 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 3296 mqd->cp_hqd_pq_wptr_poll_addr_hi); 3297 3298 /* enable the doorbell if requested */ 3299 if (ring->use_doorbell) { 3300 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER, 3301 (adev->doorbell_index.kiq * 2) << 2); 3302 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER, 3303 (adev->doorbell_index.userqueue_end * 2) << 2); 3304 } 3305 3306 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 3307 mqd->cp_hqd_pq_doorbell_control); 3308 3309 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 3310 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 3311 mqd->cp_hqd_pq_wptr_lo); 3312 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 3313 mqd->cp_hqd_pq_wptr_hi); 3314 3315 /* set the vmid for the queue */ 3316 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid); 3317 3318 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 3319 mqd->cp_hqd_persistent_state); 3320 3321 /* activate the queue */ 3322 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 3323 mqd->cp_hqd_active); 3324 3325 if (ring->use_doorbell) 3326 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1); 3327 3328 return 0; 3329 } 3330 3331 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) 3332 { 3333 struct amdgpu_device *adev = ring->adev; 3334 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3335 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS; 3336 3337 gfx_v10_0_kiq_setting(ring); 3338 3339 if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3340 /* reset MQD to a clean status */ 3341 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3342 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3343 3344 /* reset ring buffer */ 3345 ring->wptr = 0; 3346 amdgpu_ring_clear_ring(ring); 3347 3348 mutex_lock(&adev->srbm_mutex); 3349 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3350 gfx_v10_0_kiq_init_register(ring); 3351 nv_grbm_select(adev, 0, 0, 0, 0); 3352 mutex_unlock(&adev->srbm_mutex); 3353 } else { 3354 memset((void *)mqd, 0, sizeof(*mqd)); 3355 mutex_lock(&adev->srbm_mutex); 3356 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3357 gfx_v10_0_compute_mqd_init(ring); 3358 gfx_v10_0_kiq_init_register(ring); 3359 nv_grbm_select(adev, 0, 0, 0, 0); 3360 mutex_unlock(&adev->srbm_mutex); 3361 3362 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3363 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3364 } 3365 3366 return 0; 3367 } 3368 3369 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) 3370 { 3371 struct amdgpu_device *adev = ring->adev; 3372 struct v10_compute_mqd *mqd = ring->mqd_ptr; 3373 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 3374 3375 if (!adev->in_gpu_reset && !adev->in_suspend) { 3376 memset((void *)mqd, 0, sizeof(*mqd)); 3377 mutex_lock(&adev->srbm_mutex); 3378 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); 3379 gfx_v10_0_compute_mqd_init(ring); 3380 nv_grbm_select(adev, 0, 0, 0, 0); 3381 mutex_unlock(&adev->srbm_mutex); 3382 3383 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3384 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 3385 } else if (adev->in_gpu_reset) { /* for GPU_RESET case */ 3386 /* reset MQD to a clean status */ 3387 if (adev->gfx.mec.mqd_backup[mqd_idx]) 3388 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 3389 3390 /* reset ring buffer */ 3391 ring->wptr = 0; 3392 amdgpu_ring_clear_ring(ring); 3393 } else { 3394 amdgpu_ring_clear_ring(ring); 3395 } 3396 3397 return 0; 3398 } 3399 3400 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev) 3401 { 3402 struct amdgpu_ring *ring; 3403 int r; 3404 3405 ring = &adev->gfx.kiq.ring; 3406 3407 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3408 if (unlikely(r != 0)) 3409 return r; 3410 3411 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3412 if (unlikely(r != 0)) 3413 return r; 3414 3415 gfx_v10_0_kiq_init_queue(ring); 3416 amdgpu_bo_kunmap(ring->mqd_obj); 3417 ring->mqd_ptr = NULL; 3418 amdgpu_bo_unreserve(ring->mqd_obj); 3419 ring->sched.ready = true; 3420 return 0; 3421 } 3422 3423 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) 3424 { 3425 struct amdgpu_ring *ring = NULL; 3426 int r = 0, i; 3427 3428 gfx_v10_0_cp_compute_enable(adev, true); 3429 3430 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3431 ring = &adev->gfx.compute_ring[i]; 3432 3433 r = amdgpu_bo_reserve(ring->mqd_obj, false); 3434 if (unlikely(r != 0)) 3435 goto done; 3436 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 3437 if (!r) { 3438 r = gfx_v10_0_kcq_init_queue(ring); 3439 amdgpu_bo_kunmap(ring->mqd_obj); 3440 ring->mqd_ptr = NULL; 3441 } 3442 amdgpu_bo_unreserve(ring->mqd_obj); 3443 if (r) 3444 goto done; 3445 } 3446 3447 r = amdgpu_gfx_enable_kcq(adev); 3448 done: 3449 return r; 3450 } 3451 3452 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev) 3453 { 3454 int r, i; 3455 struct amdgpu_ring *ring; 3456 3457 if (!(adev->flags & AMD_IS_APU)) 3458 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3459 3460 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3461 /* legacy firmware loading */ 3462 r = gfx_v10_0_cp_gfx_load_microcode(adev); 3463 if (r) 3464 return r; 3465 3466 r = gfx_v10_0_cp_compute_load_microcode(adev); 3467 if (r) 3468 return r; 3469 } 3470 3471 r = gfx_v10_0_kiq_resume(adev); 3472 if (r) 3473 return r; 3474 3475 r = gfx_v10_0_kcq_resume(adev); 3476 if (r) 3477 return r; 3478 3479 if (!amdgpu_async_gfx_ring) { 3480 r = gfx_v10_0_cp_gfx_resume(adev); 3481 if (r) 3482 return r; 3483 } else { 3484 r = gfx_v10_0_cp_async_gfx_ring_resume(adev); 3485 if (r) 3486 return r; 3487 } 3488 3489 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 3490 ring = &adev->gfx.gfx_ring[i]; 3491 DRM_INFO("gfx %d ring me %d pipe %d q %d\n", 3492 i, ring->me, ring->pipe, ring->queue); 3493 r = amdgpu_ring_test_ring(ring); 3494 if (r) { 3495 ring->sched.ready = false; 3496 return r; 3497 } 3498 } 3499 3500 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3501 ring = &adev->gfx.compute_ring[i]; 3502 ring->sched.ready = true; 3503 DRM_INFO("compute ring %d mec %d pipe %d q %d\n", 3504 i, ring->me, ring->pipe, ring->queue); 3505 r = amdgpu_ring_test_ring(ring); 3506 if (r) 3507 ring->sched.ready = false; 3508 } 3509 3510 return 0; 3511 } 3512 3513 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable) 3514 { 3515 gfx_v10_0_cp_gfx_enable(adev, enable); 3516 gfx_v10_0_cp_compute_enable(adev, enable); 3517 } 3518 3519 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev) 3520 { 3521 uint32_t data, pattern = 0xDEADBEEF; 3522 3523 /* check if mmVGT_ESGS_RING_SIZE_UMD 3524 * has been remapped to mmVGT_ESGS_RING_SIZE */ 3525 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE); 3526 3527 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0); 3528 3529 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern); 3530 3531 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) { 3532 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data); 3533 return true; 3534 } else { 3535 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data); 3536 return false; 3537 } 3538 } 3539 3540 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev) 3541 { 3542 uint32_t data; 3543 3544 /* initialize cam_index to 0 3545 * index will auto-inc after each data writting */ 3546 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0); 3547 3548 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */ 3549 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) << 3550 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3551 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) << 3552 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3553 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3554 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3555 3556 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */ 3557 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) << 3558 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3559 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) << 3560 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3561 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3562 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3563 3564 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */ 3565 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) << 3566 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3567 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) << 3568 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3569 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3570 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3571 3572 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */ 3573 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) << 3574 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3575 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) << 3576 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3577 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3578 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3579 3580 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */ 3581 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) << 3582 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3583 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) << 3584 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3585 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3586 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3587 3588 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */ 3589 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) << 3590 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3591 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) << 3592 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3593 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3594 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3595 3596 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */ 3597 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) << 3598 GRBM_CAM_DATA__CAM_ADDR__SHIFT) | 3599 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) << 3600 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT); 3601 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0); 3602 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data); 3603 } 3604 3605 static int gfx_v10_0_hw_init(void *handle) 3606 { 3607 int r; 3608 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3609 3610 r = gfx_v10_0_csb_vram_pin(adev); 3611 if (r) 3612 return r; 3613 3614 if (!amdgpu_emu_mode) 3615 gfx_v10_0_init_golden_registers(adev); 3616 3617 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 3618 /** 3619 * For gfx 10, rlc firmware loading relies on smu firmware is 3620 * loaded firstly, so in direct type, it has to load smc ucode 3621 * here before rlc. 3622 */ 3623 r = smu_load_microcode(&adev->smu); 3624 if (r) 3625 return r; 3626 3627 r = smu_check_fw_status(&adev->smu); 3628 if (r) { 3629 pr_err("SMC firmware status is not correct\n"); 3630 return r; 3631 } 3632 } 3633 3634 /* if GRBM CAM not remapped, set up the remapping */ 3635 if (!gfx_v10_0_check_grbm_cam_remapping(adev)) 3636 gfx_v10_0_setup_grbm_cam_remapping(adev); 3637 3638 gfx_v10_0_constants_init(adev); 3639 3640 r = gfx_v10_0_rlc_resume(adev); 3641 if (r) 3642 return r; 3643 3644 /* 3645 * init golden registers and rlc resume may override some registers, 3646 * reconfig them here 3647 */ 3648 gfx_v10_0_tcp_harvest(adev); 3649 3650 r = gfx_v10_0_cp_resume(adev); 3651 if (r) 3652 return r; 3653 3654 return r; 3655 } 3656 3657 #ifndef BRING_UP_DEBUG 3658 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev) 3659 { 3660 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 3661 struct amdgpu_ring *kiq_ring = &kiq->ring; 3662 int i; 3663 3664 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 3665 return -EINVAL; 3666 3667 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size * 3668 adev->gfx.num_gfx_rings)) 3669 return -ENOMEM; 3670 3671 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 3672 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i], 3673 PREEMPT_QUEUES, 0, 0); 3674 3675 return amdgpu_ring_test_ring(kiq_ring); 3676 } 3677 #endif 3678 3679 static int gfx_v10_0_hw_fini(void *handle) 3680 { 3681 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3682 int r; 3683 3684 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 3685 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 3686 #ifndef BRING_UP_DEBUG 3687 if (amdgpu_async_gfx_ring) { 3688 r = gfx_v10_0_kiq_disable_kgq(adev); 3689 if (r) 3690 DRM_ERROR("KGQ disable failed\n"); 3691 } 3692 #endif 3693 if (amdgpu_gfx_disable_kcq(adev)) 3694 DRM_ERROR("KCQ disable failed\n"); 3695 if (amdgpu_sriov_vf(adev)) { 3696 pr_debug("For SRIOV client, shouldn't do anything.\n"); 3697 return 0; 3698 } 3699 gfx_v10_0_cp_enable(adev, false); 3700 gfx_v10_0_enable_gui_idle_interrupt(adev, false); 3701 gfx_v10_0_csb_vram_unpin(adev); 3702 3703 return 0; 3704 } 3705 3706 static int gfx_v10_0_suspend(void *handle) 3707 { 3708 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3709 3710 adev->in_suspend = true; 3711 return gfx_v10_0_hw_fini(adev); 3712 } 3713 3714 static int gfx_v10_0_resume(void *handle) 3715 { 3716 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3717 int r; 3718 3719 r = gfx_v10_0_hw_init(adev); 3720 adev->in_suspend = false; 3721 return r; 3722 } 3723 3724 static bool gfx_v10_0_is_idle(void *handle) 3725 { 3726 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3727 3728 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS), 3729 GRBM_STATUS, GUI_ACTIVE)) 3730 return false; 3731 else 3732 return true; 3733 } 3734 3735 static int gfx_v10_0_wait_for_idle(void *handle) 3736 { 3737 unsigned i; 3738 u32 tmp; 3739 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3740 3741 for (i = 0; i < adev->usec_timeout; i++) { 3742 /* read MC_STATUS */ 3743 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) & 3744 GRBM_STATUS__GUI_ACTIVE_MASK; 3745 3746 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE)) 3747 return 0; 3748 udelay(1); 3749 } 3750 return -ETIMEDOUT; 3751 } 3752 3753 static int gfx_v10_0_soft_reset(void *handle) 3754 { 3755 u32 grbm_soft_reset = 0; 3756 u32 tmp; 3757 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3758 3759 /* GRBM_STATUS */ 3760 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); 3761 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 3762 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 3763 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK | 3764 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK | 3765 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK 3766 | GRBM_STATUS__BCI_BUSY_MASK)) { 3767 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3768 GRBM_SOFT_RESET, SOFT_RESET_CP, 3769 1); 3770 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3771 GRBM_SOFT_RESET, SOFT_RESET_GFX, 3772 1); 3773 } 3774 3775 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) { 3776 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3777 GRBM_SOFT_RESET, SOFT_RESET_CP, 3778 1); 3779 } 3780 3781 /* GRBM_STATUS2 */ 3782 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2); 3783 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY)) 3784 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, 3785 GRBM_SOFT_RESET, SOFT_RESET_RLC, 3786 1); 3787 3788 if (grbm_soft_reset) { 3789 /* stop the rlc */ 3790 gfx_v10_0_rlc_stop(adev); 3791 3792 /* Disable GFX parsing/prefetching */ 3793 gfx_v10_0_cp_gfx_enable(adev, false); 3794 3795 /* Disable MEC parsing/prefetching */ 3796 gfx_v10_0_cp_compute_enable(adev, false); 3797 3798 if (grbm_soft_reset) { 3799 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3800 tmp |= grbm_soft_reset; 3801 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 3802 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3803 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3804 3805 udelay(50); 3806 3807 tmp &= ~grbm_soft_reset; 3808 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp); 3809 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); 3810 } 3811 3812 /* Wait a little for things to settle down */ 3813 udelay(50); 3814 } 3815 return 0; 3816 } 3817 3818 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev) 3819 { 3820 uint64_t clock; 3821 3822 mutex_lock(&adev->gfx.gpu_clock_mutex); 3823 WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1); 3824 clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) | 3825 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL); 3826 mutex_unlock(&adev->gfx.gpu_clock_mutex); 3827 return clock; 3828 } 3829 3830 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, 3831 uint32_t vmid, 3832 uint32_t gds_base, uint32_t gds_size, 3833 uint32_t gws_base, uint32_t gws_size, 3834 uint32_t oa_base, uint32_t oa_size) 3835 { 3836 struct amdgpu_device *adev = ring->adev; 3837 3838 /* GDS Base */ 3839 gfx_v10_0_write_data_to_reg(ring, 0, false, 3840 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid, 3841 gds_base); 3842 3843 /* GDS Size */ 3844 gfx_v10_0_write_data_to_reg(ring, 0, false, 3845 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid, 3846 gds_size); 3847 3848 /* GWS */ 3849 gfx_v10_0_write_data_to_reg(ring, 0, false, 3850 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid, 3851 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base); 3852 3853 /* OA */ 3854 gfx_v10_0_write_data_to_reg(ring, 0, false, 3855 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid, 3856 (1 << (oa_size + oa_base)) - (1 << oa_base)); 3857 } 3858 3859 static int gfx_v10_0_early_init(void *handle) 3860 { 3861 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3862 3863 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS; 3864 adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS; 3865 3866 gfx_v10_0_set_kiq_pm4_funcs(adev); 3867 gfx_v10_0_set_ring_funcs(adev); 3868 gfx_v10_0_set_irq_funcs(adev); 3869 gfx_v10_0_set_gds_init(adev); 3870 gfx_v10_0_set_rlc_funcs(adev); 3871 3872 return 0; 3873 } 3874 3875 static int gfx_v10_0_late_init(void *handle) 3876 { 3877 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3878 int r; 3879 3880 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 3881 if (r) 3882 return r; 3883 3884 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 3885 if (r) 3886 return r; 3887 3888 return 0; 3889 } 3890 3891 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev) 3892 { 3893 uint32_t rlc_cntl; 3894 3895 /* if RLC is not enabled, do nothing */ 3896 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL); 3897 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 3898 } 3899 3900 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev) 3901 { 3902 uint32_t data; 3903 unsigned i; 3904 3905 data = RLC_SAFE_MODE__CMD_MASK; 3906 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 3907 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3908 3909 /* wait for RLC_SAFE_MODE */ 3910 for (i = 0; i < adev->usec_timeout; i++) { 3911 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 3912 break; 3913 udelay(1); 3914 } 3915 } 3916 3917 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev) 3918 { 3919 uint32_t data; 3920 3921 data = RLC_SAFE_MODE__CMD_MASK; 3922 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data); 3923 } 3924 3925 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev, 3926 bool enable) 3927 { 3928 uint32_t data, def; 3929 3930 /* It is disabled by HW by default */ 3931 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { 3932 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3933 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3934 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3935 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3936 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3937 3938 /* only for Vega10 & Raven1 */ 3939 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK; 3940 3941 if (def != data) 3942 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3943 3944 /* MGLS is a global flag to control all MGLS in GFX */ 3945 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) { 3946 /* 2 - RLC memory Light sleep */ 3947 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { 3948 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3949 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3950 if (def != data) 3951 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3952 } 3953 /* 3 - CP memory Light sleep */ 3954 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { 3955 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3956 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3957 if (def != data) 3958 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3959 } 3960 } 3961 } else { 3962 /* 1 - MGCG_OVERRIDE */ 3963 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3964 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3965 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3966 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK | 3967 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK); 3968 if (def != data) 3969 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 3970 3971 /* 2 - disable MGLS in RLC */ 3972 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 3973 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) { 3974 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK; 3975 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data); 3976 } 3977 3978 /* 3 - disable MGLS in CP */ 3979 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 3980 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) { 3981 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK; 3982 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); 3983 } 3984 } 3985 } 3986 3987 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, 3988 bool enable) 3989 { 3990 uint32_t data, def; 3991 3992 /* Enable 3D CGCG/CGLS */ 3993 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { 3994 /* write cmd to clear cgcg/cgls ov */ 3995 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 3996 /* unset CGCG override */ 3997 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3998 /* update CGCG and CGLS override bits */ 3999 if (def != data) 4000 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4001 /* enable 3Dcgcg FSM(0x0000363f) */ 4002 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4003 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4004 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; 4005 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 4006 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4007 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; 4008 if (def != data) 4009 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4010 4011 /* set IDLE_POLL_COUNT(0x00900100) */ 4012 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4013 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4014 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4015 if (def != data) 4016 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4017 } else { 4018 /* Disable CGCG/CGLS */ 4019 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4020 /* disable cgcg, cgls should be disabled */ 4021 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK | 4022 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK); 4023 /* disable cgcg and cgls in FSM */ 4024 if (def != data) 4025 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data); 4026 } 4027 } 4028 4029 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 4030 bool enable) 4031 { 4032 uint32_t def, data; 4033 4034 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { 4035 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4036 /* unset CGCG override */ 4037 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 4038 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4039 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4040 else 4041 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 4042 /* update CGCG and CGLS override bits */ 4043 if (def != data) 4044 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data); 4045 4046 /* enable cgcg FSM(0x0000363F) */ 4047 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4048 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 4049 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 4050 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 4051 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 4052 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 4053 if (def != data) 4054 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4055 4056 /* set IDLE_POLL_COUNT(0x00900100) */ 4057 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); 4058 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 4059 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 4060 if (def != data) 4061 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); 4062 } else { 4063 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4064 /* reset CGCG/CGLS bits */ 4065 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); 4066 /* disable cgcg and cgls in FSM */ 4067 if (def != data) 4068 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); 4069 } 4070 } 4071 4072 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 4073 bool enable) 4074 { 4075 amdgpu_gfx_rlc_enter_safe_mode(adev); 4076 4077 if (enable) { 4078 /* CGCG/CGLS should be enabled after MGCG/MGLS 4079 * === MGCG + MGLS === 4080 */ 4081 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4082 /* === CGCG /CGLS for GFX 3D Only === */ 4083 gfx_v10_0_update_3d_clock_gating(adev, enable); 4084 /* === CGCG + CGLS === */ 4085 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4086 } else { 4087 /* CGCG/CGLS should be disabled before MGCG/MGLS 4088 * === CGCG + CGLS === 4089 */ 4090 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable); 4091 /* === CGCG /CGLS for GFX 3D Only === */ 4092 gfx_v10_0_update_3d_clock_gating(adev, enable); 4093 /* === MGCG + MGLS === */ 4094 gfx_v10_0_update_medium_grain_clock_gating(adev, enable); 4095 } 4096 4097 if (adev->cg_flags & 4098 (AMD_CG_SUPPORT_GFX_MGCG | 4099 AMD_CG_SUPPORT_GFX_CGLS | 4100 AMD_CG_SUPPORT_GFX_CGCG | 4101 AMD_CG_SUPPORT_GFX_CGLS | 4102 AMD_CG_SUPPORT_GFX_3D_CGCG | 4103 AMD_CG_SUPPORT_GFX_3D_CGLS)) 4104 gfx_v10_0_enable_gui_idle_interrupt(adev, enable); 4105 4106 amdgpu_gfx_rlc_exit_safe_mode(adev); 4107 4108 return 0; 4109 } 4110 4111 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = { 4112 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled, 4113 .set_safe_mode = gfx_v10_0_set_safe_mode, 4114 .unset_safe_mode = gfx_v10_0_unset_safe_mode, 4115 .init = gfx_v10_0_rlc_init, 4116 .get_csb_size = gfx_v10_0_get_csb_size, 4117 .get_csb_buffer = gfx_v10_0_get_csb_buffer, 4118 .resume = gfx_v10_0_rlc_resume, 4119 .stop = gfx_v10_0_rlc_stop, 4120 .reset = gfx_v10_0_rlc_reset, 4121 .start = gfx_v10_0_rlc_start 4122 }; 4123 4124 static int gfx_v10_0_set_powergating_state(void *handle, 4125 enum amd_powergating_state state) 4126 { 4127 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4128 bool enable = (state == AMD_PG_STATE_GATE) ? true : false; 4129 switch (adev->asic_type) { 4130 case CHIP_NAVI10: 4131 case CHIP_NAVI14: 4132 if (!enable) { 4133 amdgpu_gfx_off_ctrl(adev, false); 4134 cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); 4135 } else 4136 amdgpu_gfx_off_ctrl(adev, true); 4137 break; 4138 default: 4139 break; 4140 } 4141 return 0; 4142 } 4143 4144 static int gfx_v10_0_set_clockgating_state(void *handle, 4145 enum amd_clockgating_state state) 4146 { 4147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4148 4149 switch (adev->asic_type) { 4150 case CHIP_NAVI10: 4151 case CHIP_NAVI14: 4152 gfx_v10_0_update_gfx_clock_gating(adev, 4153 state == AMD_CG_STATE_GATE ? true : false); 4154 break; 4155 default: 4156 break; 4157 } 4158 return 0; 4159 } 4160 4161 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags) 4162 { 4163 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 4164 int data; 4165 4166 /* AMD_CG_SUPPORT_GFX_MGCG */ 4167 data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); 4168 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 4169 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 4170 4171 /* AMD_CG_SUPPORT_GFX_CGCG */ 4172 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); 4173 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 4174 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 4175 4176 /* AMD_CG_SUPPORT_GFX_CGLS */ 4177 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 4178 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 4179 4180 /* AMD_CG_SUPPORT_GFX_RLC_LS */ 4181 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL); 4182 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) 4183 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS; 4184 4185 /* AMD_CG_SUPPORT_GFX_CP_LS */ 4186 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); 4187 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) 4188 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS; 4189 4190 /* AMD_CG_SUPPORT_GFX_3D_CGCG */ 4191 data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D); 4192 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK) 4193 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG; 4194 4195 /* AMD_CG_SUPPORT_GFX_3D_CGLS */ 4196 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK) 4197 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS; 4198 } 4199 4200 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring) 4201 { 4202 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/ 4203 } 4204 4205 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 4206 { 4207 struct amdgpu_device *adev = ring->adev; 4208 u64 wptr; 4209 4210 /* XXX check if swapping is necessary on BE */ 4211 if (ring->use_doorbell) { 4212 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); 4213 } else { 4214 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); 4215 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; 4216 } 4217 4218 return wptr; 4219 } 4220 4221 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring) 4222 { 4223 struct amdgpu_device *adev = ring->adev; 4224 4225 if (ring->use_doorbell) { 4226 /* XXX check if swapping is necessary on BE */ 4227 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4228 WDOORBELL64(ring->doorbell_index, ring->wptr); 4229 } else { 4230 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); 4231 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); 4232 } 4233 } 4234 4235 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring) 4236 { 4237 return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */ 4238 } 4239 4240 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 4241 { 4242 u64 wptr; 4243 4244 /* XXX check if swapping is necessary on BE */ 4245 if (ring->use_doorbell) 4246 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); 4247 else 4248 BUG(); 4249 return wptr; 4250 } 4251 4252 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring) 4253 { 4254 struct amdgpu_device *adev = ring->adev; 4255 4256 /* XXX check if swapping is necessary on BE */ 4257 if (ring->use_doorbell) { 4258 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); 4259 WDOORBELL64(ring->doorbell_index, ring->wptr); 4260 } else { 4261 BUG(); /* only DOORBELL method supported on gfx10 now */ 4262 } 4263 } 4264 4265 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) 4266 { 4267 struct amdgpu_device *adev = ring->adev; 4268 u32 ref_and_mask, reg_mem_engine; 4269 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg; 4270 4271 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { 4272 switch (ring->me) { 4273 case 1: 4274 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; 4275 break; 4276 case 2: 4277 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; 4278 break; 4279 default: 4280 return; 4281 } 4282 reg_mem_engine = 0; 4283 } else { 4284 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; 4285 reg_mem_engine = 1; /* pfp */ 4286 } 4287 4288 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1, 4289 adev->nbio_funcs->get_hdp_flush_req_offset(adev), 4290 adev->nbio_funcs->get_hdp_flush_done_offset(adev), 4291 ref_and_mask, ref_and_mask, 0x20); 4292 } 4293 4294 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring, 4295 struct amdgpu_job *job, 4296 struct amdgpu_ib *ib, 4297 uint32_t flags) 4298 { 4299 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4300 u32 header, control = 0; 4301 4302 /* Prevent a hw deadlock due to a wave ID mismatch between ME and GDS. 4303 * This resets the wave ID counters. (needed by transform feedback) 4304 * TODO: This might only be needed on a VMID switch when we change 4305 * the GDS OA mapping, not sure. 4306 */ 4307 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4308 amdgpu_ring_write(ring, mmVGT_GS_MAX_WAVE_ID); 4309 amdgpu_ring_write(ring, ring->adev->gds.vgt_gs_max_wave_id); 4310 4311 if (ib->flags & AMDGPU_IB_FLAG_CE) 4312 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); 4313 else 4314 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); 4315 4316 control |= ib->length_dw | (vmid << 24); 4317 4318 if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) { 4319 control |= INDIRECT_BUFFER_PRE_ENB(1); 4320 4321 if (flags & AMDGPU_IB_PREEMPTED) 4322 control |= INDIRECT_BUFFER_PRE_RESUME(1); 4323 4324 if (!(ib->flags & AMDGPU_IB_FLAG_CE)) 4325 gfx_v10_0_ring_emit_de_meta(ring, 4326 flags & AMDGPU_IB_PREEMPTED ? true : false); 4327 } 4328 4329 amdgpu_ring_write(ring, header); 4330 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4331 amdgpu_ring_write(ring, 4332 #ifdef __BIG_ENDIAN 4333 (2 << 0) | 4334 #endif 4335 lower_32_bits(ib->gpu_addr)); 4336 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4337 amdgpu_ring_write(ring, control); 4338 } 4339 4340 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring, 4341 struct amdgpu_job *job, 4342 struct amdgpu_ib *ib, 4343 uint32_t flags) 4344 { 4345 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 4346 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24); 4347 4348 /* Currently, there is a high possibility to get wave ID mismatch 4349 * between ME and GDS, leading to a hw deadlock, because ME generates 4350 * different wave IDs than the GDS expects. This situation happens 4351 * randomly when at least 5 compute pipes use GDS ordered append. 4352 * The wave IDs generated by ME are also wrong after suspend/resume. 4353 * Those are probably bugs somewhere else in the kernel driver. 4354 * 4355 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 4356 * GDS to 0 for this ring (me/pipe). 4357 */ 4358 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 4359 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 4360 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID); 4361 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id); 4362 } 4363 4364 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 4365 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */ 4366 amdgpu_ring_write(ring, 4367 #ifdef __BIG_ENDIAN 4368 (2 << 0) | 4369 #endif 4370 lower_32_bits(ib->gpu_addr)); 4371 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 4372 amdgpu_ring_write(ring, control); 4373 } 4374 4375 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 4376 u64 seq, unsigned flags) 4377 { 4378 struct amdgpu_device *adev = ring->adev; 4379 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 4380 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 4381 4382 /* Interrupt not work fine on GFX10.1 model yet. Use fallback instead */ 4383 if (adev->pdev->device == 0x50) 4384 int_sel = false; 4385 4386 /* RELEASE_MEM - flush caches, send int */ 4387 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 4388 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | 4389 PACKET3_RELEASE_MEM_GCR_GL2_WB | 4390 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ 4391 PACKET3_RELEASE_MEM_GCR_GLM_WB | 4392 PACKET3_RELEASE_MEM_CACHE_POLICY(3) | 4393 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 4394 PACKET3_RELEASE_MEM_EVENT_INDEX(5))); 4395 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) | 4396 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0))); 4397 4398 /* 4399 * the address should be Qword aligned if 64bit write, Dword 4400 * aligned if only send 32bit data low (discard data high) 4401 */ 4402 if (write64bit) 4403 BUG_ON(addr & 0x7); 4404 else 4405 BUG_ON(addr & 0x3); 4406 amdgpu_ring_write(ring, lower_32_bits(addr)); 4407 amdgpu_ring_write(ring, upper_32_bits(addr)); 4408 amdgpu_ring_write(ring, lower_32_bits(seq)); 4409 amdgpu_ring_write(ring, upper_32_bits(seq)); 4410 amdgpu_ring_write(ring, 0); 4411 } 4412 4413 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 4414 { 4415 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); 4416 uint32_t seq = ring->fence_drv.sync_seq; 4417 uint64_t addr = ring->fence_drv.gpu_addr; 4418 4419 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr), 4420 upper_32_bits(addr), seq, 0xffffffff, 4); 4421 } 4422 4423 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring, 4424 unsigned vmid, uint64_t pd_addr) 4425 { 4426 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 4427 4428 /* compute doesn't have PFP */ 4429 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) { 4430 /* sync PFP to ME, otherwise we might get invalid PFP reads */ 4431 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); 4432 amdgpu_ring_write(ring, 0x0); 4433 } 4434 } 4435 4436 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr, 4437 u64 seq, unsigned int flags) 4438 { 4439 struct amdgpu_device *adev = ring->adev; 4440 4441 /* we only allocate 32bit for each seq wb address */ 4442 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT); 4443 4444 /* write fence seq to the "addr" */ 4445 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4446 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4447 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); 4448 amdgpu_ring_write(ring, lower_32_bits(addr)); 4449 amdgpu_ring_write(ring, upper_32_bits(addr)); 4450 amdgpu_ring_write(ring, lower_32_bits(seq)); 4451 4452 if (flags & AMDGPU_FENCE_FLAG_INT) { 4453 /* set register to trigger INT */ 4454 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4455 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) | 4456 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); 4457 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS)); 4458 amdgpu_ring_write(ring, 0); 4459 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */ 4460 } 4461 } 4462 4463 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring) 4464 { 4465 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); 4466 amdgpu_ring_write(ring, 0); 4467 } 4468 4469 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) 4470 { 4471 uint32_t dw2 = 0; 4472 4473 if (amdgpu_mcbp) 4474 gfx_v10_0_ring_emit_ce_meta(ring, 4475 flags & AMDGPU_IB_PREEMPTED ? true : false); 4476 4477 gfx_v10_0_ring_emit_tmz(ring, true); 4478 4479 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */ 4480 if (flags & AMDGPU_HAVE_CTX_SWITCH) { 4481 /* set load_global_config & load_global_uconfig */ 4482 dw2 |= 0x8001; 4483 /* set load_cs_sh_regs */ 4484 dw2 |= 0x01000000; 4485 /* set load_per_context_state & load_gfx_sh_regs for GFX */ 4486 dw2 |= 0x10002; 4487 4488 /* set load_ce_ram if preamble presented */ 4489 if (AMDGPU_PREAMBLE_IB_PRESENT & flags) 4490 dw2 |= 0x10000000; 4491 } else { 4492 /* still load_ce_ram if this is the first time preamble presented 4493 * although there is no context switch happens. 4494 */ 4495 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags) 4496 dw2 |= 0x10000000; 4497 } 4498 4499 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); 4500 amdgpu_ring_write(ring, dw2); 4501 amdgpu_ring_write(ring, 0); 4502 } 4503 4504 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring) 4505 { 4506 unsigned ret; 4507 4508 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); 4509 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); 4510 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); 4511 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */ 4512 ret = ring->wptr & ring->buf_mask; 4513 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */ 4514 4515 return ret; 4516 } 4517 4518 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset) 4519 { 4520 unsigned cur; 4521 BUG_ON(offset > ring->buf_mask); 4522 BUG_ON(ring->ring[offset] != 0x55aa55aa); 4523 4524 cur = (ring->wptr - 1) & ring->buf_mask; 4525 if (likely(cur > offset)) 4526 ring->ring[offset] = cur - offset; 4527 else 4528 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur; 4529 } 4530 4531 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring) 4532 { 4533 int i, r = 0; 4534 struct amdgpu_device *adev = ring->adev; 4535 struct amdgpu_kiq *kiq = &adev->gfx.kiq; 4536 struct amdgpu_ring *kiq_ring = &kiq->ring; 4537 4538 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 4539 return -EINVAL; 4540 4541 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) 4542 return -ENOMEM; 4543 4544 /* assert preemption condition */ 4545 amdgpu_ring_set_preempt_cond_exec(ring, false); 4546 4547 /* assert IB preemption, emit the trailing fence */ 4548 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP, 4549 ring->trail_fence_gpu_addr, 4550 ++ring->trail_seq); 4551 amdgpu_ring_commit(kiq_ring); 4552 4553 /* poll the trailing fence */ 4554 for (i = 0; i < adev->usec_timeout; i++) { 4555 if (ring->trail_seq == 4556 le32_to_cpu(*(ring->trail_fence_cpu_addr))) 4557 break; 4558 udelay(1); 4559 } 4560 4561 if (i >= adev->usec_timeout) { 4562 r = -EINVAL; 4563 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx); 4564 } 4565 4566 /* deassert preemption condition */ 4567 amdgpu_ring_set_preempt_cond_exec(ring, true); 4568 return r; 4569 } 4570 4571 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume) 4572 { 4573 struct amdgpu_device *adev = ring->adev; 4574 struct v10_ce_ib_state ce_payload = {0}; 4575 uint64_t csa_addr; 4576 int cnt; 4577 4578 cnt = (sizeof(ce_payload) >> 2) + 4 - 2; 4579 csa_addr = amdgpu_csa_vaddr(ring->adev); 4580 4581 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4582 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) | 4583 WRITE_DATA_DST_SEL(8) | 4584 WR_CONFIRM) | 4585 WRITE_DATA_CACHE_POLICY(0)); 4586 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4587 offsetof(struct v10_gfx_meta_data, ce_payload))); 4588 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4589 offsetof(struct v10_gfx_meta_data, ce_payload))); 4590 4591 if (resume) 4592 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4593 offsetof(struct v10_gfx_meta_data, 4594 ce_payload), 4595 sizeof(ce_payload) >> 2); 4596 else 4597 amdgpu_ring_write_multiple(ring, (void *)&ce_payload, 4598 sizeof(ce_payload) >> 2); 4599 } 4600 4601 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume) 4602 { 4603 struct amdgpu_device *adev = ring->adev; 4604 struct v10_de_ib_state de_payload = {0}; 4605 uint64_t csa_addr, gds_addr; 4606 int cnt; 4607 4608 csa_addr = amdgpu_csa_vaddr(ring->adev); 4609 gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size, 4610 PAGE_SIZE); 4611 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr); 4612 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr); 4613 4614 cnt = (sizeof(de_payload) >> 2) + 4 - 2; 4615 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt)); 4616 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) | 4617 WRITE_DATA_DST_SEL(8) | 4618 WR_CONFIRM) | 4619 WRITE_DATA_CACHE_POLICY(0)); 4620 amdgpu_ring_write(ring, lower_32_bits(csa_addr + 4621 offsetof(struct v10_gfx_meta_data, de_payload))); 4622 amdgpu_ring_write(ring, upper_32_bits(csa_addr + 4623 offsetof(struct v10_gfx_meta_data, de_payload))); 4624 4625 if (resume) 4626 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr + 4627 offsetof(struct v10_gfx_meta_data, 4628 de_payload), 4629 sizeof(de_payload) >> 2); 4630 else 4631 amdgpu_ring_write_multiple(ring, (void *)&de_payload, 4632 sizeof(de_payload) >> 2); 4633 } 4634 4635 static void gfx_v10_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start) 4636 { 4637 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0)); 4638 amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */ 4639 } 4640 4641 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg) 4642 { 4643 struct amdgpu_device *adev = ring->adev; 4644 4645 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); 4646 amdgpu_ring_write(ring, 0 | /* src: register*/ 4647 (5 << 8) | /* dst: memory */ 4648 (1 << 20)); /* write confirm */ 4649 amdgpu_ring_write(ring, reg); 4650 amdgpu_ring_write(ring, 0); 4651 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr + 4652 adev->virt.reg_val_offs * 4)); 4653 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr + 4654 adev->virt.reg_val_offs * 4)); 4655 } 4656 4657 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, 4658 uint32_t val) 4659 { 4660 uint32_t cmd = 0; 4661 4662 switch (ring->funcs->type) { 4663 case AMDGPU_RING_TYPE_GFX: 4664 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM; 4665 break; 4666 case AMDGPU_RING_TYPE_KIQ: 4667 cmd = (1 << 16); /* no inc addr */ 4668 break; 4669 default: 4670 cmd = WR_CONFIRM; 4671 break; 4672 } 4673 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 4674 amdgpu_ring_write(ring, cmd); 4675 amdgpu_ring_write(ring, reg); 4676 amdgpu_ring_write(ring, 0); 4677 amdgpu_ring_write(ring, val); 4678 } 4679 4680 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 4681 uint32_t val, uint32_t mask) 4682 { 4683 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 4684 } 4685 4686 static void 4687 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, 4688 uint32_t me, uint32_t pipe, 4689 enum amdgpu_interrupt_state state) 4690 { 4691 uint32_t cp_int_cntl, cp_int_cntl_reg; 4692 4693 if (!me) { 4694 switch (pipe) { 4695 case 0: 4696 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0); 4697 break; 4698 case 1: 4699 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1); 4700 break; 4701 default: 4702 DRM_DEBUG("invalid pipe %d\n", pipe); 4703 return; 4704 } 4705 } else { 4706 DRM_DEBUG("invalid me %d\n", me); 4707 return; 4708 } 4709 4710 switch (state) { 4711 case AMDGPU_IRQ_STATE_DISABLE: 4712 cp_int_cntl = RREG32(cp_int_cntl_reg); 4713 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4714 TIME_STAMP_INT_ENABLE, 0); 4715 WREG32(cp_int_cntl_reg, cp_int_cntl); 4716 case AMDGPU_IRQ_STATE_ENABLE: 4717 cp_int_cntl = RREG32(cp_int_cntl_reg); 4718 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 4719 TIME_STAMP_INT_ENABLE, 1); 4720 WREG32(cp_int_cntl_reg, cp_int_cntl); 4721 break; 4722 default: 4723 break; 4724 } 4725 } 4726 4727 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 4728 int me, int pipe, 4729 enum amdgpu_interrupt_state state) 4730 { 4731 u32 mec_int_cntl, mec_int_cntl_reg; 4732 4733 /* 4734 * amdgpu controls only the first MEC. That's why this function only 4735 * handles the setting of interrupts for this specific MEC. All other 4736 * pipes' interrupts are set by amdkfd. 4737 */ 4738 4739 if (me == 1) { 4740 switch (pipe) { 4741 case 0: 4742 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4743 break; 4744 case 1: 4745 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); 4746 break; 4747 case 2: 4748 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL); 4749 break; 4750 case 3: 4751 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL); 4752 break; 4753 default: 4754 DRM_DEBUG("invalid pipe %d\n", pipe); 4755 return; 4756 } 4757 } else { 4758 DRM_DEBUG("invalid me %d\n", me); 4759 return; 4760 } 4761 4762 switch (state) { 4763 case AMDGPU_IRQ_STATE_DISABLE: 4764 mec_int_cntl = RREG32(mec_int_cntl_reg); 4765 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4766 TIME_STAMP_INT_ENABLE, 0); 4767 WREG32(mec_int_cntl_reg, mec_int_cntl); 4768 break; 4769 case AMDGPU_IRQ_STATE_ENABLE: 4770 mec_int_cntl = RREG32(mec_int_cntl_reg); 4771 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 4772 TIME_STAMP_INT_ENABLE, 1); 4773 WREG32(mec_int_cntl_reg, mec_int_cntl); 4774 break; 4775 default: 4776 break; 4777 } 4778 } 4779 4780 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev, 4781 struct amdgpu_irq_src *src, 4782 unsigned type, 4783 enum amdgpu_interrupt_state state) 4784 { 4785 switch (type) { 4786 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP: 4787 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state); 4788 break; 4789 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP: 4790 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state); 4791 break; 4792 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 4793 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state); 4794 break; 4795 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 4796 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state); 4797 break; 4798 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 4799 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state); 4800 break; 4801 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 4802 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state); 4803 break; 4804 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP: 4805 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state); 4806 break; 4807 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP: 4808 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state); 4809 break; 4810 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP: 4811 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state); 4812 break; 4813 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP: 4814 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state); 4815 break; 4816 default: 4817 break; 4818 } 4819 return 0; 4820 } 4821 4822 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev, 4823 struct amdgpu_irq_src *source, 4824 struct amdgpu_iv_entry *entry) 4825 { 4826 int i; 4827 u8 me_id, pipe_id, queue_id; 4828 struct amdgpu_ring *ring; 4829 4830 DRM_DEBUG("IH: CP EOP\n"); 4831 me_id = (entry->ring_id & 0x0c) >> 2; 4832 pipe_id = (entry->ring_id & 0x03) >> 0; 4833 queue_id = (entry->ring_id & 0x70) >> 4; 4834 4835 switch (me_id) { 4836 case 0: 4837 if (pipe_id == 0) 4838 amdgpu_fence_process(&adev->gfx.gfx_ring[0]); 4839 else 4840 amdgpu_fence_process(&adev->gfx.gfx_ring[1]); 4841 break; 4842 case 1: 4843 case 2: 4844 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4845 ring = &adev->gfx.compute_ring[i]; 4846 /* Per-queue interrupt is supported for MEC starting from VI. 4847 * The interrupt can only be enabled/disabled per pipe instead of per queue. 4848 */ 4849 if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id)) 4850 amdgpu_fence_process(ring); 4851 } 4852 break; 4853 } 4854 return 0; 4855 } 4856 4857 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev, 4858 struct amdgpu_irq_src *source, 4859 unsigned type, 4860 enum amdgpu_interrupt_state state) 4861 { 4862 switch (state) { 4863 case AMDGPU_IRQ_STATE_DISABLE: 4864 case AMDGPU_IRQ_STATE_ENABLE: 4865 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4866 PRIV_REG_INT_ENABLE, 4867 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4868 break; 4869 default: 4870 break; 4871 } 4872 4873 return 0; 4874 } 4875 4876 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev, 4877 struct amdgpu_irq_src *source, 4878 unsigned type, 4879 enum amdgpu_interrupt_state state) 4880 { 4881 switch (state) { 4882 case AMDGPU_IRQ_STATE_DISABLE: 4883 case AMDGPU_IRQ_STATE_ENABLE: 4884 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, 4885 PRIV_INSTR_INT_ENABLE, 4886 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 4887 default: 4888 break; 4889 } 4890 4891 return 0; 4892 } 4893 4894 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev, 4895 struct amdgpu_iv_entry *entry) 4896 { 4897 u8 me_id, pipe_id, queue_id; 4898 struct amdgpu_ring *ring; 4899 int i; 4900 4901 me_id = (entry->ring_id & 0x0c) >> 2; 4902 pipe_id = (entry->ring_id & 0x03) >> 0; 4903 queue_id = (entry->ring_id & 0x70) >> 4; 4904 4905 switch (me_id) { 4906 case 0: 4907 for (i = 0; i < adev->gfx.num_gfx_rings; i++) { 4908 ring = &adev->gfx.gfx_ring[i]; 4909 /* we only enabled 1 gfx queue per pipe for now */ 4910 if (ring->me == me_id && ring->pipe == pipe_id) 4911 drm_sched_fault(&ring->sched); 4912 } 4913 break; 4914 case 1: 4915 case 2: 4916 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 4917 ring = &adev->gfx.compute_ring[i]; 4918 if (ring->me == me_id && ring->pipe == pipe_id && 4919 ring->queue == queue_id) 4920 drm_sched_fault(&ring->sched); 4921 } 4922 break; 4923 default: 4924 BUG(); 4925 } 4926 } 4927 4928 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev, 4929 struct amdgpu_irq_src *source, 4930 struct amdgpu_iv_entry *entry) 4931 { 4932 DRM_ERROR("Illegal register access in command stream\n"); 4933 gfx_v10_0_handle_priv_fault(adev, entry); 4934 return 0; 4935 } 4936 4937 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev, 4938 struct amdgpu_irq_src *source, 4939 struct amdgpu_iv_entry *entry) 4940 { 4941 DRM_ERROR("Illegal instruction in command stream\n"); 4942 gfx_v10_0_handle_priv_fault(adev, entry); 4943 return 0; 4944 } 4945 4946 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev, 4947 struct amdgpu_irq_src *src, 4948 unsigned int type, 4949 enum amdgpu_interrupt_state state) 4950 { 4951 uint32_t tmp, target; 4952 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4953 4954 if (ring->me == 1) 4955 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL); 4956 else 4957 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL); 4958 target += ring->pipe; 4959 4960 switch (type) { 4961 case AMDGPU_CP_KIQ_IRQ_DRIVER0: 4962 if (state == AMDGPU_IRQ_STATE_DISABLE) { 4963 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4964 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4965 GENERIC2_INT_ENABLE, 0); 4966 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4967 4968 tmp = RREG32(target); 4969 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4970 GENERIC2_INT_ENABLE, 0); 4971 WREG32(target, tmp); 4972 } else { 4973 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL); 4974 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL, 4975 GENERIC2_INT_ENABLE, 1); 4976 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp); 4977 4978 tmp = RREG32(target); 4979 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL, 4980 GENERIC2_INT_ENABLE, 1); 4981 WREG32(target, tmp); 4982 } 4983 break; 4984 default: 4985 BUG(); /* kiq only support GENERIC2_INT now */ 4986 break; 4987 } 4988 return 0; 4989 } 4990 4991 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev, 4992 struct amdgpu_irq_src *source, 4993 struct amdgpu_iv_entry *entry) 4994 { 4995 u8 me_id, pipe_id, queue_id; 4996 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring); 4997 4998 me_id = (entry->ring_id & 0x0c) >> 2; 4999 pipe_id = (entry->ring_id & 0x03) >> 0; 5000 queue_id = (entry->ring_id & 0x70) >> 4; 5001 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n", 5002 me_id, pipe_id, queue_id); 5003 5004 amdgpu_fence_process(ring); 5005 return 0; 5006 } 5007 5008 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { 5009 .name = "gfx_v10_0", 5010 .early_init = gfx_v10_0_early_init, 5011 .late_init = gfx_v10_0_late_init, 5012 .sw_init = gfx_v10_0_sw_init, 5013 .sw_fini = gfx_v10_0_sw_fini, 5014 .hw_init = gfx_v10_0_hw_init, 5015 .hw_fini = gfx_v10_0_hw_fini, 5016 .suspend = gfx_v10_0_suspend, 5017 .resume = gfx_v10_0_resume, 5018 .is_idle = gfx_v10_0_is_idle, 5019 .wait_for_idle = gfx_v10_0_wait_for_idle, 5020 .soft_reset = gfx_v10_0_soft_reset, 5021 .set_clockgating_state = gfx_v10_0_set_clockgating_state, 5022 .set_powergating_state = gfx_v10_0_set_powergating_state, 5023 .get_clockgating_state = gfx_v10_0_get_clockgating_state, 5024 }; 5025 5026 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { 5027 .type = AMDGPU_RING_TYPE_GFX, 5028 .align_mask = 0xff, 5029 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5030 .support_64bit_ptrs = true, 5031 .vmhub = AMDGPU_GFXHUB_0, 5032 .get_rptr = gfx_v10_0_ring_get_rptr_gfx, 5033 .get_wptr = gfx_v10_0_ring_get_wptr_gfx, 5034 .set_wptr = gfx_v10_0_ring_set_wptr_gfx, 5035 .emit_frame_size = /* totally 242 maximum if 16 IBs */ 5036 5 + /* COND_EXEC */ 5037 7 + /* PIPELINE_SYNC */ 5038 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5039 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5040 2 + /* VM_FLUSH */ 5041 8 + /* FENCE for VM_FLUSH */ 5042 20 + /* GDS switch */ 5043 4 + /* double SWITCH_BUFFER, 5044 * the first COND_EXEC jump to the place 5045 * just prior to this double SWITCH_BUFFER 5046 */ 5047 5 + /* COND_EXEC */ 5048 7 + /* HDP_flush */ 5049 4 + /* VGT_flush */ 5050 14 + /* CE_META */ 5051 31 + /* DE_META */ 5052 3 + /* CNTX_CTRL */ 5053 5 + /* HDP_INVL */ 5054 8 + 8 + /* FENCE x2 */ 5055 2, /* SWITCH_BUFFER */ 5056 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_gfx */ 5057 .emit_ib = gfx_v10_0_ring_emit_ib_gfx, 5058 .emit_fence = gfx_v10_0_ring_emit_fence, 5059 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5060 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5061 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5062 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5063 .test_ring = gfx_v10_0_ring_test_ring, 5064 .test_ib = gfx_v10_0_ring_test_ib, 5065 .insert_nop = amdgpu_ring_insert_nop, 5066 .pad_ib = amdgpu_ring_generic_pad_ib, 5067 .emit_switch_buffer = gfx_v10_0_ring_emit_sb, 5068 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl, 5069 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec, 5070 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec, 5071 .preempt_ib = gfx_v10_0_ring_preempt_ib, 5072 .emit_tmz = gfx_v10_0_ring_emit_tmz, 5073 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5074 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5075 }; 5076 5077 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { 5078 .type = AMDGPU_RING_TYPE_COMPUTE, 5079 .align_mask = 0xff, 5080 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5081 .support_64bit_ptrs = true, 5082 .vmhub = AMDGPU_GFXHUB_0, 5083 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5084 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5085 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5086 .emit_frame_size = 5087 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5088 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5089 5 + /* hdp invalidate */ 5090 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5091 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5092 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5093 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5094 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */ 5095 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5096 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5097 .emit_fence = gfx_v10_0_ring_emit_fence, 5098 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync, 5099 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush, 5100 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch, 5101 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush, 5102 .test_ring = gfx_v10_0_ring_test_ring, 5103 .test_ib = gfx_v10_0_ring_test_ib, 5104 .insert_nop = amdgpu_ring_insert_nop, 5105 .pad_ib = amdgpu_ring_generic_pad_ib, 5106 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5107 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5108 }; 5109 5110 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { 5111 .type = AMDGPU_RING_TYPE_KIQ, 5112 .align_mask = 0xff, 5113 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 5114 .support_64bit_ptrs = true, 5115 .vmhub = AMDGPU_GFXHUB_0, 5116 .get_rptr = gfx_v10_0_ring_get_rptr_compute, 5117 .get_wptr = gfx_v10_0_ring_get_wptr_compute, 5118 .set_wptr = gfx_v10_0_ring_set_wptr_compute, 5119 .emit_frame_size = 5120 20 + /* gfx_v10_0_ring_emit_gds_switch */ 5121 7 + /* gfx_v10_0_ring_emit_hdp_flush */ 5122 5 + /*hdp invalidate */ 5123 7 + /* gfx_v10_0_ring_emit_pipeline_sync */ 5124 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 5125 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 5126 2 + /* gfx_v10_0_ring_emit_vm_flush */ 5127 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */ 5128 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */ 5129 .emit_ib = gfx_v10_0_ring_emit_ib_compute, 5130 .emit_fence = gfx_v10_0_ring_emit_fence_kiq, 5131 .test_ring = gfx_v10_0_ring_test_ring, 5132 .test_ib = gfx_v10_0_ring_test_ib, 5133 .insert_nop = amdgpu_ring_insert_nop, 5134 .pad_ib = amdgpu_ring_generic_pad_ib, 5135 .emit_rreg = gfx_v10_0_ring_emit_rreg, 5136 .emit_wreg = gfx_v10_0_ring_emit_wreg, 5137 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait, 5138 }; 5139 5140 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev) 5141 { 5142 int i; 5143 5144 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq; 5145 5146 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 5147 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx; 5148 5149 for (i = 0; i < adev->gfx.num_compute_rings; i++) 5150 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute; 5151 } 5152 5153 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = { 5154 .set = gfx_v10_0_set_eop_interrupt_state, 5155 .process = gfx_v10_0_eop_irq, 5156 }; 5157 5158 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = { 5159 .set = gfx_v10_0_set_priv_reg_fault_state, 5160 .process = gfx_v10_0_priv_reg_irq, 5161 }; 5162 5163 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = { 5164 .set = gfx_v10_0_set_priv_inst_fault_state, 5165 .process = gfx_v10_0_priv_inst_irq, 5166 }; 5167 5168 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { 5169 .set = gfx_v10_0_kiq_set_interrupt_state, 5170 .process = gfx_v10_0_kiq_irq, 5171 }; 5172 5173 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) 5174 { 5175 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 5176 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs; 5177 5178 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; 5179 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs; 5180 5181 adev->gfx.priv_reg_irq.num_types = 1; 5182 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; 5183 5184 adev->gfx.priv_inst_irq.num_types = 1; 5185 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs; 5186 } 5187 5188 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev) 5189 { 5190 switch (adev->asic_type) { 5191 case CHIP_NAVI10: 5192 case CHIP_NAVI14: 5193 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs; 5194 break; 5195 default: 5196 break; 5197 } 5198 } 5199 5200 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev) 5201 { 5202 /* init asic gds info */ 5203 switch (adev->asic_type) { 5204 case CHIP_NAVI10: 5205 default: 5206 adev->gds.gds_size = 0x10000; 5207 adev->gds.gds_compute_max_wave_id = 0x4ff; 5208 adev->gds.vgt_gs_max_wave_id = 0x3ff; 5209 break; 5210 } 5211 5212 adev->gds.gws_size = 64; 5213 adev->gds.oa_size = 16; 5214 } 5215 5216 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev, 5217 u32 bitmap) 5218 { 5219 u32 data; 5220 5221 if (!bitmap) 5222 return; 5223 5224 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5225 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5226 5227 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data); 5228 } 5229 5230 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev) 5231 { 5232 u32 data, wgp_bitmask; 5233 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG); 5234 data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG); 5235 5236 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 5237 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 5238 5239 wgp_bitmask = 5240 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1); 5241 5242 return (~data) & wgp_bitmask; 5243 } 5244 5245 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev) 5246 { 5247 u32 wgp_idx, wgp_active_bitmap; 5248 u32 cu_bitmap_per_wgp, cu_active_bitmap; 5249 5250 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev); 5251 cu_active_bitmap = 0; 5252 5253 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) { 5254 /* if there is one WGP enabled, it means 2 CUs will be enabled */ 5255 cu_bitmap_per_wgp = 3 << (2 * wgp_idx); 5256 if (wgp_active_bitmap & (1 << wgp_idx)) 5257 cu_active_bitmap |= cu_bitmap_per_wgp; 5258 } 5259 5260 return cu_active_bitmap; 5261 } 5262 5263 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev, 5264 struct amdgpu_cu_info *cu_info) 5265 { 5266 int i, j, k, counter, active_cu_number = 0; 5267 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0; 5268 unsigned disable_masks[4 * 2]; 5269 5270 if (!adev || !cu_info) 5271 return -EINVAL; 5272 5273 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2); 5274 5275 mutex_lock(&adev->grbm_idx_mutex); 5276 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 5277 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 5278 mask = 1; 5279 ao_bitmap = 0; 5280 counter = 0; 5281 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff); 5282 if (i < 4 && j < 2) 5283 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh( 5284 adev, disable_masks[i * 2 + j]); 5285 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev); 5286 cu_info->bitmap[i][j] = bitmap; 5287 5288 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 5289 if (bitmap & mask) { 5290 if (counter < adev->gfx.config.max_cu_per_sh) 5291 ao_bitmap |= mask; 5292 counter++; 5293 } 5294 mask <<= 1; 5295 } 5296 active_cu_number += counter; 5297 if (i < 2 && j < 2) 5298 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8)); 5299 cu_info->ao_cu_bitmap[i][j] = ao_bitmap; 5300 } 5301 } 5302 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 5303 mutex_unlock(&adev->grbm_idx_mutex); 5304 5305 cu_info->number = active_cu_number; 5306 cu_info->ao_cu_mask = ao_cu_mask; 5307 cu_info->simd_per_cu = NUM_SIMD_PER_CU; 5308 5309 return 0; 5310 } 5311 5312 const struct amdgpu_ip_block_version gfx_v10_0_ip_block = 5313 { 5314 .type = AMD_IP_BLOCK_TYPE_GFX, 5315 .major = 10, 5316 .minor = 0, 5317 .rev = 0, 5318 .funcs = &gfx_v10_0_ip_funcs, 5319 }; 5320