1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "amdgpu.h" 24 #include "df_v3_6.h" 25 26 #include "df/df_3_6_default.h" 27 #include "df/df_3_6_offset.h" 28 #include "df/df_3_6_sh_mask.h" 29 30 static u32 df_v3_6_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 31 16, 32, 0, 0, 0, 2, 4, 8}; 32 33 /* init df format attrs */ 34 AMDGPU_PMU_ATTR(event, "config:0-7"); 35 AMDGPU_PMU_ATTR(instance, "config:8-15"); 36 AMDGPU_PMU_ATTR(umask, "config:16-23"); 37 38 /* df format attributes */ 39 static struct attribute *df_v3_6_format_attrs[] = { 40 &pmu_attr_event.attr, 41 &pmu_attr_instance.attr, 42 &pmu_attr_umask.attr, 43 NULL 44 }; 45 46 /* df format attribute group */ 47 static struct attribute_group df_v3_6_format_attr_group = { 48 .name = "format", 49 .attrs = df_v3_6_format_attrs, 50 }; 51 52 /* df event attrs */ 53 AMDGPU_PMU_ATTR(cake0_pcsout_txdata, 54 "event=0x7,instance=0x46,umask=0x2"); 55 AMDGPU_PMU_ATTR(cake1_pcsout_txdata, 56 "event=0x7,instance=0x47,umask=0x2"); 57 AMDGPU_PMU_ATTR(cake0_pcsout_txmeta, 58 "event=0x7,instance=0x46,umask=0x4"); 59 AMDGPU_PMU_ATTR(cake1_pcsout_txmeta, 60 "event=0x7,instance=0x47,umask=0x4"); 61 AMDGPU_PMU_ATTR(cake0_ftiinstat_reqalloc, 62 "event=0xb,instance=0x46,umask=0x4"); 63 AMDGPU_PMU_ATTR(cake1_ftiinstat_reqalloc, 64 "event=0xb,instance=0x47,umask=0x4"); 65 AMDGPU_PMU_ATTR(cake0_ftiinstat_rspalloc, 66 "event=0xb,instance=0x46,umask=0x8"); 67 AMDGPU_PMU_ATTR(cake1_ftiinstat_rspalloc, 68 "event=0xb,instance=0x47,umask=0x8"); 69 70 /* df event attributes */ 71 static struct attribute *df_v3_6_event_attrs[] = { 72 &pmu_attr_cake0_pcsout_txdata.attr, 73 &pmu_attr_cake1_pcsout_txdata.attr, 74 &pmu_attr_cake0_pcsout_txmeta.attr, 75 &pmu_attr_cake1_pcsout_txmeta.attr, 76 &pmu_attr_cake0_ftiinstat_reqalloc.attr, 77 &pmu_attr_cake1_ftiinstat_reqalloc.attr, 78 &pmu_attr_cake0_ftiinstat_rspalloc.attr, 79 &pmu_attr_cake1_ftiinstat_rspalloc.attr, 80 NULL 81 }; 82 83 /* df event attribute group */ 84 static struct attribute_group df_v3_6_event_attr_group = { 85 .name = "events", 86 .attrs = df_v3_6_event_attrs 87 }; 88 89 /* df event attr groups */ 90 const struct attribute_group *df_v3_6_attr_groups[] = { 91 &df_v3_6_format_attr_group, 92 &df_v3_6_event_attr_group, 93 NULL 94 }; 95 96 static uint64_t df_v3_6_get_fica(struct amdgpu_device *adev, 97 uint32_t ficaa_val) 98 { 99 unsigned long flags, address, data; 100 uint32_t ficadl_val, ficadh_val; 101 102 address = adev->nbio.funcs->get_pcie_index_offset(adev); 103 data = adev->nbio.funcs->get_pcie_data_offset(adev); 104 105 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 106 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); 107 WREG32(data, ficaa_val); 108 109 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); 110 ficadl_val = RREG32(data); 111 112 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); 113 ficadh_val = RREG32(data); 114 115 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 116 117 return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val); 118 } 119 120 static void df_v3_6_set_fica(struct amdgpu_device *adev, uint32_t ficaa_val, 121 uint32_t ficadl_val, uint32_t ficadh_val) 122 { 123 unsigned long flags, address, data; 124 125 address = adev->nbio.funcs->get_pcie_index_offset(adev); 126 data = adev->nbio.funcs->get_pcie_data_offset(adev); 127 128 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 129 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); 130 WREG32(data, ficaa_val); 131 132 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataLo3); 133 WREG32(data, ficadl_val); 134 135 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); 136 WREG32(data, ficadh_val); 137 138 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 139 } 140 141 /* 142 * df_v3_6_perfmon_rreg - read perfmon lo and hi 143 * 144 * required to be atomic. no mmio method provided so subsequent reads for lo 145 * and hi require to preserve df finite state machine 146 */ 147 static void df_v3_6_perfmon_rreg(struct amdgpu_device *adev, 148 uint32_t lo_addr, uint32_t *lo_val, 149 uint32_t hi_addr, uint32_t *hi_val) 150 { 151 unsigned long flags, address, data; 152 153 address = adev->nbio.funcs->get_pcie_index_offset(adev); 154 data = adev->nbio.funcs->get_pcie_data_offset(adev); 155 156 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 157 WREG32(address, lo_addr); 158 *lo_val = RREG32(data); 159 WREG32(address, hi_addr); 160 *hi_val = RREG32(data); 161 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 162 } 163 164 /* 165 * df_v3_6_perfmon_wreg - write to perfmon lo and hi 166 * 167 * required to be atomic. no mmio method provided so subsequent reads after 168 * data writes cannot occur to preserve data fabrics finite state machine. 169 */ 170 static void df_v3_6_perfmon_wreg(struct amdgpu_device *adev, uint32_t lo_addr, 171 uint32_t lo_val, uint32_t hi_addr, uint32_t hi_val) 172 { 173 unsigned long flags, address, data; 174 175 address = adev->nbio.funcs->get_pcie_index_offset(adev); 176 data = adev->nbio.funcs->get_pcie_data_offset(adev); 177 178 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 179 WREG32(address, lo_addr); 180 WREG32(data, lo_val); 181 WREG32(address, hi_addr); 182 WREG32(data, hi_val); 183 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 184 } 185 186 /* same as perfmon_wreg but return status on write value check */ 187 static int df_v3_6_perfmon_arm_with_status(struct amdgpu_device *adev, 188 uint32_t lo_addr, uint32_t lo_val, 189 uint32_t hi_addr, uint32_t hi_val) 190 { 191 unsigned long flags, address, data; 192 uint32_t lo_val_rb, hi_val_rb; 193 194 address = adev->nbio.funcs->get_pcie_index_offset(adev); 195 data = adev->nbio.funcs->get_pcie_data_offset(adev); 196 197 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 198 WREG32(address, lo_addr); 199 WREG32(data, lo_val); 200 WREG32(address, hi_addr); 201 WREG32(data, hi_val); 202 203 WREG32(address, lo_addr); 204 lo_val_rb = RREG32(data); 205 WREG32(address, hi_addr); 206 hi_val_rb = RREG32(data); 207 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 208 209 if (!(lo_val == lo_val_rb && hi_val == hi_val_rb)) 210 return -EBUSY; 211 212 return 0; 213 } 214 215 216 /* 217 * retry arming counters every 100 usecs within 1 millisecond interval. 218 * if retry fails after time out, return error. 219 */ 220 #define ARM_RETRY_USEC_TIMEOUT 1000 221 #define ARM_RETRY_USEC_INTERVAL 100 222 static int df_v3_6_perfmon_arm_with_retry(struct amdgpu_device *adev, 223 uint32_t lo_addr, uint32_t lo_val, 224 uint32_t hi_addr, uint32_t hi_val) 225 { 226 int countdown = ARM_RETRY_USEC_TIMEOUT; 227 228 while (countdown) { 229 230 if (!df_v3_6_perfmon_arm_with_status(adev, lo_addr, lo_val, 231 hi_addr, hi_val)) 232 break; 233 234 countdown -= ARM_RETRY_USEC_INTERVAL; 235 udelay(ARM_RETRY_USEC_INTERVAL); 236 } 237 238 return countdown > 0 ? 0 : -ETIME; 239 } 240 241 /* get the number of df counters available */ 242 static ssize_t df_v3_6_get_df_cntr_avail(struct device *dev, 243 struct device_attribute *attr, 244 char *buf) 245 { 246 struct amdgpu_device *adev; 247 struct drm_device *ddev; 248 int i, count; 249 250 ddev = dev_get_drvdata(dev); 251 adev = ddev->dev_private; 252 count = 0; 253 254 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { 255 if (adev->df_perfmon_config_assign_mask[i] == 0) 256 count++; 257 } 258 259 return snprintf(buf, PAGE_SIZE, "%i\n", count); 260 } 261 262 /* device attr for available perfmon counters */ 263 static DEVICE_ATTR(df_cntr_avail, S_IRUGO, df_v3_6_get_df_cntr_avail, NULL); 264 265 /* init perfmons */ 266 static void df_v3_6_sw_init(struct amdgpu_device *adev) 267 { 268 int i, ret; 269 270 ret = device_create_file(adev->dev, &dev_attr_df_cntr_avail); 271 if (ret) 272 DRM_ERROR("failed to create file for available df counters\n"); 273 274 for (i = 0; i < AMDGPU_MAX_DF_PERFMONS; i++) 275 adev->df_perfmon_config_assign_mask[i] = 0; 276 } 277 278 static void df_v3_6_sw_fini(struct amdgpu_device *adev) 279 { 280 281 device_remove_file(adev->dev, &dev_attr_df_cntr_avail); 282 283 } 284 285 static void df_v3_6_enable_broadcast_mode(struct amdgpu_device *adev, 286 bool enable) 287 { 288 u32 tmp; 289 290 if (enable) { 291 tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl); 292 tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK; 293 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp); 294 } else 295 WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, 296 mmFabricConfigAccessControl_DEFAULT); 297 } 298 299 static u32 df_v3_6_get_fb_channel_number(struct amdgpu_device *adev) 300 { 301 u32 tmp; 302 303 tmp = RREG32_SOC15(DF, 0, mmDF_CS_UMC_AON0_DramBaseAddress0); 304 tmp &= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan_MASK; 305 tmp >>= DF_CS_UMC_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; 306 307 return tmp; 308 } 309 310 static u32 df_v3_6_get_hbm_channel_number(struct amdgpu_device *adev) 311 { 312 int fb_channel_number; 313 314 fb_channel_number = adev->df_funcs->get_fb_channel_number(adev); 315 if (fb_channel_number >= ARRAY_SIZE(df_v3_6_channel_number)) 316 fb_channel_number = 0; 317 318 return df_v3_6_channel_number[fb_channel_number]; 319 } 320 321 static void df_v3_6_update_medium_grain_clock_gating(struct amdgpu_device *adev, 322 bool enable) 323 { 324 u32 tmp; 325 326 if (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG) { 327 /* Put DF on broadcast mode */ 328 adev->df_funcs->enable_broadcast_mode(adev, true); 329 330 if (enable) { 331 tmp = RREG32_SOC15(DF, 0, 332 mmDF_PIE_AON0_DfGlobalClkGater); 333 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 334 tmp |= DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY; 335 WREG32_SOC15(DF, 0, 336 mmDF_PIE_AON0_DfGlobalClkGater, tmp); 337 } else { 338 tmp = RREG32_SOC15(DF, 0, 339 mmDF_PIE_AON0_DfGlobalClkGater); 340 tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK; 341 tmp |= DF_V3_6_MGCG_DISABLE; 342 WREG32_SOC15(DF, 0, 343 mmDF_PIE_AON0_DfGlobalClkGater, tmp); 344 } 345 346 /* Exit broadcast mode */ 347 adev->df_funcs->enable_broadcast_mode(adev, false); 348 } 349 } 350 351 static void df_v3_6_get_clockgating_state(struct amdgpu_device *adev, 352 u32 *flags) 353 { 354 u32 tmp; 355 356 /* AMD_CG_SUPPORT_DF_MGCG */ 357 tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater); 358 if (tmp & DF_V3_6_MGCG_ENABLE_15_CYCLE_DELAY) 359 *flags |= AMD_CG_SUPPORT_DF_MGCG; 360 } 361 362 /* get assigned df perfmon ctr as int */ 363 static int df_v3_6_pmc_config_2_cntr(struct amdgpu_device *adev, 364 uint64_t config) 365 { 366 int i; 367 368 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { 369 if ((config & 0x0FFFFFFUL) == 370 adev->df_perfmon_config_assign_mask[i]) 371 return i; 372 } 373 374 return -EINVAL; 375 } 376 377 /* get address based on counter assignment */ 378 static void df_v3_6_pmc_get_addr(struct amdgpu_device *adev, 379 uint64_t config, 380 int is_ctrl, 381 uint32_t *lo_base_addr, 382 uint32_t *hi_base_addr) 383 { 384 int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 385 386 if (target_cntr < 0) 387 return; 388 389 switch (target_cntr) { 390 391 case 0: 392 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo4 : smnPerfMonCtrLo4; 393 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi4 : smnPerfMonCtrHi4; 394 break; 395 case 1: 396 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo5 : smnPerfMonCtrLo5; 397 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi5 : smnPerfMonCtrHi5; 398 break; 399 case 2: 400 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo6 : smnPerfMonCtrLo6; 401 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi6 : smnPerfMonCtrHi6; 402 break; 403 case 3: 404 *lo_base_addr = is_ctrl ? smnPerfMonCtlLo7 : smnPerfMonCtrLo7; 405 *hi_base_addr = is_ctrl ? smnPerfMonCtlHi7 : smnPerfMonCtrHi7; 406 break; 407 408 } 409 410 } 411 412 /* get read counter address */ 413 static void df_v3_6_pmc_get_read_settings(struct amdgpu_device *adev, 414 uint64_t config, 415 uint32_t *lo_base_addr, 416 uint32_t *hi_base_addr) 417 { 418 df_v3_6_pmc_get_addr(adev, config, 0, lo_base_addr, hi_base_addr); 419 } 420 421 /* get control counter settings i.e. address and values to set */ 422 static int df_v3_6_pmc_get_ctrl_settings(struct amdgpu_device *adev, 423 uint64_t config, 424 uint32_t *lo_base_addr, 425 uint32_t *hi_base_addr, 426 uint32_t *lo_val, 427 uint32_t *hi_val) 428 { 429 430 uint32_t eventsel, instance, unitmask; 431 uint32_t instance_10, instance_5432, instance_76; 432 433 df_v3_6_pmc_get_addr(adev, config, 1, lo_base_addr, hi_base_addr); 434 435 if ((*lo_base_addr == 0) || (*hi_base_addr == 0)) { 436 DRM_ERROR("[DF PMC] addressing not retrieved! Lo: %x, Hi: %x", 437 *lo_base_addr, *hi_base_addr); 438 return -ENXIO; 439 } 440 441 eventsel = DF_V3_6_GET_EVENT(config) & 0x3f; 442 unitmask = DF_V3_6_GET_UNITMASK(config) & 0xf; 443 instance = DF_V3_6_GET_INSTANCE(config); 444 445 instance_10 = instance & 0x3; 446 instance_5432 = (instance >> 2) & 0xf; 447 instance_76 = (instance >> 6) & 0x3; 448 449 *lo_val = (unitmask << 8) | (instance_10 << 6) | eventsel | (1 << 22); 450 *hi_val = (instance_76 << 29) | instance_5432; 451 452 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", 453 config, *lo_base_addr, *hi_base_addr, *lo_val, *hi_val); 454 455 return 0; 456 } 457 458 /* add df performance counters for read */ 459 static int df_v3_6_pmc_add_cntr(struct amdgpu_device *adev, 460 uint64_t config) 461 { 462 int i, target_cntr; 463 464 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 465 466 if (target_cntr >= 0) 467 return 0; 468 469 for (i = 0; i < DF_V3_6_MAX_COUNTERS; i++) { 470 if (adev->df_perfmon_config_assign_mask[i] == 0U) { 471 adev->df_perfmon_config_assign_mask[i] = 472 config & 0x0FFFFFFUL; 473 return 0; 474 } 475 } 476 477 return -ENOSPC; 478 } 479 480 #define DEFERRED_ARM_MASK (1 << 31) 481 static int df_v3_6_pmc_set_deferred(struct amdgpu_device *adev, 482 uint64_t config, bool is_deferred) 483 { 484 int target_cntr; 485 486 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 487 488 if (target_cntr < 0) 489 return -EINVAL; 490 491 if (is_deferred) 492 adev->df_perfmon_config_assign_mask[target_cntr] |= 493 DEFERRED_ARM_MASK; 494 else 495 adev->df_perfmon_config_assign_mask[target_cntr] &= 496 ~DEFERRED_ARM_MASK; 497 498 return 0; 499 } 500 501 static bool df_v3_6_pmc_is_deferred(struct amdgpu_device *adev, 502 uint64_t config) 503 { 504 int target_cntr; 505 506 target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 507 508 /* 509 * we never get target_cntr < 0 since this funciton is only called in 510 * pmc_count for now but we should check anyways. 511 */ 512 return (target_cntr >= 0 && 513 (adev->df_perfmon_config_assign_mask[target_cntr] 514 & DEFERRED_ARM_MASK)); 515 516 } 517 518 /* release performance counter */ 519 static void df_v3_6_pmc_release_cntr(struct amdgpu_device *adev, 520 uint64_t config) 521 { 522 int target_cntr = df_v3_6_pmc_config_2_cntr(adev, config); 523 524 if (target_cntr >= 0) 525 adev->df_perfmon_config_assign_mask[target_cntr] = 0ULL; 526 } 527 528 529 static void df_v3_6_reset_perfmon_cntr(struct amdgpu_device *adev, 530 uint64_t config) 531 { 532 uint32_t lo_base_addr, hi_base_addr; 533 534 df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr, 535 &hi_base_addr); 536 537 if ((lo_base_addr == 0) || (hi_base_addr == 0)) 538 return; 539 540 df_v3_6_perfmon_wreg(adev, lo_base_addr, 0, hi_base_addr, 0); 541 } 542 543 static int df_v3_6_pmc_start(struct amdgpu_device *adev, uint64_t config, 544 int is_enable) 545 { 546 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; 547 int err = 0, ret = 0; 548 549 switch (adev->asic_type) { 550 case CHIP_VEGA20: 551 if (is_enable) 552 return df_v3_6_pmc_add_cntr(adev, config); 553 554 df_v3_6_reset_perfmon_cntr(adev, config); 555 556 ret = df_v3_6_pmc_get_ctrl_settings(adev, 557 config, 558 &lo_base_addr, 559 &hi_base_addr, 560 &lo_val, 561 &hi_val); 562 563 if (ret) 564 return ret; 565 566 err = df_v3_6_perfmon_arm_with_retry(adev, 567 lo_base_addr, 568 lo_val, 569 hi_base_addr, 570 hi_val); 571 572 if (err) 573 ret = df_v3_6_pmc_set_deferred(adev, config, true); 574 575 break; 576 default: 577 break; 578 } 579 580 return ret; 581 } 582 583 static int df_v3_6_pmc_stop(struct amdgpu_device *adev, uint64_t config, 584 int is_disable) 585 { 586 uint32_t lo_base_addr, hi_base_addr, lo_val, hi_val; 587 int ret = 0; 588 589 switch (adev->asic_type) { 590 case CHIP_VEGA20: 591 ret = df_v3_6_pmc_get_ctrl_settings(adev, 592 config, 593 &lo_base_addr, 594 &hi_base_addr, 595 &lo_val, 596 &hi_val); 597 598 if (ret) 599 return ret; 600 601 df_v3_6_reset_perfmon_cntr(adev, config); 602 603 if (is_disable) 604 df_v3_6_pmc_release_cntr(adev, config); 605 606 break; 607 default: 608 break; 609 } 610 611 return ret; 612 } 613 614 static void df_v3_6_pmc_get_count(struct amdgpu_device *adev, 615 uint64_t config, 616 uint64_t *count) 617 { 618 uint32_t lo_base_addr, hi_base_addr, lo_val = 0, hi_val = 0; 619 *count = 0; 620 621 switch (adev->asic_type) { 622 case CHIP_VEGA20: 623 df_v3_6_pmc_get_read_settings(adev, config, &lo_base_addr, 624 &hi_base_addr); 625 626 if ((lo_base_addr == 0) || (hi_base_addr == 0)) 627 return; 628 629 /* rearm the counter or throw away count value on failure */ 630 if (df_v3_6_pmc_is_deferred(adev, config)) { 631 int rearm_err = df_v3_6_perfmon_arm_with_status(adev, 632 lo_base_addr, lo_val, 633 hi_base_addr, hi_val); 634 635 if (rearm_err) 636 return; 637 638 df_v3_6_pmc_set_deferred(adev, config, false); 639 } 640 641 df_v3_6_perfmon_rreg(adev, lo_base_addr, &lo_val, 642 hi_base_addr, &hi_val); 643 644 *count = ((hi_val | 0ULL) << 32) | (lo_val | 0ULL); 645 646 if (*count >= DF_V3_6_PERFMON_OVERFLOW) 647 *count = 0; 648 649 DRM_DEBUG_DRIVER("config=%llx addr=%08x:%08x val=%08x:%08x", 650 config, lo_base_addr, hi_base_addr, lo_val, hi_val); 651 652 break; 653 default: 654 break; 655 } 656 } 657 658 const struct amdgpu_df_funcs df_v3_6_funcs = { 659 .sw_init = df_v3_6_sw_init, 660 .sw_fini = df_v3_6_sw_fini, 661 .enable_broadcast_mode = df_v3_6_enable_broadcast_mode, 662 .get_fb_channel_number = df_v3_6_get_fb_channel_number, 663 .get_hbm_channel_number = df_v3_6_get_hbm_channel_number, 664 .update_medium_grain_clock_gating = 665 df_v3_6_update_medium_grain_clock_gating, 666 .get_clockgating_state = df_v3_6_get_clockgating_state, 667 .pmc_start = df_v3_6_pmc_start, 668 .pmc_stop = df_v3_6_pmc_stop, 669 .pmc_get_count = df_v3_6_pmc_get_count, 670 .get_fica = df_v3_6_get_fica, 671 .set_fica = df_v3_6_set_fica 672 }; 673