1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "cikd.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_8_0_d.h" 36 #include "dce/dce_8_0_sh_mask.h" 37 38 #include "gca/gfx_7_2_enum.h" 39 40 #include "gmc/gmc_7_1_d.h" 41 #include "gmc/gmc_7_1_sh_mask.h" 42 43 #include "oss/oss_2_0_d.h" 44 #include "oss/oss_2_0_sh_mask.h" 45 46 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev); 47 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev); 48 49 static const u32 crtc_offsets[6] = 50 { 51 CRTC0_REGISTER_OFFSET, 52 CRTC1_REGISTER_OFFSET, 53 CRTC2_REGISTER_OFFSET, 54 CRTC3_REGISTER_OFFSET, 55 CRTC4_REGISTER_OFFSET, 56 CRTC5_REGISTER_OFFSET 57 }; 58 59 static const uint32_t dig_offsets[] = { 60 CRTC0_REGISTER_OFFSET, 61 CRTC1_REGISTER_OFFSET, 62 CRTC2_REGISTER_OFFSET, 63 CRTC3_REGISTER_OFFSET, 64 CRTC4_REGISTER_OFFSET, 65 CRTC5_REGISTER_OFFSET, 66 (0x13830 - 0x7030) >> 2, 67 }; 68 69 static const struct { 70 uint32_t reg; 71 uint32_t vblank; 72 uint32_t vline; 73 uint32_t hpd; 74 75 } interrupt_status_offsets[6] = { { 76 .reg = mmDISP_INTERRUPT_STATUS, 77 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 78 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 79 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 80 }, { 81 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 82 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 83 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 84 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 85 }, { 86 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 87 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 105 } }; 106 107 static const uint32_t hpd_int_control_offsets[6] = { 108 mmDC_HPD1_INT_CONTROL, 109 mmDC_HPD2_INT_CONTROL, 110 mmDC_HPD3_INT_CONTROL, 111 mmDC_HPD4_INT_CONTROL, 112 mmDC_HPD5_INT_CONTROL, 113 mmDC_HPD6_INT_CONTROL, 114 }; 115 116 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, 117 u32 block_offset, u32 reg) 118 { 119 unsigned long flags; 120 u32 r; 121 122 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 123 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 124 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 125 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 126 127 return r; 128 } 129 130 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, 131 u32 block_offset, u32 reg, u32 v) 132 { 133 unsigned long flags; 134 135 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 136 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 137 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 138 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 139 } 140 141 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 142 { 143 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 144 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 145 return true; 146 else 147 return false; 148 } 149 150 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 151 { 152 u32 pos1, pos2; 153 154 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 155 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 156 157 if (pos1 != pos2) 158 return true; 159 else 160 return false; 161 } 162 163 /** 164 * dce_v8_0_vblank_wait - vblank wait asic callback. 165 * 166 * @adev: amdgpu_device pointer 167 * @crtc: crtc to wait for vblank on 168 * 169 * Wait for vblank on the requested crtc (evergreen+). 170 */ 171 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc) 172 { 173 unsigned i = 0; 174 175 if (crtc >= adev->mode_info.num_crtc) 176 return; 177 178 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 179 return; 180 181 /* depending on when we hit vblank, we may be close to active; if so, 182 * wait for another frame. 183 */ 184 while (dce_v8_0_is_in_vblank(adev, crtc)) { 185 if (i++ % 100 == 0) { 186 if (!dce_v8_0_is_counter_moving(adev, crtc)) 187 break; 188 } 189 } 190 191 while (!dce_v8_0_is_in_vblank(adev, crtc)) { 192 if (i++ % 100 == 0) { 193 if (!dce_v8_0_is_counter_moving(adev, crtc)) 194 break; 195 } 196 } 197 } 198 199 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 200 { 201 if (crtc >= adev->mode_info.num_crtc) 202 return 0; 203 else 204 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 205 } 206 207 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev) 208 { 209 unsigned i; 210 211 /* Enable pflip interrupts */ 212 for (i = 0; i < adev->mode_info.num_crtc; i++) 213 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 214 } 215 216 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 217 { 218 unsigned i; 219 220 /* Disable pflip interrupts */ 221 for (i = 0; i < adev->mode_info.num_crtc; i++) 222 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 223 } 224 225 /** 226 * dce_v8_0_page_flip - pageflip callback. 227 * 228 * @adev: amdgpu_device pointer 229 * @crtc_id: crtc to cleanup pageflip on 230 * @crtc_base: new address of the crtc (GPU MC address) 231 * 232 * Triggers the actual pageflip by updating the primary 233 * surface base address. 234 */ 235 static void dce_v8_0_page_flip(struct amdgpu_device *adev, 236 int crtc_id, u64 crtc_base) 237 { 238 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 239 240 /* update the primary scanout addresses */ 241 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 242 upper_32_bits(crtc_base)); 243 /* writing to the low address triggers the update */ 244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 245 lower_32_bits(crtc_base)); 246 /* post the write */ 247 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 248 } 249 250 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 251 u32 *vbl, u32 *position) 252 { 253 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 254 return -EINVAL; 255 256 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 257 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 258 259 return 0; 260 } 261 262 /** 263 * dce_v8_0_hpd_sense - hpd sense callback. 264 * 265 * @adev: amdgpu_device pointer 266 * @hpd: hpd (hotplug detect) pin 267 * 268 * Checks if a digital monitor is connected (evergreen+). 269 * Returns true if connected, false if not connected. 270 */ 271 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, 272 enum amdgpu_hpd_id hpd) 273 { 274 bool connected = false; 275 276 switch (hpd) { 277 case AMDGPU_HPD_1: 278 if (RREG32(mmDC_HPD1_INT_STATUS) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 279 connected = true; 280 break; 281 case AMDGPU_HPD_2: 282 if (RREG32(mmDC_HPD2_INT_STATUS) & DC_HPD2_INT_STATUS__DC_HPD2_SENSE_MASK) 283 connected = true; 284 break; 285 case AMDGPU_HPD_3: 286 if (RREG32(mmDC_HPD3_INT_STATUS) & DC_HPD3_INT_STATUS__DC_HPD3_SENSE_MASK) 287 connected = true; 288 break; 289 case AMDGPU_HPD_4: 290 if (RREG32(mmDC_HPD4_INT_STATUS) & DC_HPD4_INT_STATUS__DC_HPD4_SENSE_MASK) 291 connected = true; 292 break; 293 case AMDGPU_HPD_5: 294 if (RREG32(mmDC_HPD5_INT_STATUS) & DC_HPD5_INT_STATUS__DC_HPD5_SENSE_MASK) 295 connected = true; 296 break; 297 case AMDGPU_HPD_6: 298 if (RREG32(mmDC_HPD6_INT_STATUS) & DC_HPD6_INT_STATUS__DC_HPD6_SENSE_MASK) 299 connected = true; 300 break; 301 default: 302 break; 303 } 304 305 return connected; 306 } 307 308 /** 309 * dce_v8_0_hpd_set_polarity - hpd set polarity callback. 310 * 311 * @adev: amdgpu_device pointer 312 * @hpd: hpd (hotplug detect) pin 313 * 314 * Set the polarity of the hpd pin (evergreen+). 315 */ 316 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, 317 enum amdgpu_hpd_id hpd) 318 { 319 u32 tmp; 320 bool connected = dce_v8_0_hpd_sense(adev, hpd); 321 322 switch (hpd) { 323 case AMDGPU_HPD_1: 324 tmp = RREG32(mmDC_HPD1_INT_CONTROL); 325 if (connected) 326 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 327 else 328 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 329 WREG32(mmDC_HPD1_INT_CONTROL, tmp); 330 break; 331 case AMDGPU_HPD_2: 332 tmp = RREG32(mmDC_HPD2_INT_CONTROL); 333 if (connected) 334 tmp &= ~DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 335 else 336 tmp |= DC_HPD2_INT_CONTROL__DC_HPD2_INT_POLARITY_MASK; 337 WREG32(mmDC_HPD2_INT_CONTROL, tmp); 338 break; 339 case AMDGPU_HPD_3: 340 tmp = RREG32(mmDC_HPD3_INT_CONTROL); 341 if (connected) 342 tmp &= ~DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 343 else 344 tmp |= DC_HPD3_INT_CONTROL__DC_HPD3_INT_POLARITY_MASK; 345 WREG32(mmDC_HPD3_INT_CONTROL, tmp); 346 break; 347 case AMDGPU_HPD_4: 348 tmp = RREG32(mmDC_HPD4_INT_CONTROL); 349 if (connected) 350 tmp &= ~DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 351 else 352 tmp |= DC_HPD4_INT_CONTROL__DC_HPD4_INT_POLARITY_MASK; 353 WREG32(mmDC_HPD4_INT_CONTROL, tmp); 354 break; 355 case AMDGPU_HPD_5: 356 tmp = RREG32(mmDC_HPD5_INT_CONTROL); 357 if (connected) 358 tmp &= ~DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 359 else 360 tmp |= DC_HPD5_INT_CONTROL__DC_HPD5_INT_POLARITY_MASK; 361 WREG32(mmDC_HPD5_INT_CONTROL, tmp); 362 break; 363 case AMDGPU_HPD_6: 364 tmp = RREG32(mmDC_HPD6_INT_CONTROL); 365 if (connected) 366 tmp &= ~DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 367 else 368 tmp |= DC_HPD6_INT_CONTROL__DC_HPD6_INT_POLARITY_MASK; 369 WREG32(mmDC_HPD6_INT_CONTROL, tmp); 370 break; 371 default: 372 break; 373 } 374 } 375 376 /** 377 * dce_v8_0_hpd_init - hpd setup callback. 378 * 379 * @adev: amdgpu_device pointer 380 * 381 * Setup the hpd pins used by the card (evergreen+). 382 * Enable the pin, set the polarity, and enable the hpd interrupts. 383 */ 384 static void dce_v8_0_hpd_init(struct amdgpu_device *adev) 385 { 386 struct drm_device *dev = adev->ddev; 387 struct drm_connector *connector; 388 u32 tmp = (0x9c4 << DC_HPD1_CONTROL__DC_HPD1_CONNECTION_TIMER__SHIFT) | 389 (0xfa << DC_HPD1_CONTROL__DC_HPD1_RX_INT_TIMER__SHIFT) | 390 DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 391 392 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 393 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 394 395 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 396 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 397 /* don't try to enable hpd on eDP or LVDS avoid breaking the 398 * aux dp channel on imac and help (but not completely fix) 399 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 400 * also avoid interrupt storms during dpms. 401 */ 402 continue; 403 } 404 switch (amdgpu_connector->hpd.hpd) { 405 case AMDGPU_HPD_1: 406 WREG32(mmDC_HPD1_CONTROL, tmp); 407 break; 408 case AMDGPU_HPD_2: 409 WREG32(mmDC_HPD2_CONTROL, tmp); 410 break; 411 case AMDGPU_HPD_3: 412 WREG32(mmDC_HPD3_CONTROL, tmp); 413 break; 414 case AMDGPU_HPD_4: 415 WREG32(mmDC_HPD4_CONTROL, tmp); 416 break; 417 case AMDGPU_HPD_5: 418 WREG32(mmDC_HPD5_CONTROL, tmp); 419 break; 420 case AMDGPU_HPD_6: 421 WREG32(mmDC_HPD6_CONTROL, tmp); 422 break; 423 default: 424 break; 425 } 426 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 427 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 428 } 429 } 430 431 /** 432 * dce_v8_0_hpd_fini - hpd tear down callback. 433 * 434 * @adev: amdgpu_device pointer 435 * 436 * Tear down the hpd pins used by the card (evergreen+). 437 * Disable the hpd interrupts. 438 */ 439 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) 440 { 441 struct drm_device *dev = adev->ddev; 442 struct drm_connector *connector; 443 444 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 445 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 446 447 switch (amdgpu_connector->hpd.hpd) { 448 case AMDGPU_HPD_1: 449 WREG32(mmDC_HPD1_CONTROL, 0); 450 break; 451 case AMDGPU_HPD_2: 452 WREG32(mmDC_HPD2_CONTROL, 0); 453 break; 454 case AMDGPU_HPD_3: 455 WREG32(mmDC_HPD3_CONTROL, 0); 456 break; 457 case AMDGPU_HPD_4: 458 WREG32(mmDC_HPD4_CONTROL, 0); 459 break; 460 case AMDGPU_HPD_5: 461 WREG32(mmDC_HPD5_CONTROL, 0); 462 break; 463 case AMDGPU_HPD_6: 464 WREG32(mmDC_HPD6_CONTROL, 0); 465 break; 466 default: 467 break; 468 } 469 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 470 } 471 } 472 473 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 474 { 475 return mmDC_GPIO_HPD_A; 476 } 477 478 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) 479 { 480 u32 crtc_hung = 0; 481 u32 crtc_status[6]; 482 u32 i, j, tmp; 483 484 for (i = 0; i < adev->mode_info.num_crtc; i++) { 485 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 486 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 487 crtc_hung |= (1 << i); 488 } 489 } 490 491 for (j = 0; j < 10; j++) { 492 for (i = 0; i < adev->mode_info.num_crtc; i++) { 493 if (crtc_hung & (1 << i)) { 494 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 495 if (tmp != crtc_status[i]) 496 crtc_hung &= ~(1 << i); 497 } 498 } 499 if (crtc_hung == 0) 500 return false; 501 udelay(100); 502 } 503 504 return true; 505 } 506 507 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, 508 struct amdgpu_mode_mc_save *save) 509 { 510 u32 crtc_enabled, tmp; 511 int i; 512 513 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 514 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 515 516 /* disable VGA render */ 517 tmp = RREG32(mmVGA_RENDER_CONTROL); 518 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 519 WREG32(mmVGA_RENDER_CONTROL, tmp); 520 521 /* blank the display controllers */ 522 for (i = 0; i < adev->mode_info.num_crtc; i++) { 523 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 524 CRTC_CONTROL, CRTC_MASTER_EN); 525 if (crtc_enabled) { 526 #if 0 527 u32 frame_count; 528 int j; 529 530 save->crtc_enabled[i] = true; 531 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 532 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 533 amdgpu_display_vblank_wait(adev, i); 534 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 535 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 536 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 537 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 538 } 539 /* wait for the next frame */ 540 frame_count = amdgpu_display_vblank_get_counter(adev, i); 541 for (j = 0; j < adev->usec_timeout; j++) { 542 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 543 break; 544 udelay(1); 545 } 546 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 547 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 548 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 549 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 550 } 551 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 552 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 553 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 554 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 555 } 556 #else 557 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 558 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 559 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 560 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 561 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 562 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 563 save->crtc_enabled[i] = false; 564 /* ***** */ 565 #endif 566 } else { 567 save->crtc_enabled[i] = false; 568 } 569 } 570 } 571 572 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, 573 struct amdgpu_mode_mc_save *save) 574 { 575 u32 tmp, frame_count; 576 int i, j; 577 578 /* update crtc base addresses */ 579 for (i = 0; i < adev->mode_info.num_crtc; i++) { 580 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 581 upper_32_bits(adev->mc.vram_start)); 582 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 583 upper_32_bits(adev->mc.vram_start)); 584 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 585 (u32)adev->mc.vram_start); 586 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 587 (u32)adev->mc.vram_start); 588 589 if (save->crtc_enabled[i]) { 590 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 591 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 592 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 593 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 594 } 595 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 596 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 597 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 598 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 599 } 600 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 601 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 602 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 603 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 604 } 605 for (j = 0; j < adev->usec_timeout; j++) { 606 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 607 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 608 break; 609 udelay(1); 610 } 611 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 612 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 613 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 614 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 615 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 616 /* wait for the next frame */ 617 frame_count = amdgpu_display_vblank_get_counter(adev, i); 618 for (j = 0; j < adev->usec_timeout; j++) { 619 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 620 break; 621 udelay(1); 622 } 623 } 624 } 625 626 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 627 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 628 629 /* Unlock vga access */ 630 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 631 mdelay(1); 632 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 633 } 634 635 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, 636 bool render) 637 { 638 u32 tmp; 639 640 /* Lockout access through VGA aperture*/ 641 tmp = RREG32(mmVGA_HDP_CONTROL); 642 if (render) 643 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 644 else 645 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 646 WREG32(mmVGA_HDP_CONTROL, tmp); 647 648 /* disable VGA render */ 649 tmp = RREG32(mmVGA_RENDER_CONTROL); 650 if (render) 651 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 652 else 653 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 654 WREG32(mmVGA_RENDER_CONTROL, tmp); 655 } 656 657 static void dce_v8_0_program_fmt(struct drm_encoder *encoder) 658 { 659 struct drm_device *dev = encoder->dev; 660 struct amdgpu_device *adev = dev->dev_private; 661 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 662 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 663 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 664 int bpc = 0; 665 u32 tmp = 0; 666 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 667 668 if (connector) { 669 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 670 bpc = amdgpu_connector_get_monitor_bpc(connector); 671 dither = amdgpu_connector->dither; 672 } 673 674 /* LVDS/eDP FMT is set up by atom */ 675 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 676 return; 677 678 /* not needed for analog */ 679 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 680 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 681 return; 682 683 if (bpc == 0) 684 return; 685 686 switch (bpc) { 687 case 6: 688 if (dither == AMDGPU_FMT_DITHER_ENABLE) 689 /* XXX sort out optimal dither settings */ 690 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 691 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 692 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 693 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 694 else 695 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 696 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 697 break; 698 case 8: 699 if (dither == AMDGPU_FMT_DITHER_ENABLE) 700 /* XXX sort out optimal dither settings */ 701 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 702 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 703 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 704 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 705 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 706 else 707 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 708 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 709 break; 710 case 10: 711 if (dither == AMDGPU_FMT_DITHER_ENABLE) 712 /* XXX sort out optimal dither settings */ 713 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 714 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 715 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 716 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 717 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 718 else 719 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 720 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 721 break; 722 default: 723 /* not needed */ 724 break; 725 } 726 727 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 728 } 729 730 731 /* display watermark setup */ 732 /** 733 * dce_v8_0_line_buffer_adjust - Set up the line buffer 734 * 735 * @adev: amdgpu_device pointer 736 * @amdgpu_crtc: the selected display controller 737 * @mode: the current display mode on the selected display 738 * controller 739 * 740 * Setup up the line buffer allocation for 741 * the selected display controller (CIK). 742 * Returns the line buffer size in pixels. 743 */ 744 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, 745 struct amdgpu_crtc *amdgpu_crtc, 746 struct drm_display_mode *mode) 747 { 748 u32 tmp, buffer_alloc, i; 749 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 750 /* 751 * Line Buffer Setup 752 * There are 6 line buffers, one for each display controllers. 753 * There are 3 partitions per LB. Select the number of partitions 754 * to enable based on the display width. For display widths larger 755 * than 4096, you need use to use 2 display controllers and combine 756 * them using the stereo blender. 757 */ 758 if (amdgpu_crtc->base.enabled && mode) { 759 if (mode->crtc_hdisplay < 1920) { 760 tmp = 1; 761 buffer_alloc = 2; 762 } else if (mode->crtc_hdisplay < 2560) { 763 tmp = 2; 764 buffer_alloc = 2; 765 } else if (mode->crtc_hdisplay < 4096) { 766 tmp = 0; 767 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 768 } else { 769 DRM_DEBUG_KMS("Mode too big for LB!\n"); 770 tmp = 0; 771 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 772 } 773 } else { 774 tmp = 1; 775 buffer_alloc = 0; 776 } 777 778 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, 779 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) | 780 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT)); 781 782 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 783 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 784 for (i = 0; i < adev->usec_timeout; i++) { 785 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 786 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 787 break; 788 udelay(1); 789 } 790 791 if (amdgpu_crtc->base.enabled && mode) { 792 switch (tmp) { 793 case 0: 794 default: 795 return 4096 * 2; 796 case 1: 797 return 1920 * 2; 798 case 2: 799 return 2560 * 2; 800 } 801 } 802 803 /* controller not enabled, so no lb used */ 804 return 0; 805 } 806 807 /** 808 * cik_get_number_of_dram_channels - get the number of dram channels 809 * 810 * @adev: amdgpu_device pointer 811 * 812 * Look up the number of video ram channels (CIK). 813 * Used for display watermark bandwidth calculations 814 * Returns the number of dram channels 815 */ 816 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 817 { 818 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 819 820 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 821 case 0: 822 default: 823 return 1; 824 case 1: 825 return 2; 826 case 2: 827 return 4; 828 case 3: 829 return 8; 830 case 4: 831 return 3; 832 case 5: 833 return 6; 834 case 6: 835 return 10; 836 case 7: 837 return 12; 838 case 8: 839 return 16; 840 } 841 } 842 843 struct dce8_wm_params { 844 u32 dram_channels; /* number of dram channels */ 845 u32 yclk; /* bandwidth per dram data pin in kHz */ 846 u32 sclk; /* engine clock in kHz */ 847 u32 disp_clk; /* display clock in kHz */ 848 u32 src_width; /* viewport width */ 849 u32 active_time; /* active display time in ns */ 850 u32 blank_time; /* blank time in ns */ 851 bool interlaced; /* mode is interlaced */ 852 fixed20_12 vsc; /* vertical scale ratio */ 853 u32 num_heads; /* number of active crtcs */ 854 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 855 u32 lb_size; /* line buffer allocated to pipe */ 856 u32 vtaps; /* vertical scaler taps */ 857 }; 858 859 /** 860 * dce_v8_0_dram_bandwidth - get the dram bandwidth 861 * 862 * @wm: watermark calculation data 863 * 864 * Calculate the raw dram bandwidth (CIK). 865 * Used for display watermark bandwidth calculations 866 * Returns the dram bandwidth in MBytes/s 867 */ 868 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) 869 { 870 /* Calculate raw DRAM Bandwidth */ 871 fixed20_12 dram_efficiency; /* 0.7 */ 872 fixed20_12 yclk, dram_channels, bandwidth; 873 fixed20_12 a; 874 875 a.full = dfixed_const(1000); 876 yclk.full = dfixed_const(wm->yclk); 877 yclk.full = dfixed_div(yclk, a); 878 dram_channels.full = dfixed_const(wm->dram_channels * 4); 879 a.full = dfixed_const(10); 880 dram_efficiency.full = dfixed_const(7); 881 dram_efficiency.full = dfixed_div(dram_efficiency, a); 882 bandwidth.full = dfixed_mul(dram_channels, yclk); 883 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 884 885 return dfixed_trunc(bandwidth); 886 } 887 888 /** 889 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display 890 * 891 * @wm: watermark calculation data 892 * 893 * Calculate the dram bandwidth used for display (CIK). 894 * Used for display watermark bandwidth calculations 895 * Returns the dram bandwidth for display in MBytes/s 896 */ 897 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) 898 { 899 /* Calculate DRAM Bandwidth and the part allocated to display. */ 900 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 901 fixed20_12 yclk, dram_channels, bandwidth; 902 fixed20_12 a; 903 904 a.full = dfixed_const(1000); 905 yclk.full = dfixed_const(wm->yclk); 906 yclk.full = dfixed_div(yclk, a); 907 dram_channels.full = dfixed_const(wm->dram_channels * 4); 908 a.full = dfixed_const(10); 909 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 910 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 911 bandwidth.full = dfixed_mul(dram_channels, yclk); 912 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 913 914 return dfixed_trunc(bandwidth); 915 } 916 917 /** 918 * dce_v8_0_data_return_bandwidth - get the data return bandwidth 919 * 920 * @wm: watermark calculation data 921 * 922 * Calculate the data return bandwidth used for display (CIK). 923 * Used for display watermark bandwidth calculations 924 * Returns the data return bandwidth in MBytes/s 925 */ 926 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) 927 { 928 /* Calculate the display Data return Bandwidth */ 929 fixed20_12 return_efficiency; /* 0.8 */ 930 fixed20_12 sclk, bandwidth; 931 fixed20_12 a; 932 933 a.full = dfixed_const(1000); 934 sclk.full = dfixed_const(wm->sclk); 935 sclk.full = dfixed_div(sclk, a); 936 a.full = dfixed_const(10); 937 return_efficiency.full = dfixed_const(8); 938 return_efficiency.full = dfixed_div(return_efficiency, a); 939 a.full = dfixed_const(32); 940 bandwidth.full = dfixed_mul(a, sclk); 941 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 942 943 return dfixed_trunc(bandwidth); 944 } 945 946 /** 947 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth 948 * 949 * @wm: watermark calculation data 950 * 951 * Calculate the dmif bandwidth used for display (CIK). 952 * Used for display watermark bandwidth calculations 953 * Returns the dmif bandwidth in MBytes/s 954 */ 955 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) 956 { 957 /* Calculate the DMIF Request Bandwidth */ 958 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 959 fixed20_12 disp_clk, bandwidth; 960 fixed20_12 a, b; 961 962 a.full = dfixed_const(1000); 963 disp_clk.full = dfixed_const(wm->disp_clk); 964 disp_clk.full = dfixed_div(disp_clk, a); 965 a.full = dfixed_const(32); 966 b.full = dfixed_mul(a, disp_clk); 967 968 a.full = dfixed_const(10); 969 disp_clk_request_efficiency.full = dfixed_const(8); 970 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 971 972 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 973 974 return dfixed_trunc(bandwidth); 975 } 976 977 /** 978 * dce_v8_0_available_bandwidth - get the min available bandwidth 979 * 980 * @wm: watermark calculation data 981 * 982 * Calculate the min available bandwidth used for display (CIK). 983 * Used for display watermark bandwidth calculations 984 * Returns the min available bandwidth in MBytes/s 985 */ 986 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm) 987 { 988 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 989 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm); 990 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm); 991 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm); 992 993 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 994 } 995 996 /** 997 * dce_v8_0_average_bandwidth - get the average available bandwidth 998 * 999 * @wm: watermark calculation data 1000 * 1001 * Calculate the average available bandwidth used for display (CIK). 1002 * Used for display watermark bandwidth calculations 1003 * Returns the average available bandwidth in MBytes/s 1004 */ 1005 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm) 1006 { 1007 /* Calculate the display mode Average Bandwidth 1008 * DisplayMode should contain the source and destination dimensions, 1009 * timing, etc. 1010 */ 1011 fixed20_12 bpp; 1012 fixed20_12 line_time; 1013 fixed20_12 src_width; 1014 fixed20_12 bandwidth; 1015 fixed20_12 a; 1016 1017 a.full = dfixed_const(1000); 1018 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1019 line_time.full = dfixed_div(line_time, a); 1020 bpp.full = dfixed_const(wm->bytes_per_pixel); 1021 src_width.full = dfixed_const(wm->src_width); 1022 bandwidth.full = dfixed_mul(src_width, bpp); 1023 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1024 bandwidth.full = dfixed_div(bandwidth, line_time); 1025 1026 return dfixed_trunc(bandwidth); 1027 } 1028 1029 /** 1030 * dce_v8_0_latency_watermark - get the latency watermark 1031 * 1032 * @wm: watermark calculation data 1033 * 1034 * Calculate the latency watermark (CIK). 1035 * Used for display watermark bandwidth calculations 1036 * Returns the latency watermark in ns 1037 */ 1038 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) 1039 { 1040 /* First calculate the latency in ns */ 1041 u32 mc_latency = 2000; /* 2000 ns. */ 1042 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm); 1043 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1044 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1045 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1046 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1047 (wm->num_heads * cursor_line_pair_return_time); 1048 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1049 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1050 u32 tmp, dmif_size = 12288; 1051 fixed20_12 a, b, c; 1052 1053 if (wm->num_heads == 0) 1054 return 0; 1055 1056 a.full = dfixed_const(2); 1057 b.full = dfixed_const(1); 1058 if ((wm->vsc.full > a.full) || 1059 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1060 (wm->vtaps >= 5) || 1061 ((wm->vsc.full >= a.full) && wm->interlaced)) 1062 max_src_lines_per_dst_line = 4; 1063 else 1064 max_src_lines_per_dst_line = 2; 1065 1066 a.full = dfixed_const(available_bandwidth); 1067 b.full = dfixed_const(wm->num_heads); 1068 a.full = dfixed_div(a, b); 1069 1070 b.full = dfixed_const(mc_latency + 512); 1071 c.full = dfixed_const(wm->disp_clk); 1072 b.full = dfixed_div(b, c); 1073 1074 c.full = dfixed_const(dmif_size); 1075 b.full = dfixed_div(c, b); 1076 1077 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1078 1079 b.full = dfixed_const(1000); 1080 c.full = dfixed_const(wm->disp_clk); 1081 b.full = dfixed_div(c, b); 1082 c.full = dfixed_const(wm->bytes_per_pixel); 1083 b.full = dfixed_mul(b, c); 1084 1085 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1086 1087 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1088 b.full = dfixed_const(1000); 1089 c.full = dfixed_const(lb_fill_bw); 1090 b.full = dfixed_div(c, b); 1091 a.full = dfixed_div(a, b); 1092 line_fill_time = dfixed_trunc(a); 1093 1094 if (line_fill_time < wm->active_time) 1095 return latency; 1096 else 1097 return latency + (line_fill_time - wm->active_time); 1098 1099 } 1100 1101 /** 1102 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1103 * average and available dram bandwidth 1104 * 1105 * @wm: watermark calculation data 1106 * 1107 * Check if the display average bandwidth fits in the display 1108 * dram bandwidth (CIK). 1109 * Used for display watermark bandwidth calculations 1110 * Returns true if the display fits, false if not. 1111 */ 1112 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) 1113 { 1114 if (dce_v8_0_average_bandwidth(wm) <= 1115 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1116 return true; 1117 else 1118 return false; 1119 } 1120 1121 /** 1122 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check 1123 * average and available bandwidth 1124 * 1125 * @wm: watermark calculation data 1126 * 1127 * Check if the display average bandwidth fits in the display 1128 * available bandwidth (CIK). 1129 * Used for display watermark bandwidth calculations 1130 * Returns true if the display fits, false if not. 1131 */ 1132 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) 1133 { 1134 if (dce_v8_0_average_bandwidth(wm) <= 1135 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) 1136 return true; 1137 else 1138 return false; 1139 } 1140 1141 /** 1142 * dce_v8_0_check_latency_hiding - check latency hiding 1143 * 1144 * @wm: watermark calculation data 1145 * 1146 * Check latency hiding (CIK). 1147 * Used for display watermark bandwidth calculations 1148 * Returns true if the display fits, false if not. 1149 */ 1150 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm) 1151 { 1152 u32 lb_partitions = wm->lb_size / wm->src_width; 1153 u32 line_time = wm->active_time + wm->blank_time; 1154 u32 latency_tolerant_lines; 1155 u32 latency_hiding; 1156 fixed20_12 a; 1157 1158 a.full = dfixed_const(1); 1159 if (wm->vsc.full > a.full) 1160 latency_tolerant_lines = 1; 1161 else { 1162 if (lb_partitions <= (wm->vtaps + 1)) 1163 latency_tolerant_lines = 1; 1164 else 1165 latency_tolerant_lines = 2; 1166 } 1167 1168 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1169 1170 if (dce_v8_0_latency_watermark(wm) <= latency_hiding) 1171 return true; 1172 else 1173 return false; 1174 } 1175 1176 /** 1177 * dce_v8_0_program_watermarks - program display watermarks 1178 * 1179 * @adev: amdgpu_device pointer 1180 * @amdgpu_crtc: the selected display controller 1181 * @lb_size: line buffer size 1182 * @num_heads: number of display controllers in use 1183 * 1184 * Calculate and program the display watermarks for the 1185 * selected display controller (CIK). 1186 */ 1187 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, 1188 struct amdgpu_crtc *amdgpu_crtc, 1189 u32 lb_size, u32 num_heads) 1190 { 1191 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1192 struct dce8_wm_params wm_low, wm_high; 1193 u32 pixel_period; 1194 u32 line_time = 0; 1195 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1196 u32 tmp, wm_mask; 1197 1198 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1199 pixel_period = 1000000 / (u32)mode->clock; 1200 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1201 1202 /* watermark for high clocks */ 1203 if (adev->pm.dpm_enabled) { 1204 wm_high.yclk = 1205 amdgpu_dpm_get_mclk(adev, false) * 10; 1206 wm_high.sclk = 1207 amdgpu_dpm_get_sclk(adev, false) * 10; 1208 } else { 1209 wm_high.yclk = adev->pm.current_mclk * 10; 1210 wm_high.sclk = adev->pm.current_sclk * 10; 1211 } 1212 1213 wm_high.disp_clk = mode->clock; 1214 wm_high.src_width = mode->crtc_hdisplay; 1215 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1216 wm_high.blank_time = line_time - wm_high.active_time; 1217 wm_high.interlaced = false; 1218 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1219 wm_high.interlaced = true; 1220 wm_high.vsc = amdgpu_crtc->vsc; 1221 wm_high.vtaps = 1; 1222 if (amdgpu_crtc->rmx_type != RMX_OFF) 1223 wm_high.vtaps = 2; 1224 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1225 wm_high.lb_size = lb_size; 1226 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1227 wm_high.num_heads = num_heads; 1228 1229 /* set for high clocks */ 1230 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535); 1231 1232 /* possibly force display priority to high */ 1233 /* should really do this at mode validation time... */ 1234 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1235 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1236 !dce_v8_0_check_latency_hiding(&wm_high) || 1237 (adev->mode_info.disp_priority == 2)) { 1238 DRM_DEBUG_KMS("force priority to high\n"); 1239 } 1240 1241 /* watermark for low clocks */ 1242 if (adev->pm.dpm_enabled) { 1243 wm_low.yclk = 1244 amdgpu_dpm_get_mclk(adev, true) * 10; 1245 wm_low.sclk = 1246 amdgpu_dpm_get_sclk(adev, true) * 10; 1247 } else { 1248 wm_low.yclk = adev->pm.current_mclk * 10; 1249 wm_low.sclk = adev->pm.current_sclk * 10; 1250 } 1251 1252 wm_low.disp_clk = mode->clock; 1253 wm_low.src_width = mode->crtc_hdisplay; 1254 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1255 wm_low.blank_time = line_time - wm_low.active_time; 1256 wm_low.interlaced = false; 1257 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1258 wm_low.interlaced = true; 1259 wm_low.vsc = amdgpu_crtc->vsc; 1260 wm_low.vtaps = 1; 1261 if (amdgpu_crtc->rmx_type != RMX_OFF) 1262 wm_low.vtaps = 2; 1263 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1264 wm_low.lb_size = lb_size; 1265 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1266 wm_low.num_heads = num_heads; 1267 1268 /* set for low clocks */ 1269 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535); 1270 1271 /* possibly force display priority to high */ 1272 /* should really do this at mode validation time... */ 1273 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1274 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1275 !dce_v8_0_check_latency_hiding(&wm_low) || 1276 (adev->mode_info.disp_priority == 2)) { 1277 DRM_DEBUG_KMS("force priority to high\n"); 1278 } 1279 } 1280 1281 /* select wm A */ 1282 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1283 tmp = wm_mask; 1284 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1285 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1286 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1287 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1288 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1289 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1290 /* select wm B */ 1291 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1292 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1293 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1294 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1295 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1296 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1297 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1298 /* restore original selection */ 1299 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1300 1301 /* save values for DPM */ 1302 amdgpu_crtc->line_time = line_time; 1303 amdgpu_crtc->wm_high = latency_watermark_a; 1304 amdgpu_crtc->wm_low = latency_watermark_b; 1305 } 1306 1307 /** 1308 * dce_v8_0_bandwidth_update - program display watermarks 1309 * 1310 * @adev: amdgpu_device pointer 1311 * 1312 * Calculate and program the display watermarks and line 1313 * buffer allocation (CIK). 1314 */ 1315 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev) 1316 { 1317 struct drm_display_mode *mode = NULL; 1318 u32 num_heads = 0, lb_size; 1319 int i; 1320 1321 amdgpu_update_display_priority(adev); 1322 1323 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1324 if (adev->mode_info.crtcs[i]->base.enabled) 1325 num_heads++; 1326 } 1327 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1328 mode = &adev->mode_info.crtcs[i]->base.mode; 1329 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1330 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1331 lb_size, num_heads); 1332 } 1333 } 1334 1335 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev) 1336 { 1337 int i; 1338 u32 offset, tmp; 1339 1340 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1341 offset = adev->mode_info.audio.pin[i].offset; 1342 tmp = RREG32_AUDIO_ENDPT(offset, 1343 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1344 if (((tmp & 1345 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1346 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1347 adev->mode_info.audio.pin[i].connected = false; 1348 else 1349 adev->mode_info.audio.pin[i].connected = true; 1350 } 1351 } 1352 1353 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev) 1354 { 1355 int i; 1356 1357 dce_v8_0_audio_get_connected_pins(adev); 1358 1359 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1360 if (adev->mode_info.audio.pin[i].connected) 1361 return &adev->mode_info.audio.pin[i]; 1362 } 1363 DRM_ERROR("No connected audio pins found!\n"); 1364 return NULL; 1365 } 1366 1367 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1368 { 1369 struct amdgpu_device *adev = encoder->dev->dev_private; 1370 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1371 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1372 u32 offset; 1373 1374 if (!dig || !dig->afmt || !dig->afmt->pin) 1375 return; 1376 1377 offset = dig->afmt->offset; 1378 1379 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, 1380 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT)); 1381 } 1382 1383 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, 1384 struct drm_display_mode *mode) 1385 { 1386 struct amdgpu_device *adev = encoder->dev->dev_private; 1387 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1388 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1389 struct drm_connector *connector; 1390 struct amdgpu_connector *amdgpu_connector = NULL; 1391 u32 tmp = 0, offset; 1392 1393 if (!dig || !dig->afmt || !dig->afmt->pin) 1394 return; 1395 1396 offset = dig->afmt->pin->offset; 1397 1398 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1399 if (connector->encoder == encoder) { 1400 amdgpu_connector = to_amdgpu_connector(connector); 1401 break; 1402 } 1403 } 1404 1405 if (!amdgpu_connector) { 1406 DRM_ERROR("Couldn't find encoder's connector\n"); 1407 return; 1408 } 1409 1410 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1411 if (connector->latency_present[1]) 1412 tmp = 1413 (connector->video_latency[1] << 1414 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1415 (connector->audio_latency[1] << 1416 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1417 else 1418 tmp = 1419 (0 << 1420 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1421 (0 << 1422 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1423 } else { 1424 if (connector->latency_present[0]) 1425 tmp = 1426 (connector->video_latency[0] << 1427 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1428 (connector->audio_latency[0] << 1429 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1430 else 1431 tmp = 1432 (0 << 1433 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1434 (0 << 1435 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1436 1437 } 1438 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1439 } 1440 1441 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1442 { 1443 struct amdgpu_device *adev = encoder->dev->dev_private; 1444 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1445 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1446 struct drm_connector *connector; 1447 struct amdgpu_connector *amdgpu_connector = NULL; 1448 u32 offset, tmp; 1449 u8 *sadb = NULL; 1450 int sad_count; 1451 1452 if (!dig || !dig->afmt || !dig->afmt->pin) 1453 return; 1454 1455 offset = dig->afmt->pin->offset; 1456 1457 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1458 if (connector->encoder == encoder) { 1459 amdgpu_connector = to_amdgpu_connector(connector); 1460 break; 1461 } 1462 } 1463 1464 if (!amdgpu_connector) { 1465 DRM_ERROR("Couldn't find encoder's connector\n"); 1466 return; 1467 } 1468 1469 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1470 if (sad_count < 0) { 1471 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1472 sad_count = 0; 1473 } 1474 1475 /* program the speaker allocation */ 1476 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1477 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK | 1478 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK); 1479 /* set HDMI mode */ 1480 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK; 1481 if (sad_count) 1482 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); 1483 else 1484 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */ 1485 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1486 1487 kfree(sadb); 1488 } 1489 1490 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) 1491 { 1492 struct amdgpu_device *adev = encoder->dev->dev_private; 1493 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1494 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1495 u32 offset; 1496 struct drm_connector *connector; 1497 struct amdgpu_connector *amdgpu_connector = NULL; 1498 struct cea_sad *sads; 1499 int i, sad_count; 1500 1501 static const u16 eld_reg_to_type[][2] = { 1502 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1503 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1504 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1505 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1506 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1507 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1508 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1509 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1510 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1511 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1512 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1514 }; 1515 1516 if (!dig || !dig->afmt || !dig->afmt->pin) 1517 return; 1518 1519 offset = dig->afmt->pin->offset; 1520 1521 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1522 if (connector->encoder == encoder) { 1523 amdgpu_connector = to_amdgpu_connector(connector); 1524 break; 1525 } 1526 } 1527 1528 if (!amdgpu_connector) { 1529 DRM_ERROR("Couldn't find encoder's connector\n"); 1530 return; 1531 } 1532 1533 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1534 if (sad_count <= 0) { 1535 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1536 return; 1537 } 1538 BUG_ON(!sads); 1539 1540 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1541 u32 value = 0; 1542 u8 stereo_freqs = 0; 1543 int max_channels = -1; 1544 int j; 1545 1546 for (j = 0; j < sad_count; j++) { 1547 struct cea_sad *sad = &sads[j]; 1548 1549 if (sad->format == eld_reg_to_type[i][1]) { 1550 if (sad->channels > max_channels) { 1551 value = (sad->channels << 1552 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | 1553 (sad->byte2 << 1554 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | 1555 (sad->freq << 1556 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); 1557 max_channels = sad->channels; 1558 } 1559 1560 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1561 stereo_freqs |= sad->freq; 1562 else 1563 break; 1564 } 1565 } 1566 1567 value |= (stereo_freqs << 1568 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); 1569 1570 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); 1571 } 1572 1573 kfree(sads); 1574 } 1575 1576 static void dce_v8_0_audio_enable(struct amdgpu_device *adev, 1577 struct amdgpu_audio_pin *pin, 1578 bool enable) 1579 { 1580 if (!pin) 1581 return; 1582 1583 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1584 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1585 } 1586 1587 static const u32 pin_offsets[7] = 1588 { 1589 (0x1780 - 0x1780), 1590 (0x1786 - 0x1780), 1591 (0x178c - 0x1780), 1592 (0x1792 - 0x1780), 1593 (0x1798 - 0x1780), 1594 (0x179d - 0x1780), 1595 (0x17a4 - 0x1780), 1596 }; 1597 1598 static int dce_v8_0_audio_init(struct amdgpu_device *adev) 1599 { 1600 int i; 1601 1602 if (!amdgpu_audio) 1603 return 0; 1604 1605 adev->mode_info.audio.enabled = true; 1606 1607 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */ 1608 adev->mode_info.audio.num_pins = 7; 1609 else if ((adev->asic_type == CHIP_KABINI) || 1610 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */ 1611 adev->mode_info.audio.num_pins = 3; 1612 else if ((adev->asic_type == CHIP_BONAIRE) || 1613 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */ 1614 adev->mode_info.audio.num_pins = 7; 1615 else 1616 adev->mode_info.audio.num_pins = 3; 1617 1618 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1619 adev->mode_info.audio.pin[i].channels = -1; 1620 adev->mode_info.audio.pin[i].rate = -1; 1621 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1622 adev->mode_info.audio.pin[i].status_bits = 0; 1623 adev->mode_info.audio.pin[i].category_code = 0; 1624 adev->mode_info.audio.pin[i].connected = false; 1625 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1626 adev->mode_info.audio.pin[i].id = i; 1627 /* disable audio. it will be set up later */ 1628 /* XXX remove once we switch to ip funcs */ 1629 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1630 } 1631 1632 return 0; 1633 } 1634 1635 static void dce_v8_0_audio_fini(struct amdgpu_device *adev) 1636 { 1637 int i; 1638 1639 if (!adev->mode_info.audio.enabled) 1640 return; 1641 1642 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1643 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1644 1645 adev->mode_info.audio.enabled = false; 1646 } 1647 1648 /* 1649 * update the N and CTS parameters for a given pixel clock rate 1650 */ 1651 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1652 { 1653 struct drm_device *dev = encoder->dev; 1654 struct amdgpu_device *adev = dev->dev_private; 1655 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1656 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1657 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1658 uint32_t offset = dig->afmt->offset; 1659 1660 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1661 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); 1662 1663 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1664 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); 1665 1666 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); 1667 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); 1668 } 1669 1670 /* 1671 * build a HDMI Video Info Frame 1672 */ 1673 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1674 void *buffer, size_t size) 1675 { 1676 struct drm_device *dev = encoder->dev; 1677 struct amdgpu_device *adev = dev->dev_private; 1678 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1679 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1680 uint32_t offset = dig->afmt->offset; 1681 uint8_t *frame = buffer + 3; 1682 uint8_t *header = buffer; 1683 1684 WREG32(mmAFMT_AVI_INFO0 + offset, 1685 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1686 WREG32(mmAFMT_AVI_INFO1 + offset, 1687 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1688 WREG32(mmAFMT_AVI_INFO2 + offset, 1689 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1690 WREG32(mmAFMT_AVI_INFO3 + offset, 1691 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1692 } 1693 1694 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1695 { 1696 struct drm_device *dev = encoder->dev; 1697 struct amdgpu_device *adev = dev->dev_private; 1698 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1699 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1700 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1701 u32 dto_phase = 24 * 1000; 1702 u32 dto_modulo = clock; 1703 1704 if (!dig || !dig->afmt) 1705 return; 1706 1707 /* XXX two dtos; generally use dto0 for hdmi */ 1708 /* Express [24MHz / target pixel clock] as an exact rational 1709 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1710 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1711 */ 1712 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); 1713 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1714 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1715 } 1716 1717 /* 1718 * update the info frames with the data from the current display mode 1719 */ 1720 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, 1721 struct drm_display_mode *mode) 1722 { 1723 struct drm_device *dev = encoder->dev; 1724 struct amdgpu_device *adev = dev->dev_private; 1725 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1726 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1727 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1728 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1729 struct hdmi_avi_infoframe frame; 1730 uint32_t offset, val; 1731 ssize_t err; 1732 int bpc = 8; 1733 1734 if (!dig || !dig->afmt) 1735 return; 1736 1737 /* Silent, r600_hdmi_enable will raise WARN for us */ 1738 if (!dig->afmt->enabled) 1739 return; 1740 offset = dig->afmt->offset; 1741 1742 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1743 if (encoder->crtc) { 1744 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1745 bpc = amdgpu_crtc->bpc; 1746 } 1747 1748 /* disable audio prior to setting up hw */ 1749 dig->afmt->pin = dce_v8_0_audio_get_pin(adev); 1750 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1751 1752 dce_v8_0_audio_set_dto(encoder, mode->clock); 1753 1754 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1755 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */ 1756 1757 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 1758 1759 val = RREG32(mmHDMI_CONTROL + offset); 1760 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1761 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK; 1762 1763 switch (bpc) { 1764 case 0: 1765 case 6: 1766 case 8: 1767 case 16: 1768 default: 1769 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1770 connector->name, bpc); 1771 break; 1772 case 10: 1773 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1774 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1775 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1776 connector->name); 1777 break; 1778 case 12: 1779 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1780 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1781 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1782 connector->name); 1783 break; 1784 } 1785 1786 WREG32(mmHDMI_CONTROL + offset, val); 1787 1788 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1789 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */ 1790 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */ 1791 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */ 1792 1793 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, 1794 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */ 1795 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */ 1796 1797 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, 1798 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */ 1799 1800 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, 1801 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */ 1802 1803 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 1804 1805 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, 1806 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */ 1807 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */ 1808 1809 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1810 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */ 1811 1812 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 1813 1814 if (bpc > 8) 1815 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1816 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1817 else 1818 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1819 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */ 1820 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1821 1822 dce_v8_0_afmt_update_ACR(encoder, mode->clock); 1823 1824 WREG32(mmAFMT_60958_0 + offset, 1825 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT)); 1826 1827 WREG32(mmAFMT_60958_1 + offset, 1828 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT)); 1829 1830 WREG32(mmAFMT_60958_2 + offset, 1831 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) | 1832 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) | 1833 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) | 1834 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) | 1835 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) | 1836 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT)); 1837 1838 dce_v8_0_audio_write_speaker_allocation(encoder); 1839 1840 1841 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, 1842 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1843 1844 dce_v8_0_afmt_audio_select_pin(encoder); 1845 dce_v8_0_audio_write_sad_regs(encoder); 1846 dce_v8_0_audio_write_latency_fields(encoder, mode); 1847 1848 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1849 if (err < 0) { 1850 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1851 return; 1852 } 1853 1854 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1855 if (err < 0) { 1856 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1857 return; 1858 } 1859 1860 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1861 1862 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, 1863 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */ 1864 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK); /* required for audio info values to be updated */ 1865 1866 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, 1867 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */ 1868 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK); 1869 1870 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1871 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */ 1872 1873 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 1874 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 1875 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 1876 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); 1877 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); 1878 1879 /* enable audio after to setting up hw */ 1880 dce_v8_0_audio_enable(adev, dig->afmt->pin, true); 1881 } 1882 1883 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1884 { 1885 struct drm_device *dev = encoder->dev; 1886 struct amdgpu_device *adev = dev->dev_private; 1887 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1888 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1889 1890 if (!dig || !dig->afmt) 1891 return; 1892 1893 /* Silent, r600_hdmi_enable will raise WARN for us */ 1894 if (enable && dig->afmt->enabled) 1895 return; 1896 if (!enable && !dig->afmt->enabled) 1897 return; 1898 1899 if (!enable && dig->afmt->pin) { 1900 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1901 dig->afmt->pin = NULL; 1902 } 1903 1904 dig->afmt->enabled = enable; 1905 1906 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1907 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1908 } 1909 1910 static void dce_v8_0_afmt_init(struct amdgpu_device *adev) 1911 { 1912 int i; 1913 1914 for (i = 0; i < adev->mode_info.num_dig; i++) 1915 adev->mode_info.afmt[i] = NULL; 1916 1917 /* DCE8 has audio blocks tied to DIG encoders */ 1918 for (i = 0; i < adev->mode_info.num_dig; i++) { 1919 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1920 if (adev->mode_info.afmt[i]) { 1921 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1922 adev->mode_info.afmt[i]->id = i; 1923 } 1924 } 1925 } 1926 1927 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) 1928 { 1929 int i; 1930 1931 for (i = 0; i < adev->mode_info.num_dig; i++) { 1932 kfree(adev->mode_info.afmt[i]); 1933 adev->mode_info.afmt[i] = NULL; 1934 } 1935 } 1936 1937 static const u32 vga_control_regs[6] = 1938 { 1939 mmD1VGA_CONTROL, 1940 mmD2VGA_CONTROL, 1941 mmD3VGA_CONTROL, 1942 mmD4VGA_CONTROL, 1943 mmD5VGA_CONTROL, 1944 mmD6VGA_CONTROL, 1945 }; 1946 1947 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable) 1948 { 1949 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1950 struct drm_device *dev = crtc->dev; 1951 struct amdgpu_device *adev = dev->dev_private; 1952 u32 vga_control; 1953 1954 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1955 if (enable) 1956 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1957 else 1958 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1959 } 1960 1961 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) 1962 { 1963 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1964 struct drm_device *dev = crtc->dev; 1965 struct amdgpu_device *adev = dev->dev_private; 1966 1967 if (enable) 1968 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1969 else 1970 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1971 } 1972 1973 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 1974 struct drm_framebuffer *fb, 1975 int x, int y, int atomic) 1976 { 1977 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1978 struct drm_device *dev = crtc->dev; 1979 struct amdgpu_device *adev = dev->dev_private; 1980 struct amdgpu_framebuffer *amdgpu_fb; 1981 struct drm_framebuffer *target_fb; 1982 struct drm_gem_object *obj; 1983 struct amdgpu_bo *rbo; 1984 uint64_t fb_location, tiling_flags; 1985 uint32_t fb_format, fb_pitch_pixels; 1986 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1987 u32 pipe_config; 1988 u32 tmp, viewport_w, viewport_h; 1989 int r; 1990 bool bypass_lut = false; 1991 1992 /* no fb bound */ 1993 if (!atomic && !crtc->primary->fb) { 1994 DRM_DEBUG_KMS("No FB bound\n"); 1995 return 0; 1996 } 1997 1998 if (atomic) { 1999 amdgpu_fb = to_amdgpu_framebuffer(fb); 2000 target_fb = fb; 2001 } 2002 else { 2003 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2004 target_fb = crtc->primary->fb; 2005 } 2006 2007 /* If atomic, assume fb object is pinned & idle & fenced and 2008 * just update base pointers 2009 */ 2010 obj = amdgpu_fb->obj; 2011 rbo = gem_to_amdgpu_bo(obj); 2012 r = amdgpu_bo_reserve(rbo, false); 2013 if (unlikely(r != 0)) 2014 return r; 2015 2016 if (atomic) 2017 fb_location = amdgpu_bo_gpu_offset(rbo); 2018 else { 2019 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2020 if (unlikely(r != 0)) { 2021 amdgpu_bo_unreserve(rbo); 2022 return -EINVAL; 2023 } 2024 } 2025 2026 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2027 amdgpu_bo_unreserve(rbo); 2028 2029 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2030 2031 switch (target_fb->pixel_format) { 2032 case DRM_FORMAT_C8: 2033 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2034 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2035 break; 2036 case DRM_FORMAT_XRGB4444: 2037 case DRM_FORMAT_ARGB4444: 2038 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2039 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2040 #ifdef __BIG_ENDIAN 2041 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2042 #endif 2043 break; 2044 case DRM_FORMAT_XRGB1555: 2045 case DRM_FORMAT_ARGB1555: 2046 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2047 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2048 #ifdef __BIG_ENDIAN 2049 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2050 #endif 2051 break; 2052 case DRM_FORMAT_BGRX5551: 2053 case DRM_FORMAT_BGRA5551: 2054 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2055 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2056 #ifdef __BIG_ENDIAN 2057 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2058 #endif 2059 break; 2060 case DRM_FORMAT_RGB565: 2061 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2062 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2063 #ifdef __BIG_ENDIAN 2064 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2065 #endif 2066 break; 2067 case DRM_FORMAT_XRGB8888: 2068 case DRM_FORMAT_ARGB8888: 2069 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2070 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2071 #ifdef __BIG_ENDIAN 2072 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2073 #endif 2074 break; 2075 case DRM_FORMAT_XRGB2101010: 2076 case DRM_FORMAT_ARGB2101010: 2077 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2078 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2079 #ifdef __BIG_ENDIAN 2080 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2081 #endif 2082 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2083 bypass_lut = true; 2084 break; 2085 case DRM_FORMAT_BGRX1010102: 2086 case DRM_FORMAT_BGRA1010102: 2087 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 2088 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 2089 #ifdef __BIG_ENDIAN 2090 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2091 #endif 2092 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2093 bypass_lut = true; 2094 break; 2095 default: 2096 DRM_ERROR("Unsupported screen format %s\n", 2097 drm_get_format_name(target_fb->pixel_format)); 2098 return -EINVAL; 2099 } 2100 2101 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2102 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2103 2104 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2105 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2106 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2107 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2108 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2109 2110 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); 2111 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2112 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); 2113 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); 2114 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); 2115 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); 2116 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); 2117 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2118 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2119 } 2120 2121 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); 2122 2123 dce_v8_0_vga_enable(crtc, false); 2124 2125 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2126 upper_32_bits(fb_location)); 2127 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2128 upper_32_bits(fb_location)); 2129 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2130 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2131 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2132 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2133 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2134 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2135 2136 /* 2137 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2138 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2139 * retain the full precision throughout the pipeline. 2140 */ 2141 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, 2142 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0), 2143 ~LUT_10BIT_BYPASS_EN); 2144 2145 if (bypass_lut) 2146 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2147 2148 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2149 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2150 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2151 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2152 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2153 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2154 2155 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2156 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2157 2158 dce_v8_0_grph_enable(crtc, true); 2159 2160 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2161 target_fb->height); 2162 2163 x &= ~3; 2164 y &= ~1; 2165 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2166 (x << 16) | y); 2167 viewport_w = crtc->mode.hdisplay; 2168 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2169 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2170 (viewport_w << 16) | viewport_h); 2171 2172 /* pageflip setup */ 2173 /* make sure flip is at vb rather than hb */ 2174 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2175 tmp &= ~GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK; 2176 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2177 2178 /* set pageflip to happen only at start of vblank interval (front porch) */ 2179 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2180 2181 if (!atomic && fb && fb != crtc->primary->fb) { 2182 amdgpu_fb = to_amdgpu_framebuffer(fb); 2183 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2184 r = amdgpu_bo_reserve(rbo, false); 2185 if (unlikely(r != 0)) 2186 return r; 2187 amdgpu_bo_unpin(rbo); 2188 amdgpu_bo_unreserve(rbo); 2189 } 2190 2191 /* Bytes per pixel may have changed */ 2192 dce_v8_0_bandwidth_update(adev); 2193 2194 return 0; 2195 } 2196 2197 static void dce_v8_0_set_interleave(struct drm_crtc *crtc, 2198 struct drm_display_mode *mode) 2199 { 2200 struct drm_device *dev = crtc->dev; 2201 struct amdgpu_device *adev = dev->dev_private; 2202 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2203 2204 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2205 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 2206 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT); 2207 else 2208 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2209 } 2210 2211 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc) 2212 { 2213 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2214 struct drm_device *dev = crtc->dev; 2215 struct amdgpu_device *adev = dev->dev_private; 2216 int i; 2217 2218 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2219 2220 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2221 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2222 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2223 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2224 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2225 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2226 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2227 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2228 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2229 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2230 2231 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2232 2233 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2234 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2235 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2236 2237 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2238 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2239 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2240 2241 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2242 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2243 2244 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2245 for (i = 0; i < 256; i++) { 2246 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2247 (amdgpu_crtc->lut_r[i] << 20) | 2248 (amdgpu_crtc->lut_g[i] << 10) | 2249 (amdgpu_crtc->lut_b[i] << 0)); 2250 } 2251 2252 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2253 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2254 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2255 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2256 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2257 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2258 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2259 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2260 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2261 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2262 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2263 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2264 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2265 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2266 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2267 /* XXX this only needs to be programmed once per crtc at startup, 2268 * not sure where the best place for it is 2269 */ 2270 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, 2271 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK); 2272 } 2273 2274 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder) 2275 { 2276 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2278 2279 switch (amdgpu_encoder->encoder_id) { 2280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2281 if (dig->linkb) 2282 return 1; 2283 else 2284 return 0; 2285 break; 2286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2287 if (dig->linkb) 2288 return 3; 2289 else 2290 return 2; 2291 break; 2292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2293 if (dig->linkb) 2294 return 5; 2295 else 2296 return 4; 2297 break; 2298 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2299 return 6; 2300 break; 2301 default: 2302 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2303 return 0; 2304 } 2305 } 2306 2307 /** 2308 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc. 2309 * 2310 * @crtc: drm crtc 2311 * 2312 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2313 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2314 * monitors a dedicated PPLL must be used. If a particular board has 2315 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2316 * as there is no need to program the PLL itself. If we are not able to 2317 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2318 * avoid messing up an existing monitor. 2319 * 2320 * Asic specific PLL information 2321 * 2322 * DCE 8.x 2323 * KB/KV 2324 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2325 * CI 2326 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2327 * 2328 */ 2329 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc) 2330 { 2331 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2332 struct drm_device *dev = crtc->dev; 2333 struct amdgpu_device *adev = dev->dev_private; 2334 u32 pll_in_use; 2335 int pll; 2336 2337 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2338 if (adev->clock.dp_extclk) 2339 /* skip PPLL programming if using ext clock */ 2340 return ATOM_PPLL_INVALID; 2341 else { 2342 /* use the same PPLL for all DP monitors */ 2343 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2344 if (pll != ATOM_PPLL_INVALID) 2345 return pll; 2346 } 2347 } else { 2348 /* use the same PPLL for all monitors with the same clock */ 2349 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2350 if (pll != ATOM_PPLL_INVALID) 2351 return pll; 2352 } 2353 /* otherwise, pick one of the plls */ 2354 if ((adev->asic_type == CHIP_KABINI) || 2355 (adev->asic_type == CHIP_MULLINS)) { 2356 /* KB/ML has PPLL1 and PPLL2 */ 2357 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2358 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2359 return ATOM_PPLL2; 2360 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2361 return ATOM_PPLL1; 2362 DRM_ERROR("unable to allocate a PPLL\n"); 2363 return ATOM_PPLL_INVALID; 2364 } else { 2365 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 2366 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2367 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2368 return ATOM_PPLL2; 2369 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2370 return ATOM_PPLL1; 2371 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2372 return ATOM_PPLL0; 2373 DRM_ERROR("unable to allocate a PPLL\n"); 2374 return ATOM_PPLL_INVALID; 2375 } 2376 return ATOM_PPLL_INVALID; 2377 } 2378 2379 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2380 { 2381 struct amdgpu_device *adev = crtc->dev->dev_private; 2382 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2383 uint32_t cur_lock; 2384 2385 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2386 if (lock) 2387 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2388 else 2389 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2390 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2391 } 2392 2393 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc) 2394 { 2395 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2396 struct amdgpu_device *adev = crtc->dev->dev_private; 2397 2398 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2399 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2400 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2401 } 2402 2403 static void dce_v8_0_show_cursor(struct drm_crtc *crtc) 2404 { 2405 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2406 struct amdgpu_device *adev = crtc->dev->dev_private; 2407 2408 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2409 upper_32_bits(amdgpu_crtc->cursor_addr)); 2410 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2411 lower_32_bits(amdgpu_crtc->cursor_addr)); 2412 2413 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2414 CUR_CONTROL__CURSOR_EN_MASK | 2415 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2416 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2417 } 2418 2419 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, 2420 int x, int y) 2421 { 2422 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2423 struct amdgpu_device *adev = crtc->dev->dev_private; 2424 int xorigin = 0, yorigin = 0; 2425 2426 /* avivo cursor are offset into the total surface */ 2427 x += crtc->x; 2428 y += crtc->y; 2429 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2430 2431 if (x < 0) { 2432 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2433 x = 0; 2434 } 2435 if (y < 0) { 2436 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2437 y = 0; 2438 } 2439 2440 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2441 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2442 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2443 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2444 2445 amdgpu_crtc->cursor_x = x; 2446 amdgpu_crtc->cursor_y = y; 2447 2448 return 0; 2449 } 2450 2451 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, 2452 int x, int y) 2453 { 2454 int ret; 2455 2456 dce_v8_0_lock_cursor(crtc, true); 2457 ret = dce_v8_0_cursor_move_locked(crtc, x, y); 2458 dce_v8_0_lock_cursor(crtc, false); 2459 2460 return ret; 2461 } 2462 2463 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 2464 struct drm_file *file_priv, 2465 uint32_t handle, 2466 uint32_t width, 2467 uint32_t height, 2468 int32_t hot_x, 2469 int32_t hot_y) 2470 { 2471 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2472 struct drm_gem_object *obj; 2473 struct amdgpu_bo *aobj; 2474 int ret; 2475 2476 if (!handle) { 2477 /* turn off cursor */ 2478 dce_v8_0_hide_cursor(crtc); 2479 obj = NULL; 2480 goto unpin; 2481 } 2482 2483 if ((width > amdgpu_crtc->max_cursor_width) || 2484 (height > amdgpu_crtc->max_cursor_height)) { 2485 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2486 return -EINVAL; 2487 } 2488 2489 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2490 if (!obj) { 2491 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2492 return -ENOENT; 2493 } 2494 2495 aobj = gem_to_amdgpu_bo(obj); 2496 ret = amdgpu_bo_reserve(aobj, false); 2497 if (ret != 0) { 2498 drm_gem_object_unreference_unlocked(obj); 2499 return ret; 2500 } 2501 2502 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2503 amdgpu_bo_unreserve(aobj); 2504 if (ret) { 2505 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2506 drm_gem_object_unreference_unlocked(obj); 2507 return ret; 2508 } 2509 2510 amdgpu_crtc->cursor_width = width; 2511 amdgpu_crtc->cursor_height = height; 2512 2513 dce_v8_0_lock_cursor(crtc, true); 2514 2515 if (hot_x != amdgpu_crtc->cursor_hot_x || 2516 hot_y != amdgpu_crtc->cursor_hot_y) { 2517 int x, y; 2518 2519 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2520 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2521 2522 dce_v8_0_cursor_move_locked(crtc, x, y); 2523 2524 amdgpu_crtc->cursor_hot_x = hot_x; 2525 amdgpu_crtc->cursor_hot_y = hot_y; 2526 } 2527 2528 dce_v8_0_show_cursor(crtc); 2529 dce_v8_0_lock_cursor(crtc, false); 2530 2531 unpin: 2532 if (amdgpu_crtc->cursor_bo) { 2533 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2534 ret = amdgpu_bo_reserve(aobj, false); 2535 if (likely(ret == 0)) { 2536 amdgpu_bo_unpin(aobj); 2537 amdgpu_bo_unreserve(aobj); 2538 } 2539 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2540 } 2541 2542 amdgpu_crtc->cursor_bo = obj; 2543 return 0; 2544 } 2545 2546 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 2547 { 2548 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2549 2550 if (amdgpu_crtc->cursor_bo) { 2551 dce_v8_0_lock_cursor(crtc, true); 2552 2553 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2554 amdgpu_crtc->cursor_y); 2555 2556 dce_v8_0_show_cursor(crtc); 2557 2558 dce_v8_0_lock_cursor(crtc, false); 2559 } 2560 } 2561 2562 static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2563 u16 *blue, uint32_t start, uint32_t size) 2564 { 2565 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2566 int end = (start + size > 256) ? 256 : start + size, i; 2567 2568 /* userspace palettes are always correct as is */ 2569 for (i = start; i < end; i++) { 2570 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2571 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2572 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2573 } 2574 dce_v8_0_crtc_load_lut(crtc); 2575 } 2576 2577 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) 2578 { 2579 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2580 2581 drm_crtc_cleanup(crtc); 2582 destroy_workqueue(amdgpu_crtc->pflip_queue); 2583 kfree(amdgpu_crtc); 2584 } 2585 2586 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { 2587 .cursor_set2 = dce_v8_0_crtc_cursor_set2, 2588 .cursor_move = dce_v8_0_crtc_cursor_move, 2589 .gamma_set = dce_v8_0_crtc_gamma_set, 2590 .set_config = amdgpu_crtc_set_config, 2591 .destroy = dce_v8_0_crtc_destroy, 2592 .page_flip = amdgpu_crtc_page_flip, 2593 }; 2594 2595 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2596 { 2597 struct drm_device *dev = crtc->dev; 2598 struct amdgpu_device *adev = dev->dev_private; 2599 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2600 unsigned type; 2601 2602 switch (mode) { 2603 case DRM_MODE_DPMS_ON: 2604 amdgpu_crtc->enabled = true; 2605 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2606 dce_v8_0_vga_enable(crtc, true); 2607 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2608 dce_v8_0_vga_enable(crtc, false); 2609 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2610 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2611 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2612 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2613 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2614 dce_v8_0_crtc_load_lut(crtc); 2615 break; 2616 case DRM_MODE_DPMS_STANDBY: 2617 case DRM_MODE_DPMS_SUSPEND: 2618 case DRM_MODE_DPMS_OFF: 2619 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); 2620 if (amdgpu_crtc->enabled) { 2621 dce_v8_0_vga_enable(crtc, true); 2622 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2623 dce_v8_0_vga_enable(crtc, false); 2624 } 2625 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2626 amdgpu_crtc->enabled = false; 2627 break; 2628 } 2629 /* adjust pm to dpms */ 2630 amdgpu_pm_compute_clocks(adev); 2631 } 2632 2633 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc) 2634 { 2635 /* disable crtc pair power gating before programming */ 2636 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2637 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2638 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2639 } 2640 2641 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc) 2642 { 2643 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2644 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2645 } 2646 2647 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) 2648 { 2649 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2650 struct drm_device *dev = crtc->dev; 2651 struct amdgpu_device *adev = dev->dev_private; 2652 struct amdgpu_atom_ss ss; 2653 int i; 2654 2655 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2656 if (crtc->primary->fb) { 2657 int r; 2658 struct amdgpu_framebuffer *amdgpu_fb; 2659 struct amdgpu_bo *rbo; 2660 2661 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2662 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2663 r = amdgpu_bo_reserve(rbo, false); 2664 if (unlikely(r)) 2665 DRM_ERROR("failed to reserve rbo before unpin\n"); 2666 else { 2667 amdgpu_bo_unpin(rbo); 2668 amdgpu_bo_unreserve(rbo); 2669 } 2670 } 2671 /* disable the GRPH */ 2672 dce_v8_0_grph_enable(crtc, false); 2673 2674 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2675 2676 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2677 if (adev->mode_info.crtcs[i] && 2678 adev->mode_info.crtcs[i]->enabled && 2679 i != amdgpu_crtc->crtc_id && 2680 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2681 /* one other crtc is using this pll don't turn 2682 * off the pll 2683 */ 2684 goto done; 2685 } 2686 } 2687 2688 switch (amdgpu_crtc->pll_id) { 2689 case ATOM_PPLL1: 2690 case ATOM_PPLL2: 2691 /* disable the ppll */ 2692 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2693 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2694 break; 2695 case ATOM_PPLL0: 2696 /* disable the ppll */ 2697 if ((adev->asic_type == CHIP_KAVERI) || 2698 (adev->asic_type == CHIP_BONAIRE) || 2699 (adev->asic_type == CHIP_HAWAII)) 2700 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2701 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2702 break; 2703 default: 2704 break; 2705 } 2706 done: 2707 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2708 amdgpu_crtc->adjusted_clock = 0; 2709 amdgpu_crtc->encoder = NULL; 2710 amdgpu_crtc->connector = NULL; 2711 } 2712 2713 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, 2714 struct drm_display_mode *mode, 2715 struct drm_display_mode *adjusted_mode, 2716 int x, int y, struct drm_framebuffer *old_fb) 2717 { 2718 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2719 2720 if (!amdgpu_crtc->adjusted_clock) 2721 return -EINVAL; 2722 2723 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2724 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2725 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2726 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2727 amdgpu_atombios_crtc_scaler_setup(crtc); 2728 dce_v8_0_cursor_reset(crtc); 2729 /* update the hw version fpr dpm */ 2730 amdgpu_crtc->hw_mode = *adjusted_mode; 2731 2732 return 0; 2733 } 2734 2735 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, 2736 const struct drm_display_mode *mode, 2737 struct drm_display_mode *adjusted_mode) 2738 { 2739 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2740 struct drm_device *dev = crtc->dev; 2741 struct drm_encoder *encoder; 2742 2743 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2744 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2745 if (encoder->crtc == crtc) { 2746 amdgpu_crtc->encoder = encoder; 2747 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2748 break; 2749 } 2750 } 2751 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2752 amdgpu_crtc->encoder = NULL; 2753 amdgpu_crtc->connector = NULL; 2754 return false; 2755 } 2756 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2757 return false; 2758 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2759 return false; 2760 /* pick pll */ 2761 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc); 2762 /* if we can't get a PPLL for a non-DP encoder, fail */ 2763 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2764 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2765 return false; 2766 2767 return true; 2768 } 2769 2770 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2771 struct drm_framebuffer *old_fb) 2772 { 2773 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2774 } 2775 2776 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2777 struct drm_framebuffer *fb, 2778 int x, int y, enum mode_set_atomic state) 2779 { 2780 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); 2781 } 2782 2783 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { 2784 .dpms = dce_v8_0_crtc_dpms, 2785 .mode_fixup = dce_v8_0_crtc_mode_fixup, 2786 .mode_set = dce_v8_0_crtc_mode_set, 2787 .mode_set_base = dce_v8_0_crtc_set_base, 2788 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic, 2789 .prepare = dce_v8_0_crtc_prepare, 2790 .commit = dce_v8_0_crtc_commit, 2791 .load_lut = dce_v8_0_crtc_load_lut, 2792 .disable = dce_v8_0_crtc_disable, 2793 }; 2794 2795 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) 2796 { 2797 struct amdgpu_crtc *amdgpu_crtc; 2798 int i; 2799 2800 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2801 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2802 if (amdgpu_crtc == NULL) 2803 return -ENOMEM; 2804 2805 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); 2806 2807 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2808 amdgpu_crtc->crtc_id = index; 2809 amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); 2810 adev->mode_info.crtcs[index] = amdgpu_crtc; 2811 2812 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 2813 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 2814 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2815 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2816 2817 for (i = 0; i < 256; i++) { 2818 amdgpu_crtc->lut_r[i] = i << 2; 2819 amdgpu_crtc->lut_g[i] = i << 2; 2820 amdgpu_crtc->lut_b[i] = i << 2; 2821 } 2822 2823 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2824 2825 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2826 amdgpu_crtc->adjusted_clock = 0; 2827 amdgpu_crtc->encoder = NULL; 2828 amdgpu_crtc->connector = NULL; 2829 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); 2830 2831 return 0; 2832 } 2833 2834 static int dce_v8_0_early_init(void *handle) 2835 { 2836 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2837 2838 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; 2839 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; 2840 2841 dce_v8_0_set_display_funcs(adev); 2842 dce_v8_0_set_irq_funcs(adev); 2843 2844 switch (adev->asic_type) { 2845 case CHIP_BONAIRE: 2846 case CHIP_HAWAII: 2847 adev->mode_info.num_crtc = 6; 2848 adev->mode_info.num_hpd = 6; 2849 adev->mode_info.num_dig = 6; 2850 break; 2851 case CHIP_KAVERI: 2852 adev->mode_info.num_crtc = 4; 2853 adev->mode_info.num_hpd = 6; 2854 adev->mode_info.num_dig = 7; 2855 break; 2856 case CHIP_KABINI: 2857 case CHIP_MULLINS: 2858 adev->mode_info.num_crtc = 2; 2859 adev->mode_info.num_hpd = 6; 2860 adev->mode_info.num_dig = 6; /* ? */ 2861 break; 2862 default: 2863 /* FIXME: not supported yet */ 2864 return -EINVAL; 2865 } 2866 2867 return 0; 2868 } 2869 2870 static int dce_v8_0_sw_init(void *handle) 2871 { 2872 int r, i; 2873 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2874 2875 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2876 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2877 if (r) 2878 return r; 2879 } 2880 2881 for (i = 8; i < 20; i += 2) { 2882 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2883 if (r) 2884 return r; 2885 } 2886 2887 /* HPD hotplug */ 2888 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2889 if (r) 2890 return r; 2891 2892 adev->mode_info.mode_config_initialized = true; 2893 2894 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2895 2896 adev->ddev->mode_config.max_width = 16384; 2897 adev->ddev->mode_config.max_height = 16384; 2898 2899 adev->ddev->mode_config.preferred_depth = 24; 2900 adev->ddev->mode_config.prefer_shadow = 1; 2901 2902 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2903 2904 r = amdgpu_modeset_create_props(adev); 2905 if (r) 2906 return r; 2907 2908 adev->ddev->mode_config.max_width = 16384; 2909 adev->ddev->mode_config.max_height = 16384; 2910 2911 /* allocate crtcs */ 2912 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2913 r = dce_v8_0_crtc_init(adev, i); 2914 if (r) 2915 return r; 2916 } 2917 2918 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2919 amdgpu_print_display_setup(adev->ddev); 2920 else 2921 return -EINVAL; 2922 2923 /* setup afmt */ 2924 dce_v8_0_afmt_init(adev); 2925 2926 r = dce_v8_0_audio_init(adev); 2927 if (r) 2928 return r; 2929 2930 drm_kms_helper_poll_init(adev->ddev); 2931 2932 return r; 2933 } 2934 2935 static int dce_v8_0_sw_fini(void *handle) 2936 { 2937 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2938 2939 kfree(adev->mode_info.bios_hardcoded_edid); 2940 2941 drm_kms_helper_poll_fini(adev->ddev); 2942 2943 dce_v8_0_audio_fini(adev); 2944 2945 dce_v8_0_afmt_fini(adev); 2946 2947 drm_mode_config_cleanup(adev->ddev); 2948 adev->mode_info.mode_config_initialized = false; 2949 2950 return 0; 2951 } 2952 2953 static int dce_v8_0_hw_init(void *handle) 2954 { 2955 int i; 2956 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2957 2958 /* init dig PHYs, disp eng pll */ 2959 amdgpu_atombios_encoder_init_dig(adev); 2960 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2961 2962 /* initialize hpd */ 2963 dce_v8_0_hpd_init(adev); 2964 2965 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2966 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2967 } 2968 2969 dce_v8_0_pageflip_interrupt_init(adev); 2970 2971 return 0; 2972 } 2973 2974 static int dce_v8_0_hw_fini(void *handle) 2975 { 2976 int i; 2977 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2978 2979 dce_v8_0_hpd_fini(adev); 2980 2981 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2982 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2983 } 2984 2985 dce_v8_0_pageflip_interrupt_fini(adev); 2986 2987 return 0; 2988 } 2989 2990 static int dce_v8_0_suspend(void *handle) 2991 { 2992 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2993 2994 amdgpu_atombios_scratch_regs_save(adev); 2995 2996 return dce_v8_0_hw_fini(handle); 2997 } 2998 2999 static int dce_v8_0_resume(void *handle) 3000 { 3001 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3002 int ret; 3003 3004 ret = dce_v8_0_hw_init(handle); 3005 3006 amdgpu_atombios_scratch_regs_restore(adev); 3007 3008 /* turn on the BL */ 3009 if (adev->mode_info.bl_encoder) { 3010 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3011 adev->mode_info.bl_encoder); 3012 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3013 bl_level); 3014 } 3015 3016 return ret; 3017 } 3018 3019 static bool dce_v8_0_is_idle(void *handle) 3020 { 3021 return true; 3022 } 3023 3024 static int dce_v8_0_wait_for_idle(void *handle) 3025 { 3026 return 0; 3027 } 3028 3029 static void dce_v8_0_print_status(void *handle) 3030 { 3031 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3032 3033 dev_info(adev->dev, "DCE 8.x registers\n"); 3034 /* XXX todo */ 3035 } 3036 3037 static int dce_v8_0_soft_reset(void *handle) 3038 { 3039 u32 srbm_soft_reset = 0, tmp; 3040 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3041 3042 if (dce_v8_0_is_display_hung(adev)) 3043 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3044 3045 if (srbm_soft_reset) { 3046 dce_v8_0_print_status((void *)adev); 3047 3048 tmp = RREG32(mmSRBM_SOFT_RESET); 3049 tmp |= srbm_soft_reset; 3050 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3051 WREG32(mmSRBM_SOFT_RESET, tmp); 3052 tmp = RREG32(mmSRBM_SOFT_RESET); 3053 3054 udelay(50); 3055 3056 tmp &= ~srbm_soft_reset; 3057 WREG32(mmSRBM_SOFT_RESET, tmp); 3058 tmp = RREG32(mmSRBM_SOFT_RESET); 3059 3060 /* Wait a little for things to settle down */ 3061 udelay(50); 3062 dce_v8_0_print_status((void *)adev); 3063 } 3064 return 0; 3065 } 3066 3067 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3068 int crtc, 3069 enum amdgpu_interrupt_state state) 3070 { 3071 u32 reg_block, lb_interrupt_mask; 3072 3073 if (crtc >= adev->mode_info.num_crtc) { 3074 DRM_DEBUG("invalid crtc %d\n", crtc); 3075 return; 3076 } 3077 3078 switch (crtc) { 3079 case 0: 3080 reg_block = CRTC0_REGISTER_OFFSET; 3081 break; 3082 case 1: 3083 reg_block = CRTC1_REGISTER_OFFSET; 3084 break; 3085 case 2: 3086 reg_block = CRTC2_REGISTER_OFFSET; 3087 break; 3088 case 3: 3089 reg_block = CRTC3_REGISTER_OFFSET; 3090 break; 3091 case 4: 3092 reg_block = CRTC4_REGISTER_OFFSET; 3093 break; 3094 case 5: 3095 reg_block = CRTC5_REGISTER_OFFSET; 3096 break; 3097 default: 3098 DRM_DEBUG("invalid crtc %d\n", crtc); 3099 return; 3100 } 3101 3102 switch (state) { 3103 case AMDGPU_IRQ_STATE_DISABLE: 3104 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3105 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3106 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3107 break; 3108 case AMDGPU_IRQ_STATE_ENABLE: 3109 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3110 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3111 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3112 break; 3113 default: 3114 break; 3115 } 3116 } 3117 3118 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3119 int crtc, 3120 enum amdgpu_interrupt_state state) 3121 { 3122 u32 reg_block, lb_interrupt_mask; 3123 3124 if (crtc >= adev->mode_info.num_crtc) { 3125 DRM_DEBUG("invalid crtc %d\n", crtc); 3126 return; 3127 } 3128 3129 switch (crtc) { 3130 case 0: 3131 reg_block = CRTC0_REGISTER_OFFSET; 3132 break; 3133 case 1: 3134 reg_block = CRTC1_REGISTER_OFFSET; 3135 break; 3136 case 2: 3137 reg_block = CRTC2_REGISTER_OFFSET; 3138 break; 3139 case 3: 3140 reg_block = CRTC3_REGISTER_OFFSET; 3141 break; 3142 case 4: 3143 reg_block = CRTC4_REGISTER_OFFSET; 3144 break; 3145 case 5: 3146 reg_block = CRTC5_REGISTER_OFFSET; 3147 break; 3148 default: 3149 DRM_DEBUG("invalid crtc %d\n", crtc); 3150 return; 3151 } 3152 3153 switch (state) { 3154 case AMDGPU_IRQ_STATE_DISABLE: 3155 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3156 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3157 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3158 break; 3159 case AMDGPU_IRQ_STATE_ENABLE: 3160 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3161 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3162 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3163 break; 3164 default: 3165 break; 3166 } 3167 } 3168 3169 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3170 struct amdgpu_irq_src *src, 3171 unsigned type, 3172 enum amdgpu_interrupt_state state) 3173 { 3174 u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl; 3175 3176 switch (type) { 3177 case AMDGPU_HPD_1: 3178 dc_hpd_int_cntl_reg = mmDC_HPD1_INT_CONTROL; 3179 break; 3180 case AMDGPU_HPD_2: 3181 dc_hpd_int_cntl_reg = mmDC_HPD2_INT_CONTROL; 3182 break; 3183 case AMDGPU_HPD_3: 3184 dc_hpd_int_cntl_reg = mmDC_HPD3_INT_CONTROL; 3185 break; 3186 case AMDGPU_HPD_4: 3187 dc_hpd_int_cntl_reg = mmDC_HPD4_INT_CONTROL; 3188 break; 3189 case AMDGPU_HPD_5: 3190 dc_hpd_int_cntl_reg = mmDC_HPD5_INT_CONTROL; 3191 break; 3192 case AMDGPU_HPD_6: 3193 dc_hpd_int_cntl_reg = mmDC_HPD6_INT_CONTROL; 3194 break; 3195 default: 3196 DRM_DEBUG("invalid hdp %d\n", type); 3197 return 0; 3198 } 3199 3200 switch (state) { 3201 case AMDGPU_IRQ_STATE_DISABLE: 3202 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3203 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3204 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3205 break; 3206 case AMDGPU_IRQ_STATE_ENABLE: 3207 dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg); 3208 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3209 WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl); 3210 break; 3211 default: 3212 break; 3213 } 3214 3215 return 0; 3216 } 3217 3218 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3219 struct amdgpu_irq_src *src, 3220 unsigned type, 3221 enum amdgpu_interrupt_state state) 3222 { 3223 switch (type) { 3224 case AMDGPU_CRTC_IRQ_VBLANK1: 3225 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3226 break; 3227 case AMDGPU_CRTC_IRQ_VBLANK2: 3228 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3229 break; 3230 case AMDGPU_CRTC_IRQ_VBLANK3: 3231 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3232 break; 3233 case AMDGPU_CRTC_IRQ_VBLANK4: 3234 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3235 break; 3236 case AMDGPU_CRTC_IRQ_VBLANK5: 3237 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3238 break; 3239 case AMDGPU_CRTC_IRQ_VBLANK6: 3240 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3241 break; 3242 case AMDGPU_CRTC_IRQ_VLINE1: 3243 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state); 3244 break; 3245 case AMDGPU_CRTC_IRQ_VLINE2: 3246 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state); 3247 break; 3248 case AMDGPU_CRTC_IRQ_VLINE3: 3249 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state); 3250 break; 3251 case AMDGPU_CRTC_IRQ_VLINE4: 3252 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state); 3253 break; 3254 case AMDGPU_CRTC_IRQ_VLINE5: 3255 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state); 3256 break; 3257 case AMDGPU_CRTC_IRQ_VLINE6: 3258 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state); 3259 break; 3260 default: 3261 break; 3262 } 3263 return 0; 3264 } 3265 3266 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, 3267 struct amdgpu_irq_src *source, 3268 struct amdgpu_iv_entry *entry) 3269 { 3270 unsigned crtc = entry->src_id - 1; 3271 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3272 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3273 3274 switch (entry->src_data) { 3275 case 0: /* vblank */ 3276 if (disp_int & interrupt_status_offsets[crtc].vblank) 3277 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); 3278 else 3279 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3280 3281 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3282 drm_handle_vblank(adev->ddev, crtc); 3283 } 3284 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3285 3286 break; 3287 case 1: /* vline */ 3288 if (disp_int & interrupt_status_offsets[crtc].vline) 3289 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); 3290 else 3291 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3292 3293 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3294 3295 break; 3296 default: 3297 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3298 break; 3299 } 3300 3301 return 0; 3302 } 3303 3304 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3305 struct amdgpu_irq_src *src, 3306 unsigned type, 3307 enum amdgpu_interrupt_state state) 3308 { 3309 u32 reg; 3310 3311 if (type >= adev->mode_info.num_crtc) { 3312 DRM_ERROR("invalid pageflip crtc %d\n", type); 3313 return -EINVAL; 3314 } 3315 3316 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3317 if (state == AMDGPU_IRQ_STATE_DISABLE) 3318 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3319 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3320 else 3321 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3322 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3323 3324 return 0; 3325 } 3326 3327 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, 3328 struct amdgpu_irq_src *source, 3329 struct amdgpu_iv_entry *entry) 3330 { 3331 unsigned long flags; 3332 unsigned crtc_id; 3333 struct amdgpu_crtc *amdgpu_crtc; 3334 struct amdgpu_flip_work *works; 3335 3336 crtc_id = (entry->src_id - 8) >> 1; 3337 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3338 3339 if (crtc_id >= adev->mode_info.num_crtc) { 3340 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3341 return -EINVAL; 3342 } 3343 3344 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3345 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3346 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3347 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3348 3349 /* IRQ could occur when in initial stage */ 3350 if (amdgpu_crtc == NULL) 3351 return 0; 3352 3353 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3354 works = amdgpu_crtc->pflip_works; 3355 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3356 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3357 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3358 amdgpu_crtc->pflip_status, 3359 AMDGPU_FLIP_SUBMITTED); 3360 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3361 return 0; 3362 } 3363 3364 /* page flip completed. clean up */ 3365 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3366 amdgpu_crtc->pflip_works = NULL; 3367 3368 /* wakeup usersapce */ 3369 if (works->event) 3370 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3371 3372 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3373 3374 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3375 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3376 3377 return 0; 3378 } 3379 3380 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, 3381 struct amdgpu_irq_src *source, 3382 struct amdgpu_iv_entry *entry) 3383 { 3384 uint32_t disp_int, mask, int_control, tmp; 3385 unsigned hpd; 3386 3387 if (entry->src_data >= adev->mode_info.num_hpd) { 3388 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3389 return 0; 3390 } 3391 3392 hpd = entry->src_data; 3393 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3394 mask = interrupt_status_offsets[hpd].hpd; 3395 int_control = hpd_int_control_offsets[hpd]; 3396 3397 if (disp_int & mask) { 3398 tmp = RREG32(int_control); 3399 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3400 WREG32(int_control, tmp); 3401 schedule_work(&adev->hotplug_work); 3402 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3403 } 3404 3405 return 0; 3406 3407 } 3408 3409 static int dce_v8_0_set_clockgating_state(void *handle, 3410 enum amd_clockgating_state state) 3411 { 3412 return 0; 3413 } 3414 3415 static int dce_v8_0_set_powergating_state(void *handle, 3416 enum amd_powergating_state state) 3417 { 3418 return 0; 3419 } 3420 3421 const struct amd_ip_funcs dce_v8_0_ip_funcs = { 3422 .early_init = dce_v8_0_early_init, 3423 .late_init = NULL, 3424 .sw_init = dce_v8_0_sw_init, 3425 .sw_fini = dce_v8_0_sw_fini, 3426 .hw_init = dce_v8_0_hw_init, 3427 .hw_fini = dce_v8_0_hw_fini, 3428 .suspend = dce_v8_0_suspend, 3429 .resume = dce_v8_0_resume, 3430 .is_idle = dce_v8_0_is_idle, 3431 .wait_for_idle = dce_v8_0_wait_for_idle, 3432 .soft_reset = dce_v8_0_soft_reset, 3433 .print_status = dce_v8_0_print_status, 3434 .set_clockgating_state = dce_v8_0_set_clockgating_state, 3435 .set_powergating_state = dce_v8_0_set_powergating_state, 3436 }; 3437 3438 static void 3439 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder, 3440 struct drm_display_mode *mode, 3441 struct drm_display_mode *adjusted_mode) 3442 { 3443 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3444 3445 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3446 3447 /* need to call this here rather than in prepare() since we need some crtc info */ 3448 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3449 3450 /* set scaler clears this on some chips */ 3451 dce_v8_0_set_interleave(encoder->crtc, mode); 3452 3453 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3454 dce_v8_0_afmt_enable(encoder, true); 3455 dce_v8_0_afmt_setmode(encoder, adjusted_mode); 3456 } 3457 } 3458 3459 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder) 3460 { 3461 struct amdgpu_device *adev = encoder->dev->dev_private; 3462 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3463 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3464 3465 if ((amdgpu_encoder->active_device & 3466 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3467 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3468 ENCODER_OBJECT_ID_NONE)) { 3469 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3470 if (dig) { 3471 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder); 3472 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3473 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3474 } 3475 } 3476 3477 amdgpu_atombios_scratch_regs_lock(adev, true); 3478 3479 if (connector) { 3480 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3481 3482 /* select the clock/data port if it uses a router */ 3483 if (amdgpu_connector->router.cd_valid) 3484 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3485 3486 /* turn eDP panel on for mode set */ 3487 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3488 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3489 ATOM_TRANSMITTER_ACTION_POWER_ON); 3490 } 3491 3492 /* this is needed for the pll/ss setup to work correctly in some cases */ 3493 amdgpu_atombios_encoder_set_crtc_source(encoder); 3494 /* set up the FMT blocks */ 3495 dce_v8_0_program_fmt(encoder); 3496 } 3497 3498 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder) 3499 { 3500 struct drm_device *dev = encoder->dev; 3501 struct amdgpu_device *adev = dev->dev_private; 3502 3503 /* need to call this here as we need the crtc set up */ 3504 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3505 amdgpu_atombios_scratch_regs_lock(adev, false); 3506 } 3507 3508 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder) 3509 { 3510 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3511 struct amdgpu_encoder_atom_dig *dig; 3512 3513 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3514 3515 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3516 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3517 dce_v8_0_afmt_enable(encoder, false); 3518 dig = amdgpu_encoder->enc_priv; 3519 dig->dig_encoder = -1; 3520 } 3521 amdgpu_encoder->active_device = 0; 3522 } 3523 3524 /* these are handled by the primary encoders */ 3525 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder) 3526 { 3527 3528 } 3529 3530 static void dce_v8_0_ext_commit(struct drm_encoder *encoder) 3531 { 3532 3533 } 3534 3535 static void 3536 dce_v8_0_ext_mode_set(struct drm_encoder *encoder, 3537 struct drm_display_mode *mode, 3538 struct drm_display_mode *adjusted_mode) 3539 { 3540 3541 } 3542 3543 static void dce_v8_0_ext_disable(struct drm_encoder *encoder) 3544 { 3545 3546 } 3547 3548 static void 3549 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode) 3550 { 3551 3552 } 3553 3554 static bool dce_v8_0_ext_mode_fixup(struct drm_encoder *encoder, 3555 const struct drm_display_mode *mode, 3556 struct drm_display_mode *adjusted_mode) 3557 { 3558 return true; 3559 } 3560 3561 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = { 3562 .dpms = dce_v8_0_ext_dpms, 3563 .mode_fixup = dce_v8_0_ext_mode_fixup, 3564 .prepare = dce_v8_0_ext_prepare, 3565 .mode_set = dce_v8_0_ext_mode_set, 3566 .commit = dce_v8_0_ext_commit, 3567 .disable = dce_v8_0_ext_disable, 3568 /* no detect for TMDS/LVDS yet */ 3569 }; 3570 3571 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = { 3572 .dpms = amdgpu_atombios_encoder_dpms, 3573 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3574 .prepare = dce_v8_0_encoder_prepare, 3575 .mode_set = dce_v8_0_encoder_mode_set, 3576 .commit = dce_v8_0_encoder_commit, 3577 .disable = dce_v8_0_encoder_disable, 3578 .detect = amdgpu_atombios_encoder_dig_detect, 3579 }; 3580 3581 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = { 3582 .dpms = amdgpu_atombios_encoder_dpms, 3583 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3584 .prepare = dce_v8_0_encoder_prepare, 3585 .mode_set = dce_v8_0_encoder_mode_set, 3586 .commit = dce_v8_0_encoder_commit, 3587 .detect = amdgpu_atombios_encoder_dac_detect, 3588 }; 3589 3590 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder) 3591 { 3592 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3593 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3594 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3595 kfree(amdgpu_encoder->enc_priv); 3596 drm_encoder_cleanup(encoder); 3597 kfree(amdgpu_encoder); 3598 } 3599 3600 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = { 3601 .destroy = dce_v8_0_encoder_destroy, 3602 }; 3603 3604 static void dce_v8_0_encoder_add(struct amdgpu_device *adev, 3605 uint32_t encoder_enum, 3606 uint32_t supported_device, 3607 u16 caps) 3608 { 3609 struct drm_device *dev = adev->ddev; 3610 struct drm_encoder *encoder; 3611 struct amdgpu_encoder *amdgpu_encoder; 3612 3613 /* see if we already added it */ 3614 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3615 amdgpu_encoder = to_amdgpu_encoder(encoder); 3616 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3617 amdgpu_encoder->devices |= supported_device; 3618 return; 3619 } 3620 3621 } 3622 3623 /* add a new one */ 3624 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3625 if (!amdgpu_encoder) 3626 return; 3627 3628 encoder = &amdgpu_encoder->base; 3629 switch (adev->mode_info.num_crtc) { 3630 case 1: 3631 encoder->possible_crtcs = 0x1; 3632 break; 3633 case 2: 3634 default: 3635 encoder->possible_crtcs = 0x3; 3636 break; 3637 case 4: 3638 encoder->possible_crtcs = 0xf; 3639 break; 3640 case 6: 3641 encoder->possible_crtcs = 0x3f; 3642 break; 3643 } 3644 3645 amdgpu_encoder->enc_priv = NULL; 3646 3647 amdgpu_encoder->encoder_enum = encoder_enum; 3648 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3649 amdgpu_encoder->devices = supported_device; 3650 amdgpu_encoder->rmx_type = RMX_OFF; 3651 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3652 amdgpu_encoder->is_ext_encoder = false; 3653 amdgpu_encoder->caps = caps; 3654 3655 switch (amdgpu_encoder->encoder_id) { 3656 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3658 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3659 DRM_MODE_ENCODER_DAC); 3660 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); 3661 break; 3662 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3663 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3664 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3665 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3666 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3667 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3668 amdgpu_encoder->rmx_type = RMX_FULL; 3669 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3670 DRM_MODE_ENCODER_LVDS); 3671 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3672 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3673 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3674 DRM_MODE_ENCODER_DAC); 3675 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3676 } else { 3677 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3678 DRM_MODE_ENCODER_TMDS); 3679 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3680 } 3681 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); 3682 break; 3683 case ENCODER_OBJECT_ID_SI170B: 3684 case ENCODER_OBJECT_ID_CH7303: 3685 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3686 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3687 case ENCODER_OBJECT_ID_TITFP513: 3688 case ENCODER_OBJECT_ID_VT1623: 3689 case ENCODER_OBJECT_ID_HDMI_SI1930: 3690 case ENCODER_OBJECT_ID_TRAVIS: 3691 case ENCODER_OBJECT_ID_NUTMEG: 3692 /* these are handled by the primary encoders */ 3693 amdgpu_encoder->is_ext_encoder = true; 3694 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3695 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3696 DRM_MODE_ENCODER_LVDS); 3697 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3698 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3699 DRM_MODE_ENCODER_DAC); 3700 else 3701 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3702 DRM_MODE_ENCODER_TMDS); 3703 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs); 3704 break; 3705 } 3706 } 3707 3708 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { 3709 .set_vga_render_state = &dce_v8_0_set_vga_render_state, 3710 .bandwidth_update = &dce_v8_0_bandwidth_update, 3711 .vblank_get_counter = &dce_v8_0_vblank_get_counter, 3712 .vblank_wait = &dce_v8_0_vblank_wait, 3713 .is_display_hung = &dce_v8_0_is_display_hung, 3714 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3715 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3716 .hpd_sense = &dce_v8_0_hpd_sense, 3717 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity, 3718 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg, 3719 .page_flip = &dce_v8_0_page_flip, 3720 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos, 3721 .add_encoder = &dce_v8_0_encoder_add, 3722 .add_connector = &amdgpu_connector_add, 3723 .stop_mc_access = &dce_v8_0_stop_mc_access, 3724 .resume_mc_access = &dce_v8_0_resume_mc_access, 3725 }; 3726 3727 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev) 3728 { 3729 if (adev->mode_info.funcs == NULL) 3730 adev->mode_info.funcs = &dce_v8_0_display_funcs; 3731 } 3732 3733 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = { 3734 .set = dce_v8_0_set_crtc_interrupt_state, 3735 .process = dce_v8_0_crtc_irq, 3736 }; 3737 3738 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = { 3739 .set = dce_v8_0_set_pageflip_interrupt_state, 3740 .process = dce_v8_0_pageflip_irq, 3741 }; 3742 3743 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { 3744 .set = dce_v8_0_set_hpd_interrupt_state, 3745 .process = dce_v8_0_hpd_irq, 3746 }; 3747 3748 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) 3749 { 3750 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3751 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; 3752 3753 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3754 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; 3755 3756 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3757 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; 3758 } 3759