1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "cikd.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 #include "dce_v8_0.h" 35 36 #include "dce/dce_8_0_d.h" 37 #include "dce/dce_8_0_sh_mask.h" 38 39 #include "gca/gfx_7_2_enum.h" 40 41 #include "gmc/gmc_7_1_d.h" 42 #include "gmc/gmc_7_1_sh_mask.h" 43 44 #include "oss/oss_2_0_d.h" 45 #include "oss/oss_2_0_sh_mask.h" 46 47 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev); 48 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev); 49 50 static const u32 crtc_offsets[6] = 51 { 52 CRTC0_REGISTER_OFFSET, 53 CRTC1_REGISTER_OFFSET, 54 CRTC2_REGISTER_OFFSET, 55 CRTC3_REGISTER_OFFSET, 56 CRTC4_REGISTER_OFFSET, 57 CRTC5_REGISTER_OFFSET 58 }; 59 60 static const u32 hpd_offsets[] = 61 { 62 HPD0_REGISTER_OFFSET, 63 HPD1_REGISTER_OFFSET, 64 HPD2_REGISTER_OFFSET, 65 HPD3_REGISTER_OFFSET, 66 HPD4_REGISTER_OFFSET, 67 HPD5_REGISTER_OFFSET 68 }; 69 70 static const uint32_t dig_offsets[] = { 71 CRTC0_REGISTER_OFFSET, 72 CRTC1_REGISTER_OFFSET, 73 CRTC2_REGISTER_OFFSET, 74 CRTC3_REGISTER_OFFSET, 75 CRTC4_REGISTER_OFFSET, 76 CRTC5_REGISTER_OFFSET, 77 (0x13830 - 0x7030) >> 2, 78 }; 79 80 static const struct { 81 uint32_t reg; 82 uint32_t vblank; 83 uint32_t vline; 84 uint32_t hpd; 85 86 } interrupt_status_offsets[6] = { { 87 .reg = mmDISP_INTERRUPT_STATUS, 88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 91 }, { 92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 96 }, { 97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 116 } }; 117 118 static u32 dce_v8_0_audio_endpt_rreg(struct amdgpu_device *adev, 119 u32 block_offset, u32 reg) 120 { 121 unsigned long flags; 122 u32 r; 123 124 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 125 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 126 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 127 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 128 129 return r; 130 } 131 132 static void dce_v8_0_audio_endpt_wreg(struct amdgpu_device *adev, 133 u32 block_offset, u32 reg, u32 v) 134 { 135 unsigned long flags; 136 137 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 138 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 139 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 140 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 141 } 142 143 static bool dce_v8_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 144 { 145 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 146 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 147 return true; 148 else 149 return false; 150 } 151 152 static bool dce_v8_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 153 { 154 u32 pos1, pos2; 155 156 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 157 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 158 159 if (pos1 != pos2) 160 return true; 161 else 162 return false; 163 } 164 165 /** 166 * dce_v8_0_vblank_wait - vblank wait asic callback. 167 * 168 * @adev: amdgpu_device pointer 169 * @crtc: crtc to wait for vblank on 170 * 171 * Wait for vblank on the requested crtc (evergreen+). 172 */ 173 static void dce_v8_0_vblank_wait(struct amdgpu_device *adev, int crtc) 174 { 175 unsigned i = 100; 176 177 if (crtc >= adev->mode_info.num_crtc) 178 return; 179 180 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 181 return; 182 183 /* depending on when we hit vblank, we may be close to active; if so, 184 * wait for another frame. 185 */ 186 while (dce_v8_0_is_in_vblank(adev, crtc)) { 187 if (i++ == 100) { 188 i = 0; 189 if (!dce_v8_0_is_counter_moving(adev, crtc)) 190 break; 191 } 192 } 193 194 while (!dce_v8_0_is_in_vblank(adev, crtc)) { 195 if (i++ == 100) { 196 i = 0; 197 if (!dce_v8_0_is_counter_moving(adev, crtc)) 198 break; 199 } 200 } 201 } 202 203 static u32 dce_v8_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 204 { 205 if (crtc >= adev->mode_info.num_crtc) 206 return 0; 207 else 208 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 209 } 210 211 static void dce_v8_0_pageflip_interrupt_init(struct amdgpu_device *adev) 212 { 213 unsigned i; 214 215 /* Enable pflip interrupts */ 216 for (i = 0; i < adev->mode_info.num_crtc; i++) 217 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 218 } 219 220 static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 221 { 222 unsigned i; 223 224 /* Disable pflip interrupts */ 225 for (i = 0; i < adev->mode_info.num_crtc; i++) 226 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 227 } 228 229 /** 230 * dce_v8_0_page_flip - pageflip callback. 231 * 232 * @adev: amdgpu_device pointer 233 * @crtc_id: crtc to cleanup pageflip on 234 * @crtc_base: new address of the crtc (GPU MC address) 235 * 236 * Triggers the actual pageflip by updating the primary 237 * surface base address. 238 */ 239 static void dce_v8_0_page_flip(struct amdgpu_device *adev, 240 int crtc_id, u64 crtc_base, bool async) 241 { 242 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 243 244 /* flip at hsync for async, default is vsync */ 245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 246 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 247 /* update the primary scanout addresses */ 248 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 249 upper_32_bits(crtc_base)); 250 /* writing to the low address triggers the update */ 251 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 252 lower_32_bits(crtc_base)); 253 /* post the write */ 254 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 255 } 256 257 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 258 u32 *vbl, u32 *position) 259 { 260 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 261 return -EINVAL; 262 263 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 264 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 265 266 return 0; 267 } 268 269 /** 270 * dce_v8_0_hpd_sense - hpd sense callback. 271 * 272 * @adev: amdgpu_device pointer 273 * @hpd: hpd (hotplug detect) pin 274 * 275 * Checks if a digital monitor is connected (evergreen+). 276 * Returns true if connected, false if not connected. 277 */ 278 static bool dce_v8_0_hpd_sense(struct amdgpu_device *adev, 279 enum amdgpu_hpd_id hpd) 280 { 281 bool connected = false; 282 283 if (hpd >= adev->mode_info.num_hpd) 284 return connected; 285 286 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & 287 DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 288 connected = true; 289 290 return connected; 291 } 292 293 /** 294 * dce_v8_0_hpd_set_polarity - hpd set polarity callback. 295 * 296 * @adev: amdgpu_device pointer 297 * @hpd: hpd (hotplug detect) pin 298 * 299 * Set the polarity of the hpd pin (evergreen+). 300 */ 301 static void dce_v8_0_hpd_set_polarity(struct amdgpu_device *adev, 302 enum amdgpu_hpd_id hpd) 303 { 304 u32 tmp; 305 bool connected = dce_v8_0_hpd_sense(adev, hpd); 306 307 if (hpd >= adev->mode_info.num_hpd) 308 return; 309 310 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 311 if (connected) 312 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 313 else 314 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 315 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 316 } 317 318 /** 319 * dce_v8_0_hpd_init - hpd setup callback. 320 * 321 * @adev: amdgpu_device pointer 322 * 323 * Setup the hpd pins used by the card (evergreen+). 324 * Enable the pin, set the polarity, and enable the hpd interrupts. 325 */ 326 static void dce_v8_0_hpd_init(struct amdgpu_device *adev) 327 { 328 struct drm_device *dev = adev->ddev; 329 struct drm_connector *connector; 330 u32 tmp; 331 332 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 333 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 334 335 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 336 continue; 337 338 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 339 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 340 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 341 342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 344 /* don't try to enable hpd on eDP or LVDS avoid breaking the 345 * aux dp channel on imac and help (but not completely fix) 346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 347 * also avoid interrupt storms during dpms. 348 */ 349 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 350 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 351 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 352 continue; 353 } 354 355 dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 356 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 357 } 358 } 359 360 /** 361 * dce_v8_0_hpd_fini - hpd tear down callback. 362 * 363 * @adev: amdgpu_device pointer 364 * 365 * Tear down the hpd pins used by the card (evergreen+). 366 * Disable the hpd interrupts. 367 */ 368 static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) 369 { 370 struct drm_device *dev = adev->ddev; 371 struct drm_connector *connector; 372 u32 tmp; 373 374 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 375 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 376 377 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 378 continue; 379 380 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 381 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 382 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 383 384 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 385 } 386 } 387 388 static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 389 { 390 return mmDC_GPIO_HPD_A; 391 } 392 393 static bool dce_v8_0_is_display_hung(struct amdgpu_device *adev) 394 { 395 u32 crtc_hung = 0; 396 u32 crtc_status[6]; 397 u32 i, j, tmp; 398 399 for (i = 0; i < adev->mode_info.num_crtc; i++) { 400 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { 401 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 402 crtc_hung |= (1 << i); 403 } 404 } 405 406 for (j = 0; j < 10; j++) { 407 for (i = 0; i < adev->mode_info.num_crtc; i++) { 408 if (crtc_hung & (1 << i)) { 409 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 410 if (tmp != crtc_status[i]) 411 crtc_hung &= ~(1 << i); 412 } 413 } 414 if (crtc_hung == 0) 415 return false; 416 udelay(100); 417 } 418 419 return true; 420 } 421 422 static void dce_v8_0_stop_mc_access(struct amdgpu_device *adev, 423 struct amdgpu_mode_mc_save *save) 424 { 425 u32 crtc_enabled, tmp; 426 int i; 427 428 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 429 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 430 431 /* disable VGA render */ 432 tmp = RREG32(mmVGA_RENDER_CONTROL); 433 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 434 WREG32(mmVGA_RENDER_CONTROL, tmp); 435 436 /* blank the display controllers */ 437 for (i = 0; i < adev->mode_info.num_crtc; i++) { 438 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 439 CRTC_CONTROL, CRTC_MASTER_EN); 440 if (crtc_enabled) { 441 #if 1 442 save->crtc_enabled[i] = true; 443 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 444 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 445 /*it is correct only for RGB ; black is 0*/ 446 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 447 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 448 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 449 } 450 mdelay(20); 451 #else 452 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 453 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 454 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 455 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 456 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 457 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 458 save->crtc_enabled[i] = false; 459 /* ***** */ 460 #endif 461 } else { 462 save->crtc_enabled[i] = false; 463 } 464 } 465 } 466 467 static void dce_v8_0_resume_mc_access(struct amdgpu_device *adev, 468 struct amdgpu_mode_mc_save *save) 469 { 470 u32 tmp; 471 int i; 472 473 /* update crtc base addresses */ 474 for (i = 0; i < adev->mode_info.num_crtc; i++) { 475 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 476 upper_32_bits(adev->mc.vram_start)); 477 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 478 (u32)adev->mc.vram_start); 479 480 if (save->crtc_enabled[i]) { 481 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 482 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 483 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 484 } 485 mdelay(20); 486 } 487 488 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 489 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 490 491 /* Unlock vga access */ 492 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 493 mdelay(1); 494 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 495 } 496 497 static void dce_v8_0_set_vga_render_state(struct amdgpu_device *adev, 498 bool render) 499 { 500 u32 tmp; 501 502 /* Lockout access through VGA aperture*/ 503 tmp = RREG32(mmVGA_HDP_CONTROL); 504 if (render) 505 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 506 else 507 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 508 WREG32(mmVGA_HDP_CONTROL, tmp); 509 510 /* disable VGA render */ 511 tmp = RREG32(mmVGA_RENDER_CONTROL); 512 if (render) 513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 514 else 515 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 516 WREG32(mmVGA_RENDER_CONTROL, tmp); 517 } 518 519 static int dce_v8_0_get_num_crtc(struct amdgpu_device *adev) 520 { 521 int num_crtc = 0; 522 523 switch (adev->asic_type) { 524 case CHIP_BONAIRE: 525 case CHIP_HAWAII: 526 num_crtc = 6; 527 break; 528 case CHIP_KAVERI: 529 num_crtc = 4; 530 break; 531 case CHIP_KABINI: 532 case CHIP_MULLINS: 533 num_crtc = 2; 534 break; 535 default: 536 num_crtc = 0; 537 } 538 return num_crtc; 539 } 540 541 void dce_v8_0_disable_dce(struct amdgpu_device *adev) 542 { 543 /*Disable VGA render and enabled crtc, if has DCE engine*/ 544 if (amdgpu_atombios_has_dce_engine_info(adev)) { 545 u32 tmp; 546 int crtc_enabled, i; 547 548 dce_v8_0_set_vga_render_state(adev, false); 549 550 /*Disable crtc*/ 551 for (i = 0; i < dce_v8_0_get_num_crtc(adev); i++) { 552 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 553 CRTC_CONTROL, CRTC_MASTER_EN); 554 if (crtc_enabled) { 555 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 556 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 557 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 558 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 559 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 560 } 561 } 562 } 563 } 564 565 static void dce_v8_0_program_fmt(struct drm_encoder *encoder) 566 { 567 struct drm_device *dev = encoder->dev; 568 struct amdgpu_device *adev = dev->dev_private; 569 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 570 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 571 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 572 int bpc = 0; 573 u32 tmp = 0; 574 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 575 576 if (connector) { 577 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 578 bpc = amdgpu_connector_get_monitor_bpc(connector); 579 dither = amdgpu_connector->dither; 580 } 581 582 /* LVDS/eDP FMT is set up by atom */ 583 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 584 return; 585 586 /* not needed for analog */ 587 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 588 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 589 return; 590 591 if (bpc == 0) 592 return; 593 594 switch (bpc) { 595 case 6: 596 if (dither == AMDGPU_FMT_DITHER_ENABLE) 597 /* XXX sort out optimal dither settings */ 598 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 599 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 600 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 601 (0 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 602 else 603 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 604 (0 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 605 break; 606 case 8: 607 if (dither == AMDGPU_FMT_DITHER_ENABLE) 608 /* XXX sort out optimal dither settings */ 609 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 610 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 611 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 612 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 613 (1 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 614 else 615 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 616 (1 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 617 break; 618 case 10: 619 if (dither == AMDGPU_FMT_DITHER_ENABLE) 620 /* XXX sort out optimal dither settings */ 621 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 622 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 623 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 624 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 625 (2 << FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH__SHIFT)); 626 else 627 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 628 (2 << FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH__SHIFT)); 629 break; 630 default: 631 /* not needed */ 632 break; 633 } 634 635 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 636 } 637 638 639 /* display watermark setup */ 640 /** 641 * dce_v8_0_line_buffer_adjust - Set up the line buffer 642 * 643 * @adev: amdgpu_device pointer 644 * @amdgpu_crtc: the selected display controller 645 * @mode: the current display mode on the selected display 646 * controller 647 * 648 * Setup up the line buffer allocation for 649 * the selected display controller (CIK). 650 * Returns the line buffer size in pixels. 651 */ 652 static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev, 653 struct amdgpu_crtc *amdgpu_crtc, 654 struct drm_display_mode *mode) 655 { 656 u32 tmp, buffer_alloc, i; 657 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 658 /* 659 * Line Buffer Setup 660 * There are 6 line buffers, one for each display controllers. 661 * There are 3 partitions per LB. Select the number of partitions 662 * to enable based on the display width. For display widths larger 663 * than 4096, you need use to use 2 display controllers and combine 664 * them using the stereo blender. 665 */ 666 if (amdgpu_crtc->base.enabled && mode) { 667 if (mode->crtc_hdisplay < 1920) { 668 tmp = 1; 669 buffer_alloc = 2; 670 } else if (mode->crtc_hdisplay < 2560) { 671 tmp = 2; 672 buffer_alloc = 2; 673 } else if (mode->crtc_hdisplay < 4096) { 674 tmp = 0; 675 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 676 } else { 677 DRM_DEBUG_KMS("Mode too big for LB!\n"); 678 tmp = 0; 679 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 680 } 681 } else { 682 tmp = 1; 683 buffer_alloc = 0; 684 } 685 686 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, 687 (tmp << LB_MEMORY_CTRL__LB_MEMORY_CONFIG__SHIFT) | 688 (0x6B0 << LB_MEMORY_CTRL__LB_MEMORY_SIZE__SHIFT)); 689 690 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 691 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 692 for (i = 0; i < adev->usec_timeout; i++) { 693 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 694 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 695 break; 696 udelay(1); 697 } 698 699 if (amdgpu_crtc->base.enabled && mode) { 700 switch (tmp) { 701 case 0: 702 default: 703 return 4096 * 2; 704 case 1: 705 return 1920 * 2; 706 case 2: 707 return 2560 * 2; 708 } 709 } 710 711 /* controller not enabled, so no lb used */ 712 return 0; 713 } 714 715 /** 716 * cik_get_number_of_dram_channels - get the number of dram channels 717 * 718 * @adev: amdgpu_device pointer 719 * 720 * Look up the number of video ram channels (CIK). 721 * Used for display watermark bandwidth calculations 722 * Returns the number of dram channels 723 */ 724 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 725 { 726 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 727 728 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 729 case 0: 730 default: 731 return 1; 732 case 1: 733 return 2; 734 case 2: 735 return 4; 736 case 3: 737 return 8; 738 case 4: 739 return 3; 740 case 5: 741 return 6; 742 case 6: 743 return 10; 744 case 7: 745 return 12; 746 case 8: 747 return 16; 748 } 749 } 750 751 struct dce8_wm_params { 752 u32 dram_channels; /* number of dram channels */ 753 u32 yclk; /* bandwidth per dram data pin in kHz */ 754 u32 sclk; /* engine clock in kHz */ 755 u32 disp_clk; /* display clock in kHz */ 756 u32 src_width; /* viewport width */ 757 u32 active_time; /* active display time in ns */ 758 u32 blank_time; /* blank time in ns */ 759 bool interlaced; /* mode is interlaced */ 760 fixed20_12 vsc; /* vertical scale ratio */ 761 u32 num_heads; /* number of active crtcs */ 762 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 763 u32 lb_size; /* line buffer allocated to pipe */ 764 u32 vtaps; /* vertical scaler taps */ 765 }; 766 767 /** 768 * dce_v8_0_dram_bandwidth - get the dram bandwidth 769 * 770 * @wm: watermark calculation data 771 * 772 * Calculate the raw dram bandwidth (CIK). 773 * Used for display watermark bandwidth calculations 774 * Returns the dram bandwidth in MBytes/s 775 */ 776 static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) 777 { 778 /* Calculate raw DRAM Bandwidth */ 779 fixed20_12 dram_efficiency; /* 0.7 */ 780 fixed20_12 yclk, dram_channels, bandwidth; 781 fixed20_12 a; 782 783 a.full = dfixed_const(1000); 784 yclk.full = dfixed_const(wm->yclk); 785 yclk.full = dfixed_div(yclk, a); 786 dram_channels.full = dfixed_const(wm->dram_channels * 4); 787 a.full = dfixed_const(10); 788 dram_efficiency.full = dfixed_const(7); 789 dram_efficiency.full = dfixed_div(dram_efficiency, a); 790 bandwidth.full = dfixed_mul(dram_channels, yclk); 791 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 792 793 return dfixed_trunc(bandwidth); 794 } 795 796 /** 797 * dce_v8_0_dram_bandwidth_for_display - get the dram bandwidth for display 798 * 799 * @wm: watermark calculation data 800 * 801 * Calculate the dram bandwidth used for display (CIK). 802 * Used for display watermark bandwidth calculations 803 * Returns the dram bandwidth for display in MBytes/s 804 */ 805 static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) 806 { 807 /* Calculate DRAM Bandwidth and the part allocated to display. */ 808 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 809 fixed20_12 yclk, dram_channels, bandwidth; 810 fixed20_12 a; 811 812 a.full = dfixed_const(1000); 813 yclk.full = dfixed_const(wm->yclk); 814 yclk.full = dfixed_div(yclk, a); 815 dram_channels.full = dfixed_const(wm->dram_channels * 4); 816 a.full = dfixed_const(10); 817 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 818 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 819 bandwidth.full = dfixed_mul(dram_channels, yclk); 820 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 821 822 return dfixed_trunc(bandwidth); 823 } 824 825 /** 826 * dce_v8_0_data_return_bandwidth - get the data return bandwidth 827 * 828 * @wm: watermark calculation data 829 * 830 * Calculate the data return bandwidth used for display (CIK). 831 * Used for display watermark bandwidth calculations 832 * Returns the data return bandwidth in MBytes/s 833 */ 834 static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) 835 { 836 /* Calculate the display Data return Bandwidth */ 837 fixed20_12 return_efficiency; /* 0.8 */ 838 fixed20_12 sclk, bandwidth; 839 fixed20_12 a; 840 841 a.full = dfixed_const(1000); 842 sclk.full = dfixed_const(wm->sclk); 843 sclk.full = dfixed_div(sclk, a); 844 a.full = dfixed_const(10); 845 return_efficiency.full = dfixed_const(8); 846 return_efficiency.full = dfixed_div(return_efficiency, a); 847 a.full = dfixed_const(32); 848 bandwidth.full = dfixed_mul(a, sclk); 849 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 850 851 return dfixed_trunc(bandwidth); 852 } 853 854 /** 855 * dce_v8_0_dmif_request_bandwidth - get the dmif bandwidth 856 * 857 * @wm: watermark calculation data 858 * 859 * Calculate the dmif bandwidth used for display (CIK). 860 * Used for display watermark bandwidth calculations 861 * Returns the dmif bandwidth in MBytes/s 862 */ 863 static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) 864 { 865 /* Calculate the DMIF Request Bandwidth */ 866 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 867 fixed20_12 disp_clk, bandwidth; 868 fixed20_12 a, b; 869 870 a.full = dfixed_const(1000); 871 disp_clk.full = dfixed_const(wm->disp_clk); 872 disp_clk.full = dfixed_div(disp_clk, a); 873 a.full = dfixed_const(32); 874 b.full = dfixed_mul(a, disp_clk); 875 876 a.full = dfixed_const(10); 877 disp_clk_request_efficiency.full = dfixed_const(8); 878 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 879 880 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 881 882 return dfixed_trunc(bandwidth); 883 } 884 885 /** 886 * dce_v8_0_available_bandwidth - get the min available bandwidth 887 * 888 * @wm: watermark calculation data 889 * 890 * Calculate the min available bandwidth used for display (CIK). 891 * Used for display watermark bandwidth calculations 892 * Returns the min available bandwidth in MBytes/s 893 */ 894 static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm) 895 { 896 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 897 u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm); 898 u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm); 899 u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm); 900 901 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 902 } 903 904 /** 905 * dce_v8_0_average_bandwidth - get the average available bandwidth 906 * 907 * @wm: watermark calculation data 908 * 909 * Calculate the average available bandwidth used for display (CIK). 910 * Used for display watermark bandwidth calculations 911 * Returns the average available bandwidth in MBytes/s 912 */ 913 static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm) 914 { 915 /* Calculate the display mode Average Bandwidth 916 * DisplayMode should contain the source and destination dimensions, 917 * timing, etc. 918 */ 919 fixed20_12 bpp; 920 fixed20_12 line_time; 921 fixed20_12 src_width; 922 fixed20_12 bandwidth; 923 fixed20_12 a; 924 925 a.full = dfixed_const(1000); 926 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 927 line_time.full = dfixed_div(line_time, a); 928 bpp.full = dfixed_const(wm->bytes_per_pixel); 929 src_width.full = dfixed_const(wm->src_width); 930 bandwidth.full = dfixed_mul(src_width, bpp); 931 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 932 bandwidth.full = dfixed_div(bandwidth, line_time); 933 934 return dfixed_trunc(bandwidth); 935 } 936 937 /** 938 * dce_v8_0_latency_watermark - get the latency watermark 939 * 940 * @wm: watermark calculation data 941 * 942 * Calculate the latency watermark (CIK). 943 * Used for display watermark bandwidth calculations 944 * Returns the latency watermark in ns 945 */ 946 static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) 947 { 948 /* First calculate the latency in ns */ 949 u32 mc_latency = 2000; /* 2000 ns. */ 950 u32 available_bandwidth = dce_v8_0_available_bandwidth(wm); 951 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 952 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 953 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 954 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 955 (wm->num_heads * cursor_line_pair_return_time); 956 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 957 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 958 u32 tmp, dmif_size = 12288; 959 fixed20_12 a, b, c; 960 961 if (wm->num_heads == 0) 962 return 0; 963 964 a.full = dfixed_const(2); 965 b.full = dfixed_const(1); 966 if ((wm->vsc.full > a.full) || 967 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 968 (wm->vtaps >= 5) || 969 ((wm->vsc.full >= a.full) && wm->interlaced)) 970 max_src_lines_per_dst_line = 4; 971 else 972 max_src_lines_per_dst_line = 2; 973 974 a.full = dfixed_const(available_bandwidth); 975 b.full = dfixed_const(wm->num_heads); 976 a.full = dfixed_div(a, b); 977 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 978 tmp = min(dfixed_trunc(a), tmp); 979 980 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 981 982 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 983 b.full = dfixed_const(1000); 984 c.full = dfixed_const(lb_fill_bw); 985 b.full = dfixed_div(c, b); 986 a.full = dfixed_div(a, b); 987 line_fill_time = dfixed_trunc(a); 988 989 if (line_fill_time < wm->active_time) 990 return latency; 991 else 992 return latency + (line_fill_time - wm->active_time); 993 994 } 995 996 /** 997 * dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display - check 998 * average and available dram bandwidth 999 * 1000 * @wm: watermark calculation data 1001 * 1002 * Check if the display average bandwidth fits in the display 1003 * dram bandwidth (CIK). 1004 * Used for display watermark bandwidth calculations 1005 * Returns true if the display fits, false if not. 1006 */ 1007 static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) 1008 { 1009 if (dce_v8_0_average_bandwidth(wm) <= 1010 (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1011 return true; 1012 else 1013 return false; 1014 } 1015 1016 /** 1017 * dce_v8_0_average_bandwidth_vs_available_bandwidth - check 1018 * average and available bandwidth 1019 * 1020 * @wm: watermark calculation data 1021 * 1022 * Check if the display average bandwidth fits in the display 1023 * available bandwidth (CIK). 1024 * Used for display watermark bandwidth calculations 1025 * Returns true if the display fits, false if not. 1026 */ 1027 static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) 1028 { 1029 if (dce_v8_0_average_bandwidth(wm) <= 1030 (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) 1031 return true; 1032 else 1033 return false; 1034 } 1035 1036 /** 1037 * dce_v8_0_check_latency_hiding - check latency hiding 1038 * 1039 * @wm: watermark calculation data 1040 * 1041 * Check latency hiding (CIK). 1042 * Used for display watermark bandwidth calculations 1043 * Returns true if the display fits, false if not. 1044 */ 1045 static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm) 1046 { 1047 u32 lb_partitions = wm->lb_size / wm->src_width; 1048 u32 line_time = wm->active_time + wm->blank_time; 1049 u32 latency_tolerant_lines; 1050 u32 latency_hiding; 1051 fixed20_12 a; 1052 1053 a.full = dfixed_const(1); 1054 if (wm->vsc.full > a.full) 1055 latency_tolerant_lines = 1; 1056 else { 1057 if (lb_partitions <= (wm->vtaps + 1)) 1058 latency_tolerant_lines = 1; 1059 else 1060 latency_tolerant_lines = 2; 1061 } 1062 1063 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1064 1065 if (dce_v8_0_latency_watermark(wm) <= latency_hiding) 1066 return true; 1067 else 1068 return false; 1069 } 1070 1071 /** 1072 * dce_v8_0_program_watermarks - program display watermarks 1073 * 1074 * @adev: amdgpu_device pointer 1075 * @amdgpu_crtc: the selected display controller 1076 * @lb_size: line buffer size 1077 * @num_heads: number of display controllers in use 1078 * 1079 * Calculate and program the display watermarks for the 1080 * selected display controller (CIK). 1081 */ 1082 static void dce_v8_0_program_watermarks(struct amdgpu_device *adev, 1083 struct amdgpu_crtc *amdgpu_crtc, 1084 u32 lb_size, u32 num_heads) 1085 { 1086 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1087 struct dce8_wm_params wm_low, wm_high; 1088 u32 active_time; 1089 u32 line_time = 0; 1090 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1091 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1092 1093 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1094 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock; 1095 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535); 1096 1097 /* watermark for high clocks */ 1098 if (adev->pm.dpm_enabled) { 1099 wm_high.yclk = 1100 amdgpu_dpm_get_mclk(adev, false) * 10; 1101 wm_high.sclk = 1102 amdgpu_dpm_get_sclk(adev, false) * 10; 1103 } else { 1104 wm_high.yclk = adev->pm.current_mclk * 10; 1105 wm_high.sclk = adev->pm.current_sclk * 10; 1106 } 1107 1108 wm_high.disp_clk = mode->clock; 1109 wm_high.src_width = mode->crtc_hdisplay; 1110 wm_high.active_time = active_time; 1111 wm_high.blank_time = line_time - wm_high.active_time; 1112 wm_high.interlaced = false; 1113 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1114 wm_high.interlaced = true; 1115 wm_high.vsc = amdgpu_crtc->vsc; 1116 wm_high.vtaps = 1; 1117 if (amdgpu_crtc->rmx_type != RMX_OFF) 1118 wm_high.vtaps = 2; 1119 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1120 wm_high.lb_size = lb_size; 1121 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1122 wm_high.num_heads = num_heads; 1123 1124 /* set for high clocks */ 1125 latency_watermark_a = min(dce_v8_0_latency_watermark(&wm_high), (u32)65535); 1126 1127 /* possibly force display priority to high */ 1128 /* should really do this at mode validation time... */ 1129 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1130 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1131 !dce_v8_0_check_latency_hiding(&wm_high) || 1132 (adev->mode_info.disp_priority == 2)) { 1133 DRM_DEBUG_KMS("force priority to high\n"); 1134 } 1135 1136 /* watermark for low clocks */ 1137 if (adev->pm.dpm_enabled) { 1138 wm_low.yclk = 1139 amdgpu_dpm_get_mclk(adev, true) * 10; 1140 wm_low.sclk = 1141 amdgpu_dpm_get_sclk(adev, true) * 10; 1142 } else { 1143 wm_low.yclk = adev->pm.current_mclk * 10; 1144 wm_low.sclk = adev->pm.current_sclk * 10; 1145 } 1146 1147 wm_low.disp_clk = mode->clock; 1148 wm_low.src_width = mode->crtc_hdisplay; 1149 wm_low.active_time = active_time; 1150 wm_low.blank_time = line_time - wm_low.active_time; 1151 wm_low.interlaced = false; 1152 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1153 wm_low.interlaced = true; 1154 wm_low.vsc = amdgpu_crtc->vsc; 1155 wm_low.vtaps = 1; 1156 if (amdgpu_crtc->rmx_type != RMX_OFF) 1157 wm_low.vtaps = 2; 1158 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1159 wm_low.lb_size = lb_size; 1160 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1161 wm_low.num_heads = num_heads; 1162 1163 /* set for low clocks */ 1164 latency_watermark_b = min(dce_v8_0_latency_watermark(&wm_low), (u32)65535); 1165 1166 /* possibly force display priority to high */ 1167 /* should really do this at mode validation time... */ 1168 if (!dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1169 !dce_v8_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1170 !dce_v8_0_check_latency_hiding(&wm_low) || 1171 (adev->mode_info.disp_priority == 2)) { 1172 DRM_DEBUG_KMS("force priority to high\n"); 1173 } 1174 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1175 } 1176 1177 /* select wm A */ 1178 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1179 tmp = wm_mask; 1180 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1181 tmp |= (1 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1182 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1183 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1184 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1185 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1186 /* select wm B */ 1187 tmp = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1188 tmp &= ~(3 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1189 tmp |= (2 << DPG_WATERMARK_MASK_CONTROL__URGENCY_WATERMARK_MASK__SHIFT); 1190 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1191 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1192 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1193 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1194 /* restore original selection */ 1195 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1196 1197 /* save values for DPM */ 1198 amdgpu_crtc->line_time = line_time; 1199 amdgpu_crtc->wm_high = latency_watermark_a; 1200 amdgpu_crtc->wm_low = latency_watermark_b; 1201 /* Save number of lines the linebuffer leads before the scanout */ 1202 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1203 } 1204 1205 /** 1206 * dce_v8_0_bandwidth_update - program display watermarks 1207 * 1208 * @adev: amdgpu_device pointer 1209 * 1210 * Calculate and program the display watermarks and line 1211 * buffer allocation (CIK). 1212 */ 1213 static void dce_v8_0_bandwidth_update(struct amdgpu_device *adev) 1214 { 1215 struct drm_display_mode *mode = NULL; 1216 u32 num_heads = 0, lb_size; 1217 int i; 1218 1219 amdgpu_update_display_priority(adev); 1220 1221 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1222 if (adev->mode_info.crtcs[i]->base.enabled) 1223 num_heads++; 1224 } 1225 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1226 mode = &adev->mode_info.crtcs[i]->base.mode; 1227 lb_size = dce_v8_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1228 dce_v8_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1229 lb_size, num_heads); 1230 } 1231 } 1232 1233 static void dce_v8_0_audio_get_connected_pins(struct amdgpu_device *adev) 1234 { 1235 int i; 1236 u32 offset, tmp; 1237 1238 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1239 offset = adev->mode_info.audio.pin[i].offset; 1240 tmp = RREG32_AUDIO_ENDPT(offset, 1241 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1242 if (((tmp & 1243 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1244 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1245 adev->mode_info.audio.pin[i].connected = false; 1246 else 1247 adev->mode_info.audio.pin[i].connected = true; 1248 } 1249 } 1250 1251 static struct amdgpu_audio_pin *dce_v8_0_audio_get_pin(struct amdgpu_device *adev) 1252 { 1253 int i; 1254 1255 dce_v8_0_audio_get_connected_pins(adev); 1256 1257 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1258 if (adev->mode_info.audio.pin[i].connected) 1259 return &adev->mode_info.audio.pin[i]; 1260 } 1261 DRM_ERROR("No connected audio pins found!\n"); 1262 return NULL; 1263 } 1264 1265 static void dce_v8_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1266 { 1267 struct amdgpu_device *adev = encoder->dev->dev_private; 1268 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1269 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1270 u32 offset; 1271 1272 if (!dig || !dig->afmt || !dig->afmt->pin) 1273 return; 1274 1275 offset = dig->afmt->offset; 1276 1277 WREG32(mmAFMT_AUDIO_SRC_CONTROL + offset, 1278 (dig->afmt->pin->id << AFMT_AUDIO_SRC_CONTROL__AFMT_AUDIO_SRC_SELECT__SHIFT)); 1279 } 1280 1281 static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, 1282 struct drm_display_mode *mode) 1283 { 1284 struct amdgpu_device *adev = encoder->dev->dev_private; 1285 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1286 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1287 struct drm_connector *connector; 1288 struct amdgpu_connector *amdgpu_connector = NULL; 1289 u32 tmp = 0, offset; 1290 1291 if (!dig || !dig->afmt || !dig->afmt->pin) 1292 return; 1293 1294 offset = dig->afmt->pin->offset; 1295 1296 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1297 if (connector->encoder == encoder) { 1298 amdgpu_connector = to_amdgpu_connector(connector); 1299 break; 1300 } 1301 } 1302 1303 if (!amdgpu_connector) { 1304 DRM_ERROR("Couldn't find encoder's connector\n"); 1305 return; 1306 } 1307 1308 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1309 if (connector->latency_present[1]) 1310 tmp = 1311 (connector->video_latency[1] << 1312 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1313 (connector->audio_latency[1] << 1314 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1315 else 1316 tmp = 1317 (0 << 1318 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1319 (0 << 1320 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1321 } else { 1322 if (connector->latency_present[0]) 1323 tmp = 1324 (connector->video_latency[0] << 1325 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1326 (connector->audio_latency[0] << 1327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1328 else 1329 tmp = 1330 (0 << 1331 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__VIDEO_LIPSYNC__SHIFT) | 1332 (0 << 1333 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC__AUDIO_LIPSYNC__SHIFT); 1334 1335 } 1336 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1337 } 1338 1339 static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1340 { 1341 struct amdgpu_device *adev = encoder->dev->dev_private; 1342 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1343 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1344 struct drm_connector *connector; 1345 struct amdgpu_connector *amdgpu_connector = NULL; 1346 u32 offset, tmp; 1347 u8 *sadb = NULL; 1348 int sad_count; 1349 1350 if (!dig || !dig->afmt || !dig->afmt->pin) 1351 return; 1352 1353 offset = dig->afmt->pin->offset; 1354 1355 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1356 if (connector->encoder == encoder) { 1357 amdgpu_connector = to_amdgpu_connector(connector); 1358 break; 1359 } 1360 } 1361 1362 if (!amdgpu_connector) { 1363 DRM_ERROR("Couldn't find encoder's connector\n"); 1364 return; 1365 } 1366 1367 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1368 if (sad_count < 0) { 1369 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1370 sad_count = 0; 1371 } 1372 1373 /* program the speaker allocation */ 1374 tmp = RREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1375 tmp &= ~(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__DP_CONNECTION_MASK | 1376 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION_MASK); 1377 /* set HDMI mode */ 1378 tmp |= AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__HDMI_CONNECTION_MASK; 1379 if (sad_count) 1380 tmp |= (sadb[0] << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); 1381 else 1382 tmp |= (5 << AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER__SPEAKER_ALLOCATION__SHIFT); /* stereo */ 1383 WREG32_AUDIO_ENDPT(offset, ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1384 1385 kfree(sadb); 1386 } 1387 1388 static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) 1389 { 1390 struct amdgpu_device *adev = encoder->dev->dev_private; 1391 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1392 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1393 u32 offset; 1394 struct drm_connector *connector; 1395 struct amdgpu_connector *amdgpu_connector = NULL; 1396 struct cea_sad *sads; 1397 int i, sad_count; 1398 1399 static const u16 eld_reg_to_type[][2] = { 1400 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1401 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1402 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1403 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1404 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1405 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1406 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1407 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1408 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1409 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1410 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1411 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1412 }; 1413 1414 if (!dig || !dig->afmt || !dig->afmt->pin) 1415 return; 1416 1417 offset = dig->afmt->pin->offset; 1418 1419 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1420 if (connector->encoder == encoder) { 1421 amdgpu_connector = to_amdgpu_connector(connector); 1422 break; 1423 } 1424 } 1425 1426 if (!amdgpu_connector) { 1427 DRM_ERROR("Couldn't find encoder's connector\n"); 1428 return; 1429 } 1430 1431 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1432 if (sad_count <= 0) { 1433 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1434 return; 1435 } 1436 BUG_ON(!sads); 1437 1438 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1439 u32 value = 0; 1440 u8 stereo_freqs = 0; 1441 int max_channels = -1; 1442 int j; 1443 1444 for (j = 0; j < sad_count; j++) { 1445 struct cea_sad *sad = &sads[j]; 1446 1447 if (sad->format == eld_reg_to_type[i][1]) { 1448 if (sad->channels > max_channels) { 1449 value = (sad->channels << 1450 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__MAX_CHANNELS__SHIFT) | 1451 (sad->byte2 << 1452 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__DESCRIPTOR_BYTE_2__SHIFT) | 1453 (sad->freq << 1454 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES__SHIFT); 1455 max_channels = sad->channels; 1456 } 1457 1458 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1459 stereo_freqs |= sad->freq; 1460 else 1461 break; 1462 } 1463 } 1464 1465 value |= (stereo_freqs << 1466 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0__SUPPORTED_FREQUENCIES_STEREO__SHIFT); 1467 1468 WREG32_AUDIO_ENDPT(offset, eld_reg_to_type[i][0], value); 1469 } 1470 1471 kfree(sads); 1472 } 1473 1474 static void dce_v8_0_audio_enable(struct amdgpu_device *adev, 1475 struct amdgpu_audio_pin *pin, 1476 bool enable) 1477 { 1478 if (!pin) 1479 return; 1480 1481 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1482 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1483 } 1484 1485 static const u32 pin_offsets[7] = 1486 { 1487 (0x1780 - 0x1780), 1488 (0x1786 - 0x1780), 1489 (0x178c - 0x1780), 1490 (0x1792 - 0x1780), 1491 (0x1798 - 0x1780), 1492 (0x179d - 0x1780), 1493 (0x17a4 - 0x1780), 1494 }; 1495 1496 static int dce_v8_0_audio_init(struct amdgpu_device *adev) 1497 { 1498 int i; 1499 1500 if (!amdgpu_audio) 1501 return 0; 1502 1503 adev->mode_info.audio.enabled = true; 1504 1505 if (adev->asic_type == CHIP_KAVERI) /* KV: 4 streams, 7 endpoints */ 1506 adev->mode_info.audio.num_pins = 7; 1507 else if ((adev->asic_type == CHIP_KABINI) || 1508 (adev->asic_type == CHIP_MULLINS)) /* KB/ML: 2 streams, 3 endpoints */ 1509 adev->mode_info.audio.num_pins = 3; 1510 else if ((adev->asic_type == CHIP_BONAIRE) || 1511 (adev->asic_type == CHIP_HAWAII))/* BN/HW: 6 streams, 7 endpoints */ 1512 adev->mode_info.audio.num_pins = 7; 1513 else 1514 adev->mode_info.audio.num_pins = 3; 1515 1516 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1517 adev->mode_info.audio.pin[i].channels = -1; 1518 adev->mode_info.audio.pin[i].rate = -1; 1519 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1520 adev->mode_info.audio.pin[i].status_bits = 0; 1521 adev->mode_info.audio.pin[i].category_code = 0; 1522 adev->mode_info.audio.pin[i].connected = false; 1523 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1524 adev->mode_info.audio.pin[i].id = i; 1525 /* disable audio. it will be set up later */ 1526 /* XXX remove once we switch to ip funcs */ 1527 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1528 } 1529 1530 return 0; 1531 } 1532 1533 static void dce_v8_0_audio_fini(struct amdgpu_device *adev) 1534 { 1535 int i; 1536 1537 if (!amdgpu_audio) 1538 return; 1539 1540 if (!adev->mode_info.audio.enabled) 1541 return; 1542 1543 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1544 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1545 1546 adev->mode_info.audio.enabled = false; 1547 } 1548 1549 /* 1550 * update the N and CTS parameters for a given pixel clock rate 1551 */ 1552 static void dce_v8_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1553 { 1554 struct drm_device *dev = encoder->dev; 1555 struct amdgpu_device *adev = dev->dev_private; 1556 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1557 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1558 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1559 uint32_t offset = dig->afmt->offset; 1560 1561 WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz << HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT)); 1562 WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz); 1563 1564 WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz << HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT)); 1565 WREG32(mmHDMI_ACR_44_1 + offset, acr.n_44_1khz); 1566 1567 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); 1568 WREG32(mmHDMI_ACR_48_1 + offset, acr.n_48khz); 1569 } 1570 1571 /* 1572 * build a HDMI Video Info Frame 1573 */ 1574 static void dce_v8_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1575 void *buffer, size_t size) 1576 { 1577 struct drm_device *dev = encoder->dev; 1578 struct amdgpu_device *adev = dev->dev_private; 1579 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1580 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1581 uint32_t offset = dig->afmt->offset; 1582 uint8_t *frame = buffer + 3; 1583 uint8_t *header = buffer; 1584 1585 WREG32(mmAFMT_AVI_INFO0 + offset, 1586 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1587 WREG32(mmAFMT_AVI_INFO1 + offset, 1588 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1589 WREG32(mmAFMT_AVI_INFO2 + offset, 1590 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1591 WREG32(mmAFMT_AVI_INFO3 + offset, 1592 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1593 } 1594 1595 static void dce_v8_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1596 { 1597 struct drm_device *dev = encoder->dev; 1598 struct amdgpu_device *adev = dev->dev_private; 1599 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1600 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1601 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1602 u32 dto_phase = 24 * 1000; 1603 u32 dto_modulo = clock; 1604 1605 if (!dig || !dig->afmt) 1606 return; 1607 1608 /* XXX two dtos; generally use dto0 for hdmi */ 1609 /* Express [24MHz / target pixel clock] as an exact rational 1610 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1611 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1612 */ 1613 WREG32(mmDCCG_AUDIO_DTO_SOURCE, (amdgpu_crtc->crtc_id << DCCG_AUDIO_DTO_SOURCE__DCCG_AUDIO_DTO0_SOURCE_SEL__SHIFT)); 1614 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1615 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1616 } 1617 1618 /* 1619 * update the info frames with the data from the current display mode 1620 */ 1621 static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, 1622 struct drm_display_mode *mode) 1623 { 1624 struct drm_device *dev = encoder->dev; 1625 struct amdgpu_device *adev = dev->dev_private; 1626 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1627 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1628 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1629 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1630 struct hdmi_avi_infoframe frame; 1631 uint32_t offset, val; 1632 ssize_t err; 1633 int bpc = 8; 1634 1635 if (!dig || !dig->afmt) 1636 return; 1637 1638 /* Silent, r600_hdmi_enable will raise WARN for us */ 1639 if (!dig->afmt->enabled) 1640 return; 1641 1642 offset = dig->afmt->offset; 1643 1644 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1645 if (encoder->crtc) { 1646 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1647 bpc = amdgpu_crtc->bpc; 1648 } 1649 1650 /* disable audio prior to setting up hw */ 1651 dig->afmt->pin = dce_v8_0_audio_get_pin(adev); 1652 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1653 1654 dce_v8_0_audio_set_dto(encoder, mode->clock); 1655 1656 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1657 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK); /* send null packets when required */ 1658 1659 WREG32(mmAFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 1660 1661 val = RREG32(mmHDMI_CONTROL + offset); 1662 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1663 val &= ~HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH_MASK; 1664 1665 switch (bpc) { 1666 case 0: 1667 case 6: 1668 case 8: 1669 case 16: 1670 default: 1671 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1672 connector->name, bpc); 1673 break; 1674 case 10: 1675 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1676 val |= 1 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1677 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1678 connector->name); 1679 break; 1680 case 12: 1681 val |= HDMI_CONTROL__HDMI_DEEP_COLOR_ENABLE_MASK; 1682 val |= 2 << HDMI_CONTROL__HDMI_DEEP_COLOR_DEPTH__SHIFT; 1683 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1684 connector->name); 1685 break; 1686 } 1687 1688 WREG32(mmHDMI_CONTROL + offset, val); 1689 1690 WREG32(mmHDMI_VBI_PACKET_CONTROL + offset, 1691 HDMI_VBI_PACKET_CONTROL__HDMI_NULL_SEND_MASK | /* send null packets when required */ 1692 HDMI_VBI_PACKET_CONTROL__HDMI_GC_SEND_MASK | /* send general control packets */ 1693 HDMI_VBI_PACKET_CONTROL__HDMI_GC_CONT_MASK); /* send general control packets every frame */ 1694 1695 WREG32(mmHDMI_INFOFRAME_CONTROL0 + offset, 1696 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_SEND_MASK | /* enable audio info frames (frames won't be set until audio is enabled) */ 1697 HDMI_INFOFRAME_CONTROL0__HDMI_AUDIO_INFO_CONT_MASK); /* required for audio info values to be updated */ 1698 1699 WREG32(mmAFMT_INFOFRAME_CONTROL0 + offset, 1700 AFMT_INFOFRAME_CONTROL0__AFMT_AUDIO_INFO_UPDATE_MASK); /* required for audio info values to be updated */ 1701 1702 WREG32(mmHDMI_INFOFRAME_CONTROL1 + offset, 1703 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AUDIO_INFO_LINE__SHIFT)); /* anything other than 0 */ 1704 1705 WREG32(mmHDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 1706 1707 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + offset, 1708 (1 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_DELAY_EN__SHIFT) | /* set the default audio delay */ 1709 (3 << HDMI_AUDIO_PACKET_CONTROL__HDMI_AUDIO_PACKETS_PER_LINE__SHIFT)); /* should be suffient for all audio modes and small enough for all hblanks */ 1710 1711 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1712 AFMT_AUDIO_PACKET_CONTROL__AFMT_60958_CS_UPDATE_MASK); /* allow 60958 channel status fields to be updated */ 1713 1714 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */ 1715 1716 if (bpc > 8) 1717 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1718 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1719 else 1720 WREG32(mmHDMI_ACR_PACKET_CONTROL + offset, 1721 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_SOURCE_MASK | /* select SW CTS value */ 1722 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_AUTO_SEND_MASK); /* allow hw to sent ACR packets when required */ 1723 1724 dce_v8_0_afmt_update_ACR(encoder, mode->clock); 1725 1726 WREG32(mmAFMT_60958_0 + offset, 1727 (1 << AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L__SHIFT)); 1728 1729 WREG32(mmAFMT_60958_1 + offset, 1730 (2 << AFMT_60958_1__AFMT_60958_CS_CHANNEL_NUMBER_R__SHIFT)); 1731 1732 WREG32(mmAFMT_60958_2 + offset, 1733 (3 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_2__SHIFT) | 1734 (4 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_3__SHIFT) | 1735 (5 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_4__SHIFT) | 1736 (6 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_5__SHIFT) | 1737 (7 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_6__SHIFT) | 1738 (8 << AFMT_60958_2__AFMT_60958_CS_CHANNEL_NUMBER_7__SHIFT)); 1739 1740 dce_v8_0_audio_write_speaker_allocation(encoder); 1741 1742 1743 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + offset, 1744 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1745 1746 dce_v8_0_afmt_audio_select_pin(encoder); 1747 dce_v8_0_audio_write_sad_regs(encoder); 1748 dce_v8_0_audio_write_latency_fields(encoder, mode); 1749 1750 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1751 if (err < 0) { 1752 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1753 return; 1754 } 1755 1756 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1757 if (err < 0) { 1758 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1759 return; 1760 } 1761 1762 dce_v8_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1763 1764 WREG32_OR(mmHDMI_INFOFRAME_CONTROL0 + offset, 1765 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_SEND_MASK | /* enable AVI info frames */ 1766 HDMI_INFOFRAME_CONTROL0__HDMI_AVI_INFO_CONT_MASK); /* required for audio info values to be updated */ 1767 1768 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, 1769 (2 << HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE__SHIFT), /* anything other than 0 */ 1770 ~HDMI_INFOFRAME_CONTROL1__HDMI_AVI_INFO_LINE_MASK); 1771 1772 WREG32_OR(mmAFMT_AUDIO_PACKET_CONTROL + offset, 1773 AFMT_AUDIO_PACKET_CONTROL__AFMT_AUDIO_SAMPLE_SEND_MASK); /* send audio packets */ 1774 1775 WREG32(mmAFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 1776 WREG32(mmAFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); 1777 WREG32(mmAFMT_RAMP_CONTROL2 + offset, 0x00000001); 1778 WREG32(mmAFMT_RAMP_CONTROL3 + offset, 0x00000001); 1779 1780 /* enable audio after setting up hw */ 1781 dce_v8_0_audio_enable(adev, dig->afmt->pin, true); 1782 } 1783 1784 static void dce_v8_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1785 { 1786 struct drm_device *dev = encoder->dev; 1787 struct amdgpu_device *adev = dev->dev_private; 1788 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1789 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1790 1791 if (!dig || !dig->afmt) 1792 return; 1793 1794 /* Silent, r600_hdmi_enable will raise WARN for us */ 1795 if (enable && dig->afmt->enabled) 1796 return; 1797 if (!enable && !dig->afmt->enabled) 1798 return; 1799 1800 if (!enable && dig->afmt->pin) { 1801 dce_v8_0_audio_enable(adev, dig->afmt->pin, false); 1802 dig->afmt->pin = NULL; 1803 } 1804 1805 dig->afmt->enabled = enable; 1806 1807 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1808 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1809 } 1810 1811 static int dce_v8_0_afmt_init(struct amdgpu_device *adev) 1812 { 1813 int i; 1814 1815 for (i = 0; i < adev->mode_info.num_dig; i++) 1816 adev->mode_info.afmt[i] = NULL; 1817 1818 /* DCE8 has audio blocks tied to DIG encoders */ 1819 for (i = 0; i < adev->mode_info.num_dig; i++) { 1820 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1821 if (adev->mode_info.afmt[i]) { 1822 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1823 adev->mode_info.afmt[i]->id = i; 1824 } else { 1825 int j; 1826 for (j = 0; j < i; j++) { 1827 kfree(adev->mode_info.afmt[j]); 1828 adev->mode_info.afmt[j] = NULL; 1829 } 1830 return -ENOMEM; 1831 } 1832 } 1833 return 0; 1834 } 1835 1836 static void dce_v8_0_afmt_fini(struct amdgpu_device *adev) 1837 { 1838 int i; 1839 1840 for (i = 0; i < adev->mode_info.num_dig; i++) { 1841 kfree(adev->mode_info.afmt[i]); 1842 adev->mode_info.afmt[i] = NULL; 1843 } 1844 } 1845 1846 static const u32 vga_control_regs[6] = 1847 { 1848 mmD1VGA_CONTROL, 1849 mmD2VGA_CONTROL, 1850 mmD3VGA_CONTROL, 1851 mmD4VGA_CONTROL, 1852 mmD5VGA_CONTROL, 1853 mmD6VGA_CONTROL, 1854 }; 1855 1856 static void dce_v8_0_vga_enable(struct drm_crtc *crtc, bool enable) 1857 { 1858 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1859 struct drm_device *dev = crtc->dev; 1860 struct amdgpu_device *adev = dev->dev_private; 1861 u32 vga_control; 1862 1863 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1864 if (enable) 1865 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1866 else 1867 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1868 } 1869 1870 static void dce_v8_0_grph_enable(struct drm_crtc *crtc, bool enable) 1871 { 1872 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1873 struct drm_device *dev = crtc->dev; 1874 struct amdgpu_device *adev = dev->dev_private; 1875 1876 if (enable) 1877 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1878 else 1879 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1880 } 1881 1882 static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, 1883 struct drm_framebuffer *fb, 1884 int x, int y, int atomic) 1885 { 1886 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1887 struct drm_device *dev = crtc->dev; 1888 struct amdgpu_device *adev = dev->dev_private; 1889 struct amdgpu_framebuffer *amdgpu_fb; 1890 struct drm_framebuffer *target_fb; 1891 struct drm_gem_object *obj; 1892 struct amdgpu_bo *abo; 1893 uint64_t fb_location, tiling_flags; 1894 uint32_t fb_format, fb_pitch_pixels; 1895 u32 fb_swap = (GRPH_ENDIAN_NONE << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1896 u32 pipe_config; 1897 u32 viewport_w, viewport_h; 1898 int r; 1899 bool bypass_lut = false; 1900 struct drm_format_name_buf format_name; 1901 1902 /* no fb bound */ 1903 if (!atomic && !crtc->primary->fb) { 1904 DRM_DEBUG_KMS("No FB bound\n"); 1905 return 0; 1906 } 1907 1908 if (atomic) { 1909 amdgpu_fb = to_amdgpu_framebuffer(fb); 1910 target_fb = fb; 1911 } else { 1912 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 1913 target_fb = crtc->primary->fb; 1914 } 1915 1916 /* If atomic, assume fb object is pinned & idle & fenced and 1917 * just update base pointers 1918 */ 1919 obj = amdgpu_fb->obj; 1920 abo = gem_to_amdgpu_bo(obj); 1921 r = amdgpu_bo_reserve(abo, false); 1922 if (unlikely(r != 0)) 1923 return r; 1924 1925 if (atomic) { 1926 fb_location = amdgpu_bo_gpu_offset(abo); 1927 } else { 1928 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1929 if (unlikely(r != 0)) { 1930 amdgpu_bo_unreserve(abo); 1931 return -EINVAL; 1932 } 1933 } 1934 1935 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1936 amdgpu_bo_unreserve(abo); 1937 1938 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1939 1940 switch (target_fb->format->format) { 1941 case DRM_FORMAT_C8: 1942 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1943 (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1944 break; 1945 case DRM_FORMAT_XRGB4444: 1946 case DRM_FORMAT_ARGB4444: 1947 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1948 (GRPH_FORMAT_ARGB4444 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1949 #ifdef __BIG_ENDIAN 1950 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1951 #endif 1952 break; 1953 case DRM_FORMAT_XRGB1555: 1954 case DRM_FORMAT_ARGB1555: 1955 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1956 (GRPH_FORMAT_ARGB1555 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1957 #ifdef __BIG_ENDIAN 1958 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1959 #endif 1960 break; 1961 case DRM_FORMAT_BGRX5551: 1962 case DRM_FORMAT_BGRA5551: 1963 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1964 (GRPH_FORMAT_BGRA5551 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1965 #ifdef __BIG_ENDIAN 1966 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1967 #endif 1968 break; 1969 case DRM_FORMAT_RGB565: 1970 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1971 (GRPH_FORMAT_ARGB565 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1972 #ifdef __BIG_ENDIAN 1973 fb_swap = (GRPH_ENDIAN_8IN16 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1974 #endif 1975 break; 1976 case DRM_FORMAT_XRGB8888: 1977 case DRM_FORMAT_ARGB8888: 1978 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1979 (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1980 #ifdef __BIG_ENDIAN 1981 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1982 #endif 1983 break; 1984 case DRM_FORMAT_XRGB2101010: 1985 case DRM_FORMAT_ARGB2101010: 1986 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1987 (GRPH_FORMAT_ARGB2101010 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1988 #ifdef __BIG_ENDIAN 1989 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 1990 #endif 1991 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1992 bypass_lut = true; 1993 break; 1994 case DRM_FORMAT_BGRX1010102: 1995 case DRM_FORMAT_BGRA1010102: 1996 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | 1997 (GRPH_FORMAT_BGRA1010102 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); 1998 #ifdef __BIG_ENDIAN 1999 fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); 2000 #endif 2001 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2002 bypass_lut = true; 2003 break; 2004 default: 2005 DRM_ERROR("Unsupported screen format %s\n", 2006 drm_get_format_name(target_fb->format->format, &format_name)); 2007 return -EINVAL; 2008 } 2009 2010 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2011 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2012 2013 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2014 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2015 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2016 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2017 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2018 2019 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); 2020 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2021 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); 2022 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); 2023 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); 2024 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); 2025 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); 2026 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2027 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); 2028 } 2029 2030 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); 2031 2032 dce_v8_0_vga_enable(crtc, false); 2033 2034 /* Make sure surface address is updated at vertical blank rather than 2035 * horizontal blank 2036 */ 2037 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2038 2039 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2040 upper_32_bits(fb_location)); 2041 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2042 upper_32_bits(fb_location)); 2043 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2044 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2045 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2046 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2047 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2048 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2049 2050 /* 2051 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2052 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2053 * retain the full precision throughout the pipeline. 2054 */ 2055 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, 2056 (bypass_lut ? LUT_10BIT_BYPASS_EN : 0), 2057 ~LUT_10BIT_BYPASS_EN); 2058 2059 if (bypass_lut) 2060 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2061 2062 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2063 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2064 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2065 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2066 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2067 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2068 2069 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2070 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2071 2072 dce_v8_0_grph_enable(crtc, true); 2073 2074 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2075 target_fb->height); 2076 2077 x &= ~3; 2078 y &= ~1; 2079 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2080 (x << 16) | y); 2081 viewport_w = crtc->mode.hdisplay; 2082 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2083 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2084 (viewport_w << 16) | viewport_h); 2085 2086 /* set pageflip to happen anywhere in vblank interval */ 2087 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2088 2089 if (!atomic && fb && fb != crtc->primary->fb) { 2090 amdgpu_fb = to_amdgpu_framebuffer(fb); 2091 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2092 r = amdgpu_bo_reserve(abo, true); 2093 if (unlikely(r != 0)) 2094 return r; 2095 amdgpu_bo_unpin(abo); 2096 amdgpu_bo_unreserve(abo); 2097 } 2098 2099 /* Bytes per pixel may have changed */ 2100 dce_v8_0_bandwidth_update(adev); 2101 2102 return 0; 2103 } 2104 2105 static void dce_v8_0_set_interleave(struct drm_crtc *crtc, 2106 struct drm_display_mode *mode) 2107 { 2108 struct drm_device *dev = crtc->dev; 2109 struct amdgpu_device *adev = dev->dev_private; 2110 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2111 2112 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2113 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 2114 LB_DATA_FORMAT__INTERLEAVE_EN__SHIFT); 2115 else 2116 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2117 } 2118 2119 static void dce_v8_0_crtc_load_lut(struct drm_crtc *crtc) 2120 { 2121 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2122 struct drm_device *dev = crtc->dev; 2123 struct amdgpu_device *adev = dev->dev_private; 2124 int i; 2125 2126 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2127 2128 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2129 ((INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2130 (INPUT_CSC_BYPASS << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2131 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2132 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2133 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2134 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2135 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2136 ((INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2137 (INPUT_GAMMA_USE_LUT << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2138 2139 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2140 2141 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2142 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2143 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2144 2145 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2146 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2147 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2148 2149 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2150 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2151 2152 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2153 for (i = 0; i < 256; i++) { 2154 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2155 (amdgpu_crtc->lut_r[i] << 20) | 2156 (amdgpu_crtc->lut_g[i] << 10) | 2157 (amdgpu_crtc->lut_b[i] << 0)); 2158 } 2159 2160 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2161 ((DEGAMMA_BYPASS << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2162 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2163 (DEGAMMA_BYPASS << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2164 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2165 ((GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2166 (GAMUT_REMAP_BYPASS << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2167 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2168 ((REGAMMA_BYPASS << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2169 (REGAMMA_BYPASS << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2170 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2171 ((OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2172 (OUTPUT_CSC_BYPASS << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2173 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2174 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2175 /* XXX this only needs to be programmed once per crtc at startup, 2176 * not sure where the best place for it is 2177 */ 2178 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, 2179 ALPHA_CONTROL__CURSOR_ALPHA_BLND_ENA_MASK); 2180 } 2181 2182 static int dce_v8_0_pick_dig_encoder(struct drm_encoder *encoder) 2183 { 2184 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2185 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2186 2187 switch (amdgpu_encoder->encoder_id) { 2188 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2189 if (dig->linkb) 2190 return 1; 2191 else 2192 return 0; 2193 break; 2194 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2195 if (dig->linkb) 2196 return 3; 2197 else 2198 return 2; 2199 break; 2200 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2201 if (dig->linkb) 2202 return 5; 2203 else 2204 return 4; 2205 break; 2206 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2207 return 6; 2208 break; 2209 default: 2210 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2211 return 0; 2212 } 2213 } 2214 2215 /** 2216 * dce_v8_0_pick_pll - Allocate a PPLL for use by the crtc. 2217 * 2218 * @crtc: drm crtc 2219 * 2220 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2221 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2222 * monitors a dedicated PPLL must be used. If a particular board has 2223 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2224 * as there is no need to program the PLL itself. If we are not able to 2225 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2226 * avoid messing up an existing monitor. 2227 * 2228 * Asic specific PLL information 2229 * 2230 * DCE 8.x 2231 * KB/KV 2232 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2233 * CI 2234 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2235 * 2236 */ 2237 static u32 dce_v8_0_pick_pll(struct drm_crtc *crtc) 2238 { 2239 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2240 struct drm_device *dev = crtc->dev; 2241 struct amdgpu_device *adev = dev->dev_private; 2242 u32 pll_in_use; 2243 int pll; 2244 2245 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2246 if (adev->clock.dp_extclk) 2247 /* skip PPLL programming if using ext clock */ 2248 return ATOM_PPLL_INVALID; 2249 else { 2250 /* use the same PPLL for all DP monitors */ 2251 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2252 if (pll != ATOM_PPLL_INVALID) 2253 return pll; 2254 } 2255 } else { 2256 /* use the same PPLL for all monitors with the same clock */ 2257 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2258 if (pll != ATOM_PPLL_INVALID) 2259 return pll; 2260 } 2261 /* otherwise, pick one of the plls */ 2262 if ((adev->asic_type == CHIP_KABINI) || 2263 (adev->asic_type == CHIP_MULLINS)) { 2264 /* KB/ML has PPLL1 and PPLL2 */ 2265 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2266 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2267 return ATOM_PPLL2; 2268 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2269 return ATOM_PPLL1; 2270 DRM_ERROR("unable to allocate a PPLL\n"); 2271 return ATOM_PPLL_INVALID; 2272 } else { 2273 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 2274 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2275 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2276 return ATOM_PPLL2; 2277 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2278 return ATOM_PPLL1; 2279 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2280 return ATOM_PPLL0; 2281 DRM_ERROR("unable to allocate a PPLL\n"); 2282 return ATOM_PPLL_INVALID; 2283 } 2284 return ATOM_PPLL_INVALID; 2285 } 2286 2287 static void dce_v8_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2288 { 2289 struct amdgpu_device *adev = crtc->dev->dev_private; 2290 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2291 uint32_t cur_lock; 2292 2293 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2294 if (lock) 2295 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2296 else 2297 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2298 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2299 } 2300 2301 static void dce_v8_0_hide_cursor(struct drm_crtc *crtc) 2302 { 2303 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2304 struct amdgpu_device *adev = crtc->dev->dev_private; 2305 2306 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2307 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2308 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2309 } 2310 2311 static void dce_v8_0_show_cursor(struct drm_crtc *crtc) 2312 { 2313 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2314 struct amdgpu_device *adev = crtc->dev->dev_private; 2315 2316 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2317 upper_32_bits(amdgpu_crtc->cursor_addr)); 2318 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2319 lower_32_bits(amdgpu_crtc->cursor_addr)); 2320 2321 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2322 CUR_CONTROL__CURSOR_EN_MASK | 2323 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2324 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2325 } 2326 2327 static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc, 2328 int x, int y) 2329 { 2330 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2331 struct amdgpu_device *adev = crtc->dev->dev_private; 2332 int xorigin = 0, yorigin = 0; 2333 2334 amdgpu_crtc->cursor_x = x; 2335 amdgpu_crtc->cursor_y = y; 2336 2337 /* avivo cursor are offset into the total surface */ 2338 x += crtc->x; 2339 y += crtc->y; 2340 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2341 2342 if (x < 0) { 2343 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2344 x = 0; 2345 } 2346 if (y < 0) { 2347 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2348 y = 0; 2349 } 2350 2351 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2352 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2353 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2354 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2355 2356 return 0; 2357 } 2358 2359 static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc, 2360 int x, int y) 2361 { 2362 int ret; 2363 2364 dce_v8_0_lock_cursor(crtc, true); 2365 ret = dce_v8_0_cursor_move_locked(crtc, x, y); 2366 dce_v8_0_lock_cursor(crtc, false); 2367 2368 return ret; 2369 } 2370 2371 static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, 2372 struct drm_file *file_priv, 2373 uint32_t handle, 2374 uint32_t width, 2375 uint32_t height, 2376 int32_t hot_x, 2377 int32_t hot_y) 2378 { 2379 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2380 struct drm_gem_object *obj; 2381 struct amdgpu_bo *aobj; 2382 int ret; 2383 2384 if (!handle) { 2385 /* turn off cursor */ 2386 dce_v8_0_hide_cursor(crtc); 2387 obj = NULL; 2388 goto unpin; 2389 } 2390 2391 if ((width > amdgpu_crtc->max_cursor_width) || 2392 (height > amdgpu_crtc->max_cursor_height)) { 2393 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2394 return -EINVAL; 2395 } 2396 2397 obj = drm_gem_object_lookup(file_priv, handle); 2398 if (!obj) { 2399 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2400 return -ENOENT; 2401 } 2402 2403 aobj = gem_to_amdgpu_bo(obj); 2404 ret = amdgpu_bo_reserve(aobj, false); 2405 if (ret != 0) { 2406 drm_gem_object_unreference_unlocked(obj); 2407 return ret; 2408 } 2409 2410 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2411 amdgpu_bo_unreserve(aobj); 2412 if (ret) { 2413 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2414 drm_gem_object_unreference_unlocked(obj); 2415 return ret; 2416 } 2417 2418 dce_v8_0_lock_cursor(crtc, true); 2419 2420 if (width != amdgpu_crtc->cursor_width || 2421 height != amdgpu_crtc->cursor_height || 2422 hot_x != amdgpu_crtc->cursor_hot_x || 2423 hot_y != amdgpu_crtc->cursor_hot_y) { 2424 int x, y; 2425 2426 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2427 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2428 2429 dce_v8_0_cursor_move_locked(crtc, x, y); 2430 2431 amdgpu_crtc->cursor_width = width; 2432 amdgpu_crtc->cursor_height = height; 2433 amdgpu_crtc->cursor_hot_x = hot_x; 2434 amdgpu_crtc->cursor_hot_y = hot_y; 2435 } 2436 2437 dce_v8_0_show_cursor(crtc); 2438 dce_v8_0_lock_cursor(crtc, false); 2439 2440 unpin: 2441 if (amdgpu_crtc->cursor_bo) { 2442 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2443 ret = amdgpu_bo_reserve(aobj, true); 2444 if (likely(ret == 0)) { 2445 amdgpu_bo_unpin(aobj); 2446 amdgpu_bo_unreserve(aobj); 2447 } 2448 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2449 } 2450 2451 amdgpu_crtc->cursor_bo = obj; 2452 return 0; 2453 } 2454 2455 static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) 2456 { 2457 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2458 2459 if (amdgpu_crtc->cursor_bo) { 2460 dce_v8_0_lock_cursor(crtc, true); 2461 2462 dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2463 amdgpu_crtc->cursor_y); 2464 2465 dce_v8_0_show_cursor(crtc); 2466 2467 dce_v8_0_lock_cursor(crtc, false); 2468 } 2469 } 2470 2471 static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2472 u16 *blue, uint32_t size, 2473 struct drm_modeset_acquire_ctx *ctx) 2474 { 2475 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2476 int i; 2477 2478 /* userspace palettes are always correct as is */ 2479 for (i = 0; i < size; i++) { 2480 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2481 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2482 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2483 } 2484 dce_v8_0_crtc_load_lut(crtc); 2485 2486 return 0; 2487 } 2488 2489 static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) 2490 { 2491 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2492 2493 drm_crtc_cleanup(crtc); 2494 kfree(amdgpu_crtc); 2495 } 2496 2497 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { 2498 .cursor_set2 = dce_v8_0_crtc_cursor_set2, 2499 .cursor_move = dce_v8_0_crtc_cursor_move, 2500 .gamma_set = dce_v8_0_crtc_gamma_set, 2501 .set_config = amdgpu_crtc_set_config, 2502 .destroy = dce_v8_0_crtc_destroy, 2503 .page_flip_target = amdgpu_crtc_page_flip_target, 2504 }; 2505 2506 static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2507 { 2508 struct drm_device *dev = crtc->dev; 2509 struct amdgpu_device *adev = dev->dev_private; 2510 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2511 unsigned type; 2512 2513 switch (mode) { 2514 case DRM_MODE_DPMS_ON: 2515 amdgpu_crtc->enabled = true; 2516 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2517 dce_v8_0_vga_enable(crtc, true); 2518 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2519 dce_v8_0_vga_enable(crtc, false); 2520 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2521 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2522 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2523 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2524 drm_crtc_vblank_on(crtc); 2525 dce_v8_0_crtc_load_lut(crtc); 2526 break; 2527 case DRM_MODE_DPMS_STANDBY: 2528 case DRM_MODE_DPMS_SUSPEND: 2529 case DRM_MODE_DPMS_OFF: 2530 drm_crtc_vblank_off(crtc); 2531 if (amdgpu_crtc->enabled) { 2532 dce_v8_0_vga_enable(crtc, true); 2533 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2534 dce_v8_0_vga_enable(crtc, false); 2535 } 2536 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2537 amdgpu_crtc->enabled = false; 2538 break; 2539 } 2540 /* adjust pm to dpms */ 2541 amdgpu_pm_compute_clocks(adev); 2542 } 2543 2544 static void dce_v8_0_crtc_prepare(struct drm_crtc *crtc) 2545 { 2546 /* disable crtc pair power gating before programming */ 2547 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2548 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2549 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2550 } 2551 2552 static void dce_v8_0_crtc_commit(struct drm_crtc *crtc) 2553 { 2554 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2555 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2556 } 2557 2558 static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) 2559 { 2560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2561 struct drm_device *dev = crtc->dev; 2562 struct amdgpu_device *adev = dev->dev_private; 2563 struct amdgpu_atom_ss ss; 2564 int i; 2565 2566 dce_v8_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2567 if (crtc->primary->fb) { 2568 int r; 2569 struct amdgpu_framebuffer *amdgpu_fb; 2570 struct amdgpu_bo *abo; 2571 2572 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2573 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2574 r = amdgpu_bo_reserve(abo, true); 2575 if (unlikely(r)) 2576 DRM_ERROR("failed to reserve abo before unpin\n"); 2577 else { 2578 amdgpu_bo_unpin(abo); 2579 amdgpu_bo_unreserve(abo); 2580 } 2581 } 2582 /* disable the GRPH */ 2583 dce_v8_0_grph_enable(crtc, false); 2584 2585 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2586 2587 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2588 if (adev->mode_info.crtcs[i] && 2589 adev->mode_info.crtcs[i]->enabled && 2590 i != amdgpu_crtc->crtc_id && 2591 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2592 /* one other crtc is using this pll don't turn 2593 * off the pll 2594 */ 2595 goto done; 2596 } 2597 } 2598 2599 switch (amdgpu_crtc->pll_id) { 2600 case ATOM_PPLL1: 2601 case ATOM_PPLL2: 2602 /* disable the ppll */ 2603 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2604 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2605 break; 2606 case ATOM_PPLL0: 2607 /* disable the ppll */ 2608 if ((adev->asic_type == CHIP_KAVERI) || 2609 (adev->asic_type == CHIP_BONAIRE) || 2610 (adev->asic_type == CHIP_HAWAII)) 2611 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2612 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2613 break; 2614 default: 2615 break; 2616 } 2617 done: 2618 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2619 amdgpu_crtc->adjusted_clock = 0; 2620 amdgpu_crtc->encoder = NULL; 2621 amdgpu_crtc->connector = NULL; 2622 } 2623 2624 static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc, 2625 struct drm_display_mode *mode, 2626 struct drm_display_mode *adjusted_mode, 2627 int x, int y, struct drm_framebuffer *old_fb) 2628 { 2629 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2630 2631 if (!amdgpu_crtc->adjusted_clock) 2632 return -EINVAL; 2633 2634 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2635 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2636 dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2637 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2638 amdgpu_atombios_crtc_scaler_setup(crtc); 2639 dce_v8_0_cursor_reset(crtc); 2640 /* update the hw version fpr dpm */ 2641 amdgpu_crtc->hw_mode = *adjusted_mode; 2642 2643 return 0; 2644 } 2645 2646 static bool dce_v8_0_crtc_mode_fixup(struct drm_crtc *crtc, 2647 const struct drm_display_mode *mode, 2648 struct drm_display_mode *adjusted_mode) 2649 { 2650 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2651 struct drm_device *dev = crtc->dev; 2652 struct drm_encoder *encoder; 2653 2654 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2655 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2656 if (encoder->crtc == crtc) { 2657 amdgpu_crtc->encoder = encoder; 2658 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2659 break; 2660 } 2661 } 2662 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2663 amdgpu_crtc->encoder = NULL; 2664 amdgpu_crtc->connector = NULL; 2665 return false; 2666 } 2667 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2668 return false; 2669 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2670 return false; 2671 /* pick pll */ 2672 amdgpu_crtc->pll_id = dce_v8_0_pick_pll(crtc); 2673 /* if we can't get a PPLL for a non-DP encoder, fail */ 2674 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2675 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2676 return false; 2677 2678 return true; 2679 } 2680 2681 static int dce_v8_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2682 struct drm_framebuffer *old_fb) 2683 { 2684 return dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2685 } 2686 2687 static int dce_v8_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2688 struct drm_framebuffer *fb, 2689 int x, int y, enum mode_set_atomic state) 2690 { 2691 return dce_v8_0_crtc_do_set_base(crtc, fb, x, y, 1); 2692 } 2693 2694 static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { 2695 .dpms = dce_v8_0_crtc_dpms, 2696 .mode_fixup = dce_v8_0_crtc_mode_fixup, 2697 .mode_set = dce_v8_0_crtc_mode_set, 2698 .mode_set_base = dce_v8_0_crtc_set_base, 2699 .mode_set_base_atomic = dce_v8_0_crtc_set_base_atomic, 2700 .prepare = dce_v8_0_crtc_prepare, 2701 .commit = dce_v8_0_crtc_commit, 2702 .load_lut = dce_v8_0_crtc_load_lut, 2703 .disable = dce_v8_0_crtc_disable, 2704 }; 2705 2706 static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) 2707 { 2708 struct amdgpu_crtc *amdgpu_crtc; 2709 int i; 2710 2711 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2712 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2713 if (amdgpu_crtc == NULL) 2714 return -ENOMEM; 2715 2716 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v8_0_crtc_funcs); 2717 2718 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2719 amdgpu_crtc->crtc_id = index; 2720 adev->mode_info.crtcs[index] = amdgpu_crtc; 2721 2722 amdgpu_crtc->max_cursor_width = CIK_CURSOR_WIDTH; 2723 amdgpu_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; 2724 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2725 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2726 2727 for (i = 0; i < 256; i++) { 2728 amdgpu_crtc->lut_r[i] = i << 2; 2729 amdgpu_crtc->lut_g[i] = i << 2; 2730 amdgpu_crtc->lut_b[i] = i << 2; 2731 } 2732 2733 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2734 2735 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2736 amdgpu_crtc->adjusted_clock = 0; 2737 amdgpu_crtc->encoder = NULL; 2738 amdgpu_crtc->connector = NULL; 2739 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v8_0_crtc_helper_funcs); 2740 2741 return 0; 2742 } 2743 2744 static int dce_v8_0_early_init(void *handle) 2745 { 2746 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2747 2748 adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; 2749 adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; 2750 2751 dce_v8_0_set_display_funcs(adev); 2752 dce_v8_0_set_irq_funcs(adev); 2753 2754 adev->mode_info.num_crtc = dce_v8_0_get_num_crtc(adev); 2755 2756 switch (adev->asic_type) { 2757 case CHIP_BONAIRE: 2758 case CHIP_HAWAII: 2759 adev->mode_info.num_hpd = 6; 2760 adev->mode_info.num_dig = 6; 2761 break; 2762 case CHIP_KAVERI: 2763 adev->mode_info.num_hpd = 6; 2764 adev->mode_info.num_dig = 7; 2765 break; 2766 case CHIP_KABINI: 2767 case CHIP_MULLINS: 2768 adev->mode_info.num_hpd = 6; 2769 adev->mode_info.num_dig = 6; /* ? */ 2770 break; 2771 default: 2772 /* FIXME: not supported yet */ 2773 return -EINVAL; 2774 } 2775 2776 return 0; 2777 } 2778 2779 static int dce_v8_0_sw_init(void *handle) 2780 { 2781 int r, i; 2782 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2783 2784 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2785 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2786 if (r) 2787 return r; 2788 } 2789 2790 for (i = 8; i < 20; i += 2) { 2791 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2792 if (r) 2793 return r; 2794 } 2795 2796 /* HPD hotplug */ 2797 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2798 if (r) 2799 return r; 2800 2801 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2802 2803 adev->ddev->mode_config.async_page_flip = true; 2804 2805 adev->ddev->mode_config.max_width = 16384; 2806 adev->ddev->mode_config.max_height = 16384; 2807 2808 adev->ddev->mode_config.preferred_depth = 24; 2809 adev->ddev->mode_config.prefer_shadow = 1; 2810 2811 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2812 2813 r = amdgpu_modeset_create_props(adev); 2814 if (r) 2815 return r; 2816 2817 adev->ddev->mode_config.max_width = 16384; 2818 adev->ddev->mode_config.max_height = 16384; 2819 2820 /* allocate crtcs */ 2821 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2822 r = dce_v8_0_crtc_init(adev, i); 2823 if (r) 2824 return r; 2825 } 2826 2827 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2828 amdgpu_print_display_setup(adev->ddev); 2829 else 2830 return -EINVAL; 2831 2832 /* setup afmt */ 2833 r = dce_v8_0_afmt_init(adev); 2834 if (r) 2835 return r; 2836 2837 r = dce_v8_0_audio_init(adev); 2838 if (r) 2839 return r; 2840 2841 drm_kms_helper_poll_init(adev->ddev); 2842 2843 adev->mode_info.mode_config_initialized = true; 2844 return 0; 2845 } 2846 2847 static int dce_v8_0_sw_fini(void *handle) 2848 { 2849 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2850 2851 kfree(adev->mode_info.bios_hardcoded_edid); 2852 2853 drm_kms_helper_poll_fini(adev->ddev); 2854 2855 dce_v8_0_audio_fini(adev); 2856 2857 dce_v8_0_afmt_fini(adev); 2858 2859 drm_mode_config_cleanup(adev->ddev); 2860 adev->mode_info.mode_config_initialized = false; 2861 2862 return 0; 2863 } 2864 2865 static int dce_v8_0_hw_init(void *handle) 2866 { 2867 int i; 2868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2869 2870 /* init dig PHYs, disp eng pll */ 2871 amdgpu_atombios_encoder_init_dig(adev); 2872 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2873 2874 /* initialize hpd */ 2875 dce_v8_0_hpd_init(adev); 2876 2877 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2878 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2879 } 2880 2881 dce_v8_0_pageflip_interrupt_init(adev); 2882 2883 return 0; 2884 } 2885 2886 static int dce_v8_0_hw_fini(void *handle) 2887 { 2888 int i; 2889 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2890 2891 dce_v8_0_hpd_fini(adev); 2892 2893 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2894 dce_v8_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2895 } 2896 2897 dce_v8_0_pageflip_interrupt_fini(adev); 2898 2899 return 0; 2900 } 2901 2902 static int dce_v8_0_suspend(void *handle) 2903 { 2904 return dce_v8_0_hw_fini(handle); 2905 } 2906 2907 static int dce_v8_0_resume(void *handle) 2908 { 2909 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2910 int ret; 2911 2912 ret = dce_v8_0_hw_init(handle); 2913 2914 /* turn on the BL */ 2915 if (adev->mode_info.bl_encoder) { 2916 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2917 adev->mode_info.bl_encoder); 2918 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2919 bl_level); 2920 } 2921 2922 return ret; 2923 } 2924 2925 static bool dce_v8_0_is_idle(void *handle) 2926 { 2927 return true; 2928 } 2929 2930 static int dce_v8_0_wait_for_idle(void *handle) 2931 { 2932 return 0; 2933 } 2934 2935 static int dce_v8_0_soft_reset(void *handle) 2936 { 2937 u32 srbm_soft_reset = 0, tmp; 2938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2939 2940 if (dce_v8_0_is_display_hung(adev)) 2941 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 2942 2943 if (srbm_soft_reset) { 2944 tmp = RREG32(mmSRBM_SOFT_RESET); 2945 tmp |= srbm_soft_reset; 2946 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2947 WREG32(mmSRBM_SOFT_RESET, tmp); 2948 tmp = RREG32(mmSRBM_SOFT_RESET); 2949 2950 udelay(50); 2951 2952 tmp &= ~srbm_soft_reset; 2953 WREG32(mmSRBM_SOFT_RESET, tmp); 2954 tmp = RREG32(mmSRBM_SOFT_RESET); 2955 2956 /* Wait a little for things to settle down */ 2957 udelay(50); 2958 } 2959 return 0; 2960 } 2961 2962 static void dce_v8_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2963 int crtc, 2964 enum amdgpu_interrupt_state state) 2965 { 2966 u32 reg_block, lb_interrupt_mask; 2967 2968 if (crtc >= adev->mode_info.num_crtc) { 2969 DRM_DEBUG("invalid crtc %d\n", crtc); 2970 return; 2971 } 2972 2973 switch (crtc) { 2974 case 0: 2975 reg_block = CRTC0_REGISTER_OFFSET; 2976 break; 2977 case 1: 2978 reg_block = CRTC1_REGISTER_OFFSET; 2979 break; 2980 case 2: 2981 reg_block = CRTC2_REGISTER_OFFSET; 2982 break; 2983 case 3: 2984 reg_block = CRTC3_REGISTER_OFFSET; 2985 break; 2986 case 4: 2987 reg_block = CRTC4_REGISTER_OFFSET; 2988 break; 2989 case 5: 2990 reg_block = CRTC5_REGISTER_OFFSET; 2991 break; 2992 default: 2993 DRM_DEBUG("invalid crtc %d\n", crtc); 2994 return; 2995 } 2996 2997 switch (state) { 2998 case AMDGPU_IRQ_STATE_DISABLE: 2999 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3000 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3001 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3002 break; 3003 case AMDGPU_IRQ_STATE_ENABLE: 3004 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3005 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK; 3006 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3007 break; 3008 default: 3009 break; 3010 } 3011 } 3012 3013 static void dce_v8_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3014 int crtc, 3015 enum amdgpu_interrupt_state state) 3016 { 3017 u32 reg_block, lb_interrupt_mask; 3018 3019 if (crtc >= adev->mode_info.num_crtc) { 3020 DRM_DEBUG("invalid crtc %d\n", crtc); 3021 return; 3022 } 3023 3024 switch (crtc) { 3025 case 0: 3026 reg_block = CRTC0_REGISTER_OFFSET; 3027 break; 3028 case 1: 3029 reg_block = CRTC1_REGISTER_OFFSET; 3030 break; 3031 case 2: 3032 reg_block = CRTC2_REGISTER_OFFSET; 3033 break; 3034 case 3: 3035 reg_block = CRTC3_REGISTER_OFFSET; 3036 break; 3037 case 4: 3038 reg_block = CRTC4_REGISTER_OFFSET; 3039 break; 3040 case 5: 3041 reg_block = CRTC5_REGISTER_OFFSET; 3042 break; 3043 default: 3044 DRM_DEBUG("invalid crtc %d\n", crtc); 3045 return; 3046 } 3047 3048 switch (state) { 3049 case AMDGPU_IRQ_STATE_DISABLE: 3050 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3051 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3052 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3053 break; 3054 case AMDGPU_IRQ_STATE_ENABLE: 3055 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block); 3056 lb_interrupt_mask |= LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK; 3057 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask); 3058 break; 3059 default: 3060 break; 3061 } 3062 } 3063 3064 static int dce_v8_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3065 struct amdgpu_irq_src *src, 3066 unsigned type, 3067 enum amdgpu_interrupt_state state) 3068 { 3069 u32 dc_hpd_int_cntl; 3070 3071 if (type >= adev->mode_info.num_hpd) { 3072 DRM_DEBUG("invalid hdp %d\n", type); 3073 return 0; 3074 } 3075 3076 switch (state) { 3077 case AMDGPU_IRQ_STATE_DISABLE: 3078 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3079 dc_hpd_int_cntl &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3080 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3081 break; 3082 case AMDGPU_IRQ_STATE_ENABLE: 3083 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3084 dc_hpd_int_cntl |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 3085 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3086 break; 3087 default: 3088 break; 3089 } 3090 3091 return 0; 3092 } 3093 3094 static int dce_v8_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3095 struct amdgpu_irq_src *src, 3096 unsigned type, 3097 enum amdgpu_interrupt_state state) 3098 { 3099 switch (type) { 3100 case AMDGPU_CRTC_IRQ_VBLANK1: 3101 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3102 break; 3103 case AMDGPU_CRTC_IRQ_VBLANK2: 3104 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3105 break; 3106 case AMDGPU_CRTC_IRQ_VBLANK3: 3107 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3108 break; 3109 case AMDGPU_CRTC_IRQ_VBLANK4: 3110 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3111 break; 3112 case AMDGPU_CRTC_IRQ_VBLANK5: 3113 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3114 break; 3115 case AMDGPU_CRTC_IRQ_VBLANK6: 3116 dce_v8_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3117 break; 3118 case AMDGPU_CRTC_IRQ_VLINE1: 3119 dce_v8_0_set_crtc_vline_interrupt_state(adev, 0, state); 3120 break; 3121 case AMDGPU_CRTC_IRQ_VLINE2: 3122 dce_v8_0_set_crtc_vline_interrupt_state(adev, 1, state); 3123 break; 3124 case AMDGPU_CRTC_IRQ_VLINE3: 3125 dce_v8_0_set_crtc_vline_interrupt_state(adev, 2, state); 3126 break; 3127 case AMDGPU_CRTC_IRQ_VLINE4: 3128 dce_v8_0_set_crtc_vline_interrupt_state(adev, 3, state); 3129 break; 3130 case AMDGPU_CRTC_IRQ_VLINE5: 3131 dce_v8_0_set_crtc_vline_interrupt_state(adev, 4, state); 3132 break; 3133 case AMDGPU_CRTC_IRQ_VLINE6: 3134 dce_v8_0_set_crtc_vline_interrupt_state(adev, 5, state); 3135 break; 3136 default: 3137 break; 3138 } 3139 return 0; 3140 } 3141 3142 static int dce_v8_0_crtc_irq(struct amdgpu_device *adev, 3143 struct amdgpu_irq_src *source, 3144 struct amdgpu_iv_entry *entry) 3145 { 3146 unsigned crtc = entry->src_id - 1; 3147 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3148 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3149 3150 switch (entry->src_data[0]) { 3151 case 0: /* vblank */ 3152 if (disp_int & interrupt_status_offsets[crtc].vblank) 3153 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], LB_VBLANK_STATUS__VBLANK_ACK_MASK); 3154 else 3155 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3156 3157 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3158 drm_handle_vblank(adev->ddev, crtc); 3159 } 3160 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3161 break; 3162 case 1: /* vline */ 3163 if (disp_int & interrupt_status_offsets[crtc].vline) 3164 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], LB_VLINE_STATUS__VLINE_ACK_MASK); 3165 else 3166 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3167 3168 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3169 break; 3170 default: 3171 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3172 break; 3173 } 3174 3175 return 0; 3176 } 3177 3178 static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3179 struct amdgpu_irq_src *src, 3180 unsigned type, 3181 enum amdgpu_interrupt_state state) 3182 { 3183 u32 reg; 3184 3185 if (type >= adev->mode_info.num_crtc) { 3186 DRM_ERROR("invalid pageflip crtc %d\n", type); 3187 return -EINVAL; 3188 } 3189 3190 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3191 if (state == AMDGPU_IRQ_STATE_DISABLE) 3192 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3193 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3194 else 3195 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3196 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3197 3198 return 0; 3199 } 3200 3201 static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev, 3202 struct amdgpu_irq_src *source, 3203 struct amdgpu_iv_entry *entry) 3204 { 3205 unsigned long flags; 3206 unsigned crtc_id; 3207 struct amdgpu_crtc *amdgpu_crtc; 3208 struct amdgpu_flip_work *works; 3209 3210 crtc_id = (entry->src_id - 8) >> 1; 3211 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3212 3213 if (crtc_id >= adev->mode_info.num_crtc) { 3214 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3215 return -EINVAL; 3216 } 3217 3218 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3219 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3220 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3221 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3222 3223 /* IRQ could occur when in initial stage */ 3224 if (amdgpu_crtc == NULL) 3225 return 0; 3226 3227 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3228 works = amdgpu_crtc->pflip_works; 3229 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3230 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3231 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3232 amdgpu_crtc->pflip_status, 3233 AMDGPU_FLIP_SUBMITTED); 3234 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3235 return 0; 3236 } 3237 3238 /* page flip completed. clean up */ 3239 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3240 amdgpu_crtc->pflip_works = NULL; 3241 3242 /* wakeup usersapce */ 3243 if (works->event) 3244 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3245 3246 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3247 3248 drm_crtc_vblank_put(&amdgpu_crtc->base); 3249 schedule_work(&works->unpin_work); 3250 3251 return 0; 3252 } 3253 3254 static int dce_v8_0_hpd_irq(struct amdgpu_device *adev, 3255 struct amdgpu_irq_src *source, 3256 struct amdgpu_iv_entry *entry) 3257 { 3258 uint32_t disp_int, mask, tmp; 3259 unsigned hpd; 3260 3261 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3262 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3263 return 0; 3264 } 3265 3266 hpd = entry->src_data[0]; 3267 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3268 mask = interrupt_status_offsets[hpd].hpd; 3269 3270 if (disp_int & mask) { 3271 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 3272 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3273 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 3274 schedule_work(&adev->hotplug_work); 3275 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3276 } 3277 3278 return 0; 3279 3280 } 3281 3282 static int dce_v8_0_set_clockgating_state(void *handle, 3283 enum amd_clockgating_state state) 3284 { 3285 return 0; 3286 } 3287 3288 static int dce_v8_0_set_powergating_state(void *handle, 3289 enum amd_powergating_state state) 3290 { 3291 return 0; 3292 } 3293 3294 static const struct amd_ip_funcs dce_v8_0_ip_funcs = { 3295 .name = "dce_v8_0", 3296 .early_init = dce_v8_0_early_init, 3297 .late_init = NULL, 3298 .sw_init = dce_v8_0_sw_init, 3299 .sw_fini = dce_v8_0_sw_fini, 3300 .hw_init = dce_v8_0_hw_init, 3301 .hw_fini = dce_v8_0_hw_fini, 3302 .suspend = dce_v8_0_suspend, 3303 .resume = dce_v8_0_resume, 3304 .is_idle = dce_v8_0_is_idle, 3305 .wait_for_idle = dce_v8_0_wait_for_idle, 3306 .soft_reset = dce_v8_0_soft_reset, 3307 .set_clockgating_state = dce_v8_0_set_clockgating_state, 3308 .set_powergating_state = dce_v8_0_set_powergating_state, 3309 }; 3310 3311 static void 3312 dce_v8_0_encoder_mode_set(struct drm_encoder *encoder, 3313 struct drm_display_mode *mode, 3314 struct drm_display_mode *adjusted_mode) 3315 { 3316 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3317 3318 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3319 3320 /* need to call this here rather than in prepare() since we need some crtc info */ 3321 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3322 3323 /* set scaler clears this on some chips */ 3324 dce_v8_0_set_interleave(encoder->crtc, mode); 3325 3326 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3327 dce_v8_0_afmt_enable(encoder, true); 3328 dce_v8_0_afmt_setmode(encoder, adjusted_mode); 3329 } 3330 } 3331 3332 static void dce_v8_0_encoder_prepare(struct drm_encoder *encoder) 3333 { 3334 struct amdgpu_device *adev = encoder->dev->dev_private; 3335 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3336 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3337 3338 if ((amdgpu_encoder->active_device & 3339 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3340 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3341 ENCODER_OBJECT_ID_NONE)) { 3342 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3343 if (dig) { 3344 dig->dig_encoder = dce_v8_0_pick_dig_encoder(encoder); 3345 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3346 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3347 } 3348 } 3349 3350 amdgpu_atombios_scratch_regs_lock(adev, true); 3351 3352 if (connector) { 3353 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3354 3355 /* select the clock/data port if it uses a router */ 3356 if (amdgpu_connector->router.cd_valid) 3357 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3358 3359 /* turn eDP panel on for mode set */ 3360 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3361 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3362 ATOM_TRANSMITTER_ACTION_POWER_ON); 3363 } 3364 3365 /* this is needed for the pll/ss setup to work correctly in some cases */ 3366 amdgpu_atombios_encoder_set_crtc_source(encoder); 3367 /* set up the FMT blocks */ 3368 dce_v8_0_program_fmt(encoder); 3369 } 3370 3371 static void dce_v8_0_encoder_commit(struct drm_encoder *encoder) 3372 { 3373 struct drm_device *dev = encoder->dev; 3374 struct amdgpu_device *adev = dev->dev_private; 3375 3376 /* need to call this here as we need the crtc set up */ 3377 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3378 amdgpu_atombios_scratch_regs_lock(adev, false); 3379 } 3380 3381 static void dce_v8_0_encoder_disable(struct drm_encoder *encoder) 3382 { 3383 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3384 struct amdgpu_encoder_atom_dig *dig; 3385 3386 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3387 3388 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3389 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3390 dce_v8_0_afmt_enable(encoder, false); 3391 dig = amdgpu_encoder->enc_priv; 3392 dig->dig_encoder = -1; 3393 } 3394 amdgpu_encoder->active_device = 0; 3395 } 3396 3397 /* these are handled by the primary encoders */ 3398 static void dce_v8_0_ext_prepare(struct drm_encoder *encoder) 3399 { 3400 3401 } 3402 3403 static void dce_v8_0_ext_commit(struct drm_encoder *encoder) 3404 { 3405 3406 } 3407 3408 static void 3409 dce_v8_0_ext_mode_set(struct drm_encoder *encoder, 3410 struct drm_display_mode *mode, 3411 struct drm_display_mode *adjusted_mode) 3412 { 3413 3414 } 3415 3416 static void dce_v8_0_ext_disable(struct drm_encoder *encoder) 3417 { 3418 3419 } 3420 3421 static void 3422 dce_v8_0_ext_dpms(struct drm_encoder *encoder, int mode) 3423 { 3424 3425 } 3426 3427 static const struct drm_encoder_helper_funcs dce_v8_0_ext_helper_funcs = { 3428 .dpms = dce_v8_0_ext_dpms, 3429 .prepare = dce_v8_0_ext_prepare, 3430 .mode_set = dce_v8_0_ext_mode_set, 3431 .commit = dce_v8_0_ext_commit, 3432 .disable = dce_v8_0_ext_disable, 3433 /* no detect for TMDS/LVDS yet */ 3434 }; 3435 3436 static const struct drm_encoder_helper_funcs dce_v8_0_dig_helper_funcs = { 3437 .dpms = amdgpu_atombios_encoder_dpms, 3438 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3439 .prepare = dce_v8_0_encoder_prepare, 3440 .mode_set = dce_v8_0_encoder_mode_set, 3441 .commit = dce_v8_0_encoder_commit, 3442 .disable = dce_v8_0_encoder_disable, 3443 .detect = amdgpu_atombios_encoder_dig_detect, 3444 }; 3445 3446 static const struct drm_encoder_helper_funcs dce_v8_0_dac_helper_funcs = { 3447 .dpms = amdgpu_atombios_encoder_dpms, 3448 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3449 .prepare = dce_v8_0_encoder_prepare, 3450 .mode_set = dce_v8_0_encoder_mode_set, 3451 .commit = dce_v8_0_encoder_commit, 3452 .detect = amdgpu_atombios_encoder_dac_detect, 3453 }; 3454 3455 static void dce_v8_0_encoder_destroy(struct drm_encoder *encoder) 3456 { 3457 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3458 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3459 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3460 kfree(amdgpu_encoder->enc_priv); 3461 drm_encoder_cleanup(encoder); 3462 kfree(amdgpu_encoder); 3463 } 3464 3465 static const struct drm_encoder_funcs dce_v8_0_encoder_funcs = { 3466 .destroy = dce_v8_0_encoder_destroy, 3467 }; 3468 3469 static void dce_v8_0_encoder_add(struct amdgpu_device *adev, 3470 uint32_t encoder_enum, 3471 uint32_t supported_device, 3472 u16 caps) 3473 { 3474 struct drm_device *dev = adev->ddev; 3475 struct drm_encoder *encoder; 3476 struct amdgpu_encoder *amdgpu_encoder; 3477 3478 /* see if we already added it */ 3479 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3480 amdgpu_encoder = to_amdgpu_encoder(encoder); 3481 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3482 amdgpu_encoder->devices |= supported_device; 3483 return; 3484 } 3485 3486 } 3487 3488 /* add a new one */ 3489 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3490 if (!amdgpu_encoder) 3491 return; 3492 3493 encoder = &amdgpu_encoder->base; 3494 switch (adev->mode_info.num_crtc) { 3495 case 1: 3496 encoder->possible_crtcs = 0x1; 3497 break; 3498 case 2: 3499 default: 3500 encoder->possible_crtcs = 0x3; 3501 break; 3502 case 4: 3503 encoder->possible_crtcs = 0xf; 3504 break; 3505 case 6: 3506 encoder->possible_crtcs = 0x3f; 3507 break; 3508 } 3509 3510 amdgpu_encoder->enc_priv = NULL; 3511 3512 amdgpu_encoder->encoder_enum = encoder_enum; 3513 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3514 amdgpu_encoder->devices = supported_device; 3515 amdgpu_encoder->rmx_type = RMX_OFF; 3516 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3517 amdgpu_encoder->is_ext_encoder = false; 3518 amdgpu_encoder->caps = caps; 3519 3520 switch (amdgpu_encoder->encoder_id) { 3521 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3522 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3523 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3524 DRM_MODE_ENCODER_DAC, NULL); 3525 drm_encoder_helper_add(encoder, &dce_v8_0_dac_helper_funcs); 3526 break; 3527 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3528 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3529 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3530 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3531 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3532 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3533 amdgpu_encoder->rmx_type = RMX_FULL; 3534 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3535 DRM_MODE_ENCODER_LVDS, NULL); 3536 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3537 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3538 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3539 DRM_MODE_ENCODER_DAC, NULL); 3540 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3541 } else { 3542 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3543 DRM_MODE_ENCODER_TMDS, NULL); 3544 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3545 } 3546 drm_encoder_helper_add(encoder, &dce_v8_0_dig_helper_funcs); 3547 break; 3548 case ENCODER_OBJECT_ID_SI170B: 3549 case ENCODER_OBJECT_ID_CH7303: 3550 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3551 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3552 case ENCODER_OBJECT_ID_TITFP513: 3553 case ENCODER_OBJECT_ID_VT1623: 3554 case ENCODER_OBJECT_ID_HDMI_SI1930: 3555 case ENCODER_OBJECT_ID_TRAVIS: 3556 case ENCODER_OBJECT_ID_NUTMEG: 3557 /* these are handled by the primary encoders */ 3558 amdgpu_encoder->is_ext_encoder = true; 3559 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3560 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3561 DRM_MODE_ENCODER_LVDS, NULL); 3562 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3563 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3564 DRM_MODE_ENCODER_DAC, NULL); 3565 else 3566 drm_encoder_init(dev, encoder, &dce_v8_0_encoder_funcs, 3567 DRM_MODE_ENCODER_TMDS, NULL); 3568 drm_encoder_helper_add(encoder, &dce_v8_0_ext_helper_funcs); 3569 break; 3570 } 3571 } 3572 3573 static const struct amdgpu_display_funcs dce_v8_0_display_funcs = { 3574 .set_vga_render_state = &dce_v8_0_set_vga_render_state, 3575 .bandwidth_update = &dce_v8_0_bandwidth_update, 3576 .vblank_get_counter = &dce_v8_0_vblank_get_counter, 3577 .vblank_wait = &dce_v8_0_vblank_wait, 3578 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3579 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3580 .hpd_sense = &dce_v8_0_hpd_sense, 3581 .hpd_set_polarity = &dce_v8_0_hpd_set_polarity, 3582 .hpd_get_gpio_reg = &dce_v8_0_hpd_get_gpio_reg, 3583 .page_flip = &dce_v8_0_page_flip, 3584 .page_flip_get_scanoutpos = &dce_v8_0_crtc_get_scanoutpos, 3585 .add_encoder = &dce_v8_0_encoder_add, 3586 .add_connector = &amdgpu_connector_add, 3587 .stop_mc_access = &dce_v8_0_stop_mc_access, 3588 .resume_mc_access = &dce_v8_0_resume_mc_access, 3589 }; 3590 3591 static void dce_v8_0_set_display_funcs(struct amdgpu_device *adev) 3592 { 3593 if (adev->mode_info.funcs == NULL) 3594 adev->mode_info.funcs = &dce_v8_0_display_funcs; 3595 } 3596 3597 static const struct amdgpu_irq_src_funcs dce_v8_0_crtc_irq_funcs = { 3598 .set = dce_v8_0_set_crtc_interrupt_state, 3599 .process = dce_v8_0_crtc_irq, 3600 }; 3601 3602 static const struct amdgpu_irq_src_funcs dce_v8_0_pageflip_irq_funcs = { 3603 .set = dce_v8_0_set_pageflip_interrupt_state, 3604 .process = dce_v8_0_pageflip_irq, 3605 }; 3606 3607 static const struct amdgpu_irq_src_funcs dce_v8_0_hpd_irq_funcs = { 3608 .set = dce_v8_0_set_hpd_interrupt_state, 3609 .process = dce_v8_0_hpd_irq, 3610 }; 3611 3612 static void dce_v8_0_set_irq_funcs(struct amdgpu_device *adev) 3613 { 3614 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3615 adev->crtc_irq.funcs = &dce_v8_0_crtc_irq_funcs; 3616 3617 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3618 adev->pageflip_irq.funcs = &dce_v8_0_pageflip_irq_funcs; 3619 3620 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3621 adev->hpd_irq.funcs = &dce_v8_0_hpd_irq_funcs; 3622 } 3623 3624 const struct amdgpu_ip_block_version dce_v8_0_ip_block = 3625 { 3626 .type = AMD_IP_BLOCK_TYPE_DCE, 3627 .major = 8, 3628 .minor = 0, 3629 .rev = 0, 3630 .funcs = &dce_v8_0_ip_funcs, 3631 }; 3632 3633 const struct amdgpu_ip_block_version dce_v8_1_ip_block = 3634 { 3635 .type = AMD_IP_BLOCK_TYPE_DCE, 3636 .major = 8, 3637 .minor = 1, 3638 .rev = 0, 3639 .funcs = &dce_v8_0_ip_funcs, 3640 }; 3641 3642 const struct amdgpu_ip_block_version dce_v8_2_ip_block = 3643 { 3644 .type = AMD_IP_BLOCK_TYPE_DCE, 3645 .major = 8, 3646 .minor = 2, 3647 .rev = 0, 3648 .funcs = &dce_v8_0_ip_funcs, 3649 }; 3650 3651 const struct amdgpu_ip_block_version dce_v8_3_ip_block = 3652 { 3653 .type = AMD_IP_BLOCK_TYPE_DCE, 3654 .major = 8, 3655 .minor = 3, 3656 .rev = 0, 3657 .funcs = &dce_v8_0_ip_funcs, 3658 }; 3659 3660 const struct amdgpu_ip_block_version dce_v8_5_ip_block = 3661 { 3662 .type = AMD_IP_BLOCK_TYPE_DCE, 3663 .major = 8, 3664 .minor = 5, 3665 .rev = 0, 3666 .funcs = &dce_v8_0_ip_funcs, 3667 }; 3668