1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "atom.h" 28 #include "amdgpu_atombios.h" 29 #include "atombios_crtc.h" 30 #include "atombios_encoders.h" 31 #include "amdgpu_pll.h" 32 #include "amdgpu_connectors.h" 33 34 #include "bif/bif_3_0_d.h" 35 #include "bif/bif_3_0_sh_mask.h" 36 #include "oss/oss_1_0_d.h" 37 #include "oss/oss_1_0_sh_mask.h" 38 #include "gca/gfx_6_0_d.h" 39 #include "gca/gfx_6_0_sh_mask.h" 40 #include "gmc/gmc_6_0_d.h" 41 #include "gmc/gmc_6_0_sh_mask.h" 42 #include "dce/dce_6_0_d.h" 43 #include "dce/dce_6_0_sh_mask.h" 44 #include "gca/gfx_7_2_enum.h" 45 #include "si_enums.h" 46 47 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 48 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 49 50 static const u32 crtc_offsets[6] = 51 { 52 SI_CRTC0_REGISTER_OFFSET, 53 SI_CRTC1_REGISTER_OFFSET, 54 SI_CRTC2_REGISTER_OFFSET, 55 SI_CRTC3_REGISTER_OFFSET, 56 SI_CRTC4_REGISTER_OFFSET, 57 SI_CRTC5_REGISTER_OFFSET 58 }; 59 60 static const u32 hpd_offsets[] = 61 { 62 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 63 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 64 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 65 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 66 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 67 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 68 }; 69 70 static const uint32_t dig_offsets[] = { 71 SI_CRTC0_REGISTER_OFFSET, 72 SI_CRTC1_REGISTER_OFFSET, 73 SI_CRTC2_REGISTER_OFFSET, 74 SI_CRTC3_REGISTER_OFFSET, 75 SI_CRTC4_REGISTER_OFFSET, 76 SI_CRTC5_REGISTER_OFFSET, 77 (0x13830 - 0x7030) >> 2, 78 }; 79 80 static const struct { 81 uint32_t reg; 82 uint32_t vblank; 83 uint32_t vline; 84 uint32_t hpd; 85 86 } interrupt_status_offsets[6] = { { 87 .reg = mmDISP_INTERRUPT_STATUS, 88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 91 }, { 92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 96 }, { 97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 116 } }; 117 118 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 119 u32 block_offset, u32 reg) 120 { 121 DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n"); 122 return 0; 123 } 124 125 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 126 u32 block_offset, u32 reg, u32 v) 127 { 128 DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n"); 129 } 130 131 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 132 { 133 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK) 134 return true; 135 else 136 return false; 137 } 138 139 static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 140 { 141 u32 pos1, pos2; 142 143 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 144 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 145 146 if (pos1 != pos2) 147 return true; 148 else 149 return false; 150 } 151 152 /** 153 * dce_v6_0_wait_for_vblank - vblank wait asic callback. 154 * 155 * @crtc: crtc to wait for vblank on 156 * 157 * Wait for vblank on the requested crtc (evergreen+). 158 */ 159 static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc) 160 { 161 unsigned i = 100; 162 163 if (crtc >= adev->mode_info.num_crtc) 164 return; 165 166 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 167 return; 168 169 /* depending on when we hit vblank, we may be close to active; if so, 170 * wait for another frame. 171 */ 172 while (dce_v6_0_is_in_vblank(adev, crtc)) { 173 if (i++ == 100) { 174 i = 0; 175 if (!dce_v6_0_is_counter_moving(adev, crtc)) 176 break; 177 } 178 } 179 180 while (!dce_v6_0_is_in_vblank(adev, crtc)) { 181 if (i++ == 100) { 182 i = 0; 183 if (!dce_v6_0_is_counter_moving(adev, crtc)) 184 break; 185 } 186 } 187 } 188 189 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 190 { 191 if (crtc >= adev->mode_info.num_crtc) 192 return 0; 193 else 194 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 195 } 196 197 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 198 { 199 unsigned i; 200 201 /* Enable pflip interrupts */ 202 for (i = 0; i < adev->mode_info.num_crtc; i++) 203 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 204 } 205 206 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 207 { 208 unsigned i; 209 210 /* Disable pflip interrupts */ 211 for (i = 0; i < adev->mode_info.num_crtc; i++) 212 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 213 } 214 215 /** 216 * dce_v6_0_page_flip - pageflip callback. 217 * 218 * @adev: amdgpu_device pointer 219 * @crtc_id: crtc to cleanup pageflip on 220 * @crtc_base: new address of the crtc (GPU MC address) 221 * 222 * Does the actual pageflip (evergreen+). 223 * During vblank we take the crtc lock and wait for the update_pending 224 * bit to go high, when it does, we release the lock, and allow the 225 * double buffered update to take place. 226 * Returns the current update pending status. 227 */ 228 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 229 int crtc_id, u64 crtc_base, bool async) 230 { 231 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 232 233 /* flip at hsync for async, default is vsync */ 234 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 235 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 236 /* update the scanout addresses */ 237 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 238 upper_32_bits(crtc_base)); 239 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 240 (u32)crtc_base); 241 242 /* post the write */ 243 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 244 } 245 246 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 247 u32 *vbl, u32 *position) 248 { 249 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 250 return -EINVAL; 251 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 252 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 253 254 return 0; 255 256 } 257 258 /** 259 * dce_v6_0_hpd_sense - hpd sense callback. 260 * 261 * @adev: amdgpu_device pointer 262 * @hpd: hpd (hotplug detect) pin 263 * 264 * Checks if a digital monitor is connected (evergreen+). 265 * Returns true if connected, false if not connected. 266 */ 267 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 268 enum amdgpu_hpd_id hpd) 269 { 270 bool connected = false; 271 272 if (hpd >= adev->mode_info.num_hpd) 273 return connected; 274 275 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 276 connected = true; 277 278 return connected; 279 } 280 281 /** 282 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 283 * 284 * @adev: amdgpu_device pointer 285 * @hpd: hpd (hotplug detect) pin 286 * 287 * Set the polarity of the hpd pin (evergreen+). 288 */ 289 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 290 enum amdgpu_hpd_id hpd) 291 { 292 u32 tmp; 293 bool connected = dce_v6_0_hpd_sense(adev, hpd); 294 295 if (hpd >= adev->mode_info.num_hpd) 296 return; 297 298 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 299 if (connected) 300 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 301 else 302 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 303 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 304 } 305 306 /** 307 * dce_v6_0_hpd_init - hpd setup callback. 308 * 309 * @adev: amdgpu_device pointer 310 * 311 * Setup the hpd pins used by the card (evergreen+). 312 * Enable the pin, set the polarity, and enable the hpd interrupts. 313 */ 314 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 315 { 316 struct drm_device *dev = adev->ddev; 317 struct drm_connector *connector; 318 u32 tmp; 319 320 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 321 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 322 323 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 324 continue; 325 326 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 327 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 328 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 329 330 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 331 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 332 /* don't try to enable hpd on eDP or LVDS avoid breaking the 333 * aux dp channel on imac and help (but not completely fix) 334 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 335 * also avoid interrupt storms during dpms. 336 */ 337 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 338 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 339 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 340 continue; 341 } 342 343 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 344 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 345 } 346 347 } 348 349 /** 350 * dce_v6_0_hpd_fini - hpd tear down callback. 351 * 352 * @adev: amdgpu_device pointer 353 * 354 * Tear down the hpd pins used by the card (evergreen+). 355 * Disable the hpd interrupts. 356 */ 357 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 358 { 359 struct drm_device *dev = adev->ddev; 360 struct drm_connector *connector; 361 u32 tmp; 362 363 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 364 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 365 366 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 367 continue; 368 369 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 370 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 371 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 372 373 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 374 } 375 } 376 377 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 378 { 379 return mmDC_GPIO_HPD_A; 380 } 381 382 static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) 383 { 384 if (crtc >= adev->mode_info.num_crtc) 385 return 0; 386 else 387 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 388 } 389 390 static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, 391 struct amdgpu_mode_mc_save *save) 392 { 393 u32 crtc_enabled, tmp, frame_count; 394 int i, j; 395 396 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 397 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 398 399 /* disable VGA render */ 400 WREG32(mmVGA_RENDER_CONTROL, 0); 401 402 /* blank the display controllers */ 403 for (i = 0; i < adev->mode_info.num_crtc; i++) { 404 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK; 405 if (crtc_enabled) { 406 save->crtc_enabled[i] = true; 407 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 408 409 if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) { 410 dce_v6_0_vblank_wait(adev, i); 411 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 412 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK; 413 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 415 } 416 /* wait for the next frame */ 417 frame_count = evergreen_get_vblank_counter(adev, i); 418 for (j = 0; j < adev->usec_timeout; j++) { 419 if (evergreen_get_vblank_counter(adev, i) != frame_count) 420 break; 421 udelay(1); 422 } 423 424 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 425 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 426 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 427 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 428 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 429 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 430 save->crtc_enabled[i] = false; 431 /* ***** */ 432 } else { 433 save->crtc_enabled[i] = false; 434 } 435 } 436 } 437 438 static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, 439 struct amdgpu_mode_mc_save *save) 440 { 441 u32 tmp; 442 int i, j; 443 444 /* update crtc base addresses */ 445 for (i = 0; i < adev->mode_info.num_crtc; i++) { 446 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 447 upper_32_bits(adev->mc.vram_start)); 448 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 449 upper_32_bits(adev->mc.vram_start)); 450 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 451 (u32)adev->mc.vram_start); 452 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 453 (u32)adev->mc.vram_start); 454 } 455 456 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 457 WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); 458 459 /* unlock regs and wait for update */ 460 for (i = 0; i < adev->mode_info.num_crtc; i++) { 461 if (save->crtc_enabled[i]) { 462 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 463 if ((tmp & 0x7) != 0) { 464 tmp &= ~0x7; 465 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 466 } 467 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 468 if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) { 469 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; 470 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 471 } 472 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 473 if (tmp & 1) { 474 tmp &= ~1; 475 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 476 } 477 for (j = 0; j < adev->usec_timeout; j++) { 478 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 479 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0) 480 break; 481 udelay(1); 482 } 483 } 484 } 485 486 /* Unlock vga access */ 487 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 488 mdelay(1); 489 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 490 491 } 492 493 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 494 bool render) 495 { 496 if (!render) 497 WREG32(mmVGA_RENDER_CONTROL, 498 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 499 500 } 501 502 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 503 { 504 int num_crtc = 0; 505 506 switch (adev->asic_type) { 507 case CHIP_TAHITI: 508 case CHIP_PITCAIRN: 509 case CHIP_VERDE: 510 num_crtc = 6; 511 break; 512 case CHIP_OLAND: 513 num_crtc = 2; 514 break; 515 default: 516 num_crtc = 0; 517 } 518 return num_crtc; 519 } 520 521 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 522 { 523 /*Disable VGA render and enabled crtc, if has DCE engine*/ 524 if (amdgpu_atombios_has_dce_engine_info(adev)) { 525 u32 tmp; 526 int crtc_enabled, i; 527 528 dce_v6_0_set_vga_render_state(adev, false); 529 530 /*Disable crtc*/ 531 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 532 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 533 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 534 if (crtc_enabled) { 535 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 537 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 538 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 539 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 540 } 541 } 542 } 543 } 544 545 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 546 { 547 548 struct drm_device *dev = encoder->dev; 549 struct amdgpu_device *adev = dev->dev_private; 550 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 551 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 552 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 553 int bpc = 0; 554 u32 tmp = 0; 555 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 556 557 if (connector) { 558 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 559 bpc = amdgpu_connector_get_monitor_bpc(connector); 560 dither = amdgpu_connector->dither; 561 } 562 563 /* LVDS FMT is set up by atom */ 564 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 565 return; 566 567 if (bpc == 0) 568 return; 569 570 571 switch (bpc) { 572 case 6: 573 if (dither == AMDGPU_FMT_DITHER_ENABLE) 574 /* XXX sort out optimal dither settings */ 575 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 576 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 577 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 578 else 579 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 580 break; 581 case 8: 582 if (dither == AMDGPU_FMT_DITHER_ENABLE) 583 /* XXX sort out optimal dither settings */ 584 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 585 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 586 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 587 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 588 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 589 else 590 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 591 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 592 break; 593 case 10: 594 default: 595 /* not needed */ 596 break; 597 } 598 599 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 600 } 601 602 /** 603 * cik_get_number_of_dram_channels - get the number of dram channels 604 * 605 * @adev: amdgpu_device pointer 606 * 607 * Look up the number of video ram channels (CIK). 608 * Used for display watermark bandwidth calculations 609 * Returns the number of dram channels 610 */ 611 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 612 { 613 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 614 615 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 616 case 0: 617 default: 618 return 1; 619 case 1: 620 return 2; 621 case 2: 622 return 4; 623 case 3: 624 return 8; 625 case 4: 626 return 3; 627 case 5: 628 return 6; 629 case 6: 630 return 10; 631 case 7: 632 return 12; 633 case 8: 634 return 16; 635 } 636 } 637 638 struct dce6_wm_params { 639 u32 dram_channels; /* number of dram channels */ 640 u32 yclk; /* bandwidth per dram data pin in kHz */ 641 u32 sclk; /* engine clock in kHz */ 642 u32 disp_clk; /* display clock in kHz */ 643 u32 src_width; /* viewport width */ 644 u32 active_time; /* active display time in ns */ 645 u32 blank_time; /* blank time in ns */ 646 bool interlaced; /* mode is interlaced */ 647 fixed20_12 vsc; /* vertical scale ratio */ 648 u32 num_heads; /* number of active crtcs */ 649 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 650 u32 lb_size; /* line buffer allocated to pipe */ 651 u32 vtaps; /* vertical scaler taps */ 652 }; 653 654 /** 655 * dce_v6_0_dram_bandwidth - get the dram bandwidth 656 * 657 * @wm: watermark calculation data 658 * 659 * Calculate the raw dram bandwidth (CIK). 660 * Used for display watermark bandwidth calculations 661 * Returns the dram bandwidth in MBytes/s 662 */ 663 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 664 { 665 /* Calculate raw DRAM Bandwidth */ 666 fixed20_12 dram_efficiency; /* 0.7 */ 667 fixed20_12 yclk, dram_channels, bandwidth; 668 fixed20_12 a; 669 670 a.full = dfixed_const(1000); 671 yclk.full = dfixed_const(wm->yclk); 672 yclk.full = dfixed_div(yclk, a); 673 dram_channels.full = dfixed_const(wm->dram_channels * 4); 674 a.full = dfixed_const(10); 675 dram_efficiency.full = dfixed_const(7); 676 dram_efficiency.full = dfixed_div(dram_efficiency, a); 677 bandwidth.full = dfixed_mul(dram_channels, yclk); 678 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 679 680 return dfixed_trunc(bandwidth); 681 } 682 683 /** 684 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 685 * 686 * @wm: watermark calculation data 687 * 688 * Calculate the dram bandwidth used for display (CIK). 689 * Used for display watermark bandwidth calculations 690 * Returns the dram bandwidth for display in MBytes/s 691 */ 692 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 693 { 694 /* Calculate DRAM Bandwidth and the part allocated to display. */ 695 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 696 fixed20_12 yclk, dram_channels, bandwidth; 697 fixed20_12 a; 698 699 a.full = dfixed_const(1000); 700 yclk.full = dfixed_const(wm->yclk); 701 yclk.full = dfixed_div(yclk, a); 702 dram_channels.full = dfixed_const(wm->dram_channels * 4); 703 a.full = dfixed_const(10); 704 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 705 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 706 bandwidth.full = dfixed_mul(dram_channels, yclk); 707 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 708 709 return dfixed_trunc(bandwidth); 710 } 711 712 /** 713 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 714 * 715 * @wm: watermark calculation data 716 * 717 * Calculate the data return bandwidth used for display (CIK). 718 * Used for display watermark bandwidth calculations 719 * Returns the data return bandwidth in MBytes/s 720 */ 721 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 722 { 723 /* Calculate the display Data return Bandwidth */ 724 fixed20_12 return_efficiency; /* 0.8 */ 725 fixed20_12 sclk, bandwidth; 726 fixed20_12 a; 727 728 a.full = dfixed_const(1000); 729 sclk.full = dfixed_const(wm->sclk); 730 sclk.full = dfixed_div(sclk, a); 731 a.full = dfixed_const(10); 732 return_efficiency.full = dfixed_const(8); 733 return_efficiency.full = dfixed_div(return_efficiency, a); 734 a.full = dfixed_const(32); 735 bandwidth.full = dfixed_mul(a, sclk); 736 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 737 738 return dfixed_trunc(bandwidth); 739 } 740 741 /** 742 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 743 * 744 * @wm: watermark calculation data 745 * 746 * Calculate the dmif bandwidth used for display (CIK). 747 * Used for display watermark bandwidth calculations 748 * Returns the dmif bandwidth in MBytes/s 749 */ 750 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 751 { 752 /* Calculate the DMIF Request Bandwidth */ 753 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 754 fixed20_12 disp_clk, bandwidth; 755 fixed20_12 a, b; 756 757 a.full = dfixed_const(1000); 758 disp_clk.full = dfixed_const(wm->disp_clk); 759 disp_clk.full = dfixed_div(disp_clk, a); 760 a.full = dfixed_const(32); 761 b.full = dfixed_mul(a, disp_clk); 762 763 a.full = dfixed_const(10); 764 disp_clk_request_efficiency.full = dfixed_const(8); 765 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 766 767 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 768 769 return dfixed_trunc(bandwidth); 770 } 771 772 /** 773 * dce_v6_0_available_bandwidth - get the min available bandwidth 774 * 775 * @wm: watermark calculation data 776 * 777 * Calculate the min available bandwidth used for display (CIK). 778 * Used for display watermark bandwidth calculations 779 * Returns the min available bandwidth in MBytes/s 780 */ 781 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 782 { 783 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 784 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 785 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 786 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 787 788 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 789 } 790 791 /** 792 * dce_v6_0_average_bandwidth - get the average available bandwidth 793 * 794 * @wm: watermark calculation data 795 * 796 * Calculate the average available bandwidth used for display (CIK). 797 * Used for display watermark bandwidth calculations 798 * Returns the average available bandwidth in MBytes/s 799 */ 800 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 801 { 802 /* Calculate the display mode Average Bandwidth 803 * DisplayMode should contain the source and destination dimensions, 804 * timing, etc. 805 */ 806 fixed20_12 bpp; 807 fixed20_12 line_time; 808 fixed20_12 src_width; 809 fixed20_12 bandwidth; 810 fixed20_12 a; 811 812 a.full = dfixed_const(1000); 813 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 814 line_time.full = dfixed_div(line_time, a); 815 bpp.full = dfixed_const(wm->bytes_per_pixel); 816 src_width.full = dfixed_const(wm->src_width); 817 bandwidth.full = dfixed_mul(src_width, bpp); 818 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 819 bandwidth.full = dfixed_div(bandwidth, line_time); 820 821 return dfixed_trunc(bandwidth); 822 } 823 824 /** 825 * dce_v6_0_latency_watermark - get the latency watermark 826 * 827 * @wm: watermark calculation data 828 * 829 * Calculate the latency watermark (CIK). 830 * Used for display watermark bandwidth calculations 831 * Returns the latency watermark in ns 832 */ 833 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 834 { 835 /* First calculate the latency in ns */ 836 u32 mc_latency = 2000; /* 2000 ns. */ 837 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 838 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 839 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 840 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 841 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 842 (wm->num_heads * cursor_line_pair_return_time); 843 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 844 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 845 u32 tmp, dmif_size = 12288; 846 fixed20_12 a, b, c; 847 848 if (wm->num_heads == 0) 849 return 0; 850 851 a.full = dfixed_const(2); 852 b.full = dfixed_const(1); 853 if ((wm->vsc.full > a.full) || 854 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 855 (wm->vtaps >= 5) || 856 ((wm->vsc.full >= a.full) && wm->interlaced)) 857 max_src_lines_per_dst_line = 4; 858 else 859 max_src_lines_per_dst_line = 2; 860 861 a.full = dfixed_const(available_bandwidth); 862 b.full = dfixed_const(wm->num_heads); 863 a.full = dfixed_div(a, b); 864 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 865 tmp = min(dfixed_trunc(a), tmp); 866 867 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 868 869 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 870 b.full = dfixed_const(1000); 871 c.full = dfixed_const(lb_fill_bw); 872 b.full = dfixed_div(c, b); 873 a.full = dfixed_div(a, b); 874 line_fill_time = dfixed_trunc(a); 875 876 if (line_fill_time < wm->active_time) 877 return latency; 878 else 879 return latency + (line_fill_time - wm->active_time); 880 881 } 882 883 /** 884 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 885 * average and available dram bandwidth 886 * 887 * @wm: watermark calculation data 888 * 889 * Check if the display average bandwidth fits in the display 890 * dram bandwidth (CIK). 891 * Used for display watermark bandwidth calculations 892 * Returns true if the display fits, false if not. 893 */ 894 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 895 { 896 if (dce_v6_0_average_bandwidth(wm) <= 897 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 898 return true; 899 else 900 return false; 901 } 902 903 /** 904 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 905 * average and available bandwidth 906 * 907 * @wm: watermark calculation data 908 * 909 * Check if the display average bandwidth fits in the display 910 * available bandwidth (CIK). 911 * Used for display watermark bandwidth calculations 912 * Returns true if the display fits, false if not. 913 */ 914 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 915 { 916 if (dce_v6_0_average_bandwidth(wm) <= 917 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 918 return true; 919 else 920 return false; 921 } 922 923 /** 924 * dce_v6_0_check_latency_hiding - check latency hiding 925 * 926 * @wm: watermark calculation data 927 * 928 * Check latency hiding (CIK). 929 * Used for display watermark bandwidth calculations 930 * Returns true if the display fits, false if not. 931 */ 932 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 933 { 934 u32 lb_partitions = wm->lb_size / wm->src_width; 935 u32 line_time = wm->active_time + wm->blank_time; 936 u32 latency_tolerant_lines; 937 u32 latency_hiding; 938 fixed20_12 a; 939 940 a.full = dfixed_const(1); 941 if (wm->vsc.full > a.full) 942 latency_tolerant_lines = 1; 943 else { 944 if (lb_partitions <= (wm->vtaps + 1)) 945 latency_tolerant_lines = 1; 946 else 947 latency_tolerant_lines = 2; 948 } 949 950 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 951 952 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 953 return true; 954 else 955 return false; 956 } 957 958 /** 959 * dce_v6_0_program_watermarks - program display watermarks 960 * 961 * @adev: amdgpu_device pointer 962 * @amdgpu_crtc: the selected display controller 963 * @lb_size: line buffer size 964 * @num_heads: number of display controllers in use 965 * 966 * Calculate and program the display watermarks for the 967 * selected display controller (CIK). 968 */ 969 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 970 struct amdgpu_crtc *amdgpu_crtc, 971 u32 lb_size, u32 num_heads) 972 { 973 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 974 struct dce6_wm_params wm_low, wm_high; 975 u32 dram_channels; 976 u32 active_time; 977 u32 line_time = 0; 978 u32 latency_watermark_a = 0, latency_watermark_b = 0; 979 u32 priority_a_mark = 0, priority_b_mark = 0; 980 u32 priority_a_cnt = PRIORITY_OFF; 981 u32 priority_b_cnt = PRIORITY_OFF; 982 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 983 fixed20_12 a, b, c; 984 985 if (amdgpu_crtc->base.enabled && num_heads && mode) { 986 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 987 (u32)mode->clock); 988 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 989 (u32)mode->clock); 990 line_time = min(line_time, (u32)65535); 991 priority_a_cnt = 0; 992 priority_b_cnt = 0; 993 994 dram_channels = si_get_number_of_dram_channels(adev); 995 996 /* watermark for high clocks */ 997 if (adev->pm.dpm_enabled) { 998 wm_high.yclk = 999 amdgpu_dpm_get_mclk(adev, false) * 10; 1000 wm_high.sclk = 1001 amdgpu_dpm_get_sclk(adev, false) * 10; 1002 } else { 1003 wm_high.yclk = adev->pm.current_mclk * 10; 1004 wm_high.sclk = adev->pm.current_sclk * 10; 1005 } 1006 1007 wm_high.disp_clk = mode->clock; 1008 wm_high.src_width = mode->crtc_hdisplay; 1009 wm_high.active_time = active_time; 1010 wm_high.blank_time = line_time - wm_high.active_time; 1011 wm_high.interlaced = false; 1012 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1013 wm_high.interlaced = true; 1014 wm_high.vsc = amdgpu_crtc->vsc; 1015 wm_high.vtaps = 1; 1016 if (amdgpu_crtc->rmx_type != RMX_OFF) 1017 wm_high.vtaps = 2; 1018 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1019 wm_high.lb_size = lb_size; 1020 wm_high.dram_channels = dram_channels; 1021 wm_high.num_heads = num_heads; 1022 1023 if (adev->pm.dpm_enabled) { 1024 /* watermark for low clocks */ 1025 wm_low.yclk = 1026 amdgpu_dpm_get_mclk(adev, true) * 10; 1027 wm_low.sclk = 1028 amdgpu_dpm_get_sclk(adev, true) * 10; 1029 } else { 1030 wm_low.yclk = adev->pm.current_mclk * 10; 1031 wm_low.sclk = adev->pm.current_sclk * 10; 1032 } 1033 1034 wm_low.disp_clk = mode->clock; 1035 wm_low.src_width = mode->crtc_hdisplay; 1036 wm_low.active_time = active_time; 1037 wm_low.blank_time = line_time - wm_low.active_time; 1038 wm_low.interlaced = false; 1039 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1040 wm_low.interlaced = true; 1041 wm_low.vsc = amdgpu_crtc->vsc; 1042 wm_low.vtaps = 1; 1043 if (amdgpu_crtc->rmx_type != RMX_OFF) 1044 wm_low.vtaps = 2; 1045 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1046 wm_low.lb_size = lb_size; 1047 wm_low.dram_channels = dram_channels; 1048 wm_low.num_heads = num_heads; 1049 1050 /* set for high clocks */ 1051 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535); 1052 /* set for low clocks */ 1053 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535); 1054 1055 /* possibly force display priority to high */ 1056 /* should really do this at mode validation time... */ 1057 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1058 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1059 !dce_v6_0_check_latency_hiding(&wm_high) || 1060 (adev->mode_info.disp_priority == 2)) { 1061 DRM_DEBUG_KMS("force priority to high\n"); 1062 priority_a_cnt |= PRIORITY_ALWAYS_ON; 1063 priority_b_cnt |= PRIORITY_ALWAYS_ON; 1064 } 1065 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1066 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1067 !dce_v6_0_check_latency_hiding(&wm_low) || 1068 (adev->mode_info.disp_priority == 2)) { 1069 DRM_DEBUG_KMS("force priority to high\n"); 1070 priority_a_cnt |= PRIORITY_ALWAYS_ON; 1071 priority_b_cnt |= PRIORITY_ALWAYS_ON; 1072 } 1073 1074 a.full = dfixed_const(1000); 1075 b.full = dfixed_const(mode->clock); 1076 b.full = dfixed_div(b, a); 1077 c.full = dfixed_const(latency_watermark_a); 1078 c.full = dfixed_mul(c, b); 1079 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 1080 c.full = dfixed_div(c, a); 1081 a.full = dfixed_const(16); 1082 c.full = dfixed_div(c, a); 1083 priority_a_mark = dfixed_trunc(c); 1084 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 1085 1086 a.full = dfixed_const(1000); 1087 b.full = dfixed_const(mode->clock); 1088 b.full = dfixed_div(b, a); 1089 c.full = dfixed_const(latency_watermark_b); 1090 c.full = dfixed_mul(c, b); 1091 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 1092 c.full = dfixed_div(c, a); 1093 a.full = dfixed_const(16); 1094 c.full = dfixed_div(c, a); 1095 priority_b_mark = dfixed_trunc(c); 1096 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 1097 1098 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1099 } 1100 1101 /* select wm A */ 1102 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1103 tmp = arb_control3; 1104 tmp &= ~LATENCY_WATERMARK_MASK(3); 1105 tmp |= LATENCY_WATERMARK_MASK(1); 1106 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1107 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1108 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1109 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1110 /* select wm B */ 1111 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1112 tmp &= ~LATENCY_WATERMARK_MASK(3); 1113 tmp |= LATENCY_WATERMARK_MASK(2); 1114 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1115 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1116 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1117 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1118 /* restore original selection */ 1119 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1120 1121 /* write the priority marks */ 1122 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1123 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1124 1125 /* save values for DPM */ 1126 amdgpu_crtc->line_time = line_time; 1127 amdgpu_crtc->wm_high = latency_watermark_a; 1128 1129 /* Save number of lines the linebuffer leads before the scanout */ 1130 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1131 } 1132 1133 /* watermark setup */ 1134 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1135 struct amdgpu_crtc *amdgpu_crtc, 1136 struct drm_display_mode *mode, 1137 struct drm_display_mode *other_mode) 1138 { 1139 u32 tmp, buffer_alloc, i; 1140 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1141 /* 1142 * Line Buffer Setup 1143 * There are 3 line buffers, each one shared by 2 display controllers. 1144 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1145 * the display controllers. The paritioning is done via one of four 1146 * preset allocations specified in bits 21:20: 1147 * 0 - half lb 1148 * 2 - whole lb, other crtc must be disabled 1149 */ 1150 /* this can get tricky if we have two large displays on a paired group 1151 * of crtcs. Ideally for multiple large displays we'd assign them to 1152 * non-linked crtcs for maximum line buffer allocation. 1153 */ 1154 if (amdgpu_crtc->base.enabled && mode) { 1155 if (other_mode) { 1156 tmp = 0; /* 1/2 */ 1157 buffer_alloc = 1; 1158 } else { 1159 tmp = 2; /* whole */ 1160 buffer_alloc = 2; 1161 } 1162 } else { 1163 tmp = 0; 1164 buffer_alloc = 0; 1165 } 1166 1167 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1168 DC_LB_MEMORY_CONFIG(tmp)); 1169 1170 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1171 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1172 for (i = 0; i < adev->usec_timeout; i++) { 1173 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1174 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1175 break; 1176 udelay(1); 1177 } 1178 1179 if (amdgpu_crtc->base.enabled && mode) { 1180 switch (tmp) { 1181 case 0: 1182 default: 1183 return 4096 * 2; 1184 case 2: 1185 return 8192 * 2; 1186 } 1187 } 1188 1189 /* controller not enabled, so no lb used */ 1190 return 0; 1191 } 1192 1193 1194 /** 1195 * 1196 * dce_v6_0_bandwidth_update - program display watermarks 1197 * 1198 * @adev: amdgpu_device pointer 1199 * 1200 * Calculate and program the display watermarks and line 1201 * buffer allocation (CIK). 1202 */ 1203 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1204 { 1205 struct drm_display_mode *mode0 = NULL; 1206 struct drm_display_mode *mode1 = NULL; 1207 u32 num_heads = 0, lb_size; 1208 int i; 1209 1210 if (!adev->mode_info.mode_config_initialized) 1211 return; 1212 1213 amdgpu_update_display_priority(adev); 1214 1215 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1216 if (adev->mode_info.crtcs[i]->base.enabled) 1217 num_heads++; 1218 } 1219 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1220 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1221 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1222 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1223 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1224 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1225 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1226 } 1227 } 1228 /* 1229 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1230 { 1231 int i; 1232 u32 offset, tmp; 1233 1234 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1235 offset = adev->mode_info.audio.pin[i].offset; 1236 tmp = RREG32_AUDIO_ENDPT(offset, 1237 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1238 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 1239 adev->mode_info.audio.pin[i].connected = false; 1240 else 1241 adev->mode_info.audio.pin[i].connected = true; 1242 } 1243 1244 } 1245 1246 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1247 { 1248 int i; 1249 1250 dce_v6_0_audio_get_connected_pins(adev); 1251 1252 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1253 if (adev->mode_info.audio.pin[i].connected) 1254 return &adev->mode_info.audio.pin[i]; 1255 } 1256 DRM_ERROR("No connected audio pins found!\n"); 1257 return NULL; 1258 } 1259 1260 static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1261 { 1262 struct amdgpu_device *adev = encoder->dev->dev_private; 1263 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1264 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1265 u32 offset; 1266 1267 if (!dig || !dig->afmt || !dig->afmt->pin) 1268 return; 1269 1270 offset = dig->afmt->offset; 1271 1272 WREG32(AFMT_AUDIO_SRC_CONTROL + offset, 1273 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id)); 1274 1275 } 1276 1277 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1278 struct drm_display_mode *mode) 1279 { 1280 DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n"); 1281 } 1282 1283 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1284 { 1285 DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n"); 1286 } 1287 1288 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1289 { 1290 DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n"); 1291 1292 } 1293 */ 1294 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1295 struct amdgpu_audio_pin *pin, 1296 bool enable) 1297 { 1298 DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n"); 1299 } 1300 1301 static const u32 pin_offsets[7] = 1302 { 1303 (0x1780 - 0x1780), 1304 (0x1786 - 0x1780), 1305 (0x178c - 0x1780), 1306 (0x1792 - 0x1780), 1307 (0x1798 - 0x1780), 1308 (0x179d - 0x1780), 1309 (0x17a4 - 0x1780), 1310 }; 1311 1312 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1313 { 1314 return 0; 1315 } 1316 1317 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1318 { 1319 1320 } 1321 1322 /* 1323 static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1324 { 1325 DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n"); 1326 } 1327 */ 1328 /* 1329 * build a HDMI Video Info Frame 1330 */ 1331 /* 1332 static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1333 void *buffer, size_t size) 1334 { 1335 DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n"); 1336 } 1337 1338 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1339 { 1340 DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n"); 1341 } 1342 */ 1343 /* 1344 * update the info frames with the data from the current display mode 1345 */ 1346 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1347 struct drm_display_mode *mode) 1348 { 1349 DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n"); 1350 } 1351 1352 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1353 { 1354 struct drm_device *dev = encoder->dev; 1355 struct amdgpu_device *adev = dev->dev_private; 1356 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1357 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1358 1359 if (!dig || !dig->afmt) 1360 return; 1361 1362 /* Silent, r600_hdmi_enable will raise WARN for us */ 1363 if (enable && dig->afmt->enabled) 1364 return; 1365 if (!enable && !dig->afmt->enabled) 1366 return; 1367 1368 if (!enable && dig->afmt->pin) { 1369 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1370 dig->afmt->pin = NULL; 1371 } 1372 1373 dig->afmt->enabled = enable; 1374 1375 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1376 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1377 } 1378 1379 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1380 { 1381 int i, j; 1382 1383 for (i = 0; i < adev->mode_info.num_dig; i++) 1384 adev->mode_info.afmt[i] = NULL; 1385 1386 /* DCE6 has audio blocks tied to DIG encoders */ 1387 for (i = 0; i < adev->mode_info.num_dig; i++) { 1388 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1389 if (adev->mode_info.afmt[i]) { 1390 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1391 adev->mode_info.afmt[i]->id = i; 1392 } else { 1393 for (j = 0; j < i; j++) { 1394 kfree(adev->mode_info.afmt[j]); 1395 adev->mode_info.afmt[j] = NULL; 1396 } 1397 DRM_ERROR("Out of memory allocating afmt table\n"); 1398 return -ENOMEM; 1399 } 1400 } 1401 return 0; 1402 } 1403 1404 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1405 { 1406 int i; 1407 1408 for (i = 0; i < adev->mode_info.num_dig; i++) { 1409 kfree(adev->mode_info.afmt[i]); 1410 adev->mode_info.afmt[i] = NULL; 1411 } 1412 } 1413 1414 static const u32 vga_control_regs[6] = 1415 { 1416 mmD1VGA_CONTROL, 1417 mmD2VGA_CONTROL, 1418 mmD3VGA_CONTROL, 1419 mmD4VGA_CONTROL, 1420 mmD5VGA_CONTROL, 1421 mmD6VGA_CONTROL, 1422 }; 1423 1424 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1425 { 1426 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1427 struct drm_device *dev = crtc->dev; 1428 struct amdgpu_device *adev = dev->dev_private; 1429 u32 vga_control; 1430 1431 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1432 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1433 } 1434 1435 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1436 { 1437 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1438 struct drm_device *dev = crtc->dev; 1439 struct amdgpu_device *adev = dev->dev_private; 1440 1441 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1442 } 1443 1444 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1445 struct drm_framebuffer *fb, 1446 int x, int y, int atomic) 1447 { 1448 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1449 struct drm_device *dev = crtc->dev; 1450 struct amdgpu_device *adev = dev->dev_private; 1451 struct amdgpu_framebuffer *amdgpu_fb; 1452 struct drm_framebuffer *target_fb; 1453 struct drm_gem_object *obj; 1454 struct amdgpu_bo *abo; 1455 uint64_t fb_location, tiling_flags; 1456 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1457 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1458 u32 viewport_w, viewport_h; 1459 int r; 1460 bool bypass_lut = false; 1461 struct drm_format_name_buf format_name; 1462 1463 /* no fb bound */ 1464 if (!atomic && !crtc->primary->fb) { 1465 DRM_DEBUG_KMS("No FB bound\n"); 1466 return 0; 1467 } 1468 1469 if (atomic) { 1470 amdgpu_fb = to_amdgpu_framebuffer(fb); 1471 target_fb = fb; 1472 } else { 1473 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 1474 target_fb = crtc->primary->fb; 1475 } 1476 1477 /* If atomic, assume fb object is pinned & idle & fenced and 1478 * just update base pointers 1479 */ 1480 obj = amdgpu_fb->obj; 1481 abo = gem_to_amdgpu_bo(obj); 1482 r = amdgpu_bo_reserve(abo, false); 1483 if (unlikely(r != 0)) 1484 return r; 1485 1486 if (atomic) { 1487 fb_location = amdgpu_bo_gpu_offset(abo); 1488 } else { 1489 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1490 if (unlikely(r != 0)) { 1491 amdgpu_bo_unreserve(abo); 1492 return -EINVAL; 1493 } 1494 } 1495 1496 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1497 amdgpu_bo_unreserve(abo); 1498 1499 switch (target_fb->format->format) { 1500 case DRM_FORMAT_C8: 1501 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 1502 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 1503 break; 1504 case DRM_FORMAT_XRGB4444: 1505 case DRM_FORMAT_ARGB4444: 1506 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1507 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 1508 #ifdef __BIG_ENDIAN 1509 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1510 #endif 1511 break; 1512 case DRM_FORMAT_XRGB1555: 1513 case DRM_FORMAT_ARGB1555: 1514 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1515 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 1516 #ifdef __BIG_ENDIAN 1517 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1518 #endif 1519 break; 1520 case DRM_FORMAT_BGRX5551: 1521 case DRM_FORMAT_BGRA5551: 1522 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1523 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 1524 #ifdef __BIG_ENDIAN 1525 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1526 #endif 1527 break; 1528 case DRM_FORMAT_RGB565: 1529 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1530 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 1531 #ifdef __BIG_ENDIAN 1532 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1533 #endif 1534 break; 1535 case DRM_FORMAT_XRGB8888: 1536 case DRM_FORMAT_ARGB8888: 1537 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1538 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1539 #ifdef __BIG_ENDIAN 1540 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1541 #endif 1542 break; 1543 case DRM_FORMAT_XRGB2101010: 1544 case DRM_FORMAT_ARGB2101010: 1545 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1546 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 1547 #ifdef __BIG_ENDIAN 1548 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1549 #endif 1550 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1551 bypass_lut = true; 1552 break; 1553 case DRM_FORMAT_BGRX1010102: 1554 case DRM_FORMAT_BGRA1010102: 1555 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1556 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 1557 #ifdef __BIG_ENDIAN 1558 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1559 #endif 1560 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1561 bypass_lut = true; 1562 break; 1563 default: 1564 DRM_ERROR("Unsupported screen format %s\n", 1565 drm_get_format_name(target_fb->format->format, &format_name)); 1566 return -EINVAL; 1567 } 1568 1569 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1570 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1571 1572 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1573 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1574 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1575 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1576 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1577 1578 fb_format |= GRPH_NUM_BANKS(num_banks); 1579 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 1580 fb_format |= GRPH_TILE_SPLIT(tile_split); 1581 fb_format |= GRPH_BANK_WIDTH(bankw); 1582 fb_format |= GRPH_BANK_HEIGHT(bankh); 1583 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 1584 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1585 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 1586 } 1587 1588 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1589 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 1590 1591 dce_v6_0_vga_enable(crtc, false); 1592 1593 /* Make sure surface address is updated at vertical blank rather than 1594 * horizontal blank 1595 */ 1596 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 1597 1598 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1599 upper_32_bits(fb_location)); 1600 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1601 upper_32_bits(fb_location)); 1602 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1603 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1604 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1605 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1606 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1607 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 1608 1609 /* 1610 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1611 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1612 * retain the full precision throughout the pipeline. 1613 */ 1614 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 1615 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 1616 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 1617 1618 if (bypass_lut) 1619 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1620 1621 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 1622 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 1623 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 1624 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 1625 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 1626 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 1627 1628 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 1629 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 1630 1631 dce_v6_0_grph_enable(crtc, true); 1632 1633 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 1634 target_fb->height); 1635 x &= ~3; 1636 y &= ~1; 1637 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 1638 (x << 16) | y); 1639 viewport_w = crtc->mode.hdisplay; 1640 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1641 1642 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 1643 (viewport_w << 16) | viewport_h); 1644 1645 /* set pageflip to happen anywhere in vblank interval */ 1646 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 1647 1648 if (!atomic && fb && fb != crtc->primary->fb) { 1649 amdgpu_fb = to_amdgpu_framebuffer(fb); 1650 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 1651 r = amdgpu_bo_reserve(abo, true); 1652 if (unlikely(r != 0)) 1653 return r; 1654 amdgpu_bo_unpin(abo); 1655 amdgpu_bo_unreserve(abo); 1656 } 1657 1658 /* Bytes per pixel may have changed */ 1659 dce_v6_0_bandwidth_update(adev); 1660 1661 return 0; 1662 1663 } 1664 1665 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 1666 struct drm_display_mode *mode) 1667 { 1668 struct drm_device *dev = crtc->dev; 1669 struct amdgpu_device *adev = dev->dev_private; 1670 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1671 1672 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1673 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 1674 INTERLEAVE_EN); 1675 else 1676 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 1677 } 1678 1679 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 1680 { 1681 1682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1683 struct drm_device *dev = crtc->dev; 1684 struct amdgpu_device *adev = dev->dev_private; 1685 int i; 1686 1687 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 1688 1689 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 1690 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 1691 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 1692 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 1693 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 1694 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 1695 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 1696 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1697 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 1698 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 1699 1700 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 1701 1702 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 1703 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 1704 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 1705 1706 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 1707 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 1708 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 1709 1710 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 1711 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 1712 1713 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 1714 for (i = 0; i < 256; i++) { 1715 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 1716 (amdgpu_crtc->lut_r[i] << 20) | 1717 (amdgpu_crtc->lut_g[i] << 10) | 1718 (amdgpu_crtc->lut_b[i] << 0)); 1719 } 1720 1721 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1722 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 1723 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 1724 ICON_DEGAMMA_MODE(0) | 1725 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 1726 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 1727 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 1728 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 1729 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 1730 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 1731 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 1732 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 1733 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 1734 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 1735 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 1736 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 1737 1738 1739 } 1740 1741 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 1742 { 1743 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1744 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1745 1746 switch (amdgpu_encoder->encoder_id) { 1747 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 1748 return dig->linkb ? 1 : 0; 1749 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 1750 return dig->linkb ? 3 : 2; 1751 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 1752 return dig->linkb ? 5 : 4; 1753 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 1754 return 6; 1755 default: 1756 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 1757 return 0; 1758 } 1759 } 1760 1761 /** 1762 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 1763 * 1764 * @crtc: drm crtc 1765 * 1766 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1767 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1768 * monitors a dedicated PPLL must be used. If a particular board has 1769 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1770 * as there is no need to program the PLL itself. If we are not able to 1771 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1772 * avoid messing up an existing monitor. 1773 * 1774 * 1775 */ 1776 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 1777 { 1778 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1779 struct drm_device *dev = crtc->dev; 1780 struct amdgpu_device *adev = dev->dev_private; 1781 u32 pll_in_use; 1782 int pll; 1783 1784 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 1785 if (adev->clock.dp_extclk) 1786 /* skip PPLL programming if using ext clock */ 1787 return ATOM_PPLL_INVALID; 1788 else 1789 return ATOM_PPLL0; 1790 } else { 1791 /* use the same PPLL for all monitors with the same clock */ 1792 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 1793 if (pll != ATOM_PPLL_INVALID) 1794 return pll; 1795 } 1796 1797 /* PPLL1, and PPLL2 */ 1798 pll_in_use = amdgpu_pll_get_use_mask(crtc); 1799 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1800 return ATOM_PPLL2; 1801 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1802 return ATOM_PPLL1; 1803 DRM_ERROR("unable to allocate a PPLL\n"); 1804 return ATOM_PPLL_INVALID; 1805 } 1806 1807 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 1808 { 1809 struct amdgpu_device *adev = crtc->dev->dev_private; 1810 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1811 uint32_t cur_lock; 1812 1813 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 1814 if (lock) 1815 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 1816 else 1817 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 1818 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 1819 } 1820 1821 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 1822 { 1823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1824 struct amdgpu_device *adev = crtc->dev->dev_private; 1825 1826 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 1827 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 1828 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 1829 1830 1831 } 1832 1833 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 1834 { 1835 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1836 struct amdgpu_device *adev = crtc->dev->dev_private; 1837 1838 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1839 upper_32_bits(amdgpu_crtc->cursor_addr)); 1840 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1841 lower_32_bits(amdgpu_crtc->cursor_addr)); 1842 1843 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 1844 CUR_CONTROL__CURSOR_EN_MASK | 1845 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 1846 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 1847 1848 } 1849 1850 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 1851 int x, int y) 1852 { 1853 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1854 struct amdgpu_device *adev = crtc->dev->dev_private; 1855 int xorigin = 0, yorigin = 0; 1856 1857 int w = amdgpu_crtc->cursor_width; 1858 1859 amdgpu_crtc->cursor_x = x; 1860 amdgpu_crtc->cursor_y = y; 1861 1862 /* avivo cursor are offset into the total surface */ 1863 x += crtc->x; 1864 y += crtc->y; 1865 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 1866 1867 if (x < 0) { 1868 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 1869 x = 0; 1870 } 1871 if (y < 0) { 1872 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 1873 y = 0; 1874 } 1875 1876 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 1877 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 1878 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 1879 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 1880 1881 return 0; 1882 } 1883 1884 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 1885 int x, int y) 1886 { 1887 int ret; 1888 1889 dce_v6_0_lock_cursor(crtc, true); 1890 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 1891 dce_v6_0_lock_cursor(crtc, false); 1892 1893 return ret; 1894 } 1895 1896 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 1897 struct drm_file *file_priv, 1898 uint32_t handle, 1899 uint32_t width, 1900 uint32_t height, 1901 int32_t hot_x, 1902 int32_t hot_y) 1903 { 1904 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1905 struct drm_gem_object *obj; 1906 struct amdgpu_bo *aobj; 1907 int ret; 1908 1909 if (!handle) { 1910 /* turn off cursor */ 1911 dce_v6_0_hide_cursor(crtc); 1912 obj = NULL; 1913 goto unpin; 1914 } 1915 1916 if ((width > amdgpu_crtc->max_cursor_width) || 1917 (height > amdgpu_crtc->max_cursor_height)) { 1918 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 1919 return -EINVAL; 1920 } 1921 1922 obj = drm_gem_object_lookup(file_priv, handle); 1923 if (!obj) { 1924 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 1925 return -ENOENT; 1926 } 1927 1928 aobj = gem_to_amdgpu_bo(obj); 1929 ret = amdgpu_bo_reserve(aobj, false); 1930 if (ret != 0) { 1931 drm_gem_object_unreference_unlocked(obj); 1932 return ret; 1933 } 1934 1935 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 1936 amdgpu_bo_unreserve(aobj); 1937 if (ret) { 1938 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 1939 drm_gem_object_unreference_unlocked(obj); 1940 return ret; 1941 } 1942 1943 dce_v6_0_lock_cursor(crtc, true); 1944 1945 if (width != amdgpu_crtc->cursor_width || 1946 height != amdgpu_crtc->cursor_height || 1947 hot_x != amdgpu_crtc->cursor_hot_x || 1948 hot_y != amdgpu_crtc->cursor_hot_y) { 1949 int x, y; 1950 1951 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 1952 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 1953 1954 dce_v6_0_cursor_move_locked(crtc, x, y); 1955 1956 amdgpu_crtc->cursor_width = width; 1957 amdgpu_crtc->cursor_height = height; 1958 amdgpu_crtc->cursor_hot_x = hot_x; 1959 amdgpu_crtc->cursor_hot_y = hot_y; 1960 } 1961 1962 dce_v6_0_show_cursor(crtc); 1963 dce_v6_0_lock_cursor(crtc, false); 1964 1965 unpin: 1966 if (amdgpu_crtc->cursor_bo) { 1967 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 1968 ret = amdgpu_bo_reserve(aobj, true); 1969 if (likely(ret == 0)) { 1970 amdgpu_bo_unpin(aobj); 1971 amdgpu_bo_unreserve(aobj); 1972 } 1973 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 1974 } 1975 1976 amdgpu_crtc->cursor_bo = obj; 1977 return 0; 1978 } 1979 1980 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 1981 { 1982 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1983 1984 if (amdgpu_crtc->cursor_bo) { 1985 dce_v6_0_lock_cursor(crtc, true); 1986 1987 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 1988 amdgpu_crtc->cursor_y); 1989 1990 dce_v6_0_show_cursor(crtc); 1991 dce_v6_0_lock_cursor(crtc, false); 1992 } 1993 } 1994 1995 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 1996 u16 *blue, uint32_t size, 1997 struct drm_modeset_acquire_ctx *ctx) 1998 { 1999 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2000 int i; 2001 2002 /* userspace palettes are always correct as is */ 2003 for (i = 0; i < size; i++) { 2004 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2005 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2006 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2007 } 2008 dce_v6_0_crtc_load_lut(crtc); 2009 2010 return 0; 2011 } 2012 2013 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2014 { 2015 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2016 2017 drm_crtc_cleanup(crtc); 2018 kfree(amdgpu_crtc); 2019 } 2020 2021 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2022 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2023 .cursor_move = dce_v6_0_crtc_cursor_move, 2024 .gamma_set = dce_v6_0_crtc_gamma_set, 2025 .set_config = amdgpu_crtc_set_config, 2026 .destroy = dce_v6_0_crtc_destroy, 2027 .page_flip_target = amdgpu_crtc_page_flip_target, 2028 }; 2029 2030 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2031 { 2032 struct drm_device *dev = crtc->dev; 2033 struct amdgpu_device *adev = dev->dev_private; 2034 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2035 unsigned type; 2036 2037 switch (mode) { 2038 case DRM_MODE_DPMS_ON: 2039 amdgpu_crtc->enabled = true; 2040 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2041 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2042 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2043 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2044 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2045 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2046 drm_crtc_vblank_on(crtc); 2047 dce_v6_0_crtc_load_lut(crtc); 2048 break; 2049 case DRM_MODE_DPMS_STANDBY: 2050 case DRM_MODE_DPMS_SUSPEND: 2051 case DRM_MODE_DPMS_OFF: 2052 drm_crtc_vblank_off(crtc); 2053 if (amdgpu_crtc->enabled) 2054 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2055 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2056 amdgpu_crtc->enabled = false; 2057 break; 2058 } 2059 /* adjust pm to dpms */ 2060 amdgpu_pm_compute_clocks(adev); 2061 } 2062 2063 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2064 { 2065 /* disable crtc pair power gating before programming */ 2066 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2067 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2068 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2069 } 2070 2071 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2072 { 2073 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2074 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2075 } 2076 2077 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2078 { 2079 2080 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2081 struct drm_device *dev = crtc->dev; 2082 struct amdgpu_device *adev = dev->dev_private; 2083 struct amdgpu_atom_ss ss; 2084 int i; 2085 2086 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2087 if (crtc->primary->fb) { 2088 int r; 2089 struct amdgpu_framebuffer *amdgpu_fb; 2090 struct amdgpu_bo *abo; 2091 2092 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2093 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2094 r = amdgpu_bo_reserve(abo, true); 2095 if (unlikely(r)) 2096 DRM_ERROR("failed to reserve abo before unpin\n"); 2097 else { 2098 amdgpu_bo_unpin(abo); 2099 amdgpu_bo_unreserve(abo); 2100 } 2101 } 2102 /* disable the GRPH */ 2103 dce_v6_0_grph_enable(crtc, false); 2104 2105 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2106 2107 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2108 if (adev->mode_info.crtcs[i] && 2109 adev->mode_info.crtcs[i]->enabled && 2110 i != amdgpu_crtc->crtc_id && 2111 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2112 /* one other crtc is using this pll don't turn 2113 * off the pll 2114 */ 2115 goto done; 2116 } 2117 } 2118 2119 switch (amdgpu_crtc->pll_id) { 2120 case ATOM_PPLL1: 2121 case ATOM_PPLL2: 2122 /* disable the ppll */ 2123 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2124 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2125 break; 2126 default: 2127 break; 2128 } 2129 done: 2130 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2131 amdgpu_crtc->adjusted_clock = 0; 2132 amdgpu_crtc->encoder = NULL; 2133 amdgpu_crtc->connector = NULL; 2134 } 2135 2136 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2137 struct drm_display_mode *mode, 2138 struct drm_display_mode *adjusted_mode, 2139 int x, int y, struct drm_framebuffer *old_fb) 2140 { 2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2142 2143 if (!amdgpu_crtc->adjusted_clock) 2144 return -EINVAL; 2145 2146 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2147 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2148 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2149 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2150 amdgpu_atombios_crtc_scaler_setup(crtc); 2151 dce_v6_0_cursor_reset(crtc); 2152 /* update the hw version fpr dpm */ 2153 amdgpu_crtc->hw_mode = *adjusted_mode; 2154 2155 return 0; 2156 } 2157 2158 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2159 const struct drm_display_mode *mode, 2160 struct drm_display_mode *adjusted_mode) 2161 { 2162 2163 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2164 struct drm_device *dev = crtc->dev; 2165 struct drm_encoder *encoder; 2166 2167 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2168 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2169 if (encoder->crtc == crtc) { 2170 amdgpu_crtc->encoder = encoder; 2171 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2172 break; 2173 } 2174 } 2175 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2176 amdgpu_crtc->encoder = NULL; 2177 amdgpu_crtc->connector = NULL; 2178 return false; 2179 } 2180 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2181 return false; 2182 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2183 return false; 2184 /* pick pll */ 2185 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2186 /* if we can't get a PPLL for a non-DP encoder, fail */ 2187 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2188 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2189 return false; 2190 2191 return true; 2192 } 2193 2194 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2195 struct drm_framebuffer *old_fb) 2196 { 2197 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2198 } 2199 2200 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2201 struct drm_framebuffer *fb, 2202 int x, int y, enum mode_set_atomic state) 2203 { 2204 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2205 } 2206 2207 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2208 .dpms = dce_v6_0_crtc_dpms, 2209 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2210 .mode_set = dce_v6_0_crtc_mode_set, 2211 .mode_set_base = dce_v6_0_crtc_set_base, 2212 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2213 .prepare = dce_v6_0_crtc_prepare, 2214 .commit = dce_v6_0_crtc_commit, 2215 .load_lut = dce_v6_0_crtc_load_lut, 2216 .disable = dce_v6_0_crtc_disable, 2217 }; 2218 2219 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2220 { 2221 struct amdgpu_crtc *amdgpu_crtc; 2222 int i; 2223 2224 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2225 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2226 if (amdgpu_crtc == NULL) 2227 return -ENOMEM; 2228 2229 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2230 2231 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2232 amdgpu_crtc->crtc_id = index; 2233 adev->mode_info.crtcs[index] = amdgpu_crtc; 2234 2235 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2236 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2237 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2238 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2239 2240 for (i = 0; i < 256; i++) { 2241 amdgpu_crtc->lut_r[i] = i << 2; 2242 amdgpu_crtc->lut_g[i] = i << 2; 2243 amdgpu_crtc->lut_b[i] = i << 2; 2244 } 2245 2246 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2247 2248 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2249 amdgpu_crtc->adjusted_clock = 0; 2250 amdgpu_crtc->encoder = NULL; 2251 amdgpu_crtc->connector = NULL; 2252 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2253 2254 return 0; 2255 } 2256 2257 static int dce_v6_0_early_init(void *handle) 2258 { 2259 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2260 2261 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2262 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2263 2264 dce_v6_0_set_display_funcs(adev); 2265 dce_v6_0_set_irq_funcs(adev); 2266 2267 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2268 2269 switch (adev->asic_type) { 2270 case CHIP_TAHITI: 2271 case CHIP_PITCAIRN: 2272 case CHIP_VERDE: 2273 adev->mode_info.num_hpd = 6; 2274 adev->mode_info.num_dig = 6; 2275 break; 2276 case CHIP_OLAND: 2277 adev->mode_info.num_hpd = 2; 2278 adev->mode_info.num_dig = 2; 2279 break; 2280 default: 2281 return -EINVAL; 2282 } 2283 2284 return 0; 2285 } 2286 2287 static int dce_v6_0_sw_init(void *handle) 2288 { 2289 int r, i; 2290 bool ret; 2291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2292 2293 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2294 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2295 if (r) 2296 return r; 2297 } 2298 2299 for (i = 8; i < 20; i += 2) { 2300 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2301 if (r) 2302 return r; 2303 } 2304 2305 /* HPD hotplug */ 2306 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2307 if (r) 2308 return r; 2309 2310 adev->mode_info.mode_config_initialized = true; 2311 2312 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2313 adev->ddev->mode_config.async_page_flip = true; 2314 adev->ddev->mode_config.max_width = 16384; 2315 adev->ddev->mode_config.max_height = 16384; 2316 adev->ddev->mode_config.preferred_depth = 24; 2317 adev->ddev->mode_config.prefer_shadow = 1; 2318 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2319 2320 r = amdgpu_modeset_create_props(adev); 2321 if (r) 2322 return r; 2323 2324 adev->ddev->mode_config.max_width = 16384; 2325 adev->ddev->mode_config.max_height = 16384; 2326 2327 /* allocate crtcs */ 2328 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2329 r = dce_v6_0_crtc_init(adev, i); 2330 if (r) 2331 return r; 2332 } 2333 2334 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2335 if (ret) 2336 amdgpu_print_display_setup(adev->ddev); 2337 else 2338 return -EINVAL; 2339 2340 /* setup afmt */ 2341 r = dce_v6_0_afmt_init(adev); 2342 if (r) 2343 return r; 2344 2345 r = dce_v6_0_audio_init(adev); 2346 if (r) 2347 return r; 2348 2349 drm_kms_helper_poll_init(adev->ddev); 2350 2351 return r; 2352 } 2353 2354 static int dce_v6_0_sw_fini(void *handle) 2355 { 2356 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2357 2358 kfree(adev->mode_info.bios_hardcoded_edid); 2359 2360 drm_kms_helper_poll_fini(adev->ddev); 2361 2362 dce_v6_0_audio_fini(adev); 2363 dce_v6_0_afmt_fini(adev); 2364 2365 drm_mode_config_cleanup(adev->ddev); 2366 adev->mode_info.mode_config_initialized = false; 2367 2368 return 0; 2369 } 2370 2371 static int dce_v6_0_hw_init(void *handle) 2372 { 2373 int i; 2374 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2375 2376 /* init dig PHYs, disp eng pll */ 2377 amdgpu_atombios_encoder_init_dig(adev); 2378 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2379 2380 /* initialize hpd */ 2381 dce_v6_0_hpd_init(adev); 2382 2383 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2384 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2385 } 2386 2387 dce_v6_0_pageflip_interrupt_init(adev); 2388 2389 return 0; 2390 } 2391 2392 static int dce_v6_0_hw_fini(void *handle) 2393 { 2394 int i; 2395 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2396 2397 dce_v6_0_hpd_fini(adev); 2398 2399 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2400 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2401 } 2402 2403 dce_v6_0_pageflip_interrupt_fini(adev); 2404 2405 return 0; 2406 } 2407 2408 static int dce_v6_0_suspend(void *handle) 2409 { 2410 return dce_v6_0_hw_fini(handle); 2411 } 2412 2413 static int dce_v6_0_resume(void *handle) 2414 { 2415 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2416 int ret; 2417 2418 ret = dce_v6_0_hw_init(handle); 2419 2420 /* turn on the BL */ 2421 if (adev->mode_info.bl_encoder) { 2422 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2423 adev->mode_info.bl_encoder); 2424 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2425 bl_level); 2426 } 2427 2428 return ret; 2429 } 2430 2431 static bool dce_v6_0_is_idle(void *handle) 2432 { 2433 return true; 2434 } 2435 2436 static int dce_v6_0_wait_for_idle(void *handle) 2437 { 2438 return 0; 2439 } 2440 2441 static int dce_v6_0_soft_reset(void *handle) 2442 { 2443 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); 2444 return 0; 2445 } 2446 2447 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2448 int crtc, 2449 enum amdgpu_interrupt_state state) 2450 { 2451 u32 reg_block, interrupt_mask; 2452 2453 if (crtc >= adev->mode_info.num_crtc) { 2454 DRM_DEBUG("invalid crtc %d\n", crtc); 2455 return; 2456 } 2457 2458 switch (crtc) { 2459 case 0: 2460 reg_block = SI_CRTC0_REGISTER_OFFSET; 2461 break; 2462 case 1: 2463 reg_block = SI_CRTC1_REGISTER_OFFSET; 2464 break; 2465 case 2: 2466 reg_block = SI_CRTC2_REGISTER_OFFSET; 2467 break; 2468 case 3: 2469 reg_block = SI_CRTC3_REGISTER_OFFSET; 2470 break; 2471 case 4: 2472 reg_block = SI_CRTC4_REGISTER_OFFSET; 2473 break; 2474 case 5: 2475 reg_block = SI_CRTC5_REGISTER_OFFSET; 2476 break; 2477 default: 2478 DRM_DEBUG("invalid crtc %d\n", crtc); 2479 return; 2480 } 2481 2482 switch (state) { 2483 case AMDGPU_IRQ_STATE_DISABLE: 2484 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2485 interrupt_mask &= ~VBLANK_INT_MASK; 2486 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2487 break; 2488 case AMDGPU_IRQ_STATE_ENABLE: 2489 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2490 interrupt_mask |= VBLANK_INT_MASK; 2491 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2492 break; 2493 default: 2494 break; 2495 } 2496 } 2497 2498 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2499 int crtc, 2500 enum amdgpu_interrupt_state state) 2501 { 2502 2503 } 2504 2505 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 2506 struct amdgpu_irq_src *src, 2507 unsigned type, 2508 enum amdgpu_interrupt_state state) 2509 { 2510 u32 dc_hpd_int_cntl; 2511 2512 if (type >= adev->mode_info.num_hpd) { 2513 DRM_DEBUG("invalid hdp %d\n", type); 2514 return 0; 2515 } 2516 2517 switch (state) { 2518 case AMDGPU_IRQ_STATE_DISABLE: 2519 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2520 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 2521 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2522 break; 2523 case AMDGPU_IRQ_STATE_ENABLE: 2524 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2525 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 2526 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2527 break; 2528 default: 2529 break; 2530 } 2531 2532 return 0; 2533 } 2534 2535 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 2536 struct amdgpu_irq_src *src, 2537 unsigned type, 2538 enum amdgpu_interrupt_state state) 2539 { 2540 switch (type) { 2541 case AMDGPU_CRTC_IRQ_VBLANK1: 2542 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 2543 break; 2544 case AMDGPU_CRTC_IRQ_VBLANK2: 2545 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 2546 break; 2547 case AMDGPU_CRTC_IRQ_VBLANK3: 2548 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 2549 break; 2550 case AMDGPU_CRTC_IRQ_VBLANK4: 2551 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 2552 break; 2553 case AMDGPU_CRTC_IRQ_VBLANK5: 2554 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 2555 break; 2556 case AMDGPU_CRTC_IRQ_VBLANK6: 2557 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 2558 break; 2559 case AMDGPU_CRTC_IRQ_VLINE1: 2560 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 2561 break; 2562 case AMDGPU_CRTC_IRQ_VLINE2: 2563 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 2564 break; 2565 case AMDGPU_CRTC_IRQ_VLINE3: 2566 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 2567 break; 2568 case AMDGPU_CRTC_IRQ_VLINE4: 2569 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 2570 break; 2571 case AMDGPU_CRTC_IRQ_VLINE5: 2572 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 2573 break; 2574 case AMDGPU_CRTC_IRQ_VLINE6: 2575 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 2576 break; 2577 default: 2578 break; 2579 } 2580 return 0; 2581 } 2582 2583 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 2584 struct amdgpu_irq_src *source, 2585 struct amdgpu_iv_entry *entry) 2586 { 2587 unsigned crtc = entry->src_id - 1; 2588 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 2589 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 2590 2591 switch (entry->src_data[0]) { 2592 case 0: /* vblank */ 2593 if (disp_int & interrupt_status_offsets[crtc].vblank) 2594 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 2595 else 2596 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2597 2598 if (amdgpu_irq_enabled(adev, source, irq_type)) { 2599 drm_handle_vblank(adev->ddev, crtc); 2600 } 2601 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 2602 break; 2603 case 1: /* vline */ 2604 if (disp_int & interrupt_status_offsets[crtc].vline) 2605 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 2606 else 2607 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2608 2609 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 2610 break; 2611 default: 2612 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 2613 break; 2614 } 2615 2616 return 0; 2617 } 2618 2619 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 2620 struct amdgpu_irq_src *src, 2621 unsigned type, 2622 enum amdgpu_interrupt_state state) 2623 { 2624 u32 reg; 2625 2626 if (type >= adev->mode_info.num_crtc) { 2627 DRM_ERROR("invalid pageflip crtc %d\n", type); 2628 return -EINVAL; 2629 } 2630 2631 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 2632 if (state == AMDGPU_IRQ_STATE_DISABLE) 2633 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 2634 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2635 else 2636 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 2637 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2638 2639 return 0; 2640 } 2641 2642 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 2643 struct amdgpu_irq_src *source, 2644 struct amdgpu_iv_entry *entry) 2645 { 2646 unsigned long flags; 2647 unsigned crtc_id; 2648 struct amdgpu_crtc *amdgpu_crtc; 2649 struct amdgpu_flip_work *works; 2650 2651 crtc_id = (entry->src_id - 8) >> 1; 2652 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 2653 2654 if (crtc_id >= adev->mode_info.num_crtc) { 2655 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 2656 return -EINVAL; 2657 } 2658 2659 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 2660 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 2661 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 2662 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 2663 2664 /* IRQ could occur when in initial stage */ 2665 if (amdgpu_crtc == NULL) 2666 return 0; 2667 2668 spin_lock_irqsave(&adev->ddev->event_lock, flags); 2669 works = amdgpu_crtc->pflip_works; 2670 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 2671 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 2672 "AMDGPU_FLIP_SUBMITTED(%d)\n", 2673 amdgpu_crtc->pflip_status, 2674 AMDGPU_FLIP_SUBMITTED); 2675 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 2676 return 0; 2677 } 2678 2679 /* page flip completed. clean up */ 2680 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 2681 amdgpu_crtc->pflip_works = NULL; 2682 2683 /* wakeup usersapce */ 2684 if (works->event) 2685 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 2686 2687 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 2688 2689 drm_crtc_vblank_put(&amdgpu_crtc->base); 2690 schedule_work(&works->unpin_work); 2691 2692 return 0; 2693 } 2694 2695 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 2696 struct amdgpu_irq_src *source, 2697 struct amdgpu_iv_entry *entry) 2698 { 2699 uint32_t disp_int, mask, tmp; 2700 unsigned hpd; 2701 2702 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 2703 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 2704 return 0; 2705 } 2706 2707 hpd = entry->src_data[0]; 2708 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 2709 mask = interrupt_status_offsets[hpd].hpd; 2710 2711 if (disp_int & mask) { 2712 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 2713 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 2714 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 2715 schedule_work(&adev->hotplug_work); 2716 DRM_INFO("IH: HPD%d\n", hpd + 1); 2717 } 2718 2719 return 0; 2720 2721 } 2722 2723 static int dce_v6_0_set_clockgating_state(void *handle, 2724 enum amd_clockgating_state state) 2725 { 2726 return 0; 2727 } 2728 2729 static int dce_v6_0_set_powergating_state(void *handle, 2730 enum amd_powergating_state state) 2731 { 2732 return 0; 2733 } 2734 2735 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 2736 .name = "dce_v6_0", 2737 .early_init = dce_v6_0_early_init, 2738 .late_init = NULL, 2739 .sw_init = dce_v6_0_sw_init, 2740 .sw_fini = dce_v6_0_sw_fini, 2741 .hw_init = dce_v6_0_hw_init, 2742 .hw_fini = dce_v6_0_hw_fini, 2743 .suspend = dce_v6_0_suspend, 2744 .resume = dce_v6_0_resume, 2745 .is_idle = dce_v6_0_is_idle, 2746 .wait_for_idle = dce_v6_0_wait_for_idle, 2747 .soft_reset = dce_v6_0_soft_reset, 2748 .set_clockgating_state = dce_v6_0_set_clockgating_state, 2749 .set_powergating_state = dce_v6_0_set_powergating_state, 2750 }; 2751 2752 static void 2753 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 2754 struct drm_display_mode *mode, 2755 struct drm_display_mode *adjusted_mode) 2756 { 2757 2758 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2759 2760 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 2761 2762 /* need to call this here rather than in prepare() since we need some crtc info */ 2763 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2764 2765 /* set scaler clears this on some chips */ 2766 dce_v6_0_set_interleave(encoder->crtc, mode); 2767 2768 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2769 dce_v6_0_afmt_enable(encoder, true); 2770 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 2771 } 2772 } 2773 2774 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 2775 { 2776 2777 struct amdgpu_device *adev = encoder->dev->dev_private; 2778 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2779 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 2780 2781 if ((amdgpu_encoder->active_device & 2782 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 2783 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 2784 ENCODER_OBJECT_ID_NONE)) { 2785 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2786 if (dig) { 2787 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 2788 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 2789 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 2790 } 2791 } 2792 2793 amdgpu_atombios_scratch_regs_lock(adev, true); 2794 2795 if (connector) { 2796 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 2797 2798 /* select the clock/data port if it uses a router */ 2799 if (amdgpu_connector->router.cd_valid) 2800 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 2801 2802 /* turn eDP panel on for mode set */ 2803 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 2804 amdgpu_atombios_encoder_set_edp_panel_power(connector, 2805 ATOM_TRANSMITTER_ACTION_POWER_ON); 2806 } 2807 2808 /* this is needed for the pll/ss setup to work correctly in some cases */ 2809 amdgpu_atombios_encoder_set_crtc_source(encoder); 2810 /* set up the FMT blocks */ 2811 dce_v6_0_program_fmt(encoder); 2812 } 2813 2814 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 2815 { 2816 2817 struct drm_device *dev = encoder->dev; 2818 struct amdgpu_device *adev = dev->dev_private; 2819 2820 /* need to call this here as we need the crtc set up */ 2821 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 2822 amdgpu_atombios_scratch_regs_lock(adev, false); 2823 } 2824 2825 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 2826 { 2827 2828 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2829 struct amdgpu_encoder_atom_dig *dig; 2830 2831 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 2832 2833 if (amdgpu_atombios_encoder_is_digital(encoder)) { 2834 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2835 dce_v6_0_afmt_enable(encoder, false); 2836 dig = amdgpu_encoder->enc_priv; 2837 dig->dig_encoder = -1; 2838 } 2839 amdgpu_encoder->active_device = 0; 2840 } 2841 2842 /* these are handled by the primary encoders */ 2843 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 2844 { 2845 2846 } 2847 2848 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 2849 { 2850 2851 } 2852 2853 static void 2854 dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 2855 struct drm_display_mode *mode, 2856 struct drm_display_mode *adjusted_mode) 2857 { 2858 2859 } 2860 2861 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 2862 { 2863 2864 } 2865 2866 static void 2867 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 2868 { 2869 2870 } 2871 2872 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 2873 const struct drm_display_mode *mode, 2874 struct drm_display_mode *adjusted_mode) 2875 { 2876 return true; 2877 } 2878 2879 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 2880 .dpms = dce_v6_0_ext_dpms, 2881 .mode_fixup = dce_v6_0_ext_mode_fixup, 2882 .prepare = dce_v6_0_ext_prepare, 2883 .mode_set = dce_v6_0_ext_mode_set, 2884 .commit = dce_v6_0_ext_commit, 2885 .disable = dce_v6_0_ext_disable, 2886 /* no detect for TMDS/LVDS yet */ 2887 }; 2888 2889 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 2890 .dpms = amdgpu_atombios_encoder_dpms, 2891 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 2892 .prepare = dce_v6_0_encoder_prepare, 2893 .mode_set = dce_v6_0_encoder_mode_set, 2894 .commit = dce_v6_0_encoder_commit, 2895 .disable = dce_v6_0_encoder_disable, 2896 .detect = amdgpu_atombios_encoder_dig_detect, 2897 }; 2898 2899 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 2900 .dpms = amdgpu_atombios_encoder_dpms, 2901 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 2902 .prepare = dce_v6_0_encoder_prepare, 2903 .mode_set = dce_v6_0_encoder_mode_set, 2904 .commit = dce_v6_0_encoder_commit, 2905 .detect = amdgpu_atombios_encoder_dac_detect, 2906 }; 2907 2908 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 2909 { 2910 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2911 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 2912 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 2913 kfree(amdgpu_encoder->enc_priv); 2914 drm_encoder_cleanup(encoder); 2915 kfree(amdgpu_encoder); 2916 } 2917 2918 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 2919 .destroy = dce_v6_0_encoder_destroy, 2920 }; 2921 2922 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 2923 uint32_t encoder_enum, 2924 uint32_t supported_device, 2925 u16 caps) 2926 { 2927 struct drm_device *dev = adev->ddev; 2928 struct drm_encoder *encoder; 2929 struct amdgpu_encoder *amdgpu_encoder; 2930 2931 /* see if we already added it */ 2932 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2933 amdgpu_encoder = to_amdgpu_encoder(encoder); 2934 if (amdgpu_encoder->encoder_enum == encoder_enum) { 2935 amdgpu_encoder->devices |= supported_device; 2936 return; 2937 } 2938 2939 } 2940 2941 /* add a new one */ 2942 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 2943 if (!amdgpu_encoder) 2944 return; 2945 2946 encoder = &amdgpu_encoder->base; 2947 switch (adev->mode_info.num_crtc) { 2948 case 1: 2949 encoder->possible_crtcs = 0x1; 2950 break; 2951 case 2: 2952 default: 2953 encoder->possible_crtcs = 0x3; 2954 break; 2955 case 4: 2956 encoder->possible_crtcs = 0xf; 2957 break; 2958 case 6: 2959 encoder->possible_crtcs = 0x3f; 2960 break; 2961 } 2962 2963 amdgpu_encoder->enc_priv = NULL; 2964 amdgpu_encoder->encoder_enum = encoder_enum; 2965 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 2966 amdgpu_encoder->devices = supported_device; 2967 amdgpu_encoder->rmx_type = RMX_OFF; 2968 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 2969 amdgpu_encoder->is_ext_encoder = false; 2970 amdgpu_encoder->caps = caps; 2971 2972 switch (amdgpu_encoder->encoder_id) { 2973 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 2974 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 2975 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 2976 DRM_MODE_ENCODER_DAC, NULL); 2977 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 2978 break; 2979 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 2980 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2981 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2982 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2983 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2984 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 2985 amdgpu_encoder->rmx_type = RMX_FULL; 2986 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 2987 DRM_MODE_ENCODER_LVDS, NULL); 2988 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 2989 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 2990 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 2991 DRM_MODE_ENCODER_DAC, NULL); 2992 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 2993 } else { 2994 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 2995 DRM_MODE_ENCODER_TMDS, NULL); 2996 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 2997 } 2998 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 2999 break; 3000 case ENCODER_OBJECT_ID_SI170B: 3001 case ENCODER_OBJECT_ID_CH7303: 3002 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3003 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3004 case ENCODER_OBJECT_ID_TITFP513: 3005 case ENCODER_OBJECT_ID_VT1623: 3006 case ENCODER_OBJECT_ID_HDMI_SI1930: 3007 case ENCODER_OBJECT_ID_TRAVIS: 3008 case ENCODER_OBJECT_ID_NUTMEG: 3009 /* these are handled by the primary encoders */ 3010 amdgpu_encoder->is_ext_encoder = true; 3011 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3012 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3013 DRM_MODE_ENCODER_LVDS, NULL); 3014 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3015 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3016 DRM_MODE_ENCODER_DAC, NULL); 3017 else 3018 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3019 DRM_MODE_ENCODER_TMDS, NULL); 3020 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3021 break; 3022 } 3023 } 3024 3025 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3026 .set_vga_render_state = &dce_v6_0_set_vga_render_state, 3027 .bandwidth_update = &dce_v6_0_bandwidth_update, 3028 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3029 .vblank_wait = &dce_v6_0_vblank_wait, 3030 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3031 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3032 .hpd_sense = &dce_v6_0_hpd_sense, 3033 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3034 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3035 .page_flip = &dce_v6_0_page_flip, 3036 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3037 .add_encoder = &dce_v6_0_encoder_add, 3038 .add_connector = &amdgpu_connector_add, 3039 .stop_mc_access = &dce_v6_0_stop_mc_access, 3040 .resume_mc_access = &dce_v6_0_resume_mc_access, 3041 }; 3042 3043 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3044 { 3045 if (adev->mode_info.funcs == NULL) 3046 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3047 } 3048 3049 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3050 .set = dce_v6_0_set_crtc_interrupt_state, 3051 .process = dce_v6_0_crtc_irq, 3052 }; 3053 3054 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3055 .set = dce_v6_0_set_pageflip_interrupt_state, 3056 .process = dce_v6_0_pageflip_irq, 3057 }; 3058 3059 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3060 .set = dce_v6_0_set_hpd_interrupt_state, 3061 .process = dce_v6_0_hpd_irq, 3062 }; 3063 3064 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3065 { 3066 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3067 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3068 3069 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3070 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3071 3072 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3073 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3074 } 3075 3076 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3077 { 3078 .type = AMD_IP_BLOCK_TYPE_DCE, 3079 .major = 6, 3080 .minor = 0, 3081 .rev = 0, 3082 .funcs = &dce_v6_0_ip_funcs, 3083 }; 3084 3085 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3086 { 3087 .type = AMD_IP_BLOCK_TYPE_DCE, 3088 .major = 6, 3089 .minor = 4, 3090 .rev = 0, 3091 .funcs = &dce_v6_0_ip_funcs, 3092 }; 3093