1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "atom.h" 28 #include "amdgpu_atombios.h" 29 #include "atombios_crtc.h" 30 #include "atombios_encoders.h" 31 #include "amdgpu_pll.h" 32 #include "amdgpu_connectors.h" 33 34 #include "bif/bif_3_0_d.h" 35 #include "bif/bif_3_0_sh_mask.h" 36 #include "oss/oss_1_0_d.h" 37 #include "oss/oss_1_0_sh_mask.h" 38 #include "gca/gfx_6_0_d.h" 39 #include "gca/gfx_6_0_sh_mask.h" 40 #include "gmc/gmc_6_0_d.h" 41 #include "gmc/gmc_6_0_sh_mask.h" 42 #include "dce/dce_6_0_d.h" 43 #include "dce/dce_6_0_sh_mask.h" 44 #include "gca/gfx_7_2_enum.h" 45 #include "si_enums.h" 46 47 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 48 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 49 50 static const u32 crtc_offsets[6] = 51 { 52 SI_CRTC0_REGISTER_OFFSET, 53 SI_CRTC1_REGISTER_OFFSET, 54 SI_CRTC2_REGISTER_OFFSET, 55 SI_CRTC3_REGISTER_OFFSET, 56 SI_CRTC4_REGISTER_OFFSET, 57 SI_CRTC5_REGISTER_OFFSET 58 }; 59 60 static const u32 hpd_offsets[] = 61 { 62 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 63 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 64 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 65 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 66 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 67 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 68 }; 69 70 static const uint32_t dig_offsets[] = { 71 SI_CRTC0_REGISTER_OFFSET, 72 SI_CRTC1_REGISTER_OFFSET, 73 SI_CRTC2_REGISTER_OFFSET, 74 SI_CRTC3_REGISTER_OFFSET, 75 SI_CRTC4_REGISTER_OFFSET, 76 SI_CRTC5_REGISTER_OFFSET, 77 (0x13830 - 0x7030) >> 2, 78 }; 79 80 static const struct { 81 uint32_t reg; 82 uint32_t vblank; 83 uint32_t vline; 84 uint32_t hpd; 85 86 } interrupt_status_offsets[6] = { { 87 .reg = mmDISP_INTERRUPT_STATUS, 88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 91 }, { 92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 96 }, { 97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 116 } }; 117 118 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 119 u32 block_offset, u32 reg) 120 { 121 unsigned long flags; 122 u32 r; 123 124 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 125 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 126 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 127 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 128 129 return r; 130 } 131 132 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 133 u32 block_offset, u32 reg, u32 v) 134 { 135 unsigned long flags; 136 137 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 138 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 139 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 140 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 141 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 142 } 143 144 static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 145 { 146 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK) 147 return true; 148 else 149 return false; 150 } 151 152 static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 153 { 154 u32 pos1, pos2; 155 156 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 157 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 158 159 if (pos1 != pos2) 160 return true; 161 else 162 return false; 163 } 164 165 /** 166 * dce_v6_0_wait_for_vblank - vblank wait asic callback. 167 * 168 * @crtc: crtc to wait for vblank on 169 * 170 * Wait for vblank on the requested crtc (evergreen+). 171 */ 172 static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc) 173 { 174 unsigned i = 100; 175 176 if (crtc >= adev->mode_info.num_crtc) 177 return; 178 179 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 180 return; 181 182 /* depending on when we hit vblank, we may be close to active; if so, 183 * wait for another frame. 184 */ 185 while (dce_v6_0_is_in_vblank(adev, crtc)) { 186 if (i++ == 100) { 187 i = 0; 188 if (!dce_v6_0_is_counter_moving(adev, crtc)) 189 break; 190 } 191 } 192 193 while (!dce_v6_0_is_in_vblank(adev, crtc)) { 194 if (i++ == 100) { 195 i = 0; 196 if (!dce_v6_0_is_counter_moving(adev, crtc)) 197 break; 198 } 199 } 200 } 201 202 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 203 { 204 if (crtc >= adev->mode_info.num_crtc) 205 return 0; 206 else 207 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 208 } 209 210 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 211 { 212 unsigned i; 213 214 /* Enable pflip interrupts */ 215 for (i = 0; i < adev->mode_info.num_crtc; i++) 216 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 217 } 218 219 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 220 { 221 unsigned i; 222 223 /* Disable pflip interrupts */ 224 for (i = 0; i < adev->mode_info.num_crtc; i++) 225 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 226 } 227 228 /** 229 * dce_v6_0_page_flip - pageflip callback. 230 * 231 * @adev: amdgpu_device pointer 232 * @crtc_id: crtc to cleanup pageflip on 233 * @crtc_base: new address of the crtc (GPU MC address) 234 * 235 * Does the actual pageflip (evergreen+). 236 * During vblank we take the crtc lock and wait for the update_pending 237 * bit to go high, when it does, we release the lock, and allow the 238 * double buffered update to take place. 239 * Returns the current update pending status. 240 */ 241 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 242 int crtc_id, u64 crtc_base, bool async) 243 { 244 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 245 246 /* flip at hsync for async, default is vsync */ 247 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 248 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 249 /* update the scanout addresses */ 250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 251 upper_32_bits(crtc_base)); 252 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 253 (u32)crtc_base); 254 255 /* post the write */ 256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 257 } 258 259 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 260 u32 *vbl, u32 *position) 261 { 262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 263 return -EINVAL; 264 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 265 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 266 267 return 0; 268 269 } 270 271 /** 272 * dce_v6_0_hpd_sense - hpd sense callback. 273 * 274 * @adev: amdgpu_device pointer 275 * @hpd: hpd (hotplug detect) pin 276 * 277 * Checks if a digital monitor is connected (evergreen+). 278 * Returns true if connected, false if not connected. 279 */ 280 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 281 enum amdgpu_hpd_id hpd) 282 { 283 bool connected = false; 284 285 if (hpd >= adev->mode_info.num_hpd) 286 return connected; 287 288 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 289 connected = true; 290 291 return connected; 292 } 293 294 /** 295 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 296 * 297 * @adev: amdgpu_device pointer 298 * @hpd: hpd (hotplug detect) pin 299 * 300 * Set the polarity of the hpd pin (evergreen+). 301 */ 302 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 303 enum amdgpu_hpd_id hpd) 304 { 305 u32 tmp; 306 bool connected = dce_v6_0_hpd_sense(adev, hpd); 307 308 if (hpd >= adev->mode_info.num_hpd) 309 return; 310 311 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 312 if (connected) 313 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 314 else 315 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 316 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 317 } 318 319 /** 320 * dce_v6_0_hpd_init - hpd setup callback. 321 * 322 * @adev: amdgpu_device pointer 323 * 324 * Setup the hpd pins used by the card (evergreen+). 325 * Enable the pin, set the polarity, and enable the hpd interrupts. 326 */ 327 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 328 { 329 struct drm_device *dev = adev->ddev; 330 struct drm_connector *connector; 331 u32 tmp; 332 333 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 334 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 335 336 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 337 continue; 338 339 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 340 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 341 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 342 343 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 344 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 345 /* don't try to enable hpd on eDP or LVDS avoid breaking the 346 * aux dp channel on imac and help (but not completely fix) 347 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 348 * also avoid interrupt storms during dpms. 349 */ 350 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 351 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 352 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 353 continue; 354 } 355 356 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 357 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 358 } 359 360 } 361 362 /** 363 * dce_v6_0_hpd_fini - hpd tear down callback. 364 * 365 * @adev: amdgpu_device pointer 366 * 367 * Tear down the hpd pins used by the card (evergreen+). 368 * Disable the hpd interrupts. 369 */ 370 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 371 { 372 struct drm_device *dev = adev->ddev; 373 struct drm_connector *connector; 374 u32 tmp; 375 376 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 377 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 378 379 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 380 continue; 381 382 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 383 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 384 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 385 386 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 387 } 388 } 389 390 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 391 { 392 return mmDC_GPIO_HPD_A; 393 } 394 395 static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc) 396 { 397 if (crtc >= adev->mode_info.num_crtc) 398 return 0; 399 else 400 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 401 } 402 403 static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev, 404 struct amdgpu_mode_mc_save *save) 405 { 406 u32 crtc_enabled, tmp, frame_count; 407 int i, j; 408 409 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 410 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 411 412 /* disable VGA render */ 413 WREG32(mmVGA_RENDER_CONTROL, 0); 414 415 /* blank the display controllers */ 416 for (i = 0; i < adev->mode_info.num_crtc; i++) { 417 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK; 418 if (crtc_enabled) { 419 save->crtc_enabled[i] = true; 420 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 421 422 if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) { 423 dce_v6_0_vblank_wait(adev, i); 424 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 425 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK; 426 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 427 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 428 } 429 /* wait for the next frame */ 430 frame_count = evergreen_get_vblank_counter(adev, i); 431 for (j = 0; j < adev->usec_timeout; j++) { 432 if (evergreen_get_vblank_counter(adev, i) != frame_count) 433 break; 434 udelay(1); 435 } 436 437 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 438 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 439 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 440 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 441 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 442 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 443 save->crtc_enabled[i] = false; 444 /* ***** */ 445 } else { 446 save->crtc_enabled[i] = false; 447 } 448 } 449 } 450 451 static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, 452 struct amdgpu_mode_mc_save *save) 453 { 454 u32 tmp; 455 int i, j; 456 457 /* update crtc base addresses */ 458 for (i = 0; i < adev->mode_info.num_crtc; i++) { 459 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 460 upper_32_bits(adev->mc.vram_start)); 461 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 462 upper_32_bits(adev->mc.vram_start)); 463 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 464 (u32)adev->mc.vram_start); 465 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 466 (u32)adev->mc.vram_start); 467 } 468 469 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 470 WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start); 471 472 /* unlock regs and wait for update */ 473 for (i = 0; i < adev->mode_info.num_crtc; i++) { 474 if (save->crtc_enabled[i]) { 475 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 476 if ((tmp & 0x7) != 0) { 477 tmp &= ~0x7; 478 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 479 } 480 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 481 if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) { 482 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK; 483 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 484 } 485 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 486 if (tmp & 1) { 487 tmp &= ~1; 488 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 489 } 490 for (j = 0; j < adev->usec_timeout; j++) { 491 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 492 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0) 493 break; 494 udelay(1); 495 } 496 } 497 } 498 499 /* Unlock vga access */ 500 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 501 mdelay(1); 502 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 503 504 } 505 506 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 507 bool render) 508 { 509 if (!render) 510 WREG32(mmVGA_RENDER_CONTROL, 511 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 512 513 } 514 515 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 516 { 517 int num_crtc = 0; 518 519 switch (adev->asic_type) { 520 case CHIP_TAHITI: 521 case CHIP_PITCAIRN: 522 case CHIP_VERDE: 523 num_crtc = 6; 524 break; 525 case CHIP_OLAND: 526 num_crtc = 2; 527 break; 528 default: 529 num_crtc = 0; 530 } 531 return num_crtc; 532 } 533 534 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 535 { 536 /*Disable VGA render and enabled crtc, if has DCE engine*/ 537 if (amdgpu_atombios_has_dce_engine_info(adev)) { 538 u32 tmp; 539 int crtc_enabled, i; 540 541 dce_v6_0_set_vga_render_state(adev, false); 542 543 /*Disable crtc*/ 544 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 545 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 546 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 547 if (crtc_enabled) { 548 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 549 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 550 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 551 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 552 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 553 } 554 } 555 } 556 } 557 558 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 559 { 560 561 struct drm_device *dev = encoder->dev; 562 struct amdgpu_device *adev = dev->dev_private; 563 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 564 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 565 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 566 int bpc = 0; 567 u32 tmp = 0; 568 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 569 570 if (connector) { 571 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 572 bpc = amdgpu_connector_get_monitor_bpc(connector); 573 dither = amdgpu_connector->dither; 574 } 575 576 /* LVDS FMT is set up by atom */ 577 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 578 return; 579 580 if (bpc == 0) 581 return; 582 583 584 switch (bpc) { 585 case 6: 586 if (dither == AMDGPU_FMT_DITHER_ENABLE) 587 /* XXX sort out optimal dither settings */ 588 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 589 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 590 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 591 else 592 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 593 break; 594 case 8: 595 if (dither == AMDGPU_FMT_DITHER_ENABLE) 596 /* XXX sort out optimal dither settings */ 597 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 598 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 599 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 600 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 601 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 602 else 603 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 604 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 605 break; 606 case 10: 607 default: 608 /* not needed */ 609 break; 610 } 611 612 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 613 } 614 615 /** 616 * cik_get_number_of_dram_channels - get the number of dram channels 617 * 618 * @adev: amdgpu_device pointer 619 * 620 * Look up the number of video ram channels (CIK). 621 * Used for display watermark bandwidth calculations 622 * Returns the number of dram channels 623 */ 624 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 625 { 626 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 627 628 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 629 case 0: 630 default: 631 return 1; 632 case 1: 633 return 2; 634 case 2: 635 return 4; 636 case 3: 637 return 8; 638 case 4: 639 return 3; 640 case 5: 641 return 6; 642 case 6: 643 return 10; 644 case 7: 645 return 12; 646 case 8: 647 return 16; 648 } 649 } 650 651 struct dce6_wm_params { 652 u32 dram_channels; /* number of dram channels */ 653 u32 yclk; /* bandwidth per dram data pin in kHz */ 654 u32 sclk; /* engine clock in kHz */ 655 u32 disp_clk; /* display clock in kHz */ 656 u32 src_width; /* viewport width */ 657 u32 active_time; /* active display time in ns */ 658 u32 blank_time; /* blank time in ns */ 659 bool interlaced; /* mode is interlaced */ 660 fixed20_12 vsc; /* vertical scale ratio */ 661 u32 num_heads; /* number of active crtcs */ 662 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 663 u32 lb_size; /* line buffer allocated to pipe */ 664 u32 vtaps; /* vertical scaler taps */ 665 }; 666 667 /** 668 * dce_v6_0_dram_bandwidth - get the dram bandwidth 669 * 670 * @wm: watermark calculation data 671 * 672 * Calculate the raw dram bandwidth (CIK). 673 * Used for display watermark bandwidth calculations 674 * Returns the dram bandwidth in MBytes/s 675 */ 676 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 677 { 678 /* Calculate raw DRAM Bandwidth */ 679 fixed20_12 dram_efficiency; /* 0.7 */ 680 fixed20_12 yclk, dram_channels, bandwidth; 681 fixed20_12 a; 682 683 a.full = dfixed_const(1000); 684 yclk.full = dfixed_const(wm->yclk); 685 yclk.full = dfixed_div(yclk, a); 686 dram_channels.full = dfixed_const(wm->dram_channels * 4); 687 a.full = dfixed_const(10); 688 dram_efficiency.full = dfixed_const(7); 689 dram_efficiency.full = dfixed_div(dram_efficiency, a); 690 bandwidth.full = dfixed_mul(dram_channels, yclk); 691 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 692 693 return dfixed_trunc(bandwidth); 694 } 695 696 /** 697 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 698 * 699 * @wm: watermark calculation data 700 * 701 * Calculate the dram bandwidth used for display (CIK). 702 * Used for display watermark bandwidth calculations 703 * Returns the dram bandwidth for display in MBytes/s 704 */ 705 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 706 { 707 /* Calculate DRAM Bandwidth and the part allocated to display. */ 708 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 709 fixed20_12 yclk, dram_channels, bandwidth; 710 fixed20_12 a; 711 712 a.full = dfixed_const(1000); 713 yclk.full = dfixed_const(wm->yclk); 714 yclk.full = dfixed_div(yclk, a); 715 dram_channels.full = dfixed_const(wm->dram_channels * 4); 716 a.full = dfixed_const(10); 717 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 718 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 719 bandwidth.full = dfixed_mul(dram_channels, yclk); 720 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 721 722 return dfixed_trunc(bandwidth); 723 } 724 725 /** 726 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 727 * 728 * @wm: watermark calculation data 729 * 730 * Calculate the data return bandwidth used for display (CIK). 731 * Used for display watermark bandwidth calculations 732 * Returns the data return bandwidth in MBytes/s 733 */ 734 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 735 { 736 /* Calculate the display Data return Bandwidth */ 737 fixed20_12 return_efficiency; /* 0.8 */ 738 fixed20_12 sclk, bandwidth; 739 fixed20_12 a; 740 741 a.full = dfixed_const(1000); 742 sclk.full = dfixed_const(wm->sclk); 743 sclk.full = dfixed_div(sclk, a); 744 a.full = dfixed_const(10); 745 return_efficiency.full = dfixed_const(8); 746 return_efficiency.full = dfixed_div(return_efficiency, a); 747 a.full = dfixed_const(32); 748 bandwidth.full = dfixed_mul(a, sclk); 749 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 750 751 return dfixed_trunc(bandwidth); 752 } 753 754 /** 755 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 756 * 757 * @wm: watermark calculation data 758 * 759 * Calculate the dmif bandwidth used for display (CIK). 760 * Used for display watermark bandwidth calculations 761 * Returns the dmif bandwidth in MBytes/s 762 */ 763 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 764 { 765 /* Calculate the DMIF Request Bandwidth */ 766 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 767 fixed20_12 disp_clk, bandwidth; 768 fixed20_12 a, b; 769 770 a.full = dfixed_const(1000); 771 disp_clk.full = dfixed_const(wm->disp_clk); 772 disp_clk.full = dfixed_div(disp_clk, a); 773 a.full = dfixed_const(32); 774 b.full = dfixed_mul(a, disp_clk); 775 776 a.full = dfixed_const(10); 777 disp_clk_request_efficiency.full = dfixed_const(8); 778 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 779 780 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 781 782 return dfixed_trunc(bandwidth); 783 } 784 785 /** 786 * dce_v6_0_available_bandwidth - get the min available bandwidth 787 * 788 * @wm: watermark calculation data 789 * 790 * Calculate the min available bandwidth used for display (CIK). 791 * Used for display watermark bandwidth calculations 792 * Returns the min available bandwidth in MBytes/s 793 */ 794 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 795 { 796 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 797 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 798 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 799 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 800 801 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 802 } 803 804 /** 805 * dce_v6_0_average_bandwidth - get the average available bandwidth 806 * 807 * @wm: watermark calculation data 808 * 809 * Calculate the average available bandwidth used for display (CIK). 810 * Used for display watermark bandwidth calculations 811 * Returns the average available bandwidth in MBytes/s 812 */ 813 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 814 { 815 /* Calculate the display mode Average Bandwidth 816 * DisplayMode should contain the source and destination dimensions, 817 * timing, etc. 818 */ 819 fixed20_12 bpp; 820 fixed20_12 line_time; 821 fixed20_12 src_width; 822 fixed20_12 bandwidth; 823 fixed20_12 a; 824 825 a.full = dfixed_const(1000); 826 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 827 line_time.full = dfixed_div(line_time, a); 828 bpp.full = dfixed_const(wm->bytes_per_pixel); 829 src_width.full = dfixed_const(wm->src_width); 830 bandwidth.full = dfixed_mul(src_width, bpp); 831 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 832 bandwidth.full = dfixed_div(bandwidth, line_time); 833 834 return dfixed_trunc(bandwidth); 835 } 836 837 /** 838 * dce_v6_0_latency_watermark - get the latency watermark 839 * 840 * @wm: watermark calculation data 841 * 842 * Calculate the latency watermark (CIK). 843 * Used for display watermark bandwidth calculations 844 * Returns the latency watermark in ns 845 */ 846 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 847 { 848 /* First calculate the latency in ns */ 849 u32 mc_latency = 2000; /* 2000 ns. */ 850 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 851 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 852 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 853 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 854 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 855 (wm->num_heads * cursor_line_pair_return_time); 856 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 857 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 858 u32 tmp, dmif_size = 12288; 859 fixed20_12 a, b, c; 860 861 if (wm->num_heads == 0) 862 return 0; 863 864 a.full = dfixed_const(2); 865 b.full = dfixed_const(1); 866 if ((wm->vsc.full > a.full) || 867 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 868 (wm->vtaps >= 5) || 869 ((wm->vsc.full >= a.full) && wm->interlaced)) 870 max_src_lines_per_dst_line = 4; 871 else 872 max_src_lines_per_dst_line = 2; 873 874 a.full = dfixed_const(available_bandwidth); 875 b.full = dfixed_const(wm->num_heads); 876 a.full = dfixed_div(a, b); 877 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 878 tmp = min(dfixed_trunc(a), tmp); 879 880 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 881 882 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 883 b.full = dfixed_const(1000); 884 c.full = dfixed_const(lb_fill_bw); 885 b.full = dfixed_div(c, b); 886 a.full = dfixed_div(a, b); 887 line_fill_time = dfixed_trunc(a); 888 889 if (line_fill_time < wm->active_time) 890 return latency; 891 else 892 return latency + (line_fill_time - wm->active_time); 893 894 } 895 896 /** 897 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 898 * average and available dram bandwidth 899 * 900 * @wm: watermark calculation data 901 * 902 * Check if the display average bandwidth fits in the display 903 * dram bandwidth (CIK). 904 * Used for display watermark bandwidth calculations 905 * Returns true if the display fits, false if not. 906 */ 907 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 908 { 909 if (dce_v6_0_average_bandwidth(wm) <= 910 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 911 return true; 912 else 913 return false; 914 } 915 916 /** 917 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 918 * average and available bandwidth 919 * 920 * @wm: watermark calculation data 921 * 922 * Check if the display average bandwidth fits in the display 923 * available bandwidth (CIK). 924 * Used for display watermark bandwidth calculations 925 * Returns true if the display fits, false if not. 926 */ 927 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 928 { 929 if (dce_v6_0_average_bandwidth(wm) <= 930 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 931 return true; 932 else 933 return false; 934 } 935 936 /** 937 * dce_v6_0_check_latency_hiding - check latency hiding 938 * 939 * @wm: watermark calculation data 940 * 941 * Check latency hiding (CIK). 942 * Used for display watermark bandwidth calculations 943 * Returns true if the display fits, false if not. 944 */ 945 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 946 { 947 u32 lb_partitions = wm->lb_size / wm->src_width; 948 u32 line_time = wm->active_time + wm->blank_time; 949 u32 latency_tolerant_lines; 950 u32 latency_hiding; 951 fixed20_12 a; 952 953 a.full = dfixed_const(1); 954 if (wm->vsc.full > a.full) 955 latency_tolerant_lines = 1; 956 else { 957 if (lb_partitions <= (wm->vtaps + 1)) 958 latency_tolerant_lines = 1; 959 else 960 latency_tolerant_lines = 2; 961 } 962 963 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 964 965 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 966 return true; 967 else 968 return false; 969 } 970 971 /** 972 * dce_v6_0_program_watermarks - program display watermarks 973 * 974 * @adev: amdgpu_device pointer 975 * @amdgpu_crtc: the selected display controller 976 * @lb_size: line buffer size 977 * @num_heads: number of display controllers in use 978 * 979 * Calculate and program the display watermarks for the 980 * selected display controller (CIK). 981 */ 982 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 983 struct amdgpu_crtc *amdgpu_crtc, 984 u32 lb_size, u32 num_heads) 985 { 986 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 987 struct dce6_wm_params wm_low, wm_high; 988 u32 dram_channels; 989 u32 active_time; 990 u32 line_time = 0; 991 u32 latency_watermark_a = 0, latency_watermark_b = 0; 992 u32 priority_a_mark = 0, priority_b_mark = 0; 993 u32 priority_a_cnt = PRIORITY_OFF; 994 u32 priority_b_cnt = PRIORITY_OFF; 995 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 996 fixed20_12 a, b, c; 997 998 if (amdgpu_crtc->base.enabled && num_heads && mode) { 999 active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock; 1000 line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535); 1001 priority_a_cnt = 0; 1002 priority_b_cnt = 0; 1003 1004 dram_channels = si_get_number_of_dram_channels(adev); 1005 1006 /* watermark for high clocks */ 1007 if (adev->pm.dpm_enabled) { 1008 wm_high.yclk = 1009 amdgpu_dpm_get_mclk(adev, false) * 10; 1010 wm_high.sclk = 1011 amdgpu_dpm_get_sclk(adev, false) * 10; 1012 } else { 1013 wm_high.yclk = adev->pm.current_mclk * 10; 1014 wm_high.sclk = adev->pm.current_sclk * 10; 1015 } 1016 1017 wm_high.disp_clk = mode->clock; 1018 wm_high.src_width = mode->crtc_hdisplay; 1019 wm_high.active_time = active_time; 1020 wm_high.blank_time = line_time - wm_high.active_time; 1021 wm_high.interlaced = false; 1022 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1023 wm_high.interlaced = true; 1024 wm_high.vsc = amdgpu_crtc->vsc; 1025 wm_high.vtaps = 1; 1026 if (amdgpu_crtc->rmx_type != RMX_OFF) 1027 wm_high.vtaps = 2; 1028 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1029 wm_high.lb_size = lb_size; 1030 wm_high.dram_channels = dram_channels; 1031 wm_high.num_heads = num_heads; 1032 1033 if (adev->pm.dpm_enabled) { 1034 /* watermark for low clocks */ 1035 wm_low.yclk = 1036 amdgpu_dpm_get_mclk(adev, true) * 10; 1037 wm_low.sclk = 1038 amdgpu_dpm_get_sclk(adev, true) * 10; 1039 } else { 1040 wm_low.yclk = adev->pm.current_mclk * 10; 1041 wm_low.sclk = adev->pm.current_sclk * 10; 1042 } 1043 1044 wm_low.disp_clk = mode->clock; 1045 wm_low.src_width = mode->crtc_hdisplay; 1046 wm_low.active_time = active_time; 1047 wm_low.blank_time = line_time - wm_low.active_time; 1048 wm_low.interlaced = false; 1049 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1050 wm_low.interlaced = true; 1051 wm_low.vsc = amdgpu_crtc->vsc; 1052 wm_low.vtaps = 1; 1053 if (amdgpu_crtc->rmx_type != RMX_OFF) 1054 wm_low.vtaps = 2; 1055 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1056 wm_low.lb_size = lb_size; 1057 wm_low.dram_channels = dram_channels; 1058 wm_low.num_heads = num_heads; 1059 1060 /* set for high clocks */ 1061 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535); 1062 /* set for low clocks */ 1063 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535); 1064 1065 /* possibly force display priority to high */ 1066 /* should really do this at mode validation time... */ 1067 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1068 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1069 !dce_v6_0_check_latency_hiding(&wm_high) || 1070 (adev->mode_info.disp_priority == 2)) { 1071 DRM_DEBUG_KMS("force priority to high\n"); 1072 priority_a_cnt |= PRIORITY_ALWAYS_ON; 1073 priority_b_cnt |= PRIORITY_ALWAYS_ON; 1074 } 1075 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1076 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1077 !dce_v6_0_check_latency_hiding(&wm_low) || 1078 (adev->mode_info.disp_priority == 2)) { 1079 DRM_DEBUG_KMS("force priority to high\n"); 1080 priority_a_cnt |= PRIORITY_ALWAYS_ON; 1081 priority_b_cnt |= PRIORITY_ALWAYS_ON; 1082 } 1083 1084 a.full = dfixed_const(1000); 1085 b.full = dfixed_const(mode->clock); 1086 b.full = dfixed_div(b, a); 1087 c.full = dfixed_const(latency_watermark_a); 1088 c.full = dfixed_mul(c, b); 1089 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 1090 c.full = dfixed_div(c, a); 1091 a.full = dfixed_const(16); 1092 c.full = dfixed_div(c, a); 1093 priority_a_mark = dfixed_trunc(c); 1094 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 1095 1096 a.full = dfixed_const(1000); 1097 b.full = dfixed_const(mode->clock); 1098 b.full = dfixed_div(b, a); 1099 c.full = dfixed_const(latency_watermark_b); 1100 c.full = dfixed_mul(c, b); 1101 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 1102 c.full = dfixed_div(c, a); 1103 a.full = dfixed_const(16); 1104 c.full = dfixed_div(c, a); 1105 priority_b_mark = dfixed_trunc(c); 1106 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 1107 1108 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1109 } 1110 1111 /* select wm A */ 1112 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1113 tmp = arb_control3; 1114 tmp &= ~LATENCY_WATERMARK_MASK(3); 1115 tmp |= LATENCY_WATERMARK_MASK(1); 1116 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1117 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1118 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1119 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1120 /* select wm B */ 1121 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 1122 tmp &= ~LATENCY_WATERMARK_MASK(3); 1123 tmp |= LATENCY_WATERMARK_MASK(2); 1124 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 1125 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 1126 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 1127 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 1128 /* restore original selection */ 1129 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 1130 1131 /* write the priority marks */ 1132 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 1133 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 1134 1135 /* save values for DPM */ 1136 amdgpu_crtc->line_time = line_time; 1137 amdgpu_crtc->wm_high = latency_watermark_a; 1138 1139 /* Save number of lines the linebuffer leads before the scanout */ 1140 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1141 } 1142 1143 /* watermark setup */ 1144 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 1145 struct amdgpu_crtc *amdgpu_crtc, 1146 struct drm_display_mode *mode, 1147 struct drm_display_mode *other_mode) 1148 { 1149 u32 tmp, buffer_alloc, i; 1150 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 1151 /* 1152 * Line Buffer Setup 1153 * There are 3 line buffers, each one shared by 2 display controllers. 1154 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 1155 * the display controllers. The paritioning is done via one of four 1156 * preset allocations specified in bits 21:20: 1157 * 0 - half lb 1158 * 2 - whole lb, other crtc must be disabled 1159 */ 1160 /* this can get tricky if we have two large displays on a paired group 1161 * of crtcs. Ideally for multiple large displays we'd assign them to 1162 * non-linked crtcs for maximum line buffer allocation. 1163 */ 1164 if (amdgpu_crtc->base.enabled && mode) { 1165 if (other_mode) { 1166 tmp = 0; /* 1/2 */ 1167 buffer_alloc = 1; 1168 } else { 1169 tmp = 2; /* whole */ 1170 buffer_alloc = 2; 1171 } 1172 } else { 1173 tmp = 0; 1174 buffer_alloc = 0; 1175 } 1176 1177 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1178 DC_LB_MEMORY_CONFIG(tmp)); 1179 1180 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1181 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1182 for (i = 0; i < adev->usec_timeout; i++) { 1183 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1184 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1185 break; 1186 udelay(1); 1187 } 1188 1189 if (amdgpu_crtc->base.enabled && mode) { 1190 switch (tmp) { 1191 case 0: 1192 default: 1193 return 4096 * 2; 1194 case 2: 1195 return 8192 * 2; 1196 } 1197 } 1198 1199 /* controller not enabled, so no lb used */ 1200 return 0; 1201 } 1202 1203 1204 /** 1205 * 1206 * dce_v6_0_bandwidth_update - program display watermarks 1207 * 1208 * @adev: amdgpu_device pointer 1209 * 1210 * Calculate and program the display watermarks and line 1211 * buffer allocation (CIK). 1212 */ 1213 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1214 { 1215 struct drm_display_mode *mode0 = NULL; 1216 struct drm_display_mode *mode1 = NULL; 1217 u32 num_heads = 0, lb_size; 1218 int i; 1219 1220 if (!adev->mode_info.mode_config_initialized) 1221 return; 1222 1223 amdgpu_update_display_priority(adev); 1224 1225 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1226 if (adev->mode_info.crtcs[i]->base.enabled) 1227 num_heads++; 1228 } 1229 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1230 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1231 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1232 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1233 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1234 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1235 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1236 } 1237 } 1238 1239 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1240 { 1241 int i; 1242 u32 tmp; 1243 1244 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1245 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1246 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1247 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1248 PORT_CONNECTIVITY)) 1249 adev->mode_info.audio.pin[i].connected = false; 1250 else 1251 adev->mode_info.audio.pin[i].connected = true; 1252 } 1253 1254 } 1255 1256 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1257 { 1258 int i; 1259 1260 dce_v6_0_audio_get_connected_pins(adev); 1261 1262 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1263 if (adev->mode_info.audio.pin[i].connected) 1264 return &adev->mode_info.audio.pin[i]; 1265 } 1266 DRM_ERROR("No connected audio pins found!\n"); 1267 return NULL; 1268 } 1269 1270 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1271 { 1272 struct amdgpu_device *adev = encoder->dev->dev_private; 1273 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1274 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1275 1276 if (!dig || !dig->afmt || !dig->afmt->pin) 1277 return; 1278 1279 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1280 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1281 dig->afmt->pin->id)); 1282 } 1283 1284 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1285 struct drm_display_mode *mode) 1286 { 1287 struct amdgpu_device *adev = encoder->dev->dev_private; 1288 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1289 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1290 struct drm_connector *connector; 1291 struct amdgpu_connector *amdgpu_connector = NULL; 1292 int interlace = 0; 1293 u32 tmp; 1294 1295 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1296 if (connector->encoder == encoder) { 1297 amdgpu_connector = to_amdgpu_connector(connector); 1298 break; 1299 } 1300 } 1301 1302 if (!amdgpu_connector) { 1303 DRM_ERROR("Couldn't find encoder's connector\n"); 1304 return; 1305 } 1306 1307 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1308 interlace = 1; 1309 1310 if (connector->latency_present[interlace]) { 1311 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1312 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1313 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1314 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1315 } else { 1316 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1317 VIDEO_LIPSYNC, 0); 1318 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1319 AUDIO_LIPSYNC, 0); 1320 } 1321 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1322 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1323 } 1324 1325 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1326 { 1327 struct amdgpu_device *adev = encoder->dev->dev_private; 1328 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1329 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1330 struct drm_connector *connector; 1331 struct amdgpu_connector *amdgpu_connector = NULL; 1332 u8 *sadb = NULL; 1333 int sad_count; 1334 u32 tmp; 1335 1336 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1337 if (connector->encoder == encoder) { 1338 amdgpu_connector = to_amdgpu_connector(connector); 1339 break; 1340 } 1341 } 1342 1343 if (!amdgpu_connector) { 1344 DRM_ERROR("Couldn't find encoder's connector\n"); 1345 return; 1346 } 1347 1348 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1349 if (sad_count < 0) { 1350 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1351 sad_count = 0; 1352 } 1353 1354 /* program the speaker allocation */ 1355 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1356 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1357 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1358 HDMI_CONNECTION, 0); 1359 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1360 DP_CONNECTION, 0); 1361 1362 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1363 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1364 DP_CONNECTION, 1); 1365 else 1366 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1367 HDMI_CONNECTION, 1); 1368 1369 if (sad_count) 1370 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1371 SPEAKER_ALLOCATION, sadb[0]); 1372 else 1373 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1374 SPEAKER_ALLOCATION, 5); /* stereo */ 1375 1376 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1377 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1378 1379 kfree(sadb); 1380 } 1381 1382 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1383 { 1384 struct amdgpu_device *adev = encoder->dev->dev_private; 1385 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1386 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1387 struct drm_connector *connector; 1388 struct amdgpu_connector *amdgpu_connector = NULL; 1389 struct cea_sad *sads; 1390 int i, sad_count; 1391 1392 static const u16 eld_reg_to_type[][2] = { 1393 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1394 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1395 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1396 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1397 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1398 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1399 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1400 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1401 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1402 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1403 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1404 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1405 }; 1406 1407 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1408 if (connector->encoder == encoder) { 1409 amdgpu_connector = to_amdgpu_connector(connector); 1410 break; 1411 } 1412 } 1413 1414 if (!amdgpu_connector) { 1415 DRM_ERROR("Couldn't find encoder's connector\n"); 1416 return; 1417 } 1418 1419 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1420 if (sad_count <= 0) { 1421 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1422 return; 1423 } 1424 1425 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1426 u32 tmp = 0; 1427 u8 stereo_freqs = 0; 1428 int max_channels = -1; 1429 int j; 1430 1431 for (j = 0; j < sad_count; j++) { 1432 struct cea_sad *sad = &sads[j]; 1433 1434 if (sad->format == eld_reg_to_type[i][1]) { 1435 if (sad->channels > max_channels) { 1436 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1437 MAX_CHANNELS, sad->channels); 1438 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1439 DESCRIPTOR_BYTE_2, sad->byte2); 1440 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1441 SUPPORTED_FREQUENCIES, sad->freq); 1442 max_channels = sad->channels; 1443 } 1444 1445 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1446 stereo_freqs |= sad->freq; 1447 else 1448 break; 1449 } 1450 } 1451 1452 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1453 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1454 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1455 } 1456 1457 kfree(sads); 1458 1459 } 1460 1461 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1462 struct amdgpu_audio_pin *pin, 1463 bool enable) 1464 { 1465 if (!pin) 1466 return; 1467 1468 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1469 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1470 } 1471 1472 static const u32 pin_offsets[7] = 1473 { 1474 (0x1780 - 0x1780), 1475 (0x1786 - 0x1780), 1476 (0x178c - 0x1780), 1477 (0x1792 - 0x1780), 1478 (0x1798 - 0x1780), 1479 (0x179d - 0x1780), 1480 (0x17a4 - 0x1780), 1481 }; 1482 1483 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1484 { 1485 int i; 1486 1487 if (!amdgpu_audio) 1488 return 0; 1489 1490 adev->mode_info.audio.enabled = true; 1491 1492 switch (adev->asic_type) { 1493 case CHIP_TAHITI: 1494 case CHIP_PITCAIRN: 1495 case CHIP_VERDE: 1496 default: 1497 adev->mode_info.audio.num_pins = 6; 1498 break; 1499 case CHIP_OLAND: 1500 adev->mode_info.audio.num_pins = 2; 1501 break; 1502 } 1503 1504 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1505 adev->mode_info.audio.pin[i].channels = -1; 1506 adev->mode_info.audio.pin[i].rate = -1; 1507 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1508 adev->mode_info.audio.pin[i].status_bits = 0; 1509 adev->mode_info.audio.pin[i].category_code = 0; 1510 adev->mode_info.audio.pin[i].connected = false; 1511 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1512 adev->mode_info.audio.pin[i].id = i; 1513 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1514 } 1515 1516 return 0; 1517 } 1518 1519 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1520 { 1521 int i; 1522 1523 if (!amdgpu_audio) 1524 return; 1525 1526 if (!adev->mode_info.audio.enabled) 1527 return; 1528 1529 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1530 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1531 1532 adev->mode_info.audio.enabled = false; 1533 } 1534 1535 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1536 { 1537 struct drm_device *dev = encoder->dev; 1538 struct amdgpu_device *adev = dev->dev_private; 1539 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1540 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1541 u32 tmp; 1542 1543 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1544 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1545 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1546 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1547 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1548 } 1549 1550 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1551 uint32_t clock, int bpc) 1552 { 1553 struct drm_device *dev = encoder->dev; 1554 struct amdgpu_device *adev = dev->dev_private; 1555 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1556 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1557 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1558 u32 tmp; 1559 1560 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1561 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1562 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1563 bpc > 8 ? 0 : 1); 1564 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1565 1566 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1567 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1568 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1569 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1570 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1571 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1572 1573 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1574 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1575 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1576 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1577 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1578 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1579 1580 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1581 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1582 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1583 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1584 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1585 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1586 } 1587 1588 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1589 struct drm_display_mode *mode) 1590 { 1591 struct drm_device *dev = encoder->dev; 1592 struct amdgpu_device *adev = dev->dev_private; 1593 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1594 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1595 struct hdmi_avi_infoframe frame; 1596 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1597 uint8_t *payload = buffer + 3; 1598 uint8_t *header = buffer; 1599 ssize_t err; 1600 u32 tmp; 1601 1602 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1603 if (err < 0) { 1604 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1605 return; 1606 } 1607 1608 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1609 if (err < 0) { 1610 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1611 return; 1612 } 1613 1614 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1615 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1616 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1617 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1618 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1619 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1620 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1621 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1622 1623 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1624 /* anything other than 0 */ 1625 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1626 HDMI_AUDIO_INFO_LINE, 2); 1627 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1628 } 1629 1630 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1631 { 1632 struct drm_device *dev = encoder->dev; 1633 struct amdgpu_device *adev = dev->dev_private; 1634 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1635 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1636 u32 tmp; 1637 1638 /* 1639 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1640 * Express [24MHz / target pixel clock] as an exact rational 1641 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1642 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1643 */ 1644 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1645 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1646 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1647 if (em == ATOM_ENCODER_MODE_HDMI) { 1648 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1649 DCCG_AUDIO_DTO_SEL, 0); 1650 } else if (ENCODER_MODE_IS_DP(em)) { 1651 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1652 DCCG_AUDIO_DTO_SEL, 1); 1653 } 1654 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1655 if (em == ATOM_ENCODER_MODE_HDMI) { 1656 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1657 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1658 } else if (ENCODER_MODE_IS_DP(em)) { 1659 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1660 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1661 } 1662 } 1663 1664 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1665 { 1666 struct drm_device *dev = encoder->dev; 1667 struct amdgpu_device *adev = dev->dev_private; 1668 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1669 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1670 u32 tmp; 1671 1672 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1673 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1674 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1675 1676 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1677 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1678 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1679 1680 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1681 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1682 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1683 1684 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1685 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1686 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1687 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1688 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1689 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1690 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1691 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1692 1693 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1694 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1695 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1696 1697 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1698 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1699 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1700 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1701 1702 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1703 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1704 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1705 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1706 } 1707 1708 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1709 { 1710 struct drm_device *dev = encoder->dev; 1711 struct amdgpu_device *adev = dev->dev_private; 1712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1713 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1714 u32 tmp; 1715 1716 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1717 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1718 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1719 } 1720 1721 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1722 { 1723 struct drm_device *dev = encoder->dev; 1724 struct amdgpu_device *adev = dev->dev_private; 1725 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1726 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1727 u32 tmp; 1728 1729 if (enable) { 1730 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1731 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1732 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1733 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1734 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1735 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1736 1737 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1738 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1739 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1740 1741 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1742 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1743 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1744 } else { 1745 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1746 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1747 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1748 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1749 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1750 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1751 1752 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1753 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1754 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1755 } 1756 } 1757 1758 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1759 { 1760 struct drm_device *dev = encoder->dev; 1761 struct amdgpu_device *adev = dev->dev_private; 1762 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1763 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1764 u32 tmp; 1765 1766 if (enable) { 1767 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1768 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1769 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1770 1771 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1772 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1773 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1774 1775 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1776 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1777 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1778 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1779 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1780 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1781 } else { 1782 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1783 } 1784 } 1785 1786 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1787 struct drm_display_mode *mode) 1788 { 1789 struct drm_device *dev = encoder->dev; 1790 struct amdgpu_device *adev = dev->dev_private; 1791 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1792 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1793 struct drm_connector *connector; 1794 struct amdgpu_connector *amdgpu_connector = NULL; 1795 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1796 int bpc = 8; 1797 1798 if (!dig || !dig->afmt) 1799 return; 1800 1801 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1802 if (connector->encoder == encoder) { 1803 amdgpu_connector = to_amdgpu_connector(connector); 1804 break; 1805 } 1806 } 1807 1808 if (!amdgpu_connector) { 1809 DRM_ERROR("Couldn't find encoder's connector\n"); 1810 return; 1811 } 1812 1813 if (!dig->afmt->enabled) 1814 return; 1815 1816 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1817 if (!dig->afmt->pin) 1818 return; 1819 1820 if (encoder->crtc) { 1821 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1822 bpc = amdgpu_crtc->bpc; 1823 } 1824 1825 /* disable audio before setting up hw */ 1826 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1827 1828 dce_v6_0_audio_set_mute(encoder, true); 1829 dce_v6_0_audio_write_speaker_allocation(encoder); 1830 dce_v6_0_audio_write_sad_regs(encoder); 1831 dce_v6_0_audio_write_latency_fields(encoder, mode); 1832 if (em == ATOM_ENCODER_MODE_HDMI) { 1833 dce_v6_0_audio_set_dto(encoder, mode->clock); 1834 dce_v6_0_audio_set_vbi_packet(encoder); 1835 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1836 } else if (ENCODER_MODE_IS_DP(em)) { 1837 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1838 } 1839 dce_v6_0_audio_set_packet(encoder); 1840 dce_v6_0_audio_select_pin(encoder); 1841 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1842 dce_v6_0_audio_set_mute(encoder, false); 1843 if (em == ATOM_ENCODER_MODE_HDMI) { 1844 dce_v6_0_audio_hdmi_enable(encoder, 1); 1845 } else if (ENCODER_MODE_IS_DP(em)) { 1846 dce_v6_0_audio_dp_enable(encoder, 1); 1847 } 1848 1849 /* enable audio after setting up hw */ 1850 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1851 } 1852 1853 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1854 { 1855 struct drm_device *dev = encoder->dev; 1856 struct amdgpu_device *adev = dev->dev_private; 1857 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1858 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1859 1860 if (!dig || !dig->afmt) 1861 return; 1862 1863 /* Silent, r600_hdmi_enable will raise WARN for us */ 1864 if (enable && dig->afmt->enabled) 1865 return; 1866 1867 if (!enable && !dig->afmt->enabled) 1868 return; 1869 1870 if (!enable && dig->afmt->pin) { 1871 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1872 dig->afmt->pin = NULL; 1873 } 1874 1875 dig->afmt->enabled = enable; 1876 1877 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1878 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1879 } 1880 1881 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1882 { 1883 int i, j; 1884 1885 for (i = 0; i < adev->mode_info.num_dig; i++) 1886 adev->mode_info.afmt[i] = NULL; 1887 1888 /* DCE6 has audio blocks tied to DIG encoders */ 1889 for (i = 0; i < adev->mode_info.num_dig; i++) { 1890 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1891 if (adev->mode_info.afmt[i]) { 1892 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1893 adev->mode_info.afmt[i]->id = i; 1894 } else { 1895 for (j = 0; j < i; j++) { 1896 kfree(adev->mode_info.afmt[j]); 1897 adev->mode_info.afmt[j] = NULL; 1898 } 1899 DRM_ERROR("Out of memory allocating afmt table\n"); 1900 return -ENOMEM; 1901 } 1902 } 1903 return 0; 1904 } 1905 1906 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1907 { 1908 int i; 1909 1910 for (i = 0; i < adev->mode_info.num_dig; i++) { 1911 kfree(adev->mode_info.afmt[i]); 1912 adev->mode_info.afmt[i] = NULL; 1913 } 1914 } 1915 1916 static const u32 vga_control_regs[6] = 1917 { 1918 mmD1VGA_CONTROL, 1919 mmD2VGA_CONTROL, 1920 mmD3VGA_CONTROL, 1921 mmD4VGA_CONTROL, 1922 mmD5VGA_CONTROL, 1923 mmD6VGA_CONTROL, 1924 }; 1925 1926 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1927 { 1928 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1929 struct drm_device *dev = crtc->dev; 1930 struct amdgpu_device *adev = dev->dev_private; 1931 u32 vga_control; 1932 1933 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1934 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1935 } 1936 1937 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1938 { 1939 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1940 struct drm_device *dev = crtc->dev; 1941 struct amdgpu_device *adev = dev->dev_private; 1942 1943 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1944 } 1945 1946 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1947 struct drm_framebuffer *fb, 1948 int x, int y, int atomic) 1949 { 1950 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1951 struct drm_device *dev = crtc->dev; 1952 struct amdgpu_device *adev = dev->dev_private; 1953 struct amdgpu_framebuffer *amdgpu_fb; 1954 struct drm_framebuffer *target_fb; 1955 struct drm_gem_object *obj; 1956 struct amdgpu_bo *abo; 1957 uint64_t fb_location, tiling_flags; 1958 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1959 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1960 u32 viewport_w, viewport_h; 1961 int r; 1962 bool bypass_lut = false; 1963 struct drm_format_name_buf format_name; 1964 1965 /* no fb bound */ 1966 if (!atomic && !crtc->primary->fb) { 1967 DRM_DEBUG_KMS("No FB bound\n"); 1968 return 0; 1969 } 1970 1971 if (atomic) { 1972 amdgpu_fb = to_amdgpu_framebuffer(fb); 1973 target_fb = fb; 1974 } else { 1975 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 1976 target_fb = crtc->primary->fb; 1977 } 1978 1979 /* If atomic, assume fb object is pinned & idle & fenced and 1980 * just update base pointers 1981 */ 1982 obj = amdgpu_fb->obj; 1983 abo = gem_to_amdgpu_bo(obj); 1984 r = amdgpu_bo_reserve(abo, false); 1985 if (unlikely(r != 0)) 1986 return r; 1987 1988 if (atomic) { 1989 fb_location = amdgpu_bo_gpu_offset(abo); 1990 } else { 1991 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1992 if (unlikely(r != 0)) { 1993 amdgpu_bo_unreserve(abo); 1994 return -EINVAL; 1995 } 1996 } 1997 1998 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1999 amdgpu_bo_unreserve(abo); 2000 2001 switch (target_fb->format->format) { 2002 case DRM_FORMAT_C8: 2003 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 2004 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 2005 break; 2006 case DRM_FORMAT_XRGB4444: 2007 case DRM_FORMAT_ARGB4444: 2008 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 2009 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 2010 #ifdef __BIG_ENDIAN 2011 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 2012 #endif 2013 break; 2014 case DRM_FORMAT_XRGB1555: 2015 case DRM_FORMAT_ARGB1555: 2016 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 2017 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 2018 #ifdef __BIG_ENDIAN 2019 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 2020 #endif 2021 break; 2022 case DRM_FORMAT_BGRX5551: 2023 case DRM_FORMAT_BGRA5551: 2024 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 2025 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 2026 #ifdef __BIG_ENDIAN 2027 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 2028 #endif 2029 break; 2030 case DRM_FORMAT_RGB565: 2031 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 2032 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 2033 #ifdef __BIG_ENDIAN 2034 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 2035 #endif 2036 break; 2037 case DRM_FORMAT_XRGB8888: 2038 case DRM_FORMAT_ARGB8888: 2039 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 2040 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 2041 #ifdef __BIG_ENDIAN 2042 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 2043 #endif 2044 break; 2045 case DRM_FORMAT_XRGB2101010: 2046 case DRM_FORMAT_ARGB2101010: 2047 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 2048 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 2049 #ifdef __BIG_ENDIAN 2050 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 2051 #endif 2052 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2053 bypass_lut = true; 2054 break; 2055 case DRM_FORMAT_BGRX1010102: 2056 case DRM_FORMAT_BGRA1010102: 2057 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 2058 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 2059 #ifdef __BIG_ENDIAN 2060 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 2061 #endif 2062 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2063 bypass_lut = true; 2064 break; 2065 default: 2066 DRM_ERROR("Unsupported screen format %s\n", 2067 drm_get_format_name(target_fb->format->format, &format_name)); 2068 return -EINVAL; 2069 } 2070 2071 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2072 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2073 2074 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2075 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2076 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2077 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2078 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2079 2080 fb_format |= GRPH_NUM_BANKS(num_banks); 2081 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 2082 fb_format |= GRPH_TILE_SPLIT(tile_split); 2083 fb_format |= GRPH_BANK_WIDTH(bankw); 2084 fb_format |= GRPH_BANK_HEIGHT(bankh); 2085 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 2086 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2087 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 2088 } 2089 2090 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2091 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 2092 2093 dce_v6_0_vga_enable(crtc, false); 2094 2095 /* Make sure surface address is updated at vertical blank rather than 2096 * horizontal blank 2097 */ 2098 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 2099 2100 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2101 upper_32_bits(fb_location)); 2102 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2103 upper_32_bits(fb_location)); 2104 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2105 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2106 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2107 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2108 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2109 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2110 2111 /* 2112 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2113 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2114 * retain the full precision throughout the pipeline. 2115 */ 2116 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 2117 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 2118 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 2119 2120 if (bypass_lut) 2121 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2122 2123 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2124 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2125 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2126 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2127 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2128 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2129 2130 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2131 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2132 2133 dce_v6_0_grph_enable(crtc, true); 2134 2135 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2136 target_fb->height); 2137 x &= ~3; 2138 y &= ~1; 2139 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2140 (x << 16) | y); 2141 viewport_w = crtc->mode.hdisplay; 2142 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2143 2144 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2145 (viewport_w << 16) | viewport_h); 2146 2147 /* set pageflip to happen anywhere in vblank interval */ 2148 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2149 2150 if (!atomic && fb && fb != crtc->primary->fb) { 2151 amdgpu_fb = to_amdgpu_framebuffer(fb); 2152 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2153 r = amdgpu_bo_reserve(abo, true); 2154 if (unlikely(r != 0)) 2155 return r; 2156 amdgpu_bo_unpin(abo); 2157 amdgpu_bo_unreserve(abo); 2158 } 2159 2160 /* Bytes per pixel may have changed */ 2161 dce_v6_0_bandwidth_update(adev); 2162 2163 return 0; 2164 2165 } 2166 2167 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2168 struct drm_display_mode *mode) 2169 { 2170 struct drm_device *dev = crtc->dev; 2171 struct amdgpu_device *adev = dev->dev_private; 2172 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2173 2174 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2175 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2176 INTERLEAVE_EN); 2177 else 2178 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2179 } 2180 2181 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2182 { 2183 2184 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2185 struct drm_device *dev = crtc->dev; 2186 struct amdgpu_device *adev = dev->dev_private; 2187 int i; 2188 2189 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2190 2191 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2192 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2193 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2194 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2195 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2196 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2197 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2198 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2199 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2200 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2201 2202 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2203 2204 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2205 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2206 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2207 2208 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2209 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2210 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2211 2212 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2213 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2214 2215 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2216 for (i = 0; i < 256; i++) { 2217 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2218 (amdgpu_crtc->lut_r[i] << 20) | 2219 (amdgpu_crtc->lut_g[i] << 10) | 2220 (amdgpu_crtc->lut_b[i] << 0)); 2221 } 2222 2223 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2224 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2225 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2226 ICON_DEGAMMA_MODE(0) | 2227 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2228 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2229 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2230 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2231 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2232 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2233 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2234 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2235 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2236 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2237 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2238 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2239 2240 2241 } 2242 2243 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2244 { 2245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2246 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2247 2248 switch (amdgpu_encoder->encoder_id) { 2249 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2250 return dig->linkb ? 1 : 0; 2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2252 return dig->linkb ? 3 : 2; 2253 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2254 return dig->linkb ? 5 : 4; 2255 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2256 return 6; 2257 default: 2258 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2259 return 0; 2260 } 2261 } 2262 2263 /** 2264 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2265 * 2266 * @crtc: drm crtc 2267 * 2268 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2269 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2270 * monitors a dedicated PPLL must be used. If a particular board has 2271 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2272 * as there is no need to program the PLL itself. If we are not able to 2273 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2274 * avoid messing up an existing monitor. 2275 * 2276 * 2277 */ 2278 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2279 { 2280 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2281 struct drm_device *dev = crtc->dev; 2282 struct amdgpu_device *adev = dev->dev_private; 2283 u32 pll_in_use; 2284 int pll; 2285 2286 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2287 if (adev->clock.dp_extclk) 2288 /* skip PPLL programming if using ext clock */ 2289 return ATOM_PPLL_INVALID; 2290 else 2291 return ATOM_PPLL0; 2292 } else { 2293 /* use the same PPLL for all monitors with the same clock */ 2294 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2295 if (pll != ATOM_PPLL_INVALID) 2296 return pll; 2297 } 2298 2299 /* PPLL1, and PPLL2 */ 2300 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2301 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2302 return ATOM_PPLL2; 2303 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2304 return ATOM_PPLL1; 2305 DRM_ERROR("unable to allocate a PPLL\n"); 2306 return ATOM_PPLL_INVALID; 2307 } 2308 2309 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2310 { 2311 struct amdgpu_device *adev = crtc->dev->dev_private; 2312 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2313 uint32_t cur_lock; 2314 2315 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2316 if (lock) 2317 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2318 else 2319 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2320 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2321 } 2322 2323 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2324 { 2325 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2326 struct amdgpu_device *adev = crtc->dev->dev_private; 2327 2328 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2329 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2330 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2331 2332 2333 } 2334 2335 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2336 { 2337 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2338 struct amdgpu_device *adev = crtc->dev->dev_private; 2339 2340 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2341 upper_32_bits(amdgpu_crtc->cursor_addr)); 2342 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2343 lower_32_bits(amdgpu_crtc->cursor_addr)); 2344 2345 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2346 CUR_CONTROL__CURSOR_EN_MASK | 2347 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2348 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2349 2350 } 2351 2352 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2353 int x, int y) 2354 { 2355 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2356 struct amdgpu_device *adev = crtc->dev->dev_private; 2357 int xorigin = 0, yorigin = 0; 2358 2359 int w = amdgpu_crtc->cursor_width; 2360 2361 amdgpu_crtc->cursor_x = x; 2362 amdgpu_crtc->cursor_y = y; 2363 2364 /* avivo cursor are offset into the total surface */ 2365 x += crtc->x; 2366 y += crtc->y; 2367 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2368 2369 if (x < 0) { 2370 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2371 x = 0; 2372 } 2373 if (y < 0) { 2374 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2375 y = 0; 2376 } 2377 2378 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2379 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2380 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2381 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2382 2383 return 0; 2384 } 2385 2386 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2387 int x, int y) 2388 { 2389 int ret; 2390 2391 dce_v6_0_lock_cursor(crtc, true); 2392 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2393 dce_v6_0_lock_cursor(crtc, false); 2394 2395 return ret; 2396 } 2397 2398 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2399 struct drm_file *file_priv, 2400 uint32_t handle, 2401 uint32_t width, 2402 uint32_t height, 2403 int32_t hot_x, 2404 int32_t hot_y) 2405 { 2406 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2407 struct drm_gem_object *obj; 2408 struct amdgpu_bo *aobj; 2409 int ret; 2410 2411 if (!handle) { 2412 /* turn off cursor */ 2413 dce_v6_0_hide_cursor(crtc); 2414 obj = NULL; 2415 goto unpin; 2416 } 2417 2418 if ((width > amdgpu_crtc->max_cursor_width) || 2419 (height > amdgpu_crtc->max_cursor_height)) { 2420 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2421 return -EINVAL; 2422 } 2423 2424 obj = drm_gem_object_lookup(file_priv, handle); 2425 if (!obj) { 2426 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2427 return -ENOENT; 2428 } 2429 2430 aobj = gem_to_amdgpu_bo(obj); 2431 ret = amdgpu_bo_reserve(aobj, false); 2432 if (ret != 0) { 2433 drm_gem_object_unreference_unlocked(obj); 2434 return ret; 2435 } 2436 2437 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2438 amdgpu_bo_unreserve(aobj); 2439 if (ret) { 2440 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2441 drm_gem_object_unreference_unlocked(obj); 2442 return ret; 2443 } 2444 2445 dce_v6_0_lock_cursor(crtc, true); 2446 2447 if (width != amdgpu_crtc->cursor_width || 2448 height != amdgpu_crtc->cursor_height || 2449 hot_x != amdgpu_crtc->cursor_hot_x || 2450 hot_y != amdgpu_crtc->cursor_hot_y) { 2451 int x, y; 2452 2453 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2454 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2455 2456 dce_v6_0_cursor_move_locked(crtc, x, y); 2457 2458 amdgpu_crtc->cursor_width = width; 2459 amdgpu_crtc->cursor_height = height; 2460 amdgpu_crtc->cursor_hot_x = hot_x; 2461 amdgpu_crtc->cursor_hot_y = hot_y; 2462 } 2463 2464 dce_v6_0_show_cursor(crtc); 2465 dce_v6_0_lock_cursor(crtc, false); 2466 2467 unpin: 2468 if (amdgpu_crtc->cursor_bo) { 2469 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2470 ret = amdgpu_bo_reserve(aobj, true); 2471 if (likely(ret == 0)) { 2472 amdgpu_bo_unpin(aobj); 2473 amdgpu_bo_unreserve(aobj); 2474 } 2475 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2476 } 2477 2478 amdgpu_crtc->cursor_bo = obj; 2479 return 0; 2480 } 2481 2482 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2483 { 2484 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2485 2486 if (amdgpu_crtc->cursor_bo) { 2487 dce_v6_0_lock_cursor(crtc, true); 2488 2489 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2490 amdgpu_crtc->cursor_y); 2491 2492 dce_v6_0_show_cursor(crtc); 2493 dce_v6_0_lock_cursor(crtc, false); 2494 } 2495 } 2496 2497 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2498 u16 *blue, uint32_t size, 2499 struct drm_modeset_acquire_ctx *ctx) 2500 { 2501 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2502 int i; 2503 2504 /* userspace palettes are always correct as is */ 2505 for (i = 0; i < size; i++) { 2506 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2507 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2508 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2509 } 2510 dce_v6_0_crtc_load_lut(crtc); 2511 2512 return 0; 2513 } 2514 2515 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2516 { 2517 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2518 2519 drm_crtc_cleanup(crtc); 2520 kfree(amdgpu_crtc); 2521 } 2522 2523 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2524 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2525 .cursor_move = dce_v6_0_crtc_cursor_move, 2526 .gamma_set = dce_v6_0_crtc_gamma_set, 2527 .set_config = amdgpu_crtc_set_config, 2528 .destroy = dce_v6_0_crtc_destroy, 2529 .page_flip_target = amdgpu_crtc_page_flip_target, 2530 }; 2531 2532 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2533 { 2534 struct drm_device *dev = crtc->dev; 2535 struct amdgpu_device *adev = dev->dev_private; 2536 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2537 unsigned type; 2538 2539 switch (mode) { 2540 case DRM_MODE_DPMS_ON: 2541 amdgpu_crtc->enabled = true; 2542 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2543 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2544 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2545 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2546 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2547 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2548 drm_crtc_vblank_on(crtc); 2549 dce_v6_0_crtc_load_lut(crtc); 2550 break; 2551 case DRM_MODE_DPMS_STANDBY: 2552 case DRM_MODE_DPMS_SUSPEND: 2553 case DRM_MODE_DPMS_OFF: 2554 drm_crtc_vblank_off(crtc); 2555 if (amdgpu_crtc->enabled) 2556 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2557 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2558 amdgpu_crtc->enabled = false; 2559 break; 2560 } 2561 /* adjust pm to dpms */ 2562 amdgpu_pm_compute_clocks(adev); 2563 } 2564 2565 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2566 { 2567 /* disable crtc pair power gating before programming */ 2568 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2569 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2570 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2571 } 2572 2573 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2574 { 2575 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2576 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2577 } 2578 2579 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2580 { 2581 2582 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2583 struct drm_device *dev = crtc->dev; 2584 struct amdgpu_device *adev = dev->dev_private; 2585 struct amdgpu_atom_ss ss; 2586 int i; 2587 2588 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2589 if (crtc->primary->fb) { 2590 int r; 2591 struct amdgpu_framebuffer *amdgpu_fb; 2592 struct amdgpu_bo *abo; 2593 2594 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2595 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2596 r = amdgpu_bo_reserve(abo, true); 2597 if (unlikely(r)) 2598 DRM_ERROR("failed to reserve abo before unpin\n"); 2599 else { 2600 amdgpu_bo_unpin(abo); 2601 amdgpu_bo_unreserve(abo); 2602 } 2603 } 2604 /* disable the GRPH */ 2605 dce_v6_0_grph_enable(crtc, false); 2606 2607 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2608 2609 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2610 if (adev->mode_info.crtcs[i] && 2611 adev->mode_info.crtcs[i]->enabled && 2612 i != amdgpu_crtc->crtc_id && 2613 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2614 /* one other crtc is using this pll don't turn 2615 * off the pll 2616 */ 2617 goto done; 2618 } 2619 } 2620 2621 switch (amdgpu_crtc->pll_id) { 2622 case ATOM_PPLL1: 2623 case ATOM_PPLL2: 2624 /* disable the ppll */ 2625 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2626 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2627 break; 2628 default: 2629 break; 2630 } 2631 done: 2632 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2633 amdgpu_crtc->adjusted_clock = 0; 2634 amdgpu_crtc->encoder = NULL; 2635 amdgpu_crtc->connector = NULL; 2636 } 2637 2638 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2639 struct drm_display_mode *mode, 2640 struct drm_display_mode *adjusted_mode, 2641 int x, int y, struct drm_framebuffer *old_fb) 2642 { 2643 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2644 2645 if (!amdgpu_crtc->adjusted_clock) 2646 return -EINVAL; 2647 2648 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2649 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2650 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2651 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2652 amdgpu_atombios_crtc_scaler_setup(crtc); 2653 dce_v6_0_cursor_reset(crtc); 2654 /* update the hw version fpr dpm */ 2655 amdgpu_crtc->hw_mode = *adjusted_mode; 2656 2657 return 0; 2658 } 2659 2660 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2661 const struct drm_display_mode *mode, 2662 struct drm_display_mode *adjusted_mode) 2663 { 2664 2665 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2666 struct drm_device *dev = crtc->dev; 2667 struct drm_encoder *encoder; 2668 2669 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2670 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2671 if (encoder->crtc == crtc) { 2672 amdgpu_crtc->encoder = encoder; 2673 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2674 break; 2675 } 2676 } 2677 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2678 amdgpu_crtc->encoder = NULL; 2679 amdgpu_crtc->connector = NULL; 2680 return false; 2681 } 2682 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2683 return false; 2684 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2685 return false; 2686 /* pick pll */ 2687 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2688 /* if we can't get a PPLL for a non-DP encoder, fail */ 2689 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2690 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2691 return false; 2692 2693 return true; 2694 } 2695 2696 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2697 struct drm_framebuffer *old_fb) 2698 { 2699 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2700 } 2701 2702 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2703 struct drm_framebuffer *fb, 2704 int x, int y, enum mode_set_atomic state) 2705 { 2706 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2707 } 2708 2709 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2710 .dpms = dce_v6_0_crtc_dpms, 2711 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2712 .mode_set = dce_v6_0_crtc_mode_set, 2713 .mode_set_base = dce_v6_0_crtc_set_base, 2714 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2715 .prepare = dce_v6_0_crtc_prepare, 2716 .commit = dce_v6_0_crtc_commit, 2717 .load_lut = dce_v6_0_crtc_load_lut, 2718 .disable = dce_v6_0_crtc_disable, 2719 }; 2720 2721 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2722 { 2723 struct amdgpu_crtc *amdgpu_crtc; 2724 int i; 2725 2726 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2727 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2728 if (amdgpu_crtc == NULL) 2729 return -ENOMEM; 2730 2731 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2732 2733 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2734 amdgpu_crtc->crtc_id = index; 2735 adev->mode_info.crtcs[index] = amdgpu_crtc; 2736 2737 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2738 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2739 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2740 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2741 2742 for (i = 0; i < 256; i++) { 2743 amdgpu_crtc->lut_r[i] = i << 2; 2744 amdgpu_crtc->lut_g[i] = i << 2; 2745 amdgpu_crtc->lut_b[i] = i << 2; 2746 } 2747 2748 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2749 2750 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2751 amdgpu_crtc->adjusted_clock = 0; 2752 amdgpu_crtc->encoder = NULL; 2753 amdgpu_crtc->connector = NULL; 2754 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2755 2756 return 0; 2757 } 2758 2759 static int dce_v6_0_early_init(void *handle) 2760 { 2761 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2762 2763 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2764 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2765 2766 dce_v6_0_set_display_funcs(adev); 2767 dce_v6_0_set_irq_funcs(adev); 2768 2769 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2770 2771 switch (adev->asic_type) { 2772 case CHIP_TAHITI: 2773 case CHIP_PITCAIRN: 2774 case CHIP_VERDE: 2775 adev->mode_info.num_hpd = 6; 2776 adev->mode_info.num_dig = 6; 2777 break; 2778 case CHIP_OLAND: 2779 adev->mode_info.num_hpd = 2; 2780 adev->mode_info.num_dig = 2; 2781 break; 2782 default: 2783 return -EINVAL; 2784 } 2785 2786 return 0; 2787 } 2788 2789 static int dce_v6_0_sw_init(void *handle) 2790 { 2791 int r, i; 2792 bool ret; 2793 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2794 2795 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2796 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2797 if (r) 2798 return r; 2799 } 2800 2801 for (i = 8; i < 20; i += 2) { 2802 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2803 if (r) 2804 return r; 2805 } 2806 2807 /* HPD hotplug */ 2808 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2809 if (r) 2810 return r; 2811 2812 adev->mode_info.mode_config_initialized = true; 2813 2814 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2815 adev->ddev->mode_config.async_page_flip = true; 2816 adev->ddev->mode_config.max_width = 16384; 2817 adev->ddev->mode_config.max_height = 16384; 2818 adev->ddev->mode_config.preferred_depth = 24; 2819 adev->ddev->mode_config.prefer_shadow = 1; 2820 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2821 2822 r = amdgpu_modeset_create_props(adev); 2823 if (r) 2824 return r; 2825 2826 adev->ddev->mode_config.max_width = 16384; 2827 adev->ddev->mode_config.max_height = 16384; 2828 2829 /* allocate crtcs */ 2830 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2831 r = dce_v6_0_crtc_init(adev, i); 2832 if (r) 2833 return r; 2834 } 2835 2836 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2837 if (ret) 2838 amdgpu_print_display_setup(adev->ddev); 2839 else 2840 return -EINVAL; 2841 2842 /* setup afmt */ 2843 r = dce_v6_0_afmt_init(adev); 2844 if (r) 2845 return r; 2846 2847 r = dce_v6_0_audio_init(adev); 2848 if (r) 2849 return r; 2850 2851 drm_kms_helper_poll_init(adev->ddev); 2852 2853 return r; 2854 } 2855 2856 static int dce_v6_0_sw_fini(void *handle) 2857 { 2858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2859 2860 kfree(adev->mode_info.bios_hardcoded_edid); 2861 2862 drm_kms_helper_poll_fini(adev->ddev); 2863 2864 dce_v6_0_audio_fini(adev); 2865 dce_v6_0_afmt_fini(adev); 2866 2867 drm_mode_config_cleanup(adev->ddev); 2868 adev->mode_info.mode_config_initialized = false; 2869 2870 return 0; 2871 } 2872 2873 static int dce_v6_0_hw_init(void *handle) 2874 { 2875 int i; 2876 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2877 2878 /* init dig PHYs, disp eng pll */ 2879 amdgpu_atombios_encoder_init_dig(adev); 2880 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2881 2882 /* initialize hpd */ 2883 dce_v6_0_hpd_init(adev); 2884 2885 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2886 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2887 } 2888 2889 dce_v6_0_pageflip_interrupt_init(adev); 2890 2891 return 0; 2892 } 2893 2894 static int dce_v6_0_hw_fini(void *handle) 2895 { 2896 int i; 2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2898 2899 dce_v6_0_hpd_fini(adev); 2900 2901 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2902 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2903 } 2904 2905 dce_v6_0_pageflip_interrupt_fini(adev); 2906 2907 return 0; 2908 } 2909 2910 static int dce_v6_0_suspend(void *handle) 2911 { 2912 return dce_v6_0_hw_fini(handle); 2913 } 2914 2915 static int dce_v6_0_resume(void *handle) 2916 { 2917 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2918 int ret; 2919 2920 ret = dce_v6_0_hw_init(handle); 2921 2922 /* turn on the BL */ 2923 if (adev->mode_info.bl_encoder) { 2924 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2925 adev->mode_info.bl_encoder); 2926 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2927 bl_level); 2928 } 2929 2930 return ret; 2931 } 2932 2933 static bool dce_v6_0_is_idle(void *handle) 2934 { 2935 return true; 2936 } 2937 2938 static int dce_v6_0_wait_for_idle(void *handle) 2939 { 2940 return 0; 2941 } 2942 2943 static int dce_v6_0_soft_reset(void *handle) 2944 { 2945 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); 2946 return 0; 2947 } 2948 2949 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2950 int crtc, 2951 enum amdgpu_interrupt_state state) 2952 { 2953 u32 reg_block, interrupt_mask; 2954 2955 if (crtc >= adev->mode_info.num_crtc) { 2956 DRM_DEBUG("invalid crtc %d\n", crtc); 2957 return; 2958 } 2959 2960 switch (crtc) { 2961 case 0: 2962 reg_block = SI_CRTC0_REGISTER_OFFSET; 2963 break; 2964 case 1: 2965 reg_block = SI_CRTC1_REGISTER_OFFSET; 2966 break; 2967 case 2: 2968 reg_block = SI_CRTC2_REGISTER_OFFSET; 2969 break; 2970 case 3: 2971 reg_block = SI_CRTC3_REGISTER_OFFSET; 2972 break; 2973 case 4: 2974 reg_block = SI_CRTC4_REGISTER_OFFSET; 2975 break; 2976 case 5: 2977 reg_block = SI_CRTC5_REGISTER_OFFSET; 2978 break; 2979 default: 2980 DRM_DEBUG("invalid crtc %d\n", crtc); 2981 return; 2982 } 2983 2984 switch (state) { 2985 case AMDGPU_IRQ_STATE_DISABLE: 2986 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2987 interrupt_mask &= ~VBLANK_INT_MASK; 2988 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2989 break; 2990 case AMDGPU_IRQ_STATE_ENABLE: 2991 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2992 interrupt_mask |= VBLANK_INT_MASK; 2993 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2994 break; 2995 default: 2996 break; 2997 } 2998 } 2999 3000 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3001 int crtc, 3002 enum amdgpu_interrupt_state state) 3003 { 3004 3005 } 3006 3007 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 3008 struct amdgpu_irq_src *src, 3009 unsigned type, 3010 enum amdgpu_interrupt_state state) 3011 { 3012 u32 dc_hpd_int_cntl; 3013 3014 if (type >= adev->mode_info.num_hpd) { 3015 DRM_DEBUG("invalid hdp %d\n", type); 3016 return 0; 3017 } 3018 3019 switch (state) { 3020 case AMDGPU_IRQ_STATE_DISABLE: 3021 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3022 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 3023 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3024 break; 3025 case AMDGPU_IRQ_STATE_ENABLE: 3026 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 3027 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 3028 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 3029 break; 3030 default: 3031 break; 3032 } 3033 3034 return 0; 3035 } 3036 3037 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 3038 struct amdgpu_irq_src *src, 3039 unsigned type, 3040 enum amdgpu_interrupt_state state) 3041 { 3042 switch (type) { 3043 case AMDGPU_CRTC_IRQ_VBLANK1: 3044 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3045 break; 3046 case AMDGPU_CRTC_IRQ_VBLANK2: 3047 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3048 break; 3049 case AMDGPU_CRTC_IRQ_VBLANK3: 3050 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3051 break; 3052 case AMDGPU_CRTC_IRQ_VBLANK4: 3053 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3054 break; 3055 case AMDGPU_CRTC_IRQ_VBLANK5: 3056 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3057 break; 3058 case AMDGPU_CRTC_IRQ_VBLANK6: 3059 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3060 break; 3061 case AMDGPU_CRTC_IRQ_VLINE1: 3062 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 3063 break; 3064 case AMDGPU_CRTC_IRQ_VLINE2: 3065 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 3066 break; 3067 case AMDGPU_CRTC_IRQ_VLINE3: 3068 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 3069 break; 3070 case AMDGPU_CRTC_IRQ_VLINE4: 3071 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 3072 break; 3073 case AMDGPU_CRTC_IRQ_VLINE5: 3074 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 3075 break; 3076 case AMDGPU_CRTC_IRQ_VLINE6: 3077 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 3078 break; 3079 default: 3080 break; 3081 } 3082 return 0; 3083 } 3084 3085 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 3086 struct amdgpu_irq_src *source, 3087 struct amdgpu_iv_entry *entry) 3088 { 3089 unsigned crtc = entry->src_id - 1; 3090 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3091 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3092 3093 switch (entry->src_data[0]) { 3094 case 0: /* vblank */ 3095 if (disp_int & interrupt_status_offsets[crtc].vblank) 3096 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 3097 else 3098 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3099 3100 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3101 drm_handle_vblank(adev->ddev, crtc); 3102 } 3103 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3104 break; 3105 case 1: /* vline */ 3106 if (disp_int & interrupt_status_offsets[crtc].vline) 3107 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 3108 else 3109 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3110 3111 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3112 break; 3113 default: 3114 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3115 break; 3116 } 3117 3118 return 0; 3119 } 3120 3121 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 3122 struct amdgpu_irq_src *src, 3123 unsigned type, 3124 enum amdgpu_interrupt_state state) 3125 { 3126 u32 reg; 3127 3128 if (type >= adev->mode_info.num_crtc) { 3129 DRM_ERROR("invalid pageflip crtc %d\n", type); 3130 return -EINVAL; 3131 } 3132 3133 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3134 if (state == AMDGPU_IRQ_STATE_DISABLE) 3135 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3136 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3137 else 3138 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3139 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3140 3141 return 0; 3142 } 3143 3144 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 3145 struct amdgpu_irq_src *source, 3146 struct amdgpu_iv_entry *entry) 3147 { 3148 unsigned long flags; 3149 unsigned crtc_id; 3150 struct amdgpu_crtc *amdgpu_crtc; 3151 struct amdgpu_flip_work *works; 3152 3153 crtc_id = (entry->src_id - 8) >> 1; 3154 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3155 3156 if (crtc_id >= adev->mode_info.num_crtc) { 3157 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3158 return -EINVAL; 3159 } 3160 3161 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3162 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3163 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3164 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3165 3166 /* IRQ could occur when in initial stage */ 3167 if (amdgpu_crtc == NULL) 3168 return 0; 3169 3170 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3171 works = amdgpu_crtc->pflip_works; 3172 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3173 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3174 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3175 amdgpu_crtc->pflip_status, 3176 AMDGPU_FLIP_SUBMITTED); 3177 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3178 return 0; 3179 } 3180 3181 /* page flip completed. clean up */ 3182 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3183 amdgpu_crtc->pflip_works = NULL; 3184 3185 /* wakeup usersapce */ 3186 if (works->event) 3187 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3188 3189 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3190 3191 drm_crtc_vblank_put(&amdgpu_crtc->base); 3192 schedule_work(&works->unpin_work); 3193 3194 return 0; 3195 } 3196 3197 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3198 struct amdgpu_irq_src *source, 3199 struct amdgpu_iv_entry *entry) 3200 { 3201 uint32_t disp_int, mask, tmp; 3202 unsigned hpd; 3203 3204 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3205 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3206 return 0; 3207 } 3208 3209 hpd = entry->src_data[0]; 3210 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3211 mask = interrupt_status_offsets[hpd].hpd; 3212 3213 if (disp_int & mask) { 3214 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 3215 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3216 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 3217 schedule_work(&adev->hotplug_work); 3218 DRM_INFO("IH: HPD%d\n", hpd + 1); 3219 } 3220 3221 return 0; 3222 3223 } 3224 3225 static int dce_v6_0_set_clockgating_state(void *handle, 3226 enum amd_clockgating_state state) 3227 { 3228 return 0; 3229 } 3230 3231 static int dce_v6_0_set_powergating_state(void *handle, 3232 enum amd_powergating_state state) 3233 { 3234 return 0; 3235 } 3236 3237 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3238 .name = "dce_v6_0", 3239 .early_init = dce_v6_0_early_init, 3240 .late_init = NULL, 3241 .sw_init = dce_v6_0_sw_init, 3242 .sw_fini = dce_v6_0_sw_fini, 3243 .hw_init = dce_v6_0_hw_init, 3244 .hw_fini = dce_v6_0_hw_fini, 3245 .suspend = dce_v6_0_suspend, 3246 .resume = dce_v6_0_resume, 3247 .is_idle = dce_v6_0_is_idle, 3248 .wait_for_idle = dce_v6_0_wait_for_idle, 3249 .soft_reset = dce_v6_0_soft_reset, 3250 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3251 .set_powergating_state = dce_v6_0_set_powergating_state, 3252 }; 3253 3254 static void 3255 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3256 struct drm_display_mode *mode, 3257 struct drm_display_mode *adjusted_mode) 3258 { 3259 3260 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3261 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3262 3263 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3264 3265 /* need to call this here rather than in prepare() since we need some crtc info */ 3266 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3267 3268 /* set scaler clears this on some chips */ 3269 dce_v6_0_set_interleave(encoder->crtc, mode); 3270 3271 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3272 dce_v6_0_afmt_enable(encoder, true); 3273 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3274 } 3275 } 3276 3277 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3278 { 3279 3280 struct amdgpu_device *adev = encoder->dev->dev_private; 3281 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3282 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3283 3284 if ((amdgpu_encoder->active_device & 3285 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3286 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3287 ENCODER_OBJECT_ID_NONE)) { 3288 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3289 if (dig) { 3290 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3291 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3292 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3293 } 3294 } 3295 3296 amdgpu_atombios_scratch_regs_lock(adev, true); 3297 3298 if (connector) { 3299 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3300 3301 /* select the clock/data port if it uses a router */ 3302 if (amdgpu_connector->router.cd_valid) 3303 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3304 3305 /* turn eDP panel on for mode set */ 3306 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3307 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3308 ATOM_TRANSMITTER_ACTION_POWER_ON); 3309 } 3310 3311 /* this is needed for the pll/ss setup to work correctly in some cases */ 3312 amdgpu_atombios_encoder_set_crtc_source(encoder); 3313 /* set up the FMT blocks */ 3314 dce_v6_0_program_fmt(encoder); 3315 } 3316 3317 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3318 { 3319 3320 struct drm_device *dev = encoder->dev; 3321 struct amdgpu_device *adev = dev->dev_private; 3322 3323 /* need to call this here as we need the crtc set up */ 3324 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3325 amdgpu_atombios_scratch_regs_lock(adev, false); 3326 } 3327 3328 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3329 { 3330 3331 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3332 struct amdgpu_encoder_atom_dig *dig; 3333 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3334 3335 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3336 3337 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3338 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3339 dce_v6_0_afmt_enable(encoder, false); 3340 dig = amdgpu_encoder->enc_priv; 3341 dig->dig_encoder = -1; 3342 } 3343 amdgpu_encoder->active_device = 0; 3344 } 3345 3346 /* these are handled by the primary encoders */ 3347 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3348 { 3349 3350 } 3351 3352 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3353 { 3354 3355 } 3356 3357 static void 3358 dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3359 struct drm_display_mode *mode, 3360 struct drm_display_mode *adjusted_mode) 3361 { 3362 3363 } 3364 3365 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3366 { 3367 3368 } 3369 3370 static void 3371 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3372 { 3373 3374 } 3375 3376 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3377 const struct drm_display_mode *mode, 3378 struct drm_display_mode *adjusted_mode) 3379 { 3380 return true; 3381 } 3382 3383 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3384 .dpms = dce_v6_0_ext_dpms, 3385 .mode_fixup = dce_v6_0_ext_mode_fixup, 3386 .prepare = dce_v6_0_ext_prepare, 3387 .mode_set = dce_v6_0_ext_mode_set, 3388 .commit = dce_v6_0_ext_commit, 3389 .disable = dce_v6_0_ext_disable, 3390 /* no detect for TMDS/LVDS yet */ 3391 }; 3392 3393 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3394 .dpms = amdgpu_atombios_encoder_dpms, 3395 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3396 .prepare = dce_v6_0_encoder_prepare, 3397 .mode_set = dce_v6_0_encoder_mode_set, 3398 .commit = dce_v6_0_encoder_commit, 3399 .disable = dce_v6_0_encoder_disable, 3400 .detect = amdgpu_atombios_encoder_dig_detect, 3401 }; 3402 3403 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3404 .dpms = amdgpu_atombios_encoder_dpms, 3405 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3406 .prepare = dce_v6_0_encoder_prepare, 3407 .mode_set = dce_v6_0_encoder_mode_set, 3408 .commit = dce_v6_0_encoder_commit, 3409 .detect = amdgpu_atombios_encoder_dac_detect, 3410 }; 3411 3412 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3413 { 3414 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3415 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3416 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3417 kfree(amdgpu_encoder->enc_priv); 3418 drm_encoder_cleanup(encoder); 3419 kfree(amdgpu_encoder); 3420 } 3421 3422 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3423 .destroy = dce_v6_0_encoder_destroy, 3424 }; 3425 3426 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3427 uint32_t encoder_enum, 3428 uint32_t supported_device, 3429 u16 caps) 3430 { 3431 struct drm_device *dev = adev->ddev; 3432 struct drm_encoder *encoder; 3433 struct amdgpu_encoder *amdgpu_encoder; 3434 3435 /* see if we already added it */ 3436 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3437 amdgpu_encoder = to_amdgpu_encoder(encoder); 3438 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3439 amdgpu_encoder->devices |= supported_device; 3440 return; 3441 } 3442 3443 } 3444 3445 /* add a new one */ 3446 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3447 if (!amdgpu_encoder) 3448 return; 3449 3450 encoder = &amdgpu_encoder->base; 3451 switch (adev->mode_info.num_crtc) { 3452 case 1: 3453 encoder->possible_crtcs = 0x1; 3454 break; 3455 case 2: 3456 default: 3457 encoder->possible_crtcs = 0x3; 3458 break; 3459 case 4: 3460 encoder->possible_crtcs = 0xf; 3461 break; 3462 case 6: 3463 encoder->possible_crtcs = 0x3f; 3464 break; 3465 } 3466 3467 amdgpu_encoder->enc_priv = NULL; 3468 amdgpu_encoder->encoder_enum = encoder_enum; 3469 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3470 amdgpu_encoder->devices = supported_device; 3471 amdgpu_encoder->rmx_type = RMX_OFF; 3472 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3473 amdgpu_encoder->is_ext_encoder = false; 3474 amdgpu_encoder->caps = caps; 3475 3476 switch (amdgpu_encoder->encoder_id) { 3477 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3478 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3479 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3480 DRM_MODE_ENCODER_DAC, NULL); 3481 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3482 break; 3483 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3484 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3485 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3486 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3487 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3488 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3489 amdgpu_encoder->rmx_type = RMX_FULL; 3490 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3491 DRM_MODE_ENCODER_LVDS, NULL); 3492 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3493 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3494 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3495 DRM_MODE_ENCODER_DAC, NULL); 3496 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3497 } else { 3498 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3499 DRM_MODE_ENCODER_TMDS, NULL); 3500 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3501 } 3502 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3503 break; 3504 case ENCODER_OBJECT_ID_SI170B: 3505 case ENCODER_OBJECT_ID_CH7303: 3506 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3507 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3508 case ENCODER_OBJECT_ID_TITFP513: 3509 case ENCODER_OBJECT_ID_VT1623: 3510 case ENCODER_OBJECT_ID_HDMI_SI1930: 3511 case ENCODER_OBJECT_ID_TRAVIS: 3512 case ENCODER_OBJECT_ID_NUTMEG: 3513 /* these are handled by the primary encoders */ 3514 amdgpu_encoder->is_ext_encoder = true; 3515 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3516 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3517 DRM_MODE_ENCODER_LVDS, NULL); 3518 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3519 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3520 DRM_MODE_ENCODER_DAC, NULL); 3521 else 3522 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3523 DRM_MODE_ENCODER_TMDS, NULL); 3524 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3525 break; 3526 } 3527 } 3528 3529 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3530 .set_vga_render_state = &dce_v6_0_set_vga_render_state, 3531 .bandwidth_update = &dce_v6_0_bandwidth_update, 3532 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3533 .vblank_wait = &dce_v6_0_vblank_wait, 3534 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3535 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3536 .hpd_sense = &dce_v6_0_hpd_sense, 3537 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3538 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3539 .page_flip = &dce_v6_0_page_flip, 3540 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3541 .add_encoder = &dce_v6_0_encoder_add, 3542 .add_connector = &amdgpu_connector_add, 3543 .stop_mc_access = &dce_v6_0_stop_mc_access, 3544 .resume_mc_access = &dce_v6_0_resume_mc_access, 3545 }; 3546 3547 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3548 { 3549 if (adev->mode_info.funcs == NULL) 3550 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3551 } 3552 3553 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3554 .set = dce_v6_0_set_crtc_interrupt_state, 3555 .process = dce_v6_0_crtc_irq, 3556 }; 3557 3558 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3559 .set = dce_v6_0_set_pageflip_interrupt_state, 3560 .process = dce_v6_0_pageflip_irq, 3561 }; 3562 3563 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3564 .set = dce_v6_0_set_hpd_interrupt_state, 3565 .process = dce_v6_0_hpd_irq, 3566 }; 3567 3568 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3569 { 3570 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3571 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3572 3573 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3574 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3575 3576 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3577 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3578 } 3579 3580 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3581 { 3582 .type = AMD_IP_BLOCK_TYPE_DCE, 3583 .major = 6, 3584 .minor = 0, 3585 .rev = 0, 3586 .funcs = &dce_v6_0_ip_funcs, 3587 }; 3588 3589 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3590 { 3591 .type = AMD_IP_BLOCK_TYPE_DCE, 3592 .major = 6, 3593 .minor = 4, 3594 .rev = 0, 3595 .funcs = &dce_v6_0_ip_funcs, 3596 }; 3597