1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "atom.h" 28 #include "amdgpu_atombios.h" 29 #include "atombios_crtc.h" 30 #include "atombios_encoders.h" 31 #include "amdgpu_pll.h" 32 #include "amdgpu_connectors.h" 33 #include "amdgpu_display.h" 34 35 #include "bif/bif_3_0_d.h" 36 #include "bif/bif_3_0_sh_mask.h" 37 #include "oss/oss_1_0_d.h" 38 #include "oss/oss_1_0_sh_mask.h" 39 #include "gca/gfx_6_0_d.h" 40 #include "gca/gfx_6_0_sh_mask.h" 41 #include "gmc/gmc_6_0_d.h" 42 #include "gmc/gmc_6_0_sh_mask.h" 43 #include "dce/dce_6_0_d.h" 44 #include "dce/dce_6_0_sh_mask.h" 45 #include "gca/gfx_7_2_enum.h" 46 #include "dce_v6_0.h" 47 #include "si_enums.h" 48 49 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev); 50 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev); 51 52 static const u32 crtc_offsets[6] = 53 { 54 SI_CRTC0_REGISTER_OFFSET, 55 SI_CRTC1_REGISTER_OFFSET, 56 SI_CRTC2_REGISTER_OFFSET, 57 SI_CRTC3_REGISTER_OFFSET, 58 SI_CRTC4_REGISTER_OFFSET, 59 SI_CRTC5_REGISTER_OFFSET 60 }; 61 62 static const u32 hpd_offsets[] = 63 { 64 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS, 65 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS, 66 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS, 67 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS, 68 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS, 69 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS, 70 }; 71 72 static const uint32_t dig_offsets[] = { 73 SI_CRTC0_REGISTER_OFFSET, 74 SI_CRTC1_REGISTER_OFFSET, 75 SI_CRTC2_REGISTER_OFFSET, 76 SI_CRTC3_REGISTER_OFFSET, 77 SI_CRTC4_REGISTER_OFFSET, 78 SI_CRTC5_REGISTER_OFFSET, 79 (0x13830 - 0x7030) >> 2, 80 }; 81 82 static const struct { 83 uint32_t reg; 84 uint32_t vblank; 85 uint32_t vline; 86 uint32_t hpd; 87 88 } interrupt_status_offsets[6] = { { 89 .reg = mmDISP_INTERRUPT_STATUS, 90 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 91 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 92 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 93 }, { 94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 96 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 98 }, { 99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 101 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 103 }, { 104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 113 }, { 114 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 115 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 116 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 117 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 118 } }; 119 120 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev, 121 u32 block_offset, u32 reg) 122 { 123 unsigned long flags; 124 u32 r; 125 126 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 127 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 128 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 129 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 130 131 return r; 132 } 133 134 static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev, 135 u32 block_offset, u32 reg, u32 v) 136 { 137 unsigned long flags; 138 139 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 140 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, 141 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK); 142 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 143 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 144 } 145 146 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 147 { 148 if (crtc >= adev->mode_info.num_crtc) 149 return 0; 150 else 151 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 152 } 153 154 static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev) 155 { 156 unsigned i; 157 158 /* Enable pflip interrupts */ 159 for (i = 0; i < adev->mode_info.num_crtc; i++) 160 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 161 } 162 163 static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 164 { 165 unsigned i; 166 167 /* Disable pflip interrupts */ 168 for (i = 0; i < adev->mode_info.num_crtc; i++) 169 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 170 } 171 172 /** 173 * dce_v6_0_page_flip - pageflip callback. 174 * 175 * @adev: amdgpu_device pointer 176 * @crtc_id: crtc to cleanup pageflip on 177 * @crtc_base: new address of the crtc (GPU MC address) 178 * 179 * Does the actual pageflip (evergreen+). 180 * During vblank we take the crtc lock and wait for the update_pending 181 * bit to go high, when it does, we release the lock, and allow the 182 * double buffered update to take place. 183 * Returns the current update pending status. 184 */ 185 static void dce_v6_0_page_flip(struct amdgpu_device *adev, 186 int crtc_id, u64 crtc_base, bool async) 187 { 188 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 189 190 /* flip at hsync for async, default is vsync */ 191 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? 192 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); 193 /* update the scanout addresses */ 194 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 195 upper_32_bits(crtc_base)); 196 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 197 (u32)crtc_base); 198 199 /* post the write */ 200 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 201 } 202 203 static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 204 u32 *vbl, u32 *position) 205 { 206 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 207 return -EINVAL; 208 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 209 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 210 211 return 0; 212 213 } 214 215 /** 216 * dce_v6_0_hpd_sense - hpd sense callback. 217 * 218 * @adev: amdgpu_device pointer 219 * @hpd: hpd (hotplug detect) pin 220 * 221 * Checks if a digital monitor is connected (evergreen+). 222 * Returns true if connected, false if not connected. 223 */ 224 static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev, 225 enum amdgpu_hpd_id hpd) 226 { 227 bool connected = false; 228 229 if (hpd >= adev->mode_info.num_hpd) 230 return connected; 231 232 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK) 233 connected = true; 234 235 return connected; 236 } 237 238 /** 239 * dce_v6_0_hpd_set_polarity - hpd set polarity callback. 240 * 241 * @adev: amdgpu_device pointer 242 * @hpd: hpd (hotplug detect) pin 243 * 244 * Set the polarity of the hpd pin (evergreen+). 245 */ 246 static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev, 247 enum amdgpu_hpd_id hpd) 248 { 249 u32 tmp; 250 bool connected = dce_v6_0_hpd_sense(adev, hpd); 251 252 if (hpd >= adev->mode_info.num_hpd) 253 return; 254 255 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 256 if (connected) 257 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 258 else 259 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK; 260 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 261 } 262 263 /** 264 * dce_v6_0_hpd_init - hpd setup callback. 265 * 266 * @adev: amdgpu_device pointer 267 * 268 * Setup the hpd pins used by the card (evergreen+). 269 * Enable the pin, set the polarity, and enable the hpd interrupts. 270 */ 271 static void dce_v6_0_hpd_init(struct amdgpu_device *adev) 272 { 273 struct drm_device *dev = adev->ddev; 274 struct drm_connector *connector; 275 u32 tmp; 276 277 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 278 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 279 280 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 281 continue; 282 283 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 284 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 285 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 286 287 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 288 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 289 /* don't try to enable hpd on eDP or LVDS avoid breaking the 290 * aux dp channel on imac and help (but not completely fix) 291 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 292 * also avoid interrupt storms during dpms. 293 */ 294 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 295 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK; 296 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 297 continue; 298 } 299 300 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 301 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 302 } 303 304 } 305 306 /** 307 * dce_v6_0_hpd_fini - hpd tear down callback. 308 * 309 * @adev: amdgpu_device pointer 310 * 311 * Tear down the hpd pins used by the card (evergreen+). 312 * Disable the hpd interrupts. 313 */ 314 static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) 315 { 316 struct drm_device *dev = adev->ddev; 317 struct drm_connector *connector; 318 u32 tmp; 319 320 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 321 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 322 323 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 324 continue; 325 326 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 327 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK; 328 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0); 329 330 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 331 } 332 } 333 334 static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 335 { 336 return mmDC_GPIO_HPD_A; 337 } 338 339 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev, 340 bool render) 341 { 342 if (!render) 343 WREG32(mmVGA_RENDER_CONTROL, 344 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL); 345 346 } 347 348 static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev) 349 { 350 switch (adev->asic_type) { 351 case CHIP_TAHITI: 352 case CHIP_PITCAIRN: 353 case CHIP_VERDE: 354 return 6; 355 case CHIP_OLAND: 356 return 2; 357 default: 358 return 0; 359 } 360 } 361 362 void dce_v6_0_disable_dce(struct amdgpu_device *adev) 363 { 364 /*Disable VGA render and enabled crtc, if has DCE engine*/ 365 if (amdgpu_atombios_has_dce_engine_info(adev)) { 366 u32 tmp; 367 int crtc_enabled, i; 368 369 dce_v6_0_set_vga_render_state(adev, false); 370 371 /*Disable crtc*/ 372 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) { 373 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & 374 CRTC_CONTROL__CRTC_MASTER_EN_MASK; 375 if (crtc_enabled) { 376 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 377 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 378 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK; 379 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 380 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 381 } 382 } 383 } 384 } 385 386 static void dce_v6_0_program_fmt(struct drm_encoder *encoder) 387 { 388 389 struct drm_device *dev = encoder->dev; 390 struct amdgpu_device *adev = dev->dev_private; 391 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 392 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 393 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 394 int bpc = 0; 395 u32 tmp = 0; 396 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 397 398 if (connector) { 399 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 400 bpc = amdgpu_connector_get_monitor_bpc(connector); 401 dither = amdgpu_connector->dither; 402 } 403 404 /* LVDS FMT is set up by atom */ 405 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 406 return; 407 408 if (bpc == 0) 409 return; 410 411 412 switch (bpc) { 413 case 6: 414 if (dither == AMDGPU_FMT_DITHER_ENABLE) 415 /* XXX sort out optimal dither settings */ 416 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 417 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 418 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK); 419 else 420 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK; 421 break; 422 case 8: 423 if (dither == AMDGPU_FMT_DITHER_ENABLE) 424 /* XXX sort out optimal dither settings */ 425 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK | 426 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK | 427 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK | 428 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK | 429 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK); 430 else 431 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK | 432 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK); 433 break; 434 case 10: 435 default: 436 /* not needed */ 437 break; 438 } 439 440 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 441 } 442 443 /** 444 * cik_get_number_of_dram_channels - get the number of dram channels 445 * 446 * @adev: amdgpu_device pointer 447 * 448 * Look up the number of video ram channels (CIK). 449 * Used for display watermark bandwidth calculations 450 * Returns the number of dram channels 451 */ 452 static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev) 453 { 454 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 455 456 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) { 457 case 0: 458 default: 459 return 1; 460 case 1: 461 return 2; 462 case 2: 463 return 4; 464 case 3: 465 return 8; 466 case 4: 467 return 3; 468 case 5: 469 return 6; 470 case 6: 471 return 10; 472 case 7: 473 return 12; 474 case 8: 475 return 16; 476 } 477 } 478 479 struct dce6_wm_params { 480 u32 dram_channels; /* number of dram channels */ 481 u32 yclk; /* bandwidth per dram data pin in kHz */ 482 u32 sclk; /* engine clock in kHz */ 483 u32 disp_clk; /* display clock in kHz */ 484 u32 src_width; /* viewport width */ 485 u32 active_time; /* active display time in ns */ 486 u32 blank_time; /* blank time in ns */ 487 bool interlaced; /* mode is interlaced */ 488 fixed20_12 vsc; /* vertical scale ratio */ 489 u32 num_heads; /* number of active crtcs */ 490 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 491 u32 lb_size; /* line buffer allocated to pipe */ 492 u32 vtaps; /* vertical scaler taps */ 493 }; 494 495 /** 496 * dce_v6_0_dram_bandwidth - get the dram bandwidth 497 * 498 * @wm: watermark calculation data 499 * 500 * Calculate the raw dram bandwidth (CIK). 501 * Used for display watermark bandwidth calculations 502 * Returns the dram bandwidth in MBytes/s 503 */ 504 static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) 505 { 506 /* Calculate raw DRAM Bandwidth */ 507 fixed20_12 dram_efficiency; /* 0.7 */ 508 fixed20_12 yclk, dram_channels, bandwidth; 509 fixed20_12 a; 510 511 a.full = dfixed_const(1000); 512 yclk.full = dfixed_const(wm->yclk); 513 yclk.full = dfixed_div(yclk, a); 514 dram_channels.full = dfixed_const(wm->dram_channels * 4); 515 a.full = dfixed_const(10); 516 dram_efficiency.full = dfixed_const(7); 517 dram_efficiency.full = dfixed_div(dram_efficiency, a); 518 bandwidth.full = dfixed_mul(dram_channels, yclk); 519 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 520 521 return dfixed_trunc(bandwidth); 522 } 523 524 /** 525 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display 526 * 527 * @wm: watermark calculation data 528 * 529 * Calculate the dram bandwidth used for display (CIK). 530 * Used for display watermark bandwidth calculations 531 * Returns the dram bandwidth for display in MBytes/s 532 */ 533 static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) 534 { 535 /* Calculate DRAM Bandwidth and the part allocated to display. */ 536 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 537 fixed20_12 yclk, dram_channels, bandwidth; 538 fixed20_12 a; 539 540 a.full = dfixed_const(1000); 541 yclk.full = dfixed_const(wm->yclk); 542 yclk.full = dfixed_div(yclk, a); 543 dram_channels.full = dfixed_const(wm->dram_channels * 4); 544 a.full = dfixed_const(10); 545 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 546 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 547 bandwidth.full = dfixed_mul(dram_channels, yclk); 548 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 549 550 return dfixed_trunc(bandwidth); 551 } 552 553 /** 554 * dce_v6_0_data_return_bandwidth - get the data return bandwidth 555 * 556 * @wm: watermark calculation data 557 * 558 * Calculate the data return bandwidth used for display (CIK). 559 * Used for display watermark bandwidth calculations 560 * Returns the data return bandwidth in MBytes/s 561 */ 562 static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) 563 { 564 /* Calculate the display Data return Bandwidth */ 565 fixed20_12 return_efficiency; /* 0.8 */ 566 fixed20_12 sclk, bandwidth; 567 fixed20_12 a; 568 569 a.full = dfixed_const(1000); 570 sclk.full = dfixed_const(wm->sclk); 571 sclk.full = dfixed_div(sclk, a); 572 a.full = dfixed_const(10); 573 return_efficiency.full = dfixed_const(8); 574 return_efficiency.full = dfixed_div(return_efficiency, a); 575 a.full = dfixed_const(32); 576 bandwidth.full = dfixed_mul(a, sclk); 577 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 578 579 return dfixed_trunc(bandwidth); 580 } 581 582 /** 583 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth 584 * 585 * @wm: watermark calculation data 586 * 587 * Calculate the dmif bandwidth used for display (CIK). 588 * Used for display watermark bandwidth calculations 589 * Returns the dmif bandwidth in MBytes/s 590 */ 591 static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) 592 { 593 /* Calculate the DMIF Request Bandwidth */ 594 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 595 fixed20_12 disp_clk, bandwidth; 596 fixed20_12 a, b; 597 598 a.full = dfixed_const(1000); 599 disp_clk.full = dfixed_const(wm->disp_clk); 600 disp_clk.full = dfixed_div(disp_clk, a); 601 a.full = dfixed_const(32); 602 b.full = dfixed_mul(a, disp_clk); 603 604 a.full = dfixed_const(10); 605 disp_clk_request_efficiency.full = dfixed_const(8); 606 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 607 608 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 609 610 return dfixed_trunc(bandwidth); 611 } 612 613 /** 614 * dce_v6_0_available_bandwidth - get the min available bandwidth 615 * 616 * @wm: watermark calculation data 617 * 618 * Calculate the min available bandwidth used for display (CIK). 619 * Used for display watermark bandwidth calculations 620 * Returns the min available bandwidth in MBytes/s 621 */ 622 static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) 623 { 624 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 625 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); 626 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); 627 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); 628 629 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 630 } 631 632 /** 633 * dce_v6_0_average_bandwidth - get the average available bandwidth 634 * 635 * @wm: watermark calculation data 636 * 637 * Calculate the average available bandwidth used for display (CIK). 638 * Used for display watermark bandwidth calculations 639 * Returns the average available bandwidth in MBytes/s 640 */ 641 static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) 642 { 643 /* Calculate the display mode Average Bandwidth 644 * DisplayMode should contain the source and destination dimensions, 645 * timing, etc. 646 */ 647 fixed20_12 bpp; 648 fixed20_12 line_time; 649 fixed20_12 src_width; 650 fixed20_12 bandwidth; 651 fixed20_12 a; 652 653 a.full = dfixed_const(1000); 654 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 655 line_time.full = dfixed_div(line_time, a); 656 bpp.full = dfixed_const(wm->bytes_per_pixel); 657 src_width.full = dfixed_const(wm->src_width); 658 bandwidth.full = dfixed_mul(src_width, bpp); 659 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 660 bandwidth.full = dfixed_div(bandwidth, line_time); 661 662 return dfixed_trunc(bandwidth); 663 } 664 665 /** 666 * dce_v6_0_latency_watermark - get the latency watermark 667 * 668 * @wm: watermark calculation data 669 * 670 * Calculate the latency watermark (CIK). 671 * Used for display watermark bandwidth calculations 672 * Returns the latency watermark in ns 673 */ 674 static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) 675 { 676 /* First calculate the latency in ns */ 677 u32 mc_latency = 2000; /* 2000 ns. */ 678 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); 679 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 680 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 681 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 682 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 683 (wm->num_heads * cursor_line_pair_return_time); 684 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 685 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 686 u32 tmp, dmif_size = 12288; 687 fixed20_12 a, b, c; 688 689 if (wm->num_heads == 0) 690 return 0; 691 692 a.full = dfixed_const(2); 693 b.full = dfixed_const(1); 694 if ((wm->vsc.full > a.full) || 695 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 696 (wm->vtaps >= 5) || 697 ((wm->vsc.full >= a.full) && wm->interlaced)) 698 max_src_lines_per_dst_line = 4; 699 else 700 max_src_lines_per_dst_line = 2; 701 702 a.full = dfixed_const(available_bandwidth); 703 b.full = dfixed_const(wm->num_heads); 704 a.full = dfixed_div(a, b); 705 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 706 tmp = min(dfixed_trunc(a), tmp); 707 708 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 709 710 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 711 b.full = dfixed_const(1000); 712 c.full = dfixed_const(lb_fill_bw); 713 b.full = dfixed_div(c, b); 714 a.full = dfixed_div(a, b); 715 line_fill_time = dfixed_trunc(a); 716 717 if (line_fill_time < wm->active_time) 718 return latency; 719 else 720 return latency + (line_fill_time - wm->active_time); 721 722 } 723 724 /** 725 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check 726 * average and available dram bandwidth 727 * 728 * @wm: watermark calculation data 729 * 730 * Check if the display average bandwidth fits in the display 731 * dram bandwidth (CIK). 732 * Used for display watermark bandwidth calculations 733 * Returns true if the display fits, false if not. 734 */ 735 static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) 736 { 737 if (dce_v6_0_average_bandwidth(wm) <= 738 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 739 return true; 740 else 741 return false; 742 } 743 744 /** 745 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check 746 * average and available bandwidth 747 * 748 * @wm: watermark calculation data 749 * 750 * Check if the display average bandwidth fits in the display 751 * available bandwidth (CIK). 752 * Used for display watermark bandwidth calculations 753 * Returns true if the display fits, false if not. 754 */ 755 static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) 756 { 757 if (dce_v6_0_average_bandwidth(wm) <= 758 (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) 759 return true; 760 else 761 return false; 762 } 763 764 /** 765 * dce_v6_0_check_latency_hiding - check latency hiding 766 * 767 * @wm: watermark calculation data 768 * 769 * Check latency hiding (CIK). 770 * Used for display watermark bandwidth calculations 771 * Returns true if the display fits, false if not. 772 */ 773 static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) 774 { 775 u32 lb_partitions = wm->lb_size / wm->src_width; 776 u32 line_time = wm->active_time + wm->blank_time; 777 u32 latency_tolerant_lines; 778 u32 latency_hiding; 779 fixed20_12 a; 780 781 a.full = dfixed_const(1); 782 if (wm->vsc.full > a.full) 783 latency_tolerant_lines = 1; 784 else { 785 if (lb_partitions <= (wm->vtaps + 1)) 786 latency_tolerant_lines = 1; 787 else 788 latency_tolerant_lines = 2; 789 } 790 791 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 792 793 if (dce_v6_0_latency_watermark(wm) <= latency_hiding) 794 return true; 795 else 796 return false; 797 } 798 799 /** 800 * dce_v6_0_program_watermarks - program display watermarks 801 * 802 * @adev: amdgpu_device pointer 803 * @amdgpu_crtc: the selected display controller 804 * @lb_size: line buffer size 805 * @num_heads: number of display controllers in use 806 * 807 * Calculate and program the display watermarks for the 808 * selected display controller (CIK). 809 */ 810 static void dce_v6_0_program_watermarks(struct amdgpu_device *adev, 811 struct amdgpu_crtc *amdgpu_crtc, 812 u32 lb_size, u32 num_heads) 813 { 814 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 815 struct dce6_wm_params wm_low, wm_high; 816 u32 dram_channels; 817 u32 active_time; 818 u32 line_time = 0; 819 u32 latency_watermark_a = 0, latency_watermark_b = 0; 820 u32 priority_a_mark = 0, priority_b_mark = 0; 821 u32 priority_a_cnt = PRIORITY_OFF; 822 u32 priority_b_cnt = PRIORITY_OFF; 823 u32 tmp, arb_control3, lb_vblank_lead_lines = 0; 824 fixed20_12 a, b, c; 825 826 if (amdgpu_crtc->base.enabled && num_heads && mode) { 827 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 828 (u32)mode->clock); 829 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 830 (u32)mode->clock); 831 line_time = min(line_time, (u32)65535); 832 priority_a_cnt = 0; 833 priority_b_cnt = 0; 834 835 dram_channels = si_get_number_of_dram_channels(adev); 836 837 /* watermark for high clocks */ 838 if (adev->pm.dpm_enabled) { 839 wm_high.yclk = 840 amdgpu_dpm_get_mclk(adev, false) * 10; 841 wm_high.sclk = 842 amdgpu_dpm_get_sclk(adev, false) * 10; 843 } else { 844 wm_high.yclk = adev->pm.current_mclk * 10; 845 wm_high.sclk = adev->pm.current_sclk * 10; 846 } 847 848 wm_high.disp_clk = mode->clock; 849 wm_high.src_width = mode->crtc_hdisplay; 850 wm_high.active_time = active_time; 851 wm_high.blank_time = line_time - wm_high.active_time; 852 wm_high.interlaced = false; 853 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 854 wm_high.interlaced = true; 855 wm_high.vsc = amdgpu_crtc->vsc; 856 wm_high.vtaps = 1; 857 if (amdgpu_crtc->rmx_type != RMX_OFF) 858 wm_high.vtaps = 2; 859 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 860 wm_high.lb_size = lb_size; 861 wm_high.dram_channels = dram_channels; 862 wm_high.num_heads = num_heads; 863 864 if (adev->pm.dpm_enabled) { 865 /* watermark for low clocks */ 866 wm_low.yclk = 867 amdgpu_dpm_get_mclk(adev, true) * 10; 868 wm_low.sclk = 869 amdgpu_dpm_get_sclk(adev, true) * 10; 870 } else { 871 wm_low.yclk = adev->pm.current_mclk * 10; 872 wm_low.sclk = adev->pm.current_sclk * 10; 873 } 874 875 wm_low.disp_clk = mode->clock; 876 wm_low.src_width = mode->crtc_hdisplay; 877 wm_low.active_time = active_time; 878 wm_low.blank_time = line_time - wm_low.active_time; 879 wm_low.interlaced = false; 880 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 881 wm_low.interlaced = true; 882 wm_low.vsc = amdgpu_crtc->vsc; 883 wm_low.vtaps = 1; 884 if (amdgpu_crtc->rmx_type != RMX_OFF) 885 wm_low.vtaps = 2; 886 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 887 wm_low.lb_size = lb_size; 888 wm_low.dram_channels = dram_channels; 889 wm_low.num_heads = num_heads; 890 891 /* set for high clocks */ 892 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535); 893 /* set for low clocks */ 894 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535); 895 896 /* possibly force display priority to high */ 897 /* should really do this at mode validation time... */ 898 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 899 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 900 !dce_v6_0_check_latency_hiding(&wm_high) || 901 (adev->mode_info.disp_priority == 2)) { 902 DRM_DEBUG_KMS("force priority to high\n"); 903 priority_a_cnt |= PRIORITY_ALWAYS_ON; 904 priority_b_cnt |= PRIORITY_ALWAYS_ON; 905 } 906 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 907 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 908 !dce_v6_0_check_latency_hiding(&wm_low) || 909 (adev->mode_info.disp_priority == 2)) { 910 DRM_DEBUG_KMS("force priority to high\n"); 911 priority_a_cnt |= PRIORITY_ALWAYS_ON; 912 priority_b_cnt |= PRIORITY_ALWAYS_ON; 913 } 914 915 a.full = dfixed_const(1000); 916 b.full = dfixed_const(mode->clock); 917 b.full = dfixed_div(b, a); 918 c.full = dfixed_const(latency_watermark_a); 919 c.full = dfixed_mul(c, b); 920 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 921 c.full = dfixed_div(c, a); 922 a.full = dfixed_const(16); 923 c.full = dfixed_div(c, a); 924 priority_a_mark = dfixed_trunc(c); 925 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK; 926 927 a.full = dfixed_const(1000); 928 b.full = dfixed_const(mode->clock); 929 b.full = dfixed_div(b, a); 930 c.full = dfixed_const(latency_watermark_b); 931 c.full = dfixed_mul(c, b); 932 c.full = dfixed_mul(c, amdgpu_crtc->hsc); 933 c.full = dfixed_div(c, a); 934 a.full = dfixed_const(16); 935 c.full = dfixed_div(c, a); 936 priority_b_mark = dfixed_trunc(c); 937 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK; 938 939 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 940 } 941 942 /* select wm A */ 943 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 944 tmp = arb_control3; 945 tmp &= ~LATENCY_WATERMARK_MASK(3); 946 tmp |= LATENCY_WATERMARK_MASK(1); 947 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 948 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 949 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 950 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 951 /* select wm B */ 952 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset); 953 tmp &= ~LATENCY_WATERMARK_MASK(3); 954 tmp |= LATENCY_WATERMARK_MASK(2); 955 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp); 956 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, 957 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) | 958 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT))); 959 /* restore original selection */ 960 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3); 961 962 /* write the priority marks */ 963 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt); 964 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt); 965 966 /* save values for DPM */ 967 amdgpu_crtc->line_time = line_time; 968 amdgpu_crtc->wm_high = latency_watermark_a; 969 970 /* Save number of lines the linebuffer leads before the scanout */ 971 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 972 } 973 974 /* watermark setup */ 975 static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev, 976 struct amdgpu_crtc *amdgpu_crtc, 977 struct drm_display_mode *mode, 978 struct drm_display_mode *other_mode) 979 { 980 u32 tmp, buffer_alloc, i; 981 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; 982 /* 983 * Line Buffer Setup 984 * There are 3 line buffers, each one shared by 2 display controllers. 985 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between 986 * the display controllers. The paritioning is done via one of four 987 * preset allocations specified in bits 21:20: 988 * 0 - half lb 989 * 2 - whole lb, other crtc must be disabled 990 */ 991 /* this can get tricky if we have two large displays on a paired group 992 * of crtcs. Ideally for multiple large displays we'd assign them to 993 * non-linked crtcs for maximum line buffer allocation. 994 */ 995 if (amdgpu_crtc->base.enabled && mode) { 996 if (other_mode) { 997 tmp = 0; /* 1/2 */ 998 buffer_alloc = 1; 999 } else { 1000 tmp = 2; /* whole */ 1001 buffer_alloc = 2; 1002 } 1003 } else { 1004 tmp = 0; 1005 buffer_alloc = 0; 1006 } 1007 1008 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset, 1009 DC_LB_MEMORY_CONFIG(tmp)); 1010 1011 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, 1012 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT)); 1013 for (i = 0; i < adev->usec_timeout; i++) { 1014 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & 1015 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK) 1016 break; 1017 udelay(1); 1018 } 1019 1020 if (amdgpu_crtc->base.enabled && mode) { 1021 switch (tmp) { 1022 case 0: 1023 default: 1024 return 4096 * 2; 1025 case 2: 1026 return 8192 * 2; 1027 } 1028 } 1029 1030 /* controller not enabled, so no lb used */ 1031 return 0; 1032 } 1033 1034 1035 /** 1036 * 1037 * dce_v6_0_bandwidth_update - program display watermarks 1038 * 1039 * @adev: amdgpu_device pointer 1040 * 1041 * Calculate and program the display watermarks and line 1042 * buffer allocation (CIK). 1043 */ 1044 static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev) 1045 { 1046 struct drm_display_mode *mode0 = NULL; 1047 struct drm_display_mode *mode1 = NULL; 1048 u32 num_heads = 0, lb_size; 1049 int i; 1050 1051 if (!adev->mode_info.mode_config_initialized) 1052 return; 1053 1054 amdgpu_display_update_priority(adev); 1055 1056 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1057 if (adev->mode_info.crtcs[i]->base.enabled) 1058 num_heads++; 1059 } 1060 for (i = 0; i < adev->mode_info.num_crtc; i += 2) { 1061 mode0 = &adev->mode_info.crtcs[i]->base.mode; 1062 mode1 = &adev->mode_info.crtcs[i+1]->base.mode; 1063 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1); 1064 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads); 1065 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0); 1066 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads); 1067 } 1068 } 1069 1070 static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev) 1071 { 1072 int i; 1073 u32 tmp; 1074 1075 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1076 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset, 1077 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1078 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 1079 PORT_CONNECTIVITY)) 1080 adev->mode_info.audio.pin[i].connected = false; 1081 else 1082 adev->mode_info.audio.pin[i].connected = true; 1083 } 1084 1085 } 1086 1087 static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev) 1088 { 1089 int i; 1090 1091 dce_v6_0_audio_get_connected_pins(adev); 1092 1093 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1094 if (adev->mode_info.audio.pin[i].connected) 1095 return &adev->mode_info.audio.pin[i]; 1096 } 1097 DRM_ERROR("No connected audio pins found!\n"); 1098 return NULL; 1099 } 1100 1101 static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder) 1102 { 1103 struct amdgpu_device *adev = encoder->dev->dev_private; 1104 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1105 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1106 1107 if (!dig || !dig->afmt || !dig->afmt->pin) 1108 return; 1109 1110 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 1111 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, 1112 dig->afmt->pin->id)); 1113 } 1114 1115 static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, 1116 struct drm_display_mode *mode) 1117 { 1118 struct amdgpu_device *adev = encoder->dev->dev_private; 1119 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1120 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1121 struct drm_connector *connector; 1122 struct amdgpu_connector *amdgpu_connector = NULL; 1123 int interlace = 0; 1124 u32 tmp; 1125 1126 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1127 if (connector->encoder == encoder) { 1128 amdgpu_connector = to_amdgpu_connector(connector); 1129 break; 1130 } 1131 } 1132 1133 if (!amdgpu_connector) { 1134 DRM_ERROR("Couldn't find encoder's connector\n"); 1135 return; 1136 } 1137 1138 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1139 interlace = 1; 1140 1141 if (connector->latency_present[interlace]) { 1142 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1143 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1144 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1145 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1146 } else { 1147 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1148 VIDEO_LIPSYNC, 0); 1149 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1150 AUDIO_LIPSYNC, 0); 1151 } 1152 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1153 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1154 } 1155 1156 static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1157 { 1158 struct amdgpu_device *adev = encoder->dev->dev_private; 1159 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1160 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1161 struct drm_connector *connector; 1162 struct amdgpu_connector *amdgpu_connector = NULL; 1163 u8 *sadb = NULL; 1164 int sad_count; 1165 u32 tmp; 1166 1167 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1168 if (connector->encoder == encoder) { 1169 amdgpu_connector = to_amdgpu_connector(connector); 1170 break; 1171 } 1172 } 1173 1174 if (!amdgpu_connector) { 1175 DRM_ERROR("Couldn't find encoder's connector\n"); 1176 return; 1177 } 1178 1179 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1180 if (sad_count < 0) { 1181 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1182 sad_count = 0; 1183 } 1184 1185 /* program the speaker allocation */ 1186 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1187 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1188 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1189 HDMI_CONNECTION, 0); 1190 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1191 DP_CONNECTION, 0); 1192 1193 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) 1194 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1195 DP_CONNECTION, 1); 1196 else 1197 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1198 HDMI_CONNECTION, 1); 1199 1200 if (sad_count) 1201 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1202 SPEAKER_ALLOCATION, sadb[0]); 1203 else 1204 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1205 SPEAKER_ALLOCATION, 5); /* stereo */ 1206 1207 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1208 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1209 1210 kfree(sadb); 1211 } 1212 1213 static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) 1214 { 1215 struct amdgpu_device *adev = encoder->dev->dev_private; 1216 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1217 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1218 struct drm_connector *connector; 1219 struct amdgpu_connector *amdgpu_connector = NULL; 1220 struct cea_sad *sads; 1221 int i, sad_count; 1222 1223 static const u16 eld_reg_to_type[][2] = { 1224 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1225 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1226 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1227 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1228 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1229 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1230 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1231 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1232 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1233 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1234 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1235 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1236 }; 1237 1238 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1239 if (connector->encoder == encoder) { 1240 amdgpu_connector = to_amdgpu_connector(connector); 1241 break; 1242 } 1243 } 1244 1245 if (!amdgpu_connector) { 1246 DRM_ERROR("Couldn't find encoder's connector\n"); 1247 return; 1248 } 1249 1250 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1251 if (sad_count <= 0) { 1252 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1253 return; 1254 } 1255 1256 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1257 u32 tmp = 0; 1258 u8 stereo_freqs = 0; 1259 int max_channels = -1; 1260 int j; 1261 1262 for (j = 0; j < sad_count; j++) { 1263 struct cea_sad *sad = &sads[j]; 1264 1265 if (sad->format == eld_reg_to_type[i][1]) { 1266 if (sad->channels > max_channels) { 1267 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1268 MAX_CHANNELS, sad->channels); 1269 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1270 DESCRIPTOR_BYTE_2, sad->byte2); 1271 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1272 SUPPORTED_FREQUENCIES, sad->freq); 1273 max_channels = sad->channels; 1274 } 1275 1276 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1277 stereo_freqs |= sad->freq; 1278 else 1279 break; 1280 } 1281 } 1282 1283 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1284 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1285 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1286 } 1287 1288 kfree(sads); 1289 1290 } 1291 1292 static void dce_v6_0_audio_enable(struct amdgpu_device *adev, 1293 struct amdgpu_audio_pin *pin, 1294 bool enable) 1295 { 1296 if (!pin) 1297 return; 1298 1299 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1300 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1301 } 1302 1303 static const u32 pin_offsets[7] = 1304 { 1305 (0x1780 - 0x1780), 1306 (0x1786 - 0x1780), 1307 (0x178c - 0x1780), 1308 (0x1792 - 0x1780), 1309 (0x1798 - 0x1780), 1310 (0x179d - 0x1780), 1311 (0x17a4 - 0x1780), 1312 }; 1313 1314 static int dce_v6_0_audio_init(struct amdgpu_device *adev) 1315 { 1316 int i; 1317 1318 if (!amdgpu_audio) 1319 return 0; 1320 1321 adev->mode_info.audio.enabled = true; 1322 1323 switch (adev->asic_type) { 1324 case CHIP_TAHITI: 1325 case CHIP_PITCAIRN: 1326 case CHIP_VERDE: 1327 default: 1328 adev->mode_info.audio.num_pins = 6; 1329 break; 1330 case CHIP_OLAND: 1331 adev->mode_info.audio.num_pins = 2; 1332 break; 1333 } 1334 1335 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1336 adev->mode_info.audio.pin[i].channels = -1; 1337 adev->mode_info.audio.pin[i].rate = -1; 1338 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1339 adev->mode_info.audio.pin[i].status_bits = 0; 1340 adev->mode_info.audio.pin[i].category_code = 0; 1341 adev->mode_info.audio.pin[i].connected = false; 1342 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1343 adev->mode_info.audio.pin[i].id = i; 1344 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1345 } 1346 1347 return 0; 1348 } 1349 1350 static void dce_v6_0_audio_fini(struct amdgpu_device *adev) 1351 { 1352 int i; 1353 1354 if (!amdgpu_audio) 1355 return; 1356 1357 if (!adev->mode_info.audio.enabled) 1358 return; 1359 1360 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1361 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1362 1363 adev->mode_info.audio.enabled = false; 1364 } 1365 1366 static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder) 1367 { 1368 struct drm_device *dev = encoder->dev; 1369 struct amdgpu_device *adev = dev->dev_private; 1370 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1371 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1372 u32 tmp; 1373 1374 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1375 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1376 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); 1377 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); 1378 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1379 } 1380 1381 static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder, 1382 uint32_t clock, int bpc) 1383 { 1384 struct drm_device *dev = encoder->dev; 1385 struct amdgpu_device *adev = dev->dev_private; 1386 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1387 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1388 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1389 u32 tmp; 1390 1391 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1392 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1393 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1394 bpc > 8 ? 0 : 1); 1395 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1396 1397 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1398 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1399 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1400 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1401 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1402 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1403 1404 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1405 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1406 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1407 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1408 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1409 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1410 1411 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1412 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1413 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1414 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1415 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1416 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1417 } 1418 1419 static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, 1420 struct drm_display_mode *mode) 1421 { 1422 struct drm_device *dev = encoder->dev; 1423 struct amdgpu_device *adev = dev->dev_private; 1424 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1425 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1426 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1427 struct hdmi_avi_infoframe frame; 1428 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1429 uint8_t *payload = buffer + 3; 1430 uint8_t *header = buffer; 1431 ssize_t err; 1432 u32 tmp; 1433 1434 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1435 if (err < 0) { 1436 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1437 return; 1438 } 1439 1440 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1441 if (err < 0) { 1442 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1443 return; 1444 } 1445 1446 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1447 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24)); 1448 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1449 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24)); 1450 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1451 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24)); 1452 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1453 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24)); 1454 1455 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1456 /* anything other than 0 */ 1457 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, 1458 HDMI_AUDIO_INFO_LINE, 2); 1459 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1460 } 1461 1462 static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1463 { 1464 struct drm_device *dev = encoder->dev; 1465 struct amdgpu_device *adev = dev->dev_private; 1466 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1467 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1468 u32 tmp; 1469 1470 /* 1471 * Two dtos: generally use dto0 for hdmi, dto1 for dp. 1472 * Express [24MHz / target pixel clock] as an exact rational 1473 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1474 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1475 */ 1476 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1477 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1478 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id); 1479 if (em == ATOM_ENCODER_MODE_HDMI) { 1480 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1481 DCCG_AUDIO_DTO_SEL, 0); 1482 } else if (ENCODER_MODE_IS_DP(em)) { 1483 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, 1484 DCCG_AUDIO_DTO_SEL, 1); 1485 } 1486 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1487 if (em == ATOM_ENCODER_MODE_HDMI) { 1488 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000); 1489 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock); 1490 } else if (ENCODER_MODE_IS_DP(em)) { 1491 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000); 1492 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock); 1493 } 1494 } 1495 1496 static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder) 1497 { 1498 struct drm_device *dev = encoder->dev; 1499 struct amdgpu_device *adev = dev->dev_private; 1500 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1501 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1502 u32 tmp; 1503 1504 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1505 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1506 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1507 1508 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1509 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1510 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1511 1512 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1513 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1514 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1515 1516 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1517 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1518 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1519 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1520 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1521 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1522 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1523 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1524 1525 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset); 1526 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff); 1527 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp); 1528 1529 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1530 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1531 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1532 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1533 1534 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1535 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1); 1536 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1537 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1538 } 1539 1540 static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute) 1541 { 1542 struct drm_device *dev = encoder->dev; 1543 struct amdgpu_device *adev = dev->dev_private; 1544 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1545 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1546 u32 tmp; 1547 1548 tmp = RREG32(mmHDMI_GC + dig->afmt->offset); 1549 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0); 1550 WREG32(mmHDMI_GC + dig->afmt->offset, tmp); 1551 } 1552 1553 static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable) 1554 { 1555 struct drm_device *dev = encoder->dev; 1556 struct amdgpu_device *adev = dev->dev_private; 1557 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1558 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1559 u32 tmp; 1560 1561 if (enable) { 1562 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1563 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1564 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1565 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1566 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1567 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1568 1569 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1570 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1571 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1572 1573 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1574 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1575 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1576 } else { 1577 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1578 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0); 1579 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0); 1580 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0); 1581 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0); 1582 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1583 1584 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1585 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0); 1586 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1587 } 1588 } 1589 1590 static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable) 1591 { 1592 struct drm_device *dev = encoder->dev; 1593 struct amdgpu_device *adev = dev->dev_private; 1594 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1595 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1596 u32 tmp; 1597 1598 if (enable) { 1599 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1600 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1601 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1602 1603 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset); 1604 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1); 1605 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp); 1606 1607 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset); 1608 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1609 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1); 1610 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1); 1611 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1612 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp); 1613 } else { 1614 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0); 1615 } 1616 } 1617 1618 static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, 1619 struct drm_display_mode *mode) 1620 { 1621 struct drm_device *dev = encoder->dev; 1622 struct amdgpu_device *adev = dev->dev_private; 1623 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1624 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1625 struct drm_connector *connector; 1626 struct amdgpu_connector *amdgpu_connector = NULL; 1627 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 1628 int bpc = 8; 1629 1630 if (!dig || !dig->afmt) 1631 return; 1632 1633 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1634 if (connector->encoder == encoder) { 1635 amdgpu_connector = to_amdgpu_connector(connector); 1636 break; 1637 } 1638 } 1639 1640 if (!amdgpu_connector) { 1641 DRM_ERROR("Couldn't find encoder's connector\n"); 1642 return; 1643 } 1644 1645 if (!dig->afmt->enabled) 1646 return; 1647 1648 dig->afmt->pin = dce_v6_0_audio_get_pin(adev); 1649 if (!dig->afmt->pin) 1650 return; 1651 1652 if (encoder->crtc) { 1653 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1654 bpc = amdgpu_crtc->bpc; 1655 } 1656 1657 /* disable audio before setting up hw */ 1658 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1659 1660 dce_v6_0_audio_set_mute(encoder, true); 1661 dce_v6_0_audio_write_speaker_allocation(encoder); 1662 dce_v6_0_audio_write_sad_regs(encoder); 1663 dce_v6_0_audio_write_latency_fields(encoder, mode); 1664 if (em == ATOM_ENCODER_MODE_HDMI) { 1665 dce_v6_0_audio_set_dto(encoder, mode->clock); 1666 dce_v6_0_audio_set_vbi_packet(encoder); 1667 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc); 1668 } else if (ENCODER_MODE_IS_DP(em)) { 1669 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10); 1670 } 1671 dce_v6_0_audio_set_packet(encoder); 1672 dce_v6_0_audio_select_pin(encoder); 1673 dce_v6_0_audio_set_avi_infoframe(encoder, mode); 1674 dce_v6_0_audio_set_mute(encoder, false); 1675 if (em == ATOM_ENCODER_MODE_HDMI) { 1676 dce_v6_0_audio_hdmi_enable(encoder, 1); 1677 } else if (ENCODER_MODE_IS_DP(em)) { 1678 dce_v6_0_audio_dp_enable(encoder, 1); 1679 } 1680 1681 /* enable audio after setting up hw */ 1682 dce_v6_0_audio_enable(adev, dig->afmt->pin, true); 1683 } 1684 1685 static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1686 { 1687 struct drm_device *dev = encoder->dev; 1688 struct amdgpu_device *adev = dev->dev_private; 1689 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1690 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1691 1692 if (!dig || !dig->afmt) 1693 return; 1694 1695 /* Silent, r600_hdmi_enable will raise WARN for us */ 1696 if (enable && dig->afmt->enabled) 1697 return; 1698 1699 if (!enable && !dig->afmt->enabled) 1700 return; 1701 1702 if (!enable && dig->afmt->pin) { 1703 dce_v6_0_audio_enable(adev, dig->afmt->pin, false); 1704 dig->afmt->pin = NULL; 1705 } 1706 1707 dig->afmt->enabled = enable; 1708 1709 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1710 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1711 } 1712 1713 static int dce_v6_0_afmt_init(struct amdgpu_device *adev) 1714 { 1715 int i, j; 1716 1717 for (i = 0; i < adev->mode_info.num_dig; i++) 1718 adev->mode_info.afmt[i] = NULL; 1719 1720 /* DCE6 has audio blocks tied to DIG encoders */ 1721 for (i = 0; i < adev->mode_info.num_dig; i++) { 1722 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1723 if (adev->mode_info.afmt[i]) { 1724 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1725 adev->mode_info.afmt[i]->id = i; 1726 } else { 1727 for (j = 0; j < i; j++) { 1728 kfree(adev->mode_info.afmt[j]); 1729 adev->mode_info.afmt[j] = NULL; 1730 } 1731 DRM_ERROR("Out of memory allocating afmt table\n"); 1732 return -ENOMEM; 1733 } 1734 } 1735 return 0; 1736 } 1737 1738 static void dce_v6_0_afmt_fini(struct amdgpu_device *adev) 1739 { 1740 int i; 1741 1742 for (i = 0; i < adev->mode_info.num_dig; i++) { 1743 kfree(adev->mode_info.afmt[i]); 1744 adev->mode_info.afmt[i] = NULL; 1745 } 1746 } 1747 1748 static const u32 vga_control_regs[6] = 1749 { 1750 mmD1VGA_CONTROL, 1751 mmD2VGA_CONTROL, 1752 mmD3VGA_CONTROL, 1753 mmD4VGA_CONTROL, 1754 mmD5VGA_CONTROL, 1755 mmD6VGA_CONTROL, 1756 }; 1757 1758 static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable) 1759 { 1760 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1761 struct drm_device *dev = crtc->dev; 1762 struct amdgpu_device *adev = dev->dev_private; 1763 u32 vga_control; 1764 1765 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1766 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0)); 1767 } 1768 1769 static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable) 1770 { 1771 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1772 struct drm_device *dev = crtc->dev; 1773 struct amdgpu_device *adev = dev->dev_private; 1774 1775 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0); 1776 } 1777 1778 static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, 1779 struct drm_framebuffer *fb, 1780 int x, int y, int atomic) 1781 { 1782 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1783 struct drm_device *dev = crtc->dev; 1784 struct amdgpu_device *adev = dev->dev_private; 1785 struct drm_framebuffer *target_fb; 1786 struct drm_gem_object *obj; 1787 struct amdgpu_bo *abo; 1788 uint64_t fb_location, tiling_flags; 1789 uint32_t fb_format, fb_pitch_pixels, pipe_config; 1790 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE); 1791 u32 viewport_w, viewport_h; 1792 int r; 1793 bool bypass_lut = false; 1794 struct drm_format_name_buf format_name; 1795 1796 /* no fb bound */ 1797 if (!atomic && !crtc->primary->fb) { 1798 DRM_DEBUG_KMS("No FB bound\n"); 1799 return 0; 1800 } 1801 1802 if (atomic) 1803 target_fb = fb; 1804 else 1805 target_fb = crtc->primary->fb; 1806 1807 /* If atomic, assume fb object is pinned & idle & fenced and 1808 * just update base pointers 1809 */ 1810 obj = target_fb->obj[0]; 1811 abo = gem_to_amdgpu_bo(obj); 1812 r = amdgpu_bo_reserve(abo, false); 1813 if (unlikely(r != 0)) 1814 return r; 1815 1816 if (!atomic) { 1817 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1818 if (unlikely(r != 0)) { 1819 amdgpu_bo_unreserve(abo); 1820 return -EINVAL; 1821 } 1822 } 1823 fb_location = amdgpu_bo_gpu_offset(abo); 1824 1825 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1826 amdgpu_bo_unreserve(abo); 1827 1828 switch (target_fb->format->format) { 1829 case DRM_FORMAT_C8: 1830 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | 1831 GRPH_FORMAT(GRPH_FORMAT_INDEXED)); 1832 break; 1833 case DRM_FORMAT_XRGB4444: 1834 case DRM_FORMAT_ARGB4444: 1835 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1836 GRPH_FORMAT(GRPH_FORMAT_ARGB4444)); 1837 #ifdef __BIG_ENDIAN 1838 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1839 #endif 1840 break; 1841 case DRM_FORMAT_XRGB1555: 1842 case DRM_FORMAT_ARGB1555: 1843 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1844 GRPH_FORMAT(GRPH_FORMAT_ARGB1555)); 1845 #ifdef __BIG_ENDIAN 1846 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1847 #endif 1848 break; 1849 case DRM_FORMAT_BGRX5551: 1850 case DRM_FORMAT_BGRA5551: 1851 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1852 GRPH_FORMAT(GRPH_FORMAT_BGRA5551)); 1853 #ifdef __BIG_ENDIAN 1854 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1855 #endif 1856 break; 1857 case DRM_FORMAT_RGB565: 1858 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) | 1859 GRPH_FORMAT(GRPH_FORMAT_ARGB565)); 1860 #ifdef __BIG_ENDIAN 1861 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16); 1862 #endif 1863 break; 1864 case DRM_FORMAT_XRGB8888: 1865 case DRM_FORMAT_ARGB8888: 1866 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1867 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1868 #ifdef __BIG_ENDIAN 1869 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1870 #endif 1871 break; 1872 case DRM_FORMAT_XRGB2101010: 1873 case DRM_FORMAT_ARGB2101010: 1874 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1875 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010)); 1876 #ifdef __BIG_ENDIAN 1877 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1878 #endif 1879 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1880 bypass_lut = true; 1881 break; 1882 case DRM_FORMAT_BGRX1010102: 1883 case DRM_FORMAT_BGRA1010102: 1884 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1885 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102)); 1886 #ifdef __BIG_ENDIAN 1887 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1888 #endif 1889 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1890 bypass_lut = true; 1891 break; 1892 case DRM_FORMAT_XBGR8888: 1893 case DRM_FORMAT_ABGR8888: 1894 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | 1895 GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); 1896 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | 1897 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); 1898 #ifdef __BIG_ENDIAN 1899 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); 1900 #endif 1901 break; 1902 default: 1903 DRM_ERROR("Unsupported screen format %s\n", 1904 drm_get_format_name(target_fb->format->format, &format_name)); 1905 return -EINVAL; 1906 } 1907 1908 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1909 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1910 1911 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1912 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1913 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1914 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1915 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1916 1917 fb_format |= GRPH_NUM_BANKS(num_banks); 1918 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1); 1919 fb_format |= GRPH_TILE_SPLIT(tile_split); 1920 fb_format |= GRPH_BANK_WIDTH(bankw); 1921 fb_format |= GRPH_BANK_HEIGHT(bankh); 1922 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect); 1923 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1924 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1); 1925 } 1926 1927 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1928 fb_format |= GRPH_PIPE_CONFIG(pipe_config); 1929 1930 dce_v6_0_vga_enable(crtc, false); 1931 1932 /* Make sure surface address is updated at vertical blank rather than 1933 * horizontal blank 1934 */ 1935 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0); 1936 1937 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1938 upper_32_bits(fb_location)); 1939 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1940 upper_32_bits(fb_location)); 1941 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1942 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1943 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1944 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1945 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1946 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 1947 1948 /* 1949 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1950 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1951 * retain the full precision throughout the pipeline. 1952 */ 1953 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, 1954 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0), 1955 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK); 1956 1957 if (bypass_lut) 1958 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1959 1960 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 1961 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 1962 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 1963 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 1964 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 1965 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 1966 1967 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 1968 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 1969 1970 dce_v6_0_grph_enable(crtc, true); 1971 1972 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 1973 target_fb->height); 1974 x &= ~3; 1975 y &= ~1; 1976 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 1977 (x << 16) | y); 1978 viewport_w = crtc->mode.hdisplay; 1979 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1980 1981 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 1982 (viewport_w << 16) | viewport_h); 1983 1984 /* set pageflip to happen anywhere in vblank interval */ 1985 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 1986 1987 if (!atomic && fb && fb != crtc->primary->fb) { 1988 abo = gem_to_amdgpu_bo(fb->obj[0]); 1989 r = amdgpu_bo_reserve(abo, true); 1990 if (unlikely(r != 0)) 1991 return r; 1992 amdgpu_bo_unpin(abo); 1993 amdgpu_bo_unreserve(abo); 1994 } 1995 1996 /* Bytes per pixel may have changed */ 1997 dce_v6_0_bandwidth_update(adev); 1998 1999 return 0; 2000 2001 } 2002 2003 static void dce_v6_0_set_interleave(struct drm_crtc *crtc, 2004 struct drm_display_mode *mode) 2005 { 2006 struct drm_device *dev = crtc->dev; 2007 struct amdgpu_device *adev = dev->dev_private; 2008 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2009 2010 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2011 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 2012 INTERLEAVE_EN); 2013 else 2014 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0); 2015 } 2016 2017 static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc) 2018 { 2019 2020 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2021 struct drm_device *dev = crtc->dev; 2022 struct amdgpu_device *adev = dev->dev_private; 2023 u16 *r, *g, *b; 2024 int i; 2025 2026 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2027 2028 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2029 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) | 2030 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT))); 2031 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, 2032 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK); 2033 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, 2034 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK); 2035 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2036 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) | 2037 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT))); 2038 2039 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2040 2041 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2042 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2043 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2044 2045 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2046 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2047 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2048 2049 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2050 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2051 2052 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2053 r = crtc->gamma_store; 2054 g = r + crtc->gamma_size; 2055 b = g + crtc->gamma_size; 2056 for (i = 0; i < 256; i++) { 2057 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2058 ((*r++ & 0xffc0) << 14) | 2059 ((*g++ & 0xffc0) << 4) | 2060 (*b++ >> 6)); 2061 } 2062 2063 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2064 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) | 2065 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) | 2066 ICON_DEGAMMA_MODE(0) | 2067 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT))); 2068 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, 2069 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) | 2070 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT))); 2071 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, 2072 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) | 2073 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT))); 2074 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, 2075 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) | 2076 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT))); 2077 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2078 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0); 2079 2080 2081 } 2082 2083 static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder) 2084 { 2085 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2086 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2087 2088 switch (amdgpu_encoder->encoder_id) { 2089 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2090 return dig->linkb ? 1 : 0; 2091 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2092 return dig->linkb ? 3 : 2; 2093 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2094 return dig->linkb ? 5 : 4; 2095 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2096 return 6; 2097 default: 2098 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2099 return 0; 2100 } 2101 } 2102 2103 /** 2104 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc. 2105 * 2106 * @crtc: drm crtc 2107 * 2108 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2109 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2110 * monitors a dedicated PPLL must be used. If a particular board has 2111 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2112 * as there is no need to program the PLL itself. If we are not able to 2113 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2114 * avoid messing up an existing monitor. 2115 * 2116 * 2117 */ 2118 static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc) 2119 { 2120 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2121 struct drm_device *dev = crtc->dev; 2122 struct amdgpu_device *adev = dev->dev_private; 2123 u32 pll_in_use; 2124 int pll; 2125 2126 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2127 if (adev->clock.dp_extclk) 2128 /* skip PPLL programming if using ext clock */ 2129 return ATOM_PPLL_INVALID; 2130 else 2131 return ATOM_PPLL0; 2132 } else { 2133 /* use the same PPLL for all monitors with the same clock */ 2134 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2135 if (pll != ATOM_PPLL_INVALID) 2136 return pll; 2137 } 2138 2139 /* PPLL1, and PPLL2 */ 2140 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2141 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2142 return ATOM_PPLL2; 2143 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2144 return ATOM_PPLL1; 2145 DRM_ERROR("unable to allocate a PPLL\n"); 2146 return ATOM_PPLL_INVALID; 2147 } 2148 2149 static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2150 { 2151 struct amdgpu_device *adev = crtc->dev->dev_private; 2152 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2153 uint32_t cur_lock; 2154 2155 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2156 if (lock) 2157 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2158 else 2159 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK; 2160 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2161 } 2162 2163 static void dce_v6_0_hide_cursor(struct drm_crtc *crtc) 2164 { 2165 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2166 struct amdgpu_device *adev = crtc->dev->dev_private; 2167 2168 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2169 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2170 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2171 2172 2173 } 2174 2175 static void dce_v6_0_show_cursor(struct drm_crtc *crtc) 2176 { 2177 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2178 struct amdgpu_device *adev = crtc->dev->dev_private; 2179 2180 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2181 upper_32_bits(amdgpu_crtc->cursor_addr)); 2182 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2183 lower_32_bits(amdgpu_crtc->cursor_addr)); 2184 2185 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, 2186 CUR_CONTROL__CURSOR_EN_MASK | 2187 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) | 2188 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT)); 2189 2190 } 2191 2192 static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc, 2193 int x, int y) 2194 { 2195 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2196 struct amdgpu_device *adev = crtc->dev->dev_private; 2197 int xorigin = 0, yorigin = 0; 2198 2199 int w = amdgpu_crtc->cursor_width; 2200 2201 amdgpu_crtc->cursor_x = x; 2202 amdgpu_crtc->cursor_y = y; 2203 2204 /* avivo cursor are offset into the total surface */ 2205 x += crtc->x; 2206 y += crtc->y; 2207 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2208 2209 if (x < 0) { 2210 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2211 x = 0; 2212 } 2213 if (y < 0) { 2214 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2215 y = 0; 2216 } 2217 2218 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2219 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2220 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2221 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2222 2223 return 0; 2224 } 2225 2226 static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc, 2227 int x, int y) 2228 { 2229 int ret; 2230 2231 dce_v6_0_lock_cursor(crtc, true); 2232 ret = dce_v6_0_cursor_move_locked(crtc, x, y); 2233 dce_v6_0_lock_cursor(crtc, false); 2234 2235 return ret; 2236 } 2237 2238 static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, 2239 struct drm_file *file_priv, 2240 uint32_t handle, 2241 uint32_t width, 2242 uint32_t height, 2243 int32_t hot_x, 2244 int32_t hot_y) 2245 { 2246 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2247 struct drm_gem_object *obj; 2248 struct amdgpu_bo *aobj; 2249 int ret; 2250 2251 if (!handle) { 2252 /* turn off cursor */ 2253 dce_v6_0_hide_cursor(crtc); 2254 obj = NULL; 2255 goto unpin; 2256 } 2257 2258 if ((width > amdgpu_crtc->max_cursor_width) || 2259 (height > amdgpu_crtc->max_cursor_height)) { 2260 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2261 return -EINVAL; 2262 } 2263 2264 obj = drm_gem_object_lookup(file_priv, handle); 2265 if (!obj) { 2266 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2267 return -ENOENT; 2268 } 2269 2270 aobj = gem_to_amdgpu_bo(obj); 2271 ret = amdgpu_bo_reserve(aobj, false); 2272 if (ret != 0) { 2273 drm_gem_object_put_unlocked(obj); 2274 return ret; 2275 } 2276 2277 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2278 amdgpu_bo_unreserve(aobj); 2279 if (ret) { 2280 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2281 drm_gem_object_put_unlocked(obj); 2282 return ret; 2283 } 2284 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2285 2286 dce_v6_0_lock_cursor(crtc, true); 2287 2288 if (width != amdgpu_crtc->cursor_width || 2289 height != amdgpu_crtc->cursor_height || 2290 hot_x != amdgpu_crtc->cursor_hot_x || 2291 hot_y != amdgpu_crtc->cursor_hot_y) { 2292 int x, y; 2293 2294 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2295 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2296 2297 dce_v6_0_cursor_move_locked(crtc, x, y); 2298 2299 amdgpu_crtc->cursor_width = width; 2300 amdgpu_crtc->cursor_height = height; 2301 amdgpu_crtc->cursor_hot_x = hot_x; 2302 amdgpu_crtc->cursor_hot_y = hot_y; 2303 } 2304 2305 dce_v6_0_show_cursor(crtc); 2306 dce_v6_0_lock_cursor(crtc, false); 2307 2308 unpin: 2309 if (amdgpu_crtc->cursor_bo) { 2310 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2311 ret = amdgpu_bo_reserve(aobj, true); 2312 if (likely(ret == 0)) { 2313 amdgpu_bo_unpin(aobj); 2314 amdgpu_bo_unreserve(aobj); 2315 } 2316 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); 2317 } 2318 2319 amdgpu_crtc->cursor_bo = obj; 2320 return 0; 2321 } 2322 2323 static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) 2324 { 2325 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2326 2327 if (amdgpu_crtc->cursor_bo) { 2328 dce_v6_0_lock_cursor(crtc, true); 2329 2330 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2331 amdgpu_crtc->cursor_y); 2332 2333 dce_v6_0_show_cursor(crtc); 2334 dce_v6_0_lock_cursor(crtc, false); 2335 } 2336 } 2337 2338 static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2339 u16 *blue, uint32_t size, 2340 struct drm_modeset_acquire_ctx *ctx) 2341 { 2342 dce_v6_0_crtc_load_lut(crtc); 2343 2344 return 0; 2345 } 2346 2347 static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) 2348 { 2349 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2350 2351 drm_crtc_cleanup(crtc); 2352 kfree(amdgpu_crtc); 2353 } 2354 2355 static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { 2356 .cursor_set2 = dce_v6_0_crtc_cursor_set2, 2357 .cursor_move = dce_v6_0_crtc_cursor_move, 2358 .gamma_set = dce_v6_0_crtc_gamma_set, 2359 .set_config = amdgpu_display_crtc_set_config, 2360 .destroy = dce_v6_0_crtc_destroy, 2361 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2362 }; 2363 2364 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2365 { 2366 struct drm_device *dev = crtc->dev; 2367 struct amdgpu_device *adev = dev->dev_private; 2368 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2369 unsigned type; 2370 2371 switch (mode) { 2372 case DRM_MODE_DPMS_ON: 2373 amdgpu_crtc->enabled = true; 2374 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2375 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2376 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2377 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2378 amdgpu_crtc->crtc_id); 2379 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2380 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2381 drm_crtc_vblank_on(crtc); 2382 dce_v6_0_crtc_load_lut(crtc); 2383 break; 2384 case DRM_MODE_DPMS_STANDBY: 2385 case DRM_MODE_DPMS_SUSPEND: 2386 case DRM_MODE_DPMS_OFF: 2387 drm_crtc_vblank_off(crtc); 2388 if (amdgpu_crtc->enabled) 2389 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2390 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2391 amdgpu_crtc->enabled = false; 2392 break; 2393 } 2394 /* adjust pm to dpms */ 2395 amdgpu_pm_compute_clocks(adev); 2396 } 2397 2398 static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc) 2399 { 2400 /* disable crtc pair power gating before programming */ 2401 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2402 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2403 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2404 } 2405 2406 static void dce_v6_0_crtc_commit(struct drm_crtc *crtc) 2407 { 2408 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2409 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2410 } 2411 2412 static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) 2413 { 2414 2415 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2416 struct drm_device *dev = crtc->dev; 2417 struct amdgpu_device *adev = dev->dev_private; 2418 struct amdgpu_atom_ss ss; 2419 int i; 2420 2421 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2422 if (crtc->primary->fb) { 2423 int r; 2424 struct amdgpu_bo *abo; 2425 2426 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2427 r = amdgpu_bo_reserve(abo, true); 2428 if (unlikely(r)) 2429 DRM_ERROR("failed to reserve abo before unpin\n"); 2430 else { 2431 amdgpu_bo_unpin(abo); 2432 amdgpu_bo_unreserve(abo); 2433 } 2434 } 2435 /* disable the GRPH */ 2436 dce_v6_0_grph_enable(crtc, false); 2437 2438 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2439 2440 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2441 if (adev->mode_info.crtcs[i] && 2442 adev->mode_info.crtcs[i]->enabled && 2443 i != amdgpu_crtc->crtc_id && 2444 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2445 /* one other crtc is using this pll don't turn 2446 * off the pll 2447 */ 2448 goto done; 2449 } 2450 } 2451 2452 switch (amdgpu_crtc->pll_id) { 2453 case ATOM_PPLL1: 2454 case ATOM_PPLL2: 2455 /* disable the ppll */ 2456 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2457 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2458 break; 2459 default: 2460 break; 2461 } 2462 done: 2463 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2464 amdgpu_crtc->adjusted_clock = 0; 2465 amdgpu_crtc->encoder = NULL; 2466 amdgpu_crtc->connector = NULL; 2467 } 2468 2469 static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc, 2470 struct drm_display_mode *mode, 2471 struct drm_display_mode *adjusted_mode, 2472 int x, int y, struct drm_framebuffer *old_fb) 2473 { 2474 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2475 2476 if (!amdgpu_crtc->adjusted_clock) 2477 return -EINVAL; 2478 2479 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2480 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2481 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2482 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2483 amdgpu_atombios_crtc_scaler_setup(crtc); 2484 dce_v6_0_cursor_reset(crtc); 2485 /* update the hw version fpr dpm */ 2486 amdgpu_crtc->hw_mode = *adjusted_mode; 2487 2488 return 0; 2489 } 2490 2491 static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc, 2492 const struct drm_display_mode *mode, 2493 struct drm_display_mode *adjusted_mode) 2494 { 2495 2496 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2497 struct drm_device *dev = crtc->dev; 2498 struct drm_encoder *encoder; 2499 2500 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2501 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2502 if (encoder->crtc == crtc) { 2503 amdgpu_crtc->encoder = encoder; 2504 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2505 break; 2506 } 2507 } 2508 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2509 amdgpu_crtc->encoder = NULL; 2510 amdgpu_crtc->connector = NULL; 2511 return false; 2512 } 2513 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2514 return false; 2515 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2516 return false; 2517 /* pick pll */ 2518 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc); 2519 /* if we can't get a PPLL for a non-DP encoder, fail */ 2520 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2521 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2522 return false; 2523 2524 return true; 2525 } 2526 2527 static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2528 struct drm_framebuffer *old_fb) 2529 { 2530 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2531 } 2532 2533 static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2534 struct drm_framebuffer *fb, 2535 int x, int y, enum mode_set_atomic state) 2536 { 2537 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1); 2538 } 2539 2540 static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { 2541 .dpms = dce_v6_0_crtc_dpms, 2542 .mode_fixup = dce_v6_0_crtc_mode_fixup, 2543 .mode_set = dce_v6_0_crtc_mode_set, 2544 .mode_set_base = dce_v6_0_crtc_set_base, 2545 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic, 2546 .prepare = dce_v6_0_crtc_prepare, 2547 .commit = dce_v6_0_crtc_commit, 2548 .disable = dce_v6_0_crtc_disable, 2549 }; 2550 2551 static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) 2552 { 2553 struct amdgpu_crtc *amdgpu_crtc; 2554 2555 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2556 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2557 if (amdgpu_crtc == NULL) 2558 return -ENOMEM; 2559 2560 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs); 2561 2562 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2563 amdgpu_crtc->crtc_id = index; 2564 adev->mode_info.crtcs[index] = amdgpu_crtc; 2565 2566 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH; 2567 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT; 2568 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2569 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2570 2571 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id]; 2572 2573 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2574 amdgpu_crtc->adjusted_clock = 0; 2575 amdgpu_crtc->encoder = NULL; 2576 amdgpu_crtc->connector = NULL; 2577 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs); 2578 2579 return 0; 2580 } 2581 2582 static int dce_v6_0_early_init(void *handle) 2583 { 2584 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2585 2586 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; 2587 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; 2588 2589 dce_v6_0_set_display_funcs(adev); 2590 2591 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev); 2592 2593 switch (adev->asic_type) { 2594 case CHIP_TAHITI: 2595 case CHIP_PITCAIRN: 2596 case CHIP_VERDE: 2597 adev->mode_info.num_hpd = 6; 2598 adev->mode_info.num_dig = 6; 2599 break; 2600 case CHIP_OLAND: 2601 adev->mode_info.num_hpd = 2; 2602 adev->mode_info.num_dig = 2; 2603 break; 2604 default: 2605 return -EINVAL; 2606 } 2607 2608 dce_v6_0_set_irq_funcs(adev); 2609 2610 return 0; 2611 } 2612 2613 static int dce_v6_0_sw_init(void *handle) 2614 { 2615 int r, i; 2616 bool ret; 2617 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2618 2619 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2620 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2621 if (r) 2622 return r; 2623 } 2624 2625 for (i = 8; i < 20; i += 2) { 2626 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2627 if (r) 2628 return r; 2629 } 2630 2631 /* HPD hotplug */ 2632 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2633 if (r) 2634 return r; 2635 2636 adev->mode_info.mode_config_initialized = true; 2637 2638 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2639 adev->ddev->mode_config.async_page_flip = true; 2640 adev->ddev->mode_config.max_width = 16384; 2641 adev->ddev->mode_config.max_height = 16384; 2642 adev->ddev->mode_config.preferred_depth = 24; 2643 adev->ddev->mode_config.prefer_shadow = 1; 2644 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2645 2646 r = amdgpu_display_modeset_create_props(adev); 2647 if (r) 2648 return r; 2649 2650 adev->ddev->mode_config.max_width = 16384; 2651 adev->ddev->mode_config.max_height = 16384; 2652 2653 /* allocate crtcs */ 2654 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2655 r = dce_v6_0_crtc_init(adev, i); 2656 if (r) 2657 return r; 2658 } 2659 2660 ret = amdgpu_atombios_get_connector_info_from_object_table(adev); 2661 if (ret) 2662 amdgpu_display_print_display_setup(adev->ddev); 2663 else 2664 return -EINVAL; 2665 2666 /* setup afmt */ 2667 r = dce_v6_0_afmt_init(adev); 2668 if (r) 2669 return r; 2670 2671 r = dce_v6_0_audio_init(adev); 2672 if (r) 2673 return r; 2674 2675 drm_kms_helper_poll_init(adev->ddev); 2676 2677 return r; 2678 } 2679 2680 static int dce_v6_0_sw_fini(void *handle) 2681 { 2682 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2683 2684 kfree(adev->mode_info.bios_hardcoded_edid); 2685 2686 drm_kms_helper_poll_fini(adev->ddev); 2687 2688 dce_v6_0_audio_fini(adev); 2689 dce_v6_0_afmt_fini(adev); 2690 2691 drm_mode_config_cleanup(adev->ddev); 2692 adev->mode_info.mode_config_initialized = false; 2693 2694 return 0; 2695 } 2696 2697 static int dce_v6_0_hw_init(void *handle) 2698 { 2699 int i; 2700 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2701 2702 /* disable vga render */ 2703 dce_v6_0_set_vga_render_state(adev, false); 2704 /* init dig PHYs, disp eng pll */ 2705 amdgpu_atombios_encoder_init_dig(adev); 2706 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2707 2708 /* initialize hpd */ 2709 dce_v6_0_hpd_init(adev); 2710 2711 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2712 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2713 } 2714 2715 dce_v6_0_pageflip_interrupt_init(adev); 2716 2717 return 0; 2718 } 2719 2720 static int dce_v6_0_hw_fini(void *handle) 2721 { 2722 int i; 2723 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2724 2725 dce_v6_0_hpd_fini(adev); 2726 2727 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2728 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2729 } 2730 2731 dce_v6_0_pageflip_interrupt_fini(adev); 2732 2733 return 0; 2734 } 2735 2736 static int dce_v6_0_suspend(void *handle) 2737 { 2738 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2739 2740 adev->mode_info.bl_level = 2741 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2742 2743 return dce_v6_0_hw_fini(handle); 2744 } 2745 2746 static int dce_v6_0_resume(void *handle) 2747 { 2748 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2749 int ret; 2750 2751 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2752 adev->mode_info.bl_level); 2753 2754 ret = dce_v6_0_hw_init(handle); 2755 2756 /* turn on the BL */ 2757 if (adev->mode_info.bl_encoder) { 2758 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2759 adev->mode_info.bl_encoder); 2760 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2761 bl_level); 2762 } 2763 2764 return ret; 2765 } 2766 2767 static bool dce_v6_0_is_idle(void *handle) 2768 { 2769 return true; 2770 } 2771 2772 static int dce_v6_0_wait_for_idle(void *handle) 2773 { 2774 return 0; 2775 } 2776 2777 static int dce_v6_0_soft_reset(void *handle) 2778 { 2779 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); 2780 return 0; 2781 } 2782 2783 static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2784 int crtc, 2785 enum amdgpu_interrupt_state state) 2786 { 2787 u32 reg_block, interrupt_mask; 2788 2789 if (crtc >= adev->mode_info.num_crtc) { 2790 DRM_DEBUG("invalid crtc %d\n", crtc); 2791 return; 2792 } 2793 2794 switch (crtc) { 2795 case 0: 2796 reg_block = SI_CRTC0_REGISTER_OFFSET; 2797 break; 2798 case 1: 2799 reg_block = SI_CRTC1_REGISTER_OFFSET; 2800 break; 2801 case 2: 2802 reg_block = SI_CRTC2_REGISTER_OFFSET; 2803 break; 2804 case 3: 2805 reg_block = SI_CRTC3_REGISTER_OFFSET; 2806 break; 2807 case 4: 2808 reg_block = SI_CRTC4_REGISTER_OFFSET; 2809 break; 2810 case 5: 2811 reg_block = SI_CRTC5_REGISTER_OFFSET; 2812 break; 2813 default: 2814 DRM_DEBUG("invalid crtc %d\n", crtc); 2815 return; 2816 } 2817 2818 switch (state) { 2819 case AMDGPU_IRQ_STATE_DISABLE: 2820 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2821 interrupt_mask &= ~VBLANK_INT_MASK; 2822 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2823 break; 2824 case AMDGPU_IRQ_STATE_ENABLE: 2825 interrupt_mask = RREG32(mmINT_MASK + reg_block); 2826 interrupt_mask |= VBLANK_INT_MASK; 2827 WREG32(mmINT_MASK + reg_block, interrupt_mask); 2828 break; 2829 default: 2830 break; 2831 } 2832 } 2833 2834 static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2835 int crtc, 2836 enum amdgpu_interrupt_state state) 2837 { 2838 2839 } 2840 2841 static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev, 2842 struct amdgpu_irq_src *src, 2843 unsigned type, 2844 enum amdgpu_interrupt_state state) 2845 { 2846 u32 dc_hpd_int_cntl; 2847 2848 if (type >= adev->mode_info.num_hpd) { 2849 DRM_DEBUG("invalid hdp %d\n", type); 2850 return 0; 2851 } 2852 2853 switch (state) { 2854 case AMDGPU_IRQ_STATE_DISABLE: 2855 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2856 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN; 2857 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2858 break; 2859 case AMDGPU_IRQ_STATE_ENABLE: 2860 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]); 2861 dc_hpd_int_cntl |= DC_HPDx_INT_EN; 2862 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl); 2863 break; 2864 default: 2865 break; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev, 2872 struct amdgpu_irq_src *src, 2873 unsigned type, 2874 enum amdgpu_interrupt_state state) 2875 { 2876 switch (type) { 2877 case AMDGPU_CRTC_IRQ_VBLANK1: 2878 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state); 2879 break; 2880 case AMDGPU_CRTC_IRQ_VBLANK2: 2881 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state); 2882 break; 2883 case AMDGPU_CRTC_IRQ_VBLANK3: 2884 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state); 2885 break; 2886 case AMDGPU_CRTC_IRQ_VBLANK4: 2887 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state); 2888 break; 2889 case AMDGPU_CRTC_IRQ_VBLANK5: 2890 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state); 2891 break; 2892 case AMDGPU_CRTC_IRQ_VBLANK6: 2893 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state); 2894 break; 2895 case AMDGPU_CRTC_IRQ_VLINE1: 2896 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state); 2897 break; 2898 case AMDGPU_CRTC_IRQ_VLINE2: 2899 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state); 2900 break; 2901 case AMDGPU_CRTC_IRQ_VLINE3: 2902 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state); 2903 break; 2904 case AMDGPU_CRTC_IRQ_VLINE4: 2905 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state); 2906 break; 2907 case AMDGPU_CRTC_IRQ_VLINE5: 2908 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state); 2909 break; 2910 case AMDGPU_CRTC_IRQ_VLINE6: 2911 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state); 2912 break; 2913 default: 2914 break; 2915 } 2916 return 0; 2917 } 2918 2919 static int dce_v6_0_crtc_irq(struct amdgpu_device *adev, 2920 struct amdgpu_irq_src *source, 2921 struct amdgpu_iv_entry *entry) 2922 { 2923 unsigned crtc = entry->src_id - 1; 2924 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 2925 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 2926 crtc); 2927 2928 switch (entry->src_data[0]) { 2929 case 0: /* vblank */ 2930 if (disp_int & interrupt_status_offsets[crtc].vblank) 2931 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK); 2932 else 2933 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2934 2935 if (amdgpu_irq_enabled(adev, source, irq_type)) { 2936 drm_handle_vblank(adev->ddev, crtc); 2937 } 2938 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 2939 break; 2940 case 1: /* vline */ 2941 if (disp_int & interrupt_status_offsets[crtc].vline) 2942 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK); 2943 else 2944 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 2945 2946 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 2947 break; 2948 default: 2949 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 2950 break; 2951 } 2952 2953 return 0; 2954 } 2955 2956 static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev, 2957 struct amdgpu_irq_src *src, 2958 unsigned type, 2959 enum amdgpu_interrupt_state state) 2960 { 2961 u32 reg; 2962 2963 if (type >= adev->mode_info.num_crtc) { 2964 DRM_ERROR("invalid pageflip crtc %d\n", type); 2965 return -EINVAL; 2966 } 2967 2968 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 2969 if (state == AMDGPU_IRQ_STATE_DISABLE) 2970 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 2971 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2972 else 2973 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 2974 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 2975 2976 return 0; 2977 } 2978 2979 static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev, 2980 struct amdgpu_irq_src *source, 2981 struct amdgpu_iv_entry *entry) 2982 { 2983 unsigned long flags; 2984 unsigned crtc_id; 2985 struct amdgpu_crtc *amdgpu_crtc; 2986 struct amdgpu_flip_work *works; 2987 2988 crtc_id = (entry->src_id - 8) >> 1; 2989 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 2990 2991 if (crtc_id >= adev->mode_info.num_crtc) { 2992 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 2993 return -EINVAL; 2994 } 2995 2996 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 2997 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 2998 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 2999 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3000 3001 /* IRQ could occur when in initial stage */ 3002 if (amdgpu_crtc == NULL) 3003 return 0; 3004 3005 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3006 works = amdgpu_crtc->pflip_works; 3007 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3008 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3009 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3010 amdgpu_crtc->pflip_status, 3011 AMDGPU_FLIP_SUBMITTED); 3012 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3013 return 0; 3014 } 3015 3016 /* page flip completed. clean up */ 3017 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3018 amdgpu_crtc->pflip_works = NULL; 3019 3020 /* wakeup usersapce */ 3021 if (works->event) 3022 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3023 3024 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3025 3026 drm_crtc_vblank_put(&amdgpu_crtc->base); 3027 schedule_work(&works->unpin_work); 3028 3029 return 0; 3030 } 3031 3032 static int dce_v6_0_hpd_irq(struct amdgpu_device *adev, 3033 struct amdgpu_irq_src *source, 3034 struct amdgpu_iv_entry *entry) 3035 { 3036 uint32_t disp_int, mask, tmp; 3037 unsigned hpd; 3038 3039 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3040 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3041 return 0; 3042 } 3043 3044 hpd = entry->src_data[0]; 3045 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3046 mask = interrupt_status_offsets[hpd].hpd; 3047 3048 if (disp_int & mask) { 3049 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]); 3050 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK; 3051 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp); 3052 schedule_work(&adev->hotplug_work); 3053 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3054 } 3055 3056 return 0; 3057 3058 } 3059 3060 static int dce_v6_0_set_clockgating_state(void *handle, 3061 enum amd_clockgating_state state) 3062 { 3063 return 0; 3064 } 3065 3066 static int dce_v6_0_set_powergating_state(void *handle, 3067 enum amd_powergating_state state) 3068 { 3069 return 0; 3070 } 3071 3072 static const struct amd_ip_funcs dce_v6_0_ip_funcs = { 3073 .name = "dce_v6_0", 3074 .early_init = dce_v6_0_early_init, 3075 .late_init = NULL, 3076 .sw_init = dce_v6_0_sw_init, 3077 .sw_fini = dce_v6_0_sw_fini, 3078 .hw_init = dce_v6_0_hw_init, 3079 .hw_fini = dce_v6_0_hw_fini, 3080 .suspend = dce_v6_0_suspend, 3081 .resume = dce_v6_0_resume, 3082 .is_idle = dce_v6_0_is_idle, 3083 .wait_for_idle = dce_v6_0_wait_for_idle, 3084 .soft_reset = dce_v6_0_soft_reset, 3085 .set_clockgating_state = dce_v6_0_set_clockgating_state, 3086 .set_powergating_state = dce_v6_0_set_powergating_state, 3087 }; 3088 3089 static void 3090 dce_v6_0_encoder_mode_set(struct drm_encoder *encoder, 3091 struct drm_display_mode *mode, 3092 struct drm_display_mode *adjusted_mode) 3093 { 3094 3095 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3096 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3097 3098 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3099 3100 /* need to call this here rather than in prepare() since we need some crtc info */ 3101 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3102 3103 /* set scaler clears this on some chips */ 3104 dce_v6_0_set_interleave(encoder->crtc, mode); 3105 3106 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) { 3107 dce_v6_0_afmt_enable(encoder, true); 3108 dce_v6_0_afmt_setmode(encoder, adjusted_mode); 3109 } 3110 } 3111 3112 static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder) 3113 { 3114 3115 struct amdgpu_device *adev = encoder->dev->dev_private; 3116 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3117 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3118 3119 if ((amdgpu_encoder->active_device & 3120 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3121 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3122 ENCODER_OBJECT_ID_NONE)) { 3123 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3124 if (dig) { 3125 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder); 3126 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3127 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3128 } 3129 } 3130 3131 amdgpu_atombios_scratch_regs_lock(adev, true); 3132 3133 if (connector) { 3134 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3135 3136 /* select the clock/data port if it uses a router */ 3137 if (amdgpu_connector->router.cd_valid) 3138 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3139 3140 /* turn eDP panel on for mode set */ 3141 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3142 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3143 ATOM_TRANSMITTER_ACTION_POWER_ON); 3144 } 3145 3146 /* this is needed for the pll/ss setup to work correctly in some cases */ 3147 amdgpu_atombios_encoder_set_crtc_source(encoder); 3148 /* set up the FMT blocks */ 3149 dce_v6_0_program_fmt(encoder); 3150 } 3151 3152 static void dce_v6_0_encoder_commit(struct drm_encoder *encoder) 3153 { 3154 3155 struct drm_device *dev = encoder->dev; 3156 struct amdgpu_device *adev = dev->dev_private; 3157 3158 /* need to call this here as we need the crtc set up */ 3159 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3160 amdgpu_atombios_scratch_regs_lock(adev, false); 3161 } 3162 3163 static void dce_v6_0_encoder_disable(struct drm_encoder *encoder) 3164 { 3165 3166 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3167 struct amdgpu_encoder_atom_dig *dig; 3168 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); 3169 3170 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3171 3172 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3173 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) 3174 dce_v6_0_afmt_enable(encoder, false); 3175 dig = amdgpu_encoder->enc_priv; 3176 dig->dig_encoder = -1; 3177 } 3178 amdgpu_encoder->active_device = 0; 3179 } 3180 3181 /* these are handled by the primary encoders */ 3182 static void dce_v6_0_ext_prepare(struct drm_encoder *encoder) 3183 { 3184 3185 } 3186 3187 static void dce_v6_0_ext_commit(struct drm_encoder *encoder) 3188 { 3189 3190 } 3191 3192 static void 3193 dce_v6_0_ext_mode_set(struct drm_encoder *encoder, 3194 struct drm_display_mode *mode, 3195 struct drm_display_mode *adjusted_mode) 3196 { 3197 3198 } 3199 3200 static void dce_v6_0_ext_disable(struct drm_encoder *encoder) 3201 { 3202 3203 } 3204 3205 static void 3206 dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode) 3207 { 3208 3209 } 3210 3211 static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder, 3212 const struct drm_display_mode *mode, 3213 struct drm_display_mode *adjusted_mode) 3214 { 3215 return true; 3216 } 3217 3218 static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = { 3219 .dpms = dce_v6_0_ext_dpms, 3220 .mode_fixup = dce_v6_0_ext_mode_fixup, 3221 .prepare = dce_v6_0_ext_prepare, 3222 .mode_set = dce_v6_0_ext_mode_set, 3223 .commit = dce_v6_0_ext_commit, 3224 .disable = dce_v6_0_ext_disable, 3225 /* no detect for TMDS/LVDS yet */ 3226 }; 3227 3228 static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = { 3229 .dpms = amdgpu_atombios_encoder_dpms, 3230 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3231 .prepare = dce_v6_0_encoder_prepare, 3232 .mode_set = dce_v6_0_encoder_mode_set, 3233 .commit = dce_v6_0_encoder_commit, 3234 .disable = dce_v6_0_encoder_disable, 3235 .detect = amdgpu_atombios_encoder_dig_detect, 3236 }; 3237 3238 static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = { 3239 .dpms = amdgpu_atombios_encoder_dpms, 3240 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3241 .prepare = dce_v6_0_encoder_prepare, 3242 .mode_set = dce_v6_0_encoder_mode_set, 3243 .commit = dce_v6_0_encoder_commit, 3244 .detect = amdgpu_atombios_encoder_dac_detect, 3245 }; 3246 3247 static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder) 3248 { 3249 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3250 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3251 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3252 kfree(amdgpu_encoder->enc_priv); 3253 drm_encoder_cleanup(encoder); 3254 kfree(amdgpu_encoder); 3255 } 3256 3257 static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = { 3258 .destroy = dce_v6_0_encoder_destroy, 3259 }; 3260 3261 static void dce_v6_0_encoder_add(struct amdgpu_device *adev, 3262 uint32_t encoder_enum, 3263 uint32_t supported_device, 3264 u16 caps) 3265 { 3266 struct drm_device *dev = adev->ddev; 3267 struct drm_encoder *encoder; 3268 struct amdgpu_encoder *amdgpu_encoder; 3269 3270 /* see if we already added it */ 3271 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3272 amdgpu_encoder = to_amdgpu_encoder(encoder); 3273 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3274 amdgpu_encoder->devices |= supported_device; 3275 return; 3276 } 3277 3278 } 3279 3280 /* add a new one */ 3281 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3282 if (!amdgpu_encoder) 3283 return; 3284 3285 encoder = &amdgpu_encoder->base; 3286 switch (adev->mode_info.num_crtc) { 3287 case 1: 3288 encoder->possible_crtcs = 0x1; 3289 break; 3290 case 2: 3291 default: 3292 encoder->possible_crtcs = 0x3; 3293 break; 3294 case 4: 3295 encoder->possible_crtcs = 0xf; 3296 break; 3297 case 6: 3298 encoder->possible_crtcs = 0x3f; 3299 break; 3300 } 3301 3302 amdgpu_encoder->enc_priv = NULL; 3303 amdgpu_encoder->encoder_enum = encoder_enum; 3304 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3305 amdgpu_encoder->devices = supported_device; 3306 amdgpu_encoder->rmx_type = RMX_OFF; 3307 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3308 amdgpu_encoder->is_ext_encoder = false; 3309 amdgpu_encoder->caps = caps; 3310 3311 switch (amdgpu_encoder->encoder_id) { 3312 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3313 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3314 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3315 DRM_MODE_ENCODER_DAC, NULL); 3316 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs); 3317 break; 3318 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3319 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3320 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3321 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3322 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3323 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3324 amdgpu_encoder->rmx_type = RMX_FULL; 3325 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3326 DRM_MODE_ENCODER_LVDS, NULL); 3327 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3328 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3329 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3330 DRM_MODE_ENCODER_DAC, NULL); 3331 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3332 } else { 3333 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3334 DRM_MODE_ENCODER_TMDS, NULL); 3335 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3336 } 3337 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs); 3338 break; 3339 case ENCODER_OBJECT_ID_SI170B: 3340 case ENCODER_OBJECT_ID_CH7303: 3341 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3342 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3343 case ENCODER_OBJECT_ID_TITFP513: 3344 case ENCODER_OBJECT_ID_VT1623: 3345 case ENCODER_OBJECT_ID_HDMI_SI1930: 3346 case ENCODER_OBJECT_ID_TRAVIS: 3347 case ENCODER_OBJECT_ID_NUTMEG: 3348 /* these are handled by the primary encoders */ 3349 amdgpu_encoder->is_ext_encoder = true; 3350 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3351 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3352 DRM_MODE_ENCODER_LVDS, NULL); 3353 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3354 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3355 DRM_MODE_ENCODER_DAC, NULL); 3356 else 3357 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs, 3358 DRM_MODE_ENCODER_TMDS, NULL); 3359 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs); 3360 break; 3361 } 3362 } 3363 3364 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = { 3365 .bandwidth_update = &dce_v6_0_bandwidth_update, 3366 .vblank_get_counter = &dce_v6_0_vblank_get_counter, 3367 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3368 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3369 .hpd_sense = &dce_v6_0_hpd_sense, 3370 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity, 3371 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg, 3372 .page_flip = &dce_v6_0_page_flip, 3373 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos, 3374 .add_encoder = &dce_v6_0_encoder_add, 3375 .add_connector = &amdgpu_connector_add, 3376 }; 3377 3378 static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev) 3379 { 3380 adev->mode_info.funcs = &dce_v6_0_display_funcs; 3381 } 3382 3383 static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = { 3384 .set = dce_v6_0_set_crtc_interrupt_state, 3385 .process = dce_v6_0_crtc_irq, 3386 }; 3387 3388 static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = { 3389 .set = dce_v6_0_set_pageflip_interrupt_state, 3390 .process = dce_v6_0_pageflip_irq, 3391 }; 3392 3393 static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = { 3394 .set = dce_v6_0_set_hpd_interrupt_state, 3395 .process = dce_v6_0_hpd_irq, 3396 }; 3397 3398 static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev) 3399 { 3400 if (adev->mode_info.num_crtc > 0) 3401 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3402 else 3403 adev->crtc_irq.num_types = 0; 3404 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs; 3405 3406 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3407 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs; 3408 3409 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3410 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs; 3411 } 3412 3413 const struct amdgpu_ip_block_version dce_v6_0_ip_block = 3414 { 3415 .type = AMD_IP_BLOCK_TYPE_DCE, 3416 .major = 6, 3417 .minor = 0, 3418 .rev = 0, 3419 .funcs = &dce_v6_0_ip_funcs, 3420 }; 3421 3422 const struct amdgpu_ip_block_version dce_v6_4_ip_block = 3423 { 3424 .type = AMD_IP_BLOCK_TYPE_DCE, 3425 .major = 6, 3426 .minor = 4, 3427 .rev = 0, 3428 .funcs = &dce_v6_0_ip_funcs, 3429 }; 3430