1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 #include "dce/dce_11_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET, 75 DIG7_REGISTER_OFFSET, 76 DIG8_REGISTER_OFFSET 77 }; 78 79 static const struct { 80 uint32_t reg; 81 uint32_t vblank; 82 uint32_t vline; 83 uint32_t hpd; 84 85 } interrupt_status_offsets[] = { { 86 .reg = mmDISP_INTERRUPT_STATUS, 87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 } }; 116 117 static const u32 cz_golden_settings_a11[] = 118 { 119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000, 121 }; 122 123 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 124 { 125 switch (adev->asic_type) { 126 case CHIP_CARRIZO: 127 amdgpu_program_register_sequence(adev, 128 cz_golden_settings_a11, 129 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 130 break; 131 default: 132 break; 133 } 134 } 135 136 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 137 u32 block_offset, u32 reg) 138 { 139 unsigned long flags; 140 u32 r; 141 142 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 143 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 144 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 145 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 146 147 return r; 148 } 149 150 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 151 u32 block_offset, u32 reg, u32 v) 152 { 153 unsigned long flags; 154 155 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 156 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 157 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 158 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 159 } 160 161 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 162 { 163 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 164 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 165 return true; 166 else 167 return false; 168 } 169 170 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 171 { 172 u32 pos1, pos2; 173 174 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 175 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 176 177 if (pos1 != pos2) 178 return true; 179 else 180 return false; 181 } 182 183 /** 184 * dce_v11_0_vblank_wait - vblank wait asic callback. 185 * 186 * @adev: amdgpu_device pointer 187 * @crtc: crtc to wait for vblank on 188 * 189 * Wait for vblank on the requested crtc (evergreen+). 190 */ 191 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 192 { 193 unsigned i = 0; 194 195 if (crtc >= adev->mode_info.num_crtc) 196 return; 197 198 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 199 return; 200 201 /* depending on when we hit vblank, we may be close to active; if so, 202 * wait for another frame. 203 */ 204 while (dce_v11_0_is_in_vblank(adev, crtc)) { 205 if (i++ % 100 == 0) { 206 if (!dce_v11_0_is_counter_moving(adev, crtc)) 207 break; 208 } 209 } 210 211 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 212 if (i++ % 100 == 0) { 213 if (!dce_v11_0_is_counter_moving(adev, crtc)) 214 break; 215 } 216 } 217 } 218 219 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 220 { 221 if (crtc >= adev->mode_info.num_crtc) 222 return 0; 223 else 224 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 225 } 226 227 /** 228 * dce_v11_0_page_flip - pageflip callback. 229 * 230 * @adev: amdgpu_device pointer 231 * @crtc_id: crtc to cleanup pageflip on 232 * @crtc_base: new address of the crtc (GPU MC address) 233 * 234 * Does the actual pageflip (evergreen+). 235 * During vblank we take the crtc lock and wait for the update_pending 236 * bit to go high, when it does, we release the lock, and allow the 237 * double buffered update to take place. 238 * Returns the current update pending status. 239 */ 240 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 241 int crtc_id, u64 crtc_base) 242 { 243 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 244 u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); 245 int i; 246 247 /* Lock the graphics update lock */ 248 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 249 WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); 250 251 /* update the scanout addresses */ 252 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 253 upper_32_bits(crtc_base)); 254 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 255 lower_32_bits(crtc_base)); 256 257 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 258 upper_32_bits(crtc_base)); 259 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 260 lower_32_bits(crtc_base)); 261 262 /* Wait for update_pending to go high. */ 263 for (i = 0; i < adev->usec_timeout; i++) { 264 if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & 265 GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) 266 break; 267 udelay(1); 268 } 269 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); 270 271 /* Unlock the lock, so double-buffering can take place inside vblank */ 272 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 273 WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); 274 } 275 276 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 277 u32 *vbl, u32 *position) 278 { 279 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 280 return -EINVAL; 281 282 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 283 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 284 285 return 0; 286 } 287 288 /** 289 * dce_v11_0_hpd_sense - hpd sense callback. 290 * 291 * @adev: amdgpu_device pointer 292 * @hpd: hpd (hotplug detect) pin 293 * 294 * Checks if a digital monitor is connected (evergreen+). 295 * Returns true if connected, false if not connected. 296 */ 297 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 298 enum amdgpu_hpd_id hpd) 299 { 300 int idx; 301 bool connected = false; 302 303 switch (hpd) { 304 case AMDGPU_HPD_1: 305 idx = 0; 306 break; 307 case AMDGPU_HPD_2: 308 idx = 1; 309 break; 310 case AMDGPU_HPD_3: 311 idx = 2; 312 break; 313 case AMDGPU_HPD_4: 314 idx = 3; 315 break; 316 case AMDGPU_HPD_5: 317 idx = 4; 318 break; 319 case AMDGPU_HPD_6: 320 idx = 5; 321 break; 322 default: 323 return connected; 324 } 325 326 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 327 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 328 connected = true; 329 330 return connected; 331 } 332 333 /** 334 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 335 * 336 * @adev: amdgpu_device pointer 337 * @hpd: hpd (hotplug detect) pin 338 * 339 * Set the polarity of the hpd pin (evergreen+). 340 */ 341 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 342 enum amdgpu_hpd_id hpd) 343 { 344 u32 tmp; 345 bool connected = dce_v11_0_hpd_sense(adev, hpd); 346 int idx; 347 348 switch (hpd) { 349 case AMDGPU_HPD_1: 350 idx = 0; 351 break; 352 case AMDGPU_HPD_2: 353 idx = 1; 354 break; 355 case AMDGPU_HPD_3: 356 idx = 2; 357 break; 358 case AMDGPU_HPD_4: 359 idx = 3; 360 break; 361 case AMDGPU_HPD_5: 362 idx = 4; 363 break; 364 case AMDGPU_HPD_6: 365 idx = 5; 366 break; 367 default: 368 return; 369 } 370 371 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 372 if (connected) 373 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 374 else 375 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 376 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 377 } 378 379 /** 380 * dce_v11_0_hpd_init - hpd setup callback. 381 * 382 * @adev: amdgpu_device pointer 383 * 384 * Setup the hpd pins used by the card (evergreen+). 385 * Enable the pin, set the polarity, and enable the hpd interrupts. 386 */ 387 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 388 { 389 struct drm_device *dev = adev->ddev; 390 struct drm_connector *connector; 391 u32 tmp; 392 int idx; 393 394 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 395 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 396 397 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 398 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 399 /* don't try to enable hpd on eDP or LVDS avoid breaking the 400 * aux dp channel on imac and help (but not completely fix) 401 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 402 * also avoid interrupt storms during dpms. 403 */ 404 continue; 405 } 406 407 switch (amdgpu_connector->hpd.hpd) { 408 case AMDGPU_HPD_1: 409 idx = 0; 410 break; 411 case AMDGPU_HPD_2: 412 idx = 1; 413 break; 414 case AMDGPU_HPD_3: 415 idx = 2; 416 break; 417 case AMDGPU_HPD_4: 418 idx = 3; 419 break; 420 case AMDGPU_HPD_5: 421 idx = 4; 422 break; 423 case AMDGPU_HPD_6: 424 idx = 5; 425 break; 426 default: 427 continue; 428 } 429 430 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 431 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 432 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 433 434 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 435 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 436 DC_HPD_CONNECT_INT_DELAY, 437 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 438 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 439 DC_HPD_DISCONNECT_INT_DELAY, 440 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 441 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 442 443 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 444 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 445 } 446 } 447 448 /** 449 * dce_v11_0_hpd_fini - hpd tear down callback. 450 * 451 * @adev: amdgpu_device pointer 452 * 453 * Tear down the hpd pins used by the card (evergreen+). 454 * Disable the hpd interrupts. 455 */ 456 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 457 { 458 struct drm_device *dev = adev->ddev; 459 struct drm_connector *connector; 460 u32 tmp; 461 int idx; 462 463 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 464 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 465 466 switch (amdgpu_connector->hpd.hpd) { 467 case AMDGPU_HPD_1: 468 idx = 0; 469 break; 470 case AMDGPU_HPD_2: 471 idx = 1; 472 break; 473 case AMDGPU_HPD_3: 474 idx = 2; 475 break; 476 case AMDGPU_HPD_4: 477 idx = 3; 478 break; 479 case AMDGPU_HPD_5: 480 idx = 4; 481 break; 482 case AMDGPU_HPD_6: 483 idx = 5; 484 break; 485 default: 486 continue; 487 } 488 489 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 490 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 491 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 492 493 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 494 } 495 } 496 497 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 498 { 499 return mmDC_GPIO_HPD_A; 500 } 501 502 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 503 { 504 u32 crtc_hung = 0; 505 u32 crtc_status[6]; 506 u32 i, j, tmp; 507 508 for (i = 0; i < adev->mode_info.num_crtc; i++) { 509 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 510 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 511 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 512 crtc_hung |= (1 << i); 513 } 514 } 515 516 for (j = 0; j < 10; j++) { 517 for (i = 0; i < adev->mode_info.num_crtc; i++) { 518 if (crtc_hung & (1 << i)) { 519 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 520 if (tmp != crtc_status[i]) 521 crtc_hung &= ~(1 << i); 522 } 523 } 524 if (crtc_hung == 0) 525 return false; 526 udelay(100); 527 } 528 529 return true; 530 } 531 532 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 533 struct amdgpu_mode_mc_save *save) 534 { 535 u32 crtc_enabled, tmp; 536 int i; 537 538 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 539 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 540 541 /* disable VGA render */ 542 tmp = RREG32(mmVGA_RENDER_CONTROL); 543 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 544 WREG32(mmVGA_RENDER_CONTROL, tmp); 545 546 /* blank the display controllers */ 547 for (i = 0; i < adev->mode_info.num_crtc; i++) { 548 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 549 CRTC_CONTROL, CRTC_MASTER_EN); 550 if (crtc_enabled) { 551 #if 0 552 u32 frame_count; 553 int j; 554 555 save->crtc_enabled[i] = true; 556 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 557 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 558 amdgpu_display_vblank_wait(adev, i); 559 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 560 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 561 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 562 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 563 } 564 /* wait for the next frame */ 565 frame_count = amdgpu_display_vblank_get_counter(adev, i); 566 for (j = 0; j < adev->usec_timeout; j++) { 567 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 568 break; 569 udelay(1); 570 } 571 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 572 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 573 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 574 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 575 } 576 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); 577 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 578 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 579 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 580 } 581 #else 582 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 583 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 584 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 585 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 586 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 587 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 588 save->crtc_enabled[i] = false; 589 /* ***** */ 590 #endif 591 } else { 592 save->crtc_enabled[i] = false; 593 } 594 } 595 } 596 597 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 598 struct amdgpu_mode_mc_save *save) 599 { 600 u32 tmp, frame_count; 601 int i, j; 602 603 /* update crtc base addresses */ 604 for (i = 0; i < adev->mode_info.num_crtc; i++) { 605 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 606 upper_32_bits(adev->mc.vram_start)); 607 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 608 upper_32_bits(adev->mc.vram_start)); 609 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 610 (u32)adev->mc.vram_start); 611 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 612 (u32)adev->mc.vram_start); 613 614 if (save->crtc_enabled[i]) { 615 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); 616 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 617 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 618 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 619 } 620 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 621 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 622 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 623 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 624 } 625 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); 626 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 627 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 628 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 629 } 630 for (j = 0; j < adev->usec_timeout; j++) { 631 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 632 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 633 break; 634 udelay(1); 635 } 636 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 637 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 638 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 639 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 640 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 641 /* wait for the next frame */ 642 frame_count = amdgpu_display_vblank_get_counter(adev, i); 643 for (j = 0; j < adev->usec_timeout; j++) { 644 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 645 break; 646 udelay(1); 647 } 648 } 649 } 650 651 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 652 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 653 654 /* Unlock vga access */ 655 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 656 mdelay(1); 657 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 658 } 659 660 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 661 bool render) 662 { 663 u32 tmp; 664 665 /* Lockout access through VGA aperture*/ 666 tmp = RREG32(mmVGA_HDP_CONTROL); 667 if (render) 668 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 669 else 670 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 671 WREG32(mmVGA_HDP_CONTROL, tmp); 672 673 /* disable VGA render */ 674 tmp = RREG32(mmVGA_RENDER_CONTROL); 675 if (render) 676 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 677 else 678 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 679 WREG32(mmVGA_RENDER_CONTROL, tmp); 680 } 681 682 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 683 { 684 struct drm_device *dev = encoder->dev; 685 struct amdgpu_device *adev = dev->dev_private; 686 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 687 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 688 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 689 int bpc = 0; 690 u32 tmp = 0; 691 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 692 693 if (connector) { 694 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 695 bpc = amdgpu_connector_get_monitor_bpc(connector); 696 dither = amdgpu_connector->dither; 697 } 698 699 /* LVDS/eDP FMT is set up by atom */ 700 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 701 return; 702 703 /* not needed for analog */ 704 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 705 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 706 return; 707 708 if (bpc == 0) 709 return; 710 711 switch (bpc) { 712 case 6: 713 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 714 /* XXX sort out optimal dither settings */ 715 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 716 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 717 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 718 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 719 } else { 720 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 721 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 722 } 723 break; 724 case 8: 725 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 726 /* XXX sort out optimal dither settings */ 727 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 729 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 730 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 731 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 732 } else { 733 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 734 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 735 } 736 break; 737 case 10: 738 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 739 /* XXX sort out optimal dither settings */ 740 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 742 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 743 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 745 } else { 746 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 748 } 749 break; 750 default: 751 /* not needed */ 752 break; 753 } 754 755 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 756 } 757 758 759 /* display watermark setup */ 760 /** 761 * dce_v11_0_line_buffer_adjust - Set up the line buffer 762 * 763 * @adev: amdgpu_device pointer 764 * @amdgpu_crtc: the selected display controller 765 * @mode: the current display mode on the selected display 766 * controller 767 * 768 * Setup up the line buffer allocation for 769 * the selected display controller (CIK). 770 * Returns the line buffer size in pixels. 771 */ 772 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 773 struct amdgpu_crtc *amdgpu_crtc, 774 struct drm_display_mode *mode) 775 { 776 u32 tmp, buffer_alloc, i, mem_cfg; 777 u32 pipe_offset = amdgpu_crtc->crtc_id; 778 /* 779 * Line Buffer Setup 780 * There are 6 line buffers, one for each display controllers. 781 * There are 3 partitions per LB. Select the number of partitions 782 * to enable based on the display width. For display widths larger 783 * than 4096, you need use to use 2 display controllers and combine 784 * them using the stereo blender. 785 */ 786 if (amdgpu_crtc->base.enabled && mode) { 787 if (mode->crtc_hdisplay < 1920) { 788 mem_cfg = 1; 789 buffer_alloc = 2; 790 } else if (mode->crtc_hdisplay < 2560) { 791 mem_cfg = 2; 792 buffer_alloc = 2; 793 } else if (mode->crtc_hdisplay < 4096) { 794 mem_cfg = 0; 795 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 796 } else { 797 DRM_DEBUG_KMS("Mode too big for LB!\n"); 798 mem_cfg = 0; 799 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 800 } 801 } else { 802 mem_cfg = 1; 803 buffer_alloc = 0; 804 } 805 806 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 807 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 808 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 809 810 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 811 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 812 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 813 814 for (i = 0; i < adev->usec_timeout; i++) { 815 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 816 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 817 break; 818 udelay(1); 819 } 820 821 if (amdgpu_crtc->base.enabled && mode) { 822 switch (mem_cfg) { 823 case 0: 824 default: 825 return 4096 * 2; 826 case 1: 827 return 1920 * 2; 828 case 2: 829 return 2560 * 2; 830 } 831 } 832 833 /* controller not enabled, so no lb used */ 834 return 0; 835 } 836 837 /** 838 * cik_get_number_of_dram_channels - get the number of dram channels 839 * 840 * @adev: amdgpu_device pointer 841 * 842 * Look up the number of video ram channels (CIK). 843 * Used for display watermark bandwidth calculations 844 * Returns the number of dram channels 845 */ 846 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 847 { 848 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 849 850 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 851 case 0: 852 default: 853 return 1; 854 case 1: 855 return 2; 856 case 2: 857 return 4; 858 case 3: 859 return 8; 860 case 4: 861 return 3; 862 case 5: 863 return 6; 864 case 6: 865 return 10; 866 case 7: 867 return 12; 868 case 8: 869 return 16; 870 } 871 } 872 873 struct dce10_wm_params { 874 u32 dram_channels; /* number of dram channels */ 875 u32 yclk; /* bandwidth per dram data pin in kHz */ 876 u32 sclk; /* engine clock in kHz */ 877 u32 disp_clk; /* display clock in kHz */ 878 u32 src_width; /* viewport width */ 879 u32 active_time; /* active display time in ns */ 880 u32 blank_time; /* blank time in ns */ 881 bool interlaced; /* mode is interlaced */ 882 fixed20_12 vsc; /* vertical scale ratio */ 883 u32 num_heads; /* number of active crtcs */ 884 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 885 u32 lb_size; /* line buffer allocated to pipe */ 886 u32 vtaps; /* vertical scaler taps */ 887 }; 888 889 /** 890 * dce_v11_0_dram_bandwidth - get the dram bandwidth 891 * 892 * @wm: watermark calculation data 893 * 894 * Calculate the raw dram bandwidth (CIK). 895 * Used for display watermark bandwidth calculations 896 * Returns the dram bandwidth in MBytes/s 897 */ 898 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 899 { 900 /* Calculate raw DRAM Bandwidth */ 901 fixed20_12 dram_efficiency; /* 0.7 */ 902 fixed20_12 yclk, dram_channels, bandwidth; 903 fixed20_12 a; 904 905 a.full = dfixed_const(1000); 906 yclk.full = dfixed_const(wm->yclk); 907 yclk.full = dfixed_div(yclk, a); 908 dram_channels.full = dfixed_const(wm->dram_channels * 4); 909 a.full = dfixed_const(10); 910 dram_efficiency.full = dfixed_const(7); 911 dram_efficiency.full = dfixed_div(dram_efficiency, a); 912 bandwidth.full = dfixed_mul(dram_channels, yclk); 913 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 914 915 return dfixed_trunc(bandwidth); 916 } 917 918 /** 919 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 920 * 921 * @wm: watermark calculation data 922 * 923 * Calculate the dram bandwidth used for display (CIK). 924 * Used for display watermark bandwidth calculations 925 * Returns the dram bandwidth for display in MBytes/s 926 */ 927 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 928 { 929 /* Calculate DRAM Bandwidth and the part allocated to display. */ 930 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 931 fixed20_12 yclk, dram_channels, bandwidth; 932 fixed20_12 a; 933 934 a.full = dfixed_const(1000); 935 yclk.full = dfixed_const(wm->yclk); 936 yclk.full = dfixed_div(yclk, a); 937 dram_channels.full = dfixed_const(wm->dram_channels * 4); 938 a.full = dfixed_const(10); 939 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 940 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 941 bandwidth.full = dfixed_mul(dram_channels, yclk); 942 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 943 944 return dfixed_trunc(bandwidth); 945 } 946 947 /** 948 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 949 * 950 * @wm: watermark calculation data 951 * 952 * Calculate the data return bandwidth used for display (CIK). 953 * Used for display watermark bandwidth calculations 954 * Returns the data return bandwidth in MBytes/s 955 */ 956 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 957 { 958 /* Calculate the display Data return Bandwidth */ 959 fixed20_12 return_efficiency; /* 0.8 */ 960 fixed20_12 sclk, bandwidth; 961 fixed20_12 a; 962 963 a.full = dfixed_const(1000); 964 sclk.full = dfixed_const(wm->sclk); 965 sclk.full = dfixed_div(sclk, a); 966 a.full = dfixed_const(10); 967 return_efficiency.full = dfixed_const(8); 968 return_efficiency.full = dfixed_div(return_efficiency, a); 969 a.full = dfixed_const(32); 970 bandwidth.full = dfixed_mul(a, sclk); 971 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 972 973 return dfixed_trunc(bandwidth); 974 } 975 976 /** 977 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 978 * 979 * @wm: watermark calculation data 980 * 981 * Calculate the dmif bandwidth used for display (CIK). 982 * Used for display watermark bandwidth calculations 983 * Returns the dmif bandwidth in MBytes/s 984 */ 985 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 986 { 987 /* Calculate the DMIF Request Bandwidth */ 988 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 989 fixed20_12 disp_clk, bandwidth; 990 fixed20_12 a, b; 991 992 a.full = dfixed_const(1000); 993 disp_clk.full = dfixed_const(wm->disp_clk); 994 disp_clk.full = dfixed_div(disp_clk, a); 995 a.full = dfixed_const(32); 996 b.full = dfixed_mul(a, disp_clk); 997 998 a.full = dfixed_const(10); 999 disp_clk_request_efficiency.full = dfixed_const(8); 1000 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1001 1002 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1003 1004 return dfixed_trunc(bandwidth); 1005 } 1006 1007 /** 1008 * dce_v11_0_available_bandwidth - get the min available bandwidth 1009 * 1010 * @wm: watermark calculation data 1011 * 1012 * Calculate the min available bandwidth used for display (CIK). 1013 * Used for display watermark bandwidth calculations 1014 * Returns the min available bandwidth in MBytes/s 1015 */ 1016 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 1017 { 1018 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1019 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 1020 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 1021 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 1022 1023 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1024 } 1025 1026 /** 1027 * dce_v11_0_average_bandwidth - get the average available bandwidth 1028 * 1029 * @wm: watermark calculation data 1030 * 1031 * Calculate the average available bandwidth used for display (CIK). 1032 * Used for display watermark bandwidth calculations 1033 * Returns the average available bandwidth in MBytes/s 1034 */ 1035 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 1036 { 1037 /* Calculate the display mode Average Bandwidth 1038 * DisplayMode should contain the source and destination dimensions, 1039 * timing, etc. 1040 */ 1041 fixed20_12 bpp; 1042 fixed20_12 line_time; 1043 fixed20_12 src_width; 1044 fixed20_12 bandwidth; 1045 fixed20_12 a; 1046 1047 a.full = dfixed_const(1000); 1048 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1049 line_time.full = dfixed_div(line_time, a); 1050 bpp.full = dfixed_const(wm->bytes_per_pixel); 1051 src_width.full = dfixed_const(wm->src_width); 1052 bandwidth.full = dfixed_mul(src_width, bpp); 1053 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1054 bandwidth.full = dfixed_div(bandwidth, line_time); 1055 1056 return dfixed_trunc(bandwidth); 1057 } 1058 1059 /** 1060 * dce_v11_0_latency_watermark - get the latency watermark 1061 * 1062 * @wm: watermark calculation data 1063 * 1064 * Calculate the latency watermark (CIK). 1065 * Used for display watermark bandwidth calculations 1066 * Returns the latency watermark in ns 1067 */ 1068 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1069 { 1070 /* First calculate the latency in ns */ 1071 u32 mc_latency = 2000; /* 2000 ns. */ 1072 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1073 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1074 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1075 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1076 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1077 (wm->num_heads * cursor_line_pair_return_time); 1078 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1079 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1080 u32 tmp, dmif_size = 12288; 1081 fixed20_12 a, b, c; 1082 1083 if (wm->num_heads == 0) 1084 return 0; 1085 1086 a.full = dfixed_const(2); 1087 b.full = dfixed_const(1); 1088 if ((wm->vsc.full > a.full) || 1089 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1090 (wm->vtaps >= 5) || 1091 ((wm->vsc.full >= a.full) && wm->interlaced)) 1092 max_src_lines_per_dst_line = 4; 1093 else 1094 max_src_lines_per_dst_line = 2; 1095 1096 a.full = dfixed_const(available_bandwidth); 1097 b.full = dfixed_const(wm->num_heads); 1098 a.full = dfixed_div(a, b); 1099 1100 b.full = dfixed_const(mc_latency + 512); 1101 c.full = dfixed_const(wm->disp_clk); 1102 b.full = dfixed_div(b, c); 1103 1104 c.full = dfixed_const(dmif_size); 1105 b.full = dfixed_div(c, b); 1106 1107 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1108 1109 b.full = dfixed_const(1000); 1110 c.full = dfixed_const(wm->disp_clk); 1111 b.full = dfixed_div(c, b); 1112 c.full = dfixed_const(wm->bytes_per_pixel); 1113 b.full = dfixed_mul(b, c); 1114 1115 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1116 1117 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1118 b.full = dfixed_const(1000); 1119 c.full = dfixed_const(lb_fill_bw); 1120 b.full = dfixed_div(c, b); 1121 a.full = dfixed_div(a, b); 1122 line_fill_time = dfixed_trunc(a); 1123 1124 if (line_fill_time < wm->active_time) 1125 return latency; 1126 else 1127 return latency + (line_fill_time - wm->active_time); 1128 1129 } 1130 1131 /** 1132 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1133 * average and available dram bandwidth 1134 * 1135 * @wm: watermark calculation data 1136 * 1137 * Check if the display average bandwidth fits in the display 1138 * dram bandwidth (CIK). 1139 * Used for display watermark bandwidth calculations 1140 * Returns true if the display fits, false if not. 1141 */ 1142 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1143 { 1144 if (dce_v11_0_average_bandwidth(wm) <= 1145 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1146 return true; 1147 else 1148 return false; 1149 } 1150 1151 /** 1152 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1153 * average and available bandwidth 1154 * 1155 * @wm: watermark calculation data 1156 * 1157 * Check if the display average bandwidth fits in the display 1158 * available bandwidth (CIK). 1159 * Used for display watermark bandwidth calculations 1160 * Returns true if the display fits, false if not. 1161 */ 1162 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1163 { 1164 if (dce_v11_0_average_bandwidth(wm) <= 1165 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1166 return true; 1167 else 1168 return false; 1169 } 1170 1171 /** 1172 * dce_v11_0_check_latency_hiding - check latency hiding 1173 * 1174 * @wm: watermark calculation data 1175 * 1176 * Check latency hiding (CIK). 1177 * Used for display watermark bandwidth calculations 1178 * Returns true if the display fits, false if not. 1179 */ 1180 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1181 { 1182 u32 lb_partitions = wm->lb_size / wm->src_width; 1183 u32 line_time = wm->active_time + wm->blank_time; 1184 u32 latency_tolerant_lines; 1185 u32 latency_hiding; 1186 fixed20_12 a; 1187 1188 a.full = dfixed_const(1); 1189 if (wm->vsc.full > a.full) 1190 latency_tolerant_lines = 1; 1191 else { 1192 if (lb_partitions <= (wm->vtaps + 1)) 1193 latency_tolerant_lines = 1; 1194 else 1195 latency_tolerant_lines = 2; 1196 } 1197 1198 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1199 1200 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1201 return true; 1202 else 1203 return false; 1204 } 1205 1206 /** 1207 * dce_v11_0_program_watermarks - program display watermarks 1208 * 1209 * @adev: amdgpu_device pointer 1210 * @amdgpu_crtc: the selected display controller 1211 * @lb_size: line buffer size 1212 * @num_heads: number of display controllers in use 1213 * 1214 * Calculate and program the display watermarks for the 1215 * selected display controller (CIK). 1216 */ 1217 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1218 struct amdgpu_crtc *amdgpu_crtc, 1219 u32 lb_size, u32 num_heads) 1220 { 1221 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1222 struct dce10_wm_params wm_low, wm_high; 1223 u32 pixel_period; 1224 u32 line_time = 0; 1225 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1226 u32 tmp, wm_mask; 1227 1228 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1229 pixel_period = 1000000 / (u32)mode->clock; 1230 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1231 1232 /* watermark for high clocks */ 1233 if (adev->pm.dpm_enabled) { 1234 wm_high.yclk = 1235 amdgpu_dpm_get_mclk(adev, false) * 10; 1236 wm_high.sclk = 1237 amdgpu_dpm_get_sclk(adev, false) * 10; 1238 } else { 1239 wm_high.yclk = adev->pm.current_mclk * 10; 1240 wm_high.sclk = adev->pm.current_sclk * 10; 1241 } 1242 1243 wm_high.disp_clk = mode->clock; 1244 wm_high.src_width = mode->crtc_hdisplay; 1245 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1246 wm_high.blank_time = line_time - wm_high.active_time; 1247 wm_high.interlaced = false; 1248 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1249 wm_high.interlaced = true; 1250 wm_high.vsc = amdgpu_crtc->vsc; 1251 wm_high.vtaps = 1; 1252 if (amdgpu_crtc->rmx_type != RMX_OFF) 1253 wm_high.vtaps = 2; 1254 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1255 wm_high.lb_size = lb_size; 1256 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1257 wm_high.num_heads = num_heads; 1258 1259 /* set for high clocks */ 1260 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1261 1262 /* possibly force display priority to high */ 1263 /* should really do this at mode validation time... */ 1264 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1265 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1266 !dce_v11_0_check_latency_hiding(&wm_high) || 1267 (adev->mode_info.disp_priority == 2)) { 1268 DRM_DEBUG_KMS("force priority to high\n"); 1269 } 1270 1271 /* watermark for low clocks */ 1272 if (adev->pm.dpm_enabled) { 1273 wm_low.yclk = 1274 amdgpu_dpm_get_mclk(adev, true) * 10; 1275 wm_low.sclk = 1276 amdgpu_dpm_get_sclk(adev, true) * 10; 1277 } else { 1278 wm_low.yclk = adev->pm.current_mclk * 10; 1279 wm_low.sclk = adev->pm.current_sclk * 10; 1280 } 1281 1282 wm_low.disp_clk = mode->clock; 1283 wm_low.src_width = mode->crtc_hdisplay; 1284 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1285 wm_low.blank_time = line_time - wm_low.active_time; 1286 wm_low.interlaced = false; 1287 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1288 wm_low.interlaced = true; 1289 wm_low.vsc = amdgpu_crtc->vsc; 1290 wm_low.vtaps = 1; 1291 if (amdgpu_crtc->rmx_type != RMX_OFF) 1292 wm_low.vtaps = 2; 1293 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1294 wm_low.lb_size = lb_size; 1295 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1296 wm_low.num_heads = num_heads; 1297 1298 /* set for low clocks */ 1299 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1300 1301 /* possibly force display priority to high */ 1302 /* should really do this at mode validation time... */ 1303 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1304 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1305 !dce_v11_0_check_latency_hiding(&wm_low) || 1306 (adev->mode_info.disp_priority == 2)) { 1307 DRM_DEBUG_KMS("force priority to high\n"); 1308 } 1309 } 1310 1311 /* select wm A */ 1312 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1313 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1314 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1315 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1316 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1317 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1318 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1319 /* select wm B */ 1320 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1321 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1322 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1323 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1324 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1325 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1326 /* restore original selection */ 1327 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1328 1329 /* save values for DPM */ 1330 amdgpu_crtc->line_time = line_time; 1331 amdgpu_crtc->wm_high = latency_watermark_a; 1332 amdgpu_crtc->wm_low = latency_watermark_b; 1333 } 1334 1335 /** 1336 * dce_v11_0_bandwidth_update - program display watermarks 1337 * 1338 * @adev: amdgpu_device pointer 1339 * 1340 * Calculate and program the display watermarks and line 1341 * buffer allocation (CIK). 1342 */ 1343 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1344 { 1345 struct drm_display_mode *mode = NULL; 1346 u32 num_heads = 0, lb_size; 1347 int i; 1348 1349 amdgpu_update_display_priority(adev); 1350 1351 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1352 if (adev->mode_info.crtcs[i]->base.enabled) 1353 num_heads++; 1354 } 1355 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1356 mode = &adev->mode_info.crtcs[i]->base.mode; 1357 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1358 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1359 lb_size, num_heads); 1360 } 1361 } 1362 1363 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1364 { 1365 int i; 1366 u32 offset, tmp; 1367 1368 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1369 offset = adev->mode_info.audio.pin[i].offset; 1370 tmp = RREG32_AUDIO_ENDPT(offset, 1371 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1372 if (((tmp & 1373 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1374 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1375 adev->mode_info.audio.pin[i].connected = false; 1376 else 1377 adev->mode_info.audio.pin[i].connected = true; 1378 } 1379 } 1380 1381 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1382 { 1383 int i; 1384 1385 dce_v11_0_audio_get_connected_pins(adev); 1386 1387 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1388 if (adev->mode_info.audio.pin[i].connected) 1389 return &adev->mode_info.audio.pin[i]; 1390 } 1391 DRM_ERROR("No connected audio pins found!\n"); 1392 return NULL; 1393 } 1394 1395 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1396 { 1397 struct amdgpu_device *adev = encoder->dev->dev_private; 1398 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1399 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1400 u32 tmp; 1401 1402 if (!dig || !dig->afmt || !dig->afmt->pin) 1403 return; 1404 1405 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1406 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1407 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1408 } 1409 1410 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1411 struct drm_display_mode *mode) 1412 { 1413 struct amdgpu_device *adev = encoder->dev->dev_private; 1414 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1415 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1416 struct drm_connector *connector; 1417 struct amdgpu_connector *amdgpu_connector = NULL; 1418 u32 tmp; 1419 int interlace = 0; 1420 1421 if (!dig || !dig->afmt || !dig->afmt->pin) 1422 return; 1423 1424 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1425 if (connector->encoder == encoder) { 1426 amdgpu_connector = to_amdgpu_connector(connector); 1427 break; 1428 } 1429 } 1430 1431 if (!amdgpu_connector) { 1432 DRM_ERROR("Couldn't find encoder's connector\n"); 1433 return; 1434 } 1435 1436 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1437 interlace = 1; 1438 if (connector->latency_present[interlace]) { 1439 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1440 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1441 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1442 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1443 } else { 1444 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1445 VIDEO_LIPSYNC, 0); 1446 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1447 AUDIO_LIPSYNC, 0); 1448 } 1449 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1450 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1451 } 1452 1453 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1454 { 1455 struct amdgpu_device *adev = encoder->dev->dev_private; 1456 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1457 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1458 struct drm_connector *connector; 1459 struct amdgpu_connector *amdgpu_connector = NULL; 1460 u32 tmp; 1461 u8 *sadb = NULL; 1462 int sad_count; 1463 1464 if (!dig || !dig->afmt || !dig->afmt->pin) 1465 return; 1466 1467 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1468 if (connector->encoder == encoder) { 1469 amdgpu_connector = to_amdgpu_connector(connector); 1470 break; 1471 } 1472 } 1473 1474 if (!amdgpu_connector) { 1475 DRM_ERROR("Couldn't find encoder's connector\n"); 1476 return; 1477 } 1478 1479 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1480 if (sad_count < 0) { 1481 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1482 sad_count = 0; 1483 } 1484 1485 /* program the speaker allocation */ 1486 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1487 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1488 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1489 DP_CONNECTION, 0); 1490 /* set HDMI mode */ 1491 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1492 HDMI_CONNECTION, 1); 1493 if (sad_count) 1494 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1495 SPEAKER_ALLOCATION, sadb[0]); 1496 else 1497 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1498 SPEAKER_ALLOCATION, 5); /* stereo */ 1499 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1500 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1501 1502 kfree(sadb); 1503 } 1504 1505 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1506 { 1507 struct amdgpu_device *adev = encoder->dev->dev_private; 1508 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1509 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1510 struct drm_connector *connector; 1511 struct amdgpu_connector *amdgpu_connector = NULL; 1512 struct cea_sad *sads; 1513 int i, sad_count; 1514 1515 static const u16 eld_reg_to_type[][2] = { 1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1520 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1521 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1522 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1523 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1524 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1525 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1526 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1527 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1528 }; 1529 1530 if (!dig || !dig->afmt || !dig->afmt->pin) 1531 return; 1532 1533 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1534 if (connector->encoder == encoder) { 1535 amdgpu_connector = to_amdgpu_connector(connector); 1536 break; 1537 } 1538 } 1539 1540 if (!amdgpu_connector) { 1541 DRM_ERROR("Couldn't find encoder's connector\n"); 1542 return; 1543 } 1544 1545 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1546 if (sad_count <= 0) { 1547 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1548 return; 1549 } 1550 BUG_ON(!sads); 1551 1552 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1553 u32 tmp = 0; 1554 u8 stereo_freqs = 0; 1555 int max_channels = -1; 1556 int j; 1557 1558 for (j = 0; j < sad_count; j++) { 1559 struct cea_sad *sad = &sads[j]; 1560 1561 if (sad->format == eld_reg_to_type[i][1]) { 1562 if (sad->channels > max_channels) { 1563 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1564 MAX_CHANNELS, sad->channels); 1565 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1566 DESCRIPTOR_BYTE_2, sad->byte2); 1567 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1568 SUPPORTED_FREQUENCIES, sad->freq); 1569 max_channels = sad->channels; 1570 } 1571 1572 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1573 stereo_freqs |= sad->freq; 1574 else 1575 break; 1576 } 1577 } 1578 1579 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1580 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1581 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1582 } 1583 1584 kfree(sads); 1585 } 1586 1587 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1588 struct amdgpu_audio_pin *pin, 1589 bool enable) 1590 { 1591 if (!pin) 1592 return; 1593 1594 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1595 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1596 } 1597 1598 static const u32 pin_offsets[] = 1599 { 1600 AUD0_REGISTER_OFFSET, 1601 AUD1_REGISTER_OFFSET, 1602 AUD2_REGISTER_OFFSET, 1603 AUD3_REGISTER_OFFSET, 1604 AUD4_REGISTER_OFFSET, 1605 AUD5_REGISTER_OFFSET, 1606 AUD6_REGISTER_OFFSET, 1607 }; 1608 1609 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1610 { 1611 int i; 1612 1613 if (!amdgpu_audio) 1614 return 0; 1615 1616 adev->mode_info.audio.enabled = true; 1617 1618 adev->mode_info.audio.num_pins = 7; 1619 1620 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1621 adev->mode_info.audio.pin[i].channels = -1; 1622 adev->mode_info.audio.pin[i].rate = -1; 1623 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1624 adev->mode_info.audio.pin[i].status_bits = 0; 1625 adev->mode_info.audio.pin[i].category_code = 0; 1626 adev->mode_info.audio.pin[i].connected = false; 1627 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1628 adev->mode_info.audio.pin[i].id = i; 1629 /* disable audio. it will be set up later */ 1630 /* XXX remove once we switch to ip funcs */ 1631 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1632 } 1633 1634 return 0; 1635 } 1636 1637 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1638 { 1639 int i; 1640 1641 if (!adev->mode_info.audio.enabled) 1642 return; 1643 1644 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1645 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1646 1647 adev->mode_info.audio.enabled = false; 1648 } 1649 1650 /* 1651 * update the N and CTS parameters for a given pixel clock rate 1652 */ 1653 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1654 { 1655 struct drm_device *dev = encoder->dev; 1656 struct amdgpu_device *adev = dev->dev_private; 1657 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1658 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1659 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1660 u32 tmp; 1661 1662 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1663 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1664 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1665 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1666 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1667 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1668 1669 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1670 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1671 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1672 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1673 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1674 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1675 1676 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1677 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1678 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1679 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1680 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1681 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1682 1683 } 1684 1685 /* 1686 * build a HDMI Video Info Frame 1687 */ 1688 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1689 void *buffer, size_t size) 1690 { 1691 struct drm_device *dev = encoder->dev; 1692 struct amdgpu_device *adev = dev->dev_private; 1693 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1694 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1695 uint8_t *frame = buffer + 3; 1696 uint8_t *header = buffer; 1697 1698 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1699 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1700 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1701 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1702 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1703 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1704 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1705 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1706 } 1707 1708 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1709 { 1710 struct drm_device *dev = encoder->dev; 1711 struct amdgpu_device *adev = dev->dev_private; 1712 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1713 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1714 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1715 u32 dto_phase = 24 * 1000; 1716 u32 dto_modulo = clock; 1717 u32 tmp; 1718 1719 if (!dig || !dig->afmt) 1720 return; 1721 1722 /* XXX two dtos; generally use dto0 for hdmi */ 1723 /* Express [24MHz / target pixel clock] as an exact rational 1724 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1725 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1726 */ 1727 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1728 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1729 amdgpu_crtc->crtc_id); 1730 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1731 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1732 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1733 } 1734 1735 /* 1736 * update the info frames with the data from the current display mode 1737 */ 1738 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1739 struct drm_display_mode *mode) 1740 { 1741 struct drm_device *dev = encoder->dev; 1742 struct amdgpu_device *adev = dev->dev_private; 1743 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1744 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1745 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1746 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1747 struct hdmi_avi_infoframe frame; 1748 ssize_t err; 1749 u32 tmp; 1750 int bpc = 8; 1751 1752 if (!dig || !dig->afmt) 1753 return; 1754 1755 /* Silent, r600_hdmi_enable will raise WARN for us */ 1756 if (!dig->afmt->enabled) 1757 return; 1758 1759 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1760 if (encoder->crtc) { 1761 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1762 bpc = amdgpu_crtc->bpc; 1763 } 1764 1765 /* disable audio prior to setting up hw */ 1766 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1767 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1768 1769 dce_v11_0_audio_set_dto(encoder, mode->clock); 1770 1771 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1772 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1773 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1774 1775 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1776 1777 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1778 switch (bpc) { 1779 case 0: 1780 case 6: 1781 case 8: 1782 case 16: 1783 default: 1784 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1785 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1786 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1787 connector->name, bpc); 1788 break; 1789 case 10: 1790 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1791 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1792 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1793 connector->name); 1794 break; 1795 case 12: 1796 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1797 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1798 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1799 connector->name); 1800 break; 1801 } 1802 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1803 1804 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1805 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1806 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1807 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1808 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1809 1810 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1811 /* enable audio info frames (frames won't be set until audio is enabled) */ 1812 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1813 /* required for audio info values to be updated */ 1814 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1815 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1816 1817 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1818 /* required for audio info values to be updated */ 1819 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1820 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1821 1822 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1823 /* anything other than 0 */ 1824 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1825 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1826 1827 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1828 1829 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1830 /* set the default audio delay */ 1831 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1832 /* should be suffient for all audio modes and small enough for all hblanks */ 1833 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1834 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1835 1836 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1837 /* allow 60958 channel status fields to be updated */ 1838 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1839 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1840 1841 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1842 if (bpc > 8) 1843 /* clear SW CTS value */ 1844 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1845 else 1846 /* select SW CTS value */ 1847 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1848 /* allow hw to sent ACR packets when required */ 1849 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1850 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1851 1852 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1853 1854 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1855 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1856 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1857 1858 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1859 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1860 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1861 1862 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1863 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1864 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1865 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1866 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1867 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1868 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1869 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1870 1871 dce_v11_0_audio_write_speaker_allocation(encoder); 1872 1873 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1874 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1875 1876 dce_v11_0_afmt_audio_select_pin(encoder); 1877 dce_v11_0_audio_write_sad_regs(encoder); 1878 dce_v11_0_audio_write_latency_fields(encoder, mode); 1879 1880 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1881 if (err < 0) { 1882 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1883 return; 1884 } 1885 1886 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1887 if (err < 0) { 1888 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1889 return; 1890 } 1891 1892 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1893 1894 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1895 /* enable AVI info frames */ 1896 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1897 /* required for audio info values to be updated */ 1898 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1899 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1900 1901 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1902 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1903 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1904 1905 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1906 /* send audio packets */ 1907 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1908 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1909 1910 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1911 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1912 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1913 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1914 1915 /* enable audio after to setting up hw */ 1916 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1917 } 1918 1919 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1920 { 1921 struct drm_device *dev = encoder->dev; 1922 struct amdgpu_device *adev = dev->dev_private; 1923 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1924 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1925 1926 if (!dig || !dig->afmt) 1927 return; 1928 1929 /* Silent, r600_hdmi_enable will raise WARN for us */ 1930 if (enable && dig->afmt->enabled) 1931 return; 1932 if (!enable && !dig->afmt->enabled) 1933 return; 1934 1935 if (!enable && dig->afmt->pin) { 1936 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1937 dig->afmt->pin = NULL; 1938 } 1939 1940 dig->afmt->enabled = enable; 1941 1942 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1943 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1944 } 1945 1946 static void dce_v11_0_afmt_init(struct amdgpu_device *adev) 1947 { 1948 int i; 1949 1950 for (i = 0; i < adev->mode_info.num_dig; i++) 1951 adev->mode_info.afmt[i] = NULL; 1952 1953 /* DCE11 has audio blocks tied to DIG encoders */ 1954 for (i = 0; i < adev->mode_info.num_dig; i++) { 1955 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1956 if (adev->mode_info.afmt[i]) { 1957 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1958 adev->mode_info.afmt[i]->id = i; 1959 } 1960 } 1961 } 1962 1963 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1964 { 1965 int i; 1966 1967 for (i = 0; i < adev->mode_info.num_dig; i++) { 1968 kfree(adev->mode_info.afmt[i]); 1969 adev->mode_info.afmt[i] = NULL; 1970 } 1971 } 1972 1973 static const u32 vga_control_regs[6] = 1974 { 1975 mmD1VGA_CONTROL, 1976 mmD2VGA_CONTROL, 1977 mmD3VGA_CONTROL, 1978 mmD4VGA_CONTROL, 1979 mmD5VGA_CONTROL, 1980 mmD6VGA_CONTROL, 1981 }; 1982 1983 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1984 { 1985 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1986 struct drm_device *dev = crtc->dev; 1987 struct amdgpu_device *adev = dev->dev_private; 1988 u32 vga_control; 1989 1990 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1991 if (enable) 1992 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1993 else 1994 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1995 } 1996 1997 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1998 { 1999 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2000 struct drm_device *dev = crtc->dev; 2001 struct amdgpu_device *adev = dev->dev_private; 2002 2003 if (enable) 2004 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2005 else 2006 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2007 } 2008 2009 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 2010 struct drm_framebuffer *fb, 2011 int x, int y, int atomic) 2012 { 2013 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2014 struct drm_device *dev = crtc->dev; 2015 struct amdgpu_device *adev = dev->dev_private; 2016 struct amdgpu_framebuffer *amdgpu_fb; 2017 struct drm_framebuffer *target_fb; 2018 struct drm_gem_object *obj; 2019 struct amdgpu_bo *rbo; 2020 uint64_t fb_location, tiling_flags; 2021 uint32_t fb_format, fb_pitch_pixels; 2022 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2023 u32 pipe_config; 2024 u32 tmp, viewport_w, viewport_h; 2025 int r; 2026 bool bypass_lut = false; 2027 2028 /* no fb bound */ 2029 if (!atomic && !crtc->primary->fb) { 2030 DRM_DEBUG_KMS("No FB bound\n"); 2031 return 0; 2032 } 2033 2034 if (atomic) { 2035 amdgpu_fb = to_amdgpu_framebuffer(fb); 2036 target_fb = fb; 2037 } 2038 else { 2039 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2040 target_fb = crtc->primary->fb; 2041 } 2042 2043 /* If atomic, assume fb object is pinned & idle & fenced and 2044 * just update base pointers 2045 */ 2046 obj = amdgpu_fb->obj; 2047 rbo = gem_to_amdgpu_bo(obj); 2048 r = amdgpu_bo_reserve(rbo, false); 2049 if (unlikely(r != 0)) 2050 return r; 2051 2052 if (atomic) 2053 fb_location = amdgpu_bo_gpu_offset(rbo); 2054 else { 2055 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2056 if (unlikely(r != 0)) { 2057 amdgpu_bo_unreserve(rbo); 2058 return -EINVAL; 2059 } 2060 } 2061 2062 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2063 amdgpu_bo_unreserve(rbo); 2064 2065 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2066 2067 switch (target_fb->pixel_format) { 2068 case DRM_FORMAT_C8: 2069 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2070 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2071 break; 2072 case DRM_FORMAT_XRGB4444: 2073 case DRM_FORMAT_ARGB4444: 2074 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2075 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2076 #ifdef __BIG_ENDIAN 2077 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2078 ENDIAN_8IN16); 2079 #endif 2080 break; 2081 case DRM_FORMAT_XRGB1555: 2082 case DRM_FORMAT_ARGB1555: 2083 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2084 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2085 #ifdef __BIG_ENDIAN 2086 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2087 ENDIAN_8IN16); 2088 #endif 2089 break; 2090 case DRM_FORMAT_BGRX5551: 2091 case DRM_FORMAT_BGRA5551: 2092 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2093 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2094 #ifdef __BIG_ENDIAN 2095 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2096 ENDIAN_8IN16); 2097 #endif 2098 break; 2099 case DRM_FORMAT_RGB565: 2100 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2101 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2102 #ifdef __BIG_ENDIAN 2103 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2104 ENDIAN_8IN16); 2105 #endif 2106 break; 2107 case DRM_FORMAT_XRGB8888: 2108 case DRM_FORMAT_ARGB8888: 2109 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2110 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2111 #ifdef __BIG_ENDIAN 2112 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2113 ENDIAN_8IN32); 2114 #endif 2115 break; 2116 case DRM_FORMAT_XRGB2101010: 2117 case DRM_FORMAT_ARGB2101010: 2118 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2119 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2120 #ifdef __BIG_ENDIAN 2121 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2122 ENDIAN_8IN32); 2123 #endif 2124 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2125 bypass_lut = true; 2126 break; 2127 case DRM_FORMAT_BGRX1010102: 2128 case DRM_FORMAT_BGRA1010102: 2129 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2130 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2131 #ifdef __BIG_ENDIAN 2132 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2133 ENDIAN_8IN32); 2134 #endif 2135 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2136 bypass_lut = true; 2137 break; 2138 default: 2139 DRM_ERROR("Unsupported screen format %s\n", 2140 drm_get_format_name(target_fb->pixel_format)); 2141 return -EINVAL; 2142 } 2143 2144 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2145 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2146 2147 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2148 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2149 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2150 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2151 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2152 2153 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2154 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2155 ARRAY_2D_TILED_THIN1); 2156 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2157 tile_split); 2158 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2159 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2160 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2161 mtaspect); 2162 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2163 ADDR_SURF_MICRO_TILING_DISPLAY); 2164 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2165 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2166 ARRAY_1D_TILED_THIN1); 2167 } 2168 2169 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2170 pipe_config); 2171 2172 dce_v11_0_vga_enable(crtc, false); 2173 2174 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2175 upper_32_bits(fb_location)); 2176 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2177 upper_32_bits(fb_location)); 2178 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2179 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2180 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2181 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2182 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2183 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2184 2185 /* 2186 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2187 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2188 * retain the full precision throughout the pipeline. 2189 */ 2190 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2191 if (bypass_lut) 2192 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2193 else 2194 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2195 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2196 2197 if (bypass_lut) 2198 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2199 2200 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2201 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2202 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2203 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2204 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2205 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2206 2207 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2208 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2209 2210 dce_v11_0_grph_enable(crtc, true); 2211 2212 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2213 target_fb->height); 2214 2215 x &= ~3; 2216 y &= ~1; 2217 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2218 (x << 16) | y); 2219 viewport_w = crtc->mode.hdisplay; 2220 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2221 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2222 (viewport_w << 16) | viewport_h); 2223 2224 /* pageflip setup */ 2225 /* make sure flip is at vb rather than hb */ 2226 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2227 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2228 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2229 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2230 2231 /* set pageflip to happen only at start of vblank interval (front porch) */ 2232 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2233 2234 if (!atomic && fb && fb != crtc->primary->fb) { 2235 amdgpu_fb = to_amdgpu_framebuffer(fb); 2236 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2237 r = amdgpu_bo_reserve(rbo, false); 2238 if (unlikely(r != 0)) 2239 return r; 2240 amdgpu_bo_unpin(rbo); 2241 amdgpu_bo_unreserve(rbo); 2242 } 2243 2244 /* Bytes per pixel may have changed */ 2245 dce_v11_0_bandwidth_update(adev); 2246 2247 return 0; 2248 } 2249 2250 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2251 struct drm_display_mode *mode) 2252 { 2253 struct drm_device *dev = crtc->dev; 2254 struct amdgpu_device *adev = dev->dev_private; 2255 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2256 u32 tmp; 2257 2258 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2259 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2260 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2261 else 2262 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2263 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2264 } 2265 2266 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2267 { 2268 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2269 struct drm_device *dev = crtc->dev; 2270 struct amdgpu_device *adev = dev->dev_private; 2271 int i; 2272 u32 tmp; 2273 2274 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2275 2276 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2277 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2278 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2279 2280 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2281 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2282 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2283 2284 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2285 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2286 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2287 2288 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2289 2290 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2291 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2292 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2293 2294 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2295 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2296 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2297 2298 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2299 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2300 2301 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2302 for (i = 0; i < 256; i++) { 2303 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2304 (amdgpu_crtc->lut_r[i] << 20) | 2305 (amdgpu_crtc->lut_g[i] << 10) | 2306 (amdgpu_crtc->lut_b[i] << 0)); 2307 } 2308 2309 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2310 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2311 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2312 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2313 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2314 2315 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2316 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2317 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2318 2319 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2320 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2321 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2322 2323 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2324 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2325 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2326 2327 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2328 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2329 /* XXX this only needs to be programmed once per crtc at startup, 2330 * not sure where the best place for it is 2331 */ 2332 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2333 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2334 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2335 } 2336 2337 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2338 { 2339 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2340 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2341 2342 switch (amdgpu_encoder->encoder_id) { 2343 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2344 if (dig->linkb) 2345 return 1; 2346 else 2347 return 0; 2348 break; 2349 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2350 if (dig->linkb) 2351 return 3; 2352 else 2353 return 2; 2354 break; 2355 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2356 if (dig->linkb) 2357 return 5; 2358 else 2359 return 4; 2360 break; 2361 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2362 return 6; 2363 break; 2364 default: 2365 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2366 return 0; 2367 } 2368 } 2369 2370 /** 2371 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2372 * 2373 * @crtc: drm crtc 2374 * 2375 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2376 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2377 * monitors a dedicated PPLL must be used. If a particular board has 2378 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2379 * as there is no need to program the PLL itself. If we are not able to 2380 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2381 * avoid messing up an existing monitor. 2382 * 2383 * Asic specific PLL information 2384 * 2385 * DCE 10.x 2386 * Tonga 2387 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2388 * CI 2389 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2390 * 2391 */ 2392 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2393 { 2394 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2395 struct drm_device *dev = crtc->dev; 2396 struct amdgpu_device *adev = dev->dev_private; 2397 u32 pll_in_use; 2398 int pll; 2399 2400 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2401 if (adev->clock.dp_extclk) 2402 /* skip PPLL programming if using ext clock */ 2403 return ATOM_PPLL_INVALID; 2404 else { 2405 /* use the same PPLL for all DP monitors */ 2406 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2407 if (pll != ATOM_PPLL_INVALID) 2408 return pll; 2409 } 2410 } else { 2411 /* use the same PPLL for all monitors with the same clock */ 2412 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2413 if (pll != ATOM_PPLL_INVALID) 2414 return pll; 2415 } 2416 2417 /* XXX need to determine what plls are available on each DCE11 part */ 2418 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2419 if (adev->asic_type == CHIP_CARRIZO) { 2420 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2421 return ATOM_PPLL1; 2422 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2423 return ATOM_PPLL0; 2424 DRM_ERROR("unable to allocate a PPLL\n"); 2425 return ATOM_PPLL_INVALID; 2426 } else { 2427 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2428 return ATOM_PPLL2; 2429 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2430 return ATOM_PPLL1; 2431 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2432 return ATOM_PPLL0; 2433 DRM_ERROR("unable to allocate a PPLL\n"); 2434 return ATOM_PPLL_INVALID; 2435 } 2436 return ATOM_PPLL_INVALID; 2437 } 2438 2439 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2440 { 2441 struct amdgpu_device *adev = crtc->dev->dev_private; 2442 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2443 uint32_t cur_lock; 2444 2445 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2446 if (lock) 2447 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2448 else 2449 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2450 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2451 } 2452 2453 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2454 { 2455 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2456 struct amdgpu_device *adev = crtc->dev->dev_private; 2457 u32 tmp; 2458 2459 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2460 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2461 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2462 } 2463 2464 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2465 { 2466 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2467 struct amdgpu_device *adev = crtc->dev->dev_private; 2468 u32 tmp; 2469 2470 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2471 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2472 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2473 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2474 } 2475 2476 static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, 2477 uint64_t gpu_addr) 2478 { 2479 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2480 struct amdgpu_device *adev = crtc->dev->dev_private; 2481 2482 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2483 upper_32_bits(gpu_addr)); 2484 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2485 lower_32_bits(gpu_addr)); 2486 } 2487 2488 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2489 int x, int y) 2490 { 2491 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2492 struct amdgpu_device *adev = crtc->dev->dev_private; 2493 int xorigin = 0, yorigin = 0; 2494 2495 /* avivo cursor are offset into the total surface */ 2496 x += crtc->x; 2497 y += crtc->y; 2498 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2499 2500 if (x < 0) { 2501 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2502 x = 0; 2503 } 2504 if (y < 0) { 2505 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2506 y = 0; 2507 } 2508 2509 dce_v11_0_lock_cursor(crtc, true); 2510 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2511 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2512 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2513 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2514 dce_v11_0_lock_cursor(crtc, false); 2515 2516 return 0; 2517 } 2518 2519 static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc, 2520 struct drm_file *file_priv, 2521 uint32_t handle, 2522 uint32_t width, 2523 uint32_t height) 2524 { 2525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2526 struct drm_gem_object *obj; 2527 struct amdgpu_bo *robj; 2528 uint64_t gpu_addr; 2529 int ret; 2530 2531 if (!handle) { 2532 /* turn off cursor */ 2533 dce_v11_0_hide_cursor(crtc); 2534 obj = NULL; 2535 goto unpin; 2536 } 2537 2538 if ((width > amdgpu_crtc->max_cursor_width) || 2539 (height > amdgpu_crtc->max_cursor_height)) { 2540 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2541 return -EINVAL; 2542 } 2543 2544 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2545 if (!obj) { 2546 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2547 return -ENOENT; 2548 } 2549 2550 robj = gem_to_amdgpu_bo(obj); 2551 ret = amdgpu_bo_reserve(robj, false); 2552 if (unlikely(ret != 0)) 2553 goto fail; 2554 ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, 2555 0, &gpu_addr); 2556 amdgpu_bo_unreserve(robj); 2557 if (ret) 2558 goto fail; 2559 2560 amdgpu_crtc->cursor_width = width; 2561 amdgpu_crtc->cursor_height = height; 2562 2563 dce_v11_0_lock_cursor(crtc, true); 2564 dce_v11_0_set_cursor(crtc, obj, gpu_addr); 2565 dce_v11_0_show_cursor(crtc); 2566 dce_v11_0_lock_cursor(crtc, false); 2567 2568 unpin: 2569 if (amdgpu_crtc->cursor_bo) { 2570 robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2571 ret = amdgpu_bo_reserve(robj, false); 2572 if (likely(ret == 0)) { 2573 amdgpu_bo_unpin(robj); 2574 amdgpu_bo_unreserve(robj); 2575 } 2576 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2577 } 2578 2579 amdgpu_crtc->cursor_bo = obj; 2580 return 0; 2581 fail: 2582 drm_gem_object_unreference_unlocked(obj); 2583 2584 return ret; 2585 } 2586 2587 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2588 u16 *blue, uint32_t start, uint32_t size) 2589 { 2590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2591 int end = (start + size > 256) ? 256 : start + size, i; 2592 2593 /* userspace palettes are always correct as is */ 2594 for (i = start; i < end; i++) { 2595 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2596 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2597 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2598 } 2599 dce_v11_0_crtc_load_lut(crtc); 2600 } 2601 2602 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2603 { 2604 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2605 2606 drm_crtc_cleanup(crtc); 2607 destroy_workqueue(amdgpu_crtc->pflip_queue); 2608 kfree(amdgpu_crtc); 2609 } 2610 2611 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2612 .cursor_set = dce_v11_0_crtc_cursor_set, 2613 .cursor_move = dce_v11_0_crtc_cursor_move, 2614 .gamma_set = dce_v11_0_crtc_gamma_set, 2615 .set_config = amdgpu_crtc_set_config, 2616 .destroy = dce_v11_0_crtc_destroy, 2617 .page_flip = amdgpu_crtc_page_flip, 2618 }; 2619 2620 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2621 { 2622 struct drm_device *dev = crtc->dev; 2623 struct amdgpu_device *adev = dev->dev_private; 2624 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2625 2626 switch (mode) { 2627 case DRM_MODE_DPMS_ON: 2628 amdgpu_crtc->enabled = true; 2629 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2630 dce_v11_0_vga_enable(crtc, true); 2631 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2632 dce_v11_0_vga_enable(crtc, false); 2633 drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); 2634 dce_v11_0_crtc_load_lut(crtc); 2635 break; 2636 case DRM_MODE_DPMS_STANDBY: 2637 case DRM_MODE_DPMS_SUSPEND: 2638 case DRM_MODE_DPMS_OFF: 2639 drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); 2640 if (amdgpu_crtc->enabled) { 2641 dce_v11_0_vga_enable(crtc, true); 2642 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2643 dce_v11_0_vga_enable(crtc, false); 2644 } 2645 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2646 amdgpu_crtc->enabled = false; 2647 break; 2648 } 2649 /* adjust pm to dpms */ 2650 amdgpu_pm_compute_clocks(adev); 2651 } 2652 2653 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2654 { 2655 /* disable crtc pair power gating before programming */ 2656 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2657 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2658 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2659 } 2660 2661 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2662 { 2663 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2664 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2665 } 2666 2667 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2668 { 2669 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2670 struct drm_device *dev = crtc->dev; 2671 struct amdgpu_device *adev = dev->dev_private; 2672 struct amdgpu_atom_ss ss; 2673 int i; 2674 2675 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2676 if (crtc->primary->fb) { 2677 int r; 2678 struct amdgpu_framebuffer *amdgpu_fb; 2679 struct amdgpu_bo *rbo; 2680 2681 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2682 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2683 r = amdgpu_bo_reserve(rbo, false); 2684 if (unlikely(r)) 2685 DRM_ERROR("failed to reserve rbo before unpin\n"); 2686 else { 2687 amdgpu_bo_unpin(rbo); 2688 amdgpu_bo_unreserve(rbo); 2689 } 2690 } 2691 /* disable the GRPH */ 2692 dce_v11_0_grph_enable(crtc, false); 2693 2694 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2695 2696 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2697 if (adev->mode_info.crtcs[i] && 2698 adev->mode_info.crtcs[i]->enabled && 2699 i != amdgpu_crtc->crtc_id && 2700 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2701 /* one other crtc is using this pll don't turn 2702 * off the pll 2703 */ 2704 goto done; 2705 } 2706 } 2707 2708 switch (amdgpu_crtc->pll_id) { 2709 case ATOM_PPLL0: 2710 case ATOM_PPLL1: 2711 case ATOM_PPLL2: 2712 /* disable the ppll */ 2713 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2714 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2715 break; 2716 default: 2717 break; 2718 } 2719 done: 2720 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2721 amdgpu_crtc->adjusted_clock = 0; 2722 amdgpu_crtc->encoder = NULL; 2723 amdgpu_crtc->connector = NULL; 2724 } 2725 2726 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2727 struct drm_display_mode *mode, 2728 struct drm_display_mode *adjusted_mode, 2729 int x, int y, struct drm_framebuffer *old_fb) 2730 { 2731 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2732 2733 if (!amdgpu_crtc->adjusted_clock) 2734 return -EINVAL; 2735 2736 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2737 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2738 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2739 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2740 amdgpu_atombios_crtc_scaler_setup(crtc); 2741 /* update the hw version fpr dpm */ 2742 amdgpu_crtc->hw_mode = *adjusted_mode; 2743 2744 return 0; 2745 } 2746 2747 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2748 const struct drm_display_mode *mode, 2749 struct drm_display_mode *adjusted_mode) 2750 { 2751 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2752 struct drm_device *dev = crtc->dev; 2753 struct drm_encoder *encoder; 2754 2755 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2756 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2757 if (encoder->crtc == crtc) { 2758 amdgpu_crtc->encoder = encoder; 2759 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2760 break; 2761 } 2762 } 2763 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2764 amdgpu_crtc->encoder = NULL; 2765 amdgpu_crtc->connector = NULL; 2766 return false; 2767 } 2768 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2769 return false; 2770 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2771 return false; 2772 /* pick pll */ 2773 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2774 /* if we can't get a PPLL for a non-DP encoder, fail */ 2775 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2776 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2777 return false; 2778 2779 return true; 2780 } 2781 2782 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2783 struct drm_framebuffer *old_fb) 2784 { 2785 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2786 } 2787 2788 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2789 struct drm_framebuffer *fb, 2790 int x, int y, enum mode_set_atomic state) 2791 { 2792 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2793 } 2794 2795 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2796 .dpms = dce_v11_0_crtc_dpms, 2797 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2798 .mode_set = dce_v11_0_crtc_mode_set, 2799 .mode_set_base = dce_v11_0_crtc_set_base, 2800 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2801 .prepare = dce_v11_0_crtc_prepare, 2802 .commit = dce_v11_0_crtc_commit, 2803 .load_lut = dce_v11_0_crtc_load_lut, 2804 .disable = dce_v11_0_crtc_disable, 2805 }; 2806 2807 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2808 { 2809 struct amdgpu_crtc *amdgpu_crtc; 2810 int i; 2811 2812 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2813 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2814 if (amdgpu_crtc == NULL) 2815 return -ENOMEM; 2816 2817 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2818 2819 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2820 amdgpu_crtc->crtc_id = index; 2821 amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); 2822 adev->mode_info.crtcs[index] = amdgpu_crtc; 2823 2824 amdgpu_crtc->max_cursor_width = 128; 2825 amdgpu_crtc->max_cursor_height = 128; 2826 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2827 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2828 2829 for (i = 0; i < 256; i++) { 2830 amdgpu_crtc->lut_r[i] = i << 2; 2831 amdgpu_crtc->lut_g[i] = i << 2; 2832 amdgpu_crtc->lut_b[i] = i << 2; 2833 } 2834 2835 switch (amdgpu_crtc->crtc_id) { 2836 case 0: 2837 default: 2838 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2839 break; 2840 case 1: 2841 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2842 break; 2843 case 2: 2844 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2845 break; 2846 case 3: 2847 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2848 break; 2849 case 4: 2850 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2851 break; 2852 case 5: 2853 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2854 break; 2855 } 2856 2857 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2858 amdgpu_crtc->adjusted_clock = 0; 2859 amdgpu_crtc->encoder = NULL; 2860 amdgpu_crtc->connector = NULL; 2861 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2862 2863 return 0; 2864 } 2865 2866 static int dce_v11_0_early_init(struct amdgpu_device *adev) 2867 { 2868 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2869 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2870 2871 dce_v11_0_set_display_funcs(adev); 2872 dce_v11_0_set_irq_funcs(adev); 2873 2874 switch (adev->asic_type) { 2875 case CHIP_CARRIZO: 2876 adev->mode_info.num_crtc = 4; 2877 adev->mode_info.num_hpd = 6; 2878 adev->mode_info.num_dig = 9; 2879 break; 2880 default: 2881 /* FIXME: not supported yet */ 2882 return -EINVAL; 2883 } 2884 2885 return 0; 2886 } 2887 2888 static int dce_v11_0_sw_init(struct amdgpu_device *adev) 2889 { 2890 int r, i; 2891 2892 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2893 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2894 if (r) 2895 return r; 2896 } 2897 2898 for (i = 8; i < 20; i += 2) { 2899 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2900 if (r) 2901 return r; 2902 } 2903 2904 /* HPD hotplug */ 2905 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2906 if (r) 2907 return r; 2908 2909 adev->mode_info.mode_config_initialized = true; 2910 2911 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2912 2913 adev->ddev->mode_config.max_width = 16384; 2914 adev->ddev->mode_config.max_height = 16384; 2915 2916 adev->ddev->mode_config.preferred_depth = 24; 2917 adev->ddev->mode_config.prefer_shadow = 1; 2918 2919 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2920 2921 r = amdgpu_modeset_create_props(adev); 2922 if (r) 2923 return r; 2924 2925 adev->ddev->mode_config.max_width = 16384; 2926 adev->ddev->mode_config.max_height = 16384; 2927 2928 /* allocate crtcs */ 2929 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2930 r = dce_v11_0_crtc_init(adev, i); 2931 if (r) 2932 return r; 2933 } 2934 2935 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2936 amdgpu_print_display_setup(adev->ddev); 2937 else 2938 return -EINVAL; 2939 2940 /* setup afmt */ 2941 dce_v11_0_afmt_init(adev); 2942 2943 r = dce_v11_0_audio_init(adev); 2944 if (r) 2945 return r; 2946 2947 drm_kms_helper_poll_init(adev->ddev); 2948 2949 return r; 2950 } 2951 2952 static int dce_v11_0_sw_fini(struct amdgpu_device *adev) 2953 { 2954 kfree(adev->mode_info.bios_hardcoded_edid); 2955 2956 drm_kms_helper_poll_fini(adev->ddev); 2957 2958 dce_v11_0_audio_fini(adev); 2959 2960 dce_v11_0_afmt_fini(adev); 2961 2962 adev->mode_info.mode_config_initialized = false; 2963 2964 return 0; 2965 } 2966 2967 static int dce_v11_0_hw_init(struct amdgpu_device *adev) 2968 { 2969 int i; 2970 2971 dce_v11_0_init_golden_registers(adev); 2972 2973 /* init dig PHYs, disp eng pll */ 2974 amdgpu_atombios_encoder_init_dig(adev); 2975 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2976 2977 /* initialize hpd */ 2978 dce_v11_0_hpd_init(adev); 2979 2980 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2981 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2982 } 2983 2984 return 0; 2985 } 2986 2987 static int dce_v11_0_hw_fini(struct amdgpu_device *adev) 2988 { 2989 int i; 2990 2991 dce_v11_0_hpd_fini(adev); 2992 2993 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2994 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2995 } 2996 2997 return 0; 2998 } 2999 3000 static int dce_v11_0_suspend(struct amdgpu_device *adev) 3001 { 3002 struct drm_connector *connector; 3003 3004 drm_kms_helper_poll_disable(adev->ddev); 3005 3006 /* turn off display hw */ 3007 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { 3008 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 3009 } 3010 3011 amdgpu_atombios_scratch_regs_save(adev); 3012 3013 dce_v11_0_hpd_fini(adev); 3014 3015 return 0; 3016 } 3017 3018 static int dce_v11_0_resume(struct amdgpu_device *adev) 3019 { 3020 struct drm_connector *connector; 3021 3022 dce_v11_0_init_golden_registers(adev); 3023 3024 amdgpu_atombios_scratch_regs_restore(adev); 3025 3026 /* init dig PHYs, disp eng pll */ 3027 amdgpu_atombios_crtc_powergate_init(adev); 3028 amdgpu_atombios_encoder_init_dig(adev); 3029 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3030 /* turn on the BL */ 3031 if (adev->mode_info.bl_encoder) { 3032 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3033 adev->mode_info.bl_encoder); 3034 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3035 bl_level); 3036 } 3037 3038 /* initialize hpd */ 3039 dce_v11_0_hpd_init(adev); 3040 3041 /* blat the mode back in */ 3042 drm_helper_resume_force_mode(adev->ddev); 3043 /* turn on display hw */ 3044 list_for_each_entry(connector, &adev->ddev->mode_config.connector_list, head) { 3045 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 3046 } 3047 3048 drm_kms_helper_poll_enable(adev->ddev); 3049 3050 return 0; 3051 } 3052 3053 static bool dce_v11_0_is_idle(struct amdgpu_device *adev) 3054 { 3055 /* XXX todo */ 3056 return true; 3057 } 3058 3059 static int dce_v11_0_wait_for_idle(struct amdgpu_device *adev) 3060 { 3061 /* XXX todo */ 3062 return 0; 3063 } 3064 3065 static void dce_v11_0_print_status(struct amdgpu_device *adev) 3066 { 3067 dev_info(adev->dev, "DCE 10.x registers\n"); 3068 /* XXX todo */ 3069 } 3070 3071 static int dce_v11_0_soft_reset(struct amdgpu_device *adev) 3072 { 3073 u32 srbm_soft_reset = 0, tmp; 3074 3075 if (dce_v11_0_is_display_hung(adev)) 3076 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3077 3078 if (srbm_soft_reset) { 3079 dce_v11_0_print_status(adev); 3080 3081 tmp = RREG32(mmSRBM_SOFT_RESET); 3082 tmp |= srbm_soft_reset; 3083 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3084 WREG32(mmSRBM_SOFT_RESET, tmp); 3085 tmp = RREG32(mmSRBM_SOFT_RESET); 3086 3087 udelay(50); 3088 3089 tmp &= ~srbm_soft_reset; 3090 WREG32(mmSRBM_SOFT_RESET, tmp); 3091 tmp = RREG32(mmSRBM_SOFT_RESET); 3092 3093 /* Wait a little for things to settle down */ 3094 udelay(50); 3095 dce_v11_0_print_status(adev); 3096 } 3097 return 0; 3098 } 3099 3100 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3101 int crtc, 3102 enum amdgpu_interrupt_state state) 3103 { 3104 u32 lb_interrupt_mask; 3105 3106 if (crtc >= adev->mode_info.num_crtc) { 3107 DRM_DEBUG("invalid crtc %d\n", crtc); 3108 return; 3109 } 3110 3111 switch (state) { 3112 case AMDGPU_IRQ_STATE_DISABLE: 3113 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3114 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3115 VBLANK_INTERRUPT_MASK, 0); 3116 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3117 break; 3118 case AMDGPU_IRQ_STATE_ENABLE: 3119 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3120 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3121 VBLANK_INTERRUPT_MASK, 1); 3122 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3123 break; 3124 default: 3125 break; 3126 } 3127 } 3128 3129 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3130 int crtc, 3131 enum amdgpu_interrupt_state state) 3132 { 3133 u32 lb_interrupt_mask; 3134 3135 if (crtc >= adev->mode_info.num_crtc) { 3136 DRM_DEBUG("invalid crtc %d\n", crtc); 3137 return; 3138 } 3139 3140 switch (state) { 3141 case AMDGPU_IRQ_STATE_DISABLE: 3142 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3143 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3144 VLINE_INTERRUPT_MASK, 0); 3145 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3146 break; 3147 case AMDGPU_IRQ_STATE_ENABLE: 3148 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3149 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3150 VLINE_INTERRUPT_MASK, 1); 3151 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3152 break; 3153 default: 3154 break; 3155 } 3156 } 3157 3158 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3159 struct amdgpu_irq_src *source, 3160 unsigned hpd, 3161 enum amdgpu_interrupt_state state) 3162 { 3163 u32 tmp; 3164 3165 if (hpd >= adev->mode_info.num_hpd) { 3166 DRM_DEBUG("invalid hdp %d\n", hpd); 3167 return 0; 3168 } 3169 3170 switch (state) { 3171 case AMDGPU_IRQ_STATE_DISABLE: 3172 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3173 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3174 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3175 break; 3176 case AMDGPU_IRQ_STATE_ENABLE: 3177 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3178 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3179 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3180 break; 3181 default: 3182 break; 3183 } 3184 3185 return 0; 3186 } 3187 3188 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3189 struct amdgpu_irq_src *source, 3190 unsigned type, 3191 enum amdgpu_interrupt_state state) 3192 { 3193 switch (type) { 3194 case AMDGPU_CRTC_IRQ_VBLANK1: 3195 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3196 break; 3197 case AMDGPU_CRTC_IRQ_VBLANK2: 3198 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3199 break; 3200 case AMDGPU_CRTC_IRQ_VBLANK3: 3201 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3202 break; 3203 case AMDGPU_CRTC_IRQ_VBLANK4: 3204 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3205 break; 3206 case AMDGPU_CRTC_IRQ_VBLANK5: 3207 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3208 break; 3209 case AMDGPU_CRTC_IRQ_VBLANK6: 3210 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3211 break; 3212 case AMDGPU_CRTC_IRQ_VLINE1: 3213 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3214 break; 3215 case AMDGPU_CRTC_IRQ_VLINE2: 3216 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3217 break; 3218 case AMDGPU_CRTC_IRQ_VLINE3: 3219 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3220 break; 3221 case AMDGPU_CRTC_IRQ_VLINE4: 3222 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3223 break; 3224 case AMDGPU_CRTC_IRQ_VLINE5: 3225 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3226 break; 3227 case AMDGPU_CRTC_IRQ_VLINE6: 3228 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3229 break; 3230 default: 3231 break; 3232 } 3233 return 0; 3234 } 3235 3236 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3237 struct amdgpu_irq_src *src, 3238 unsigned type, 3239 enum amdgpu_interrupt_state state) 3240 { 3241 u32 reg, reg_block; 3242 /* now deal with page flip IRQ */ 3243 switch (type) { 3244 case AMDGPU_PAGEFLIP_IRQ_D1: 3245 reg_block = CRTC0_REGISTER_OFFSET; 3246 break; 3247 case AMDGPU_PAGEFLIP_IRQ_D2: 3248 reg_block = CRTC1_REGISTER_OFFSET; 3249 break; 3250 case AMDGPU_PAGEFLIP_IRQ_D3: 3251 reg_block = CRTC2_REGISTER_OFFSET; 3252 break; 3253 case AMDGPU_PAGEFLIP_IRQ_D4: 3254 reg_block = CRTC3_REGISTER_OFFSET; 3255 break; 3256 case AMDGPU_PAGEFLIP_IRQ_D5: 3257 reg_block = CRTC4_REGISTER_OFFSET; 3258 break; 3259 case AMDGPU_PAGEFLIP_IRQ_D6: 3260 reg_block = CRTC5_REGISTER_OFFSET; 3261 break; 3262 default: 3263 DRM_ERROR("invalid pageflip crtc %d\n", type); 3264 return -EINVAL; 3265 } 3266 3267 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); 3268 if (state == AMDGPU_IRQ_STATE_DISABLE) 3269 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3270 else 3271 WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3272 3273 return 0; 3274 } 3275 3276 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3277 struct amdgpu_irq_src *source, 3278 struct amdgpu_iv_entry *entry) 3279 { 3280 int reg_block; 3281 unsigned long flags; 3282 unsigned crtc_id; 3283 struct amdgpu_crtc *amdgpu_crtc; 3284 struct amdgpu_flip_work *works; 3285 3286 crtc_id = (entry->src_id - 8) >> 1; 3287 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3288 3289 /* ack the interrupt */ 3290 switch(crtc_id){ 3291 case AMDGPU_PAGEFLIP_IRQ_D1: 3292 reg_block = CRTC0_REGISTER_OFFSET; 3293 break; 3294 case AMDGPU_PAGEFLIP_IRQ_D2: 3295 reg_block = CRTC1_REGISTER_OFFSET; 3296 break; 3297 case AMDGPU_PAGEFLIP_IRQ_D3: 3298 reg_block = CRTC2_REGISTER_OFFSET; 3299 break; 3300 case AMDGPU_PAGEFLIP_IRQ_D4: 3301 reg_block = CRTC3_REGISTER_OFFSET; 3302 break; 3303 case AMDGPU_PAGEFLIP_IRQ_D5: 3304 reg_block = CRTC4_REGISTER_OFFSET; 3305 break; 3306 case AMDGPU_PAGEFLIP_IRQ_D6: 3307 reg_block = CRTC5_REGISTER_OFFSET; 3308 break; 3309 default: 3310 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3311 return -EINVAL; 3312 } 3313 3314 if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3315 WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3316 3317 /* IRQ could occur when in initial stage */ 3318 if(amdgpu_crtc == NULL) 3319 return 0; 3320 3321 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3322 works = amdgpu_crtc->pflip_works; 3323 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3324 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3325 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3326 amdgpu_crtc->pflip_status, 3327 AMDGPU_FLIP_SUBMITTED); 3328 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3329 return 0; 3330 } 3331 3332 /* page flip completed. clean up */ 3333 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3334 amdgpu_crtc->pflip_works = NULL; 3335 3336 /* wakeup usersapce */ 3337 if(works->event) 3338 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3339 3340 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3341 3342 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3343 amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); 3344 queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); 3345 3346 return 0; 3347 } 3348 3349 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3350 int hpd) 3351 { 3352 u32 tmp; 3353 3354 if (hpd >= adev->mode_info.num_hpd) { 3355 DRM_DEBUG("invalid hdp %d\n", hpd); 3356 return; 3357 } 3358 3359 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3360 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3361 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3362 } 3363 3364 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3365 int crtc) 3366 { 3367 u32 tmp; 3368 3369 if (crtc >= adev->mode_info.num_crtc) { 3370 DRM_DEBUG("invalid crtc %d\n", crtc); 3371 return; 3372 } 3373 3374 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3375 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3376 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3377 } 3378 3379 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3380 int crtc) 3381 { 3382 u32 tmp; 3383 3384 if (crtc >= adev->mode_info.num_crtc) { 3385 DRM_DEBUG("invalid crtc %d\n", crtc); 3386 return; 3387 } 3388 3389 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3390 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3391 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3392 } 3393 3394 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3395 struct amdgpu_irq_src *source, 3396 struct amdgpu_iv_entry *entry) 3397 { 3398 unsigned crtc = entry->src_id - 1; 3399 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3400 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3401 3402 switch (entry->src_data) { 3403 case 0: /* vblank */ 3404 if (disp_int & interrupt_status_offsets[crtc].vblank) { 3405 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3406 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3407 drm_handle_vblank(adev->ddev, crtc); 3408 } 3409 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3410 } 3411 break; 3412 case 1: /* vline */ 3413 if (disp_int & interrupt_status_offsets[crtc].vline) { 3414 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3415 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3416 } 3417 break; 3418 default: 3419 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3420 break; 3421 } 3422 3423 return 0; 3424 } 3425 3426 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3427 struct amdgpu_irq_src *source, 3428 struct amdgpu_iv_entry *entry) 3429 { 3430 uint32_t disp_int, mask; 3431 unsigned hpd; 3432 3433 if (entry->src_data >= adev->mode_info.num_hpd) { 3434 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3435 return 0; 3436 } 3437 3438 hpd = entry->src_data; 3439 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3440 mask = interrupt_status_offsets[hpd].hpd; 3441 3442 if (disp_int & mask) { 3443 dce_v11_0_hpd_int_ack(adev, hpd); 3444 schedule_work(&adev->hotplug_work); 3445 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3446 } 3447 3448 return 0; 3449 } 3450 3451 static int dce_v11_0_set_clockgating_state(struct amdgpu_device *adev, 3452 enum amdgpu_clockgating_state state) 3453 { 3454 return 0; 3455 } 3456 3457 static int dce_v11_0_set_powergating_state(struct amdgpu_device *adev, 3458 enum amdgpu_powergating_state state) 3459 { 3460 return 0; 3461 } 3462 3463 const struct amdgpu_ip_funcs dce_v11_0_ip_funcs = { 3464 .early_init = dce_v11_0_early_init, 3465 .late_init = NULL, 3466 .sw_init = dce_v11_0_sw_init, 3467 .sw_fini = dce_v11_0_sw_fini, 3468 .hw_init = dce_v11_0_hw_init, 3469 .hw_fini = dce_v11_0_hw_fini, 3470 .suspend = dce_v11_0_suspend, 3471 .resume = dce_v11_0_resume, 3472 .is_idle = dce_v11_0_is_idle, 3473 .wait_for_idle = dce_v11_0_wait_for_idle, 3474 .soft_reset = dce_v11_0_soft_reset, 3475 .print_status = dce_v11_0_print_status, 3476 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3477 .set_powergating_state = dce_v11_0_set_powergating_state, 3478 }; 3479 3480 static void 3481 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3482 struct drm_display_mode *mode, 3483 struct drm_display_mode *adjusted_mode) 3484 { 3485 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3486 3487 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3488 3489 /* need to call this here rather than in prepare() since we need some crtc info */ 3490 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3491 3492 /* set scaler clears this on some chips */ 3493 dce_v11_0_set_interleave(encoder->crtc, mode); 3494 3495 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3496 dce_v11_0_afmt_enable(encoder, true); 3497 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3498 } 3499 } 3500 3501 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3502 { 3503 struct amdgpu_device *adev = encoder->dev->dev_private; 3504 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3505 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3506 3507 if ((amdgpu_encoder->active_device & 3508 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3509 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3510 ENCODER_OBJECT_ID_NONE)) { 3511 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3512 if (dig) { 3513 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3514 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3515 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3516 } 3517 } 3518 3519 amdgpu_atombios_scratch_regs_lock(adev, true); 3520 3521 if (connector) { 3522 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3523 3524 /* select the clock/data port if it uses a router */ 3525 if (amdgpu_connector->router.cd_valid) 3526 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3527 3528 /* turn eDP panel on for mode set */ 3529 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3530 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3531 ATOM_TRANSMITTER_ACTION_POWER_ON); 3532 } 3533 3534 /* this is needed for the pll/ss setup to work correctly in some cases */ 3535 amdgpu_atombios_encoder_set_crtc_source(encoder); 3536 /* set up the FMT blocks */ 3537 dce_v11_0_program_fmt(encoder); 3538 } 3539 3540 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3541 { 3542 struct drm_device *dev = encoder->dev; 3543 struct amdgpu_device *adev = dev->dev_private; 3544 3545 /* need to call this here as we need the crtc set up */ 3546 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3547 amdgpu_atombios_scratch_regs_lock(adev, false); 3548 } 3549 3550 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3551 { 3552 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3553 struct amdgpu_encoder_atom_dig *dig; 3554 3555 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3556 3557 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3558 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3559 dce_v11_0_afmt_enable(encoder, false); 3560 dig = amdgpu_encoder->enc_priv; 3561 dig->dig_encoder = -1; 3562 } 3563 amdgpu_encoder->active_device = 0; 3564 } 3565 3566 /* these are handled by the primary encoders */ 3567 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3568 { 3569 3570 } 3571 3572 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3573 { 3574 3575 } 3576 3577 static void 3578 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3579 struct drm_display_mode *mode, 3580 struct drm_display_mode *adjusted_mode) 3581 { 3582 3583 } 3584 3585 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3586 { 3587 3588 } 3589 3590 static void 3591 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3592 { 3593 3594 } 3595 3596 static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder, 3597 const struct drm_display_mode *mode, 3598 struct drm_display_mode *adjusted_mode) 3599 { 3600 return true; 3601 } 3602 3603 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3604 .dpms = dce_v11_0_ext_dpms, 3605 .mode_fixup = dce_v11_0_ext_mode_fixup, 3606 .prepare = dce_v11_0_ext_prepare, 3607 .mode_set = dce_v11_0_ext_mode_set, 3608 .commit = dce_v11_0_ext_commit, 3609 .disable = dce_v11_0_ext_disable, 3610 /* no detect for TMDS/LVDS yet */ 3611 }; 3612 3613 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3614 .dpms = amdgpu_atombios_encoder_dpms, 3615 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3616 .prepare = dce_v11_0_encoder_prepare, 3617 .mode_set = dce_v11_0_encoder_mode_set, 3618 .commit = dce_v11_0_encoder_commit, 3619 .disable = dce_v11_0_encoder_disable, 3620 .detect = amdgpu_atombios_encoder_dig_detect, 3621 }; 3622 3623 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3624 .dpms = amdgpu_atombios_encoder_dpms, 3625 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3626 .prepare = dce_v11_0_encoder_prepare, 3627 .mode_set = dce_v11_0_encoder_mode_set, 3628 .commit = dce_v11_0_encoder_commit, 3629 .detect = amdgpu_atombios_encoder_dac_detect, 3630 }; 3631 3632 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3633 { 3634 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3635 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3636 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3637 kfree(amdgpu_encoder->enc_priv); 3638 drm_encoder_cleanup(encoder); 3639 kfree(amdgpu_encoder); 3640 } 3641 3642 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3643 .destroy = dce_v11_0_encoder_destroy, 3644 }; 3645 3646 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3647 uint32_t encoder_enum, 3648 uint32_t supported_device, 3649 u16 caps) 3650 { 3651 struct drm_device *dev = adev->ddev; 3652 struct drm_encoder *encoder; 3653 struct amdgpu_encoder *amdgpu_encoder; 3654 3655 /* see if we already added it */ 3656 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3657 amdgpu_encoder = to_amdgpu_encoder(encoder); 3658 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3659 amdgpu_encoder->devices |= supported_device; 3660 return; 3661 } 3662 3663 } 3664 3665 /* add a new one */ 3666 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3667 if (!amdgpu_encoder) 3668 return; 3669 3670 encoder = &amdgpu_encoder->base; 3671 switch (adev->mode_info.num_crtc) { 3672 case 1: 3673 encoder->possible_crtcs = 0x1; 3674 break; 3675 case 2: 3676 default: 3677 encoder->possible_crtcs = 0x3; 3678 break; 3679 case 4: 3680 encoder->possible_crtcs = 0xf; 3681 break; 3682 case 6: 3683 encoder->possible_crtcs = 0x3f; 3684 break; 3685 } 3686 3687 amdgpu_encoder->enc_priv = NULL; 3688 3689 amdgpu_encoder->encoder_enum = encoder_enum; 3690 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3691 amdgpu_encoder->devices = supported_device; 3692 amdgpu_encoder->rmx_type = RMX_OFF; 3693 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3694 amdgpu_encoder->is_ext_encoder = false; 3695 amdgpu_encoder->caps = caps; 3696 3697 switch (amdgpu_encoder->encoder_id) { 3698 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3699 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3700 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3701 DRM_MODE_ENCODER_DAC); 3702 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3703 break; 3704 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3705 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3706 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3707 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3708 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3709 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3710 amdgpu_encoder->rmx_type = RMX_FULL; 3711 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3712 DRM_MODE_ENCODER_LVDS); 3713 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3714 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3715 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3716 DRM_MODE_ENCODER_DAC); 3717 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3718 } else { 3719 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3720 DRM_MODE_ENCODER_TMDS); 3721 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3722 } 3723 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3724 break; 3725 case ENCODER_OBJECT_ID_SI170B: 3726 case ENCODER_OBJECT_ID_CH7303: 3727 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3728 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3729 case ENCODER_OBJECT_ID_TITFP513: 3730 case ENCODER_OBJECT_ID_VT1623: 3731 case ENCODER_OBJECT_ID_HDMI_SI1930: 3732 case ENCODER_OBJECT_ID_TRAVIS: 3733 case ENCODER_OBJECT_ID_NUTMEG: 3734 /* these are handled by the primary encoders */ 3735 amdgpu_encoder->is_ext_encoder = true; 3736 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3737 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3738 DRM_MODE_ENCODER_LVDS); 3739 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3740 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3741 DRM_MODE_ENCODER_DAC); 3742 else 3743 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3744 DRM_MODE_ENCODER_TMDS); 3745 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3746 break; 3747 } 3748 } 3749 3750 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3751 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3752 .bandwidth_update = &dce_v11_0_bandwidth_update, 3753 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3754 .vblank_wait = &dce_v11_0_vblank_wait, 3755 .is_display_hung = &dce_v11_0_is_display_hung, 3756 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3757 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3758 .hpd_sense = &dce_v11_0_hpd_sense, 3759 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3760 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3761 .page_flip = &dce_v11_0_page_flip, 3762 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3763 .add_encoder = &dce_v11_0_encoder_add, 3764 .add_connector = &amdgpu_connector_add, 3765 .stop_mc_access = &dce_v11_0_stop_mc_access, 3766 .resume_mc_access = &dce_v11_0_resume_mc_access, 3767 }; 3768 3769 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3770 { 3771 if (adev->mode_info.funcs == NULL) 3772 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3773 } 3774 3775 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3776 .set = dce_v11_0_set_crtc_irq_state, 3777 .process = dce_v11_0_crtc_irq, 3778 }; 3779 3780 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3781 .set = dce_v11_0_set_pageflip_irq_state, 3782 .process = dce_v11_0_pageflip_irq, 3783 }; 3784 3785 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3786 .set = dce_v11_0_set_hpd_irq_state, 3787 .process = dce_v11_0_hpd_irq, 3788 }; 3789 3790 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3791 { 3792 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3793 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3794 3795 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3796 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3797 3798 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3799 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3800 } 3801