1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drm_fourcc.h> 25 #include <drm/drm_modeset_helper.h> 26 #include <drm/drm_modeset_helper_vtables.h> 27 #include <drm/drm_vblank.h> 28 29 #include "amdgpu.h" 30 #include "amdgpu_pm.h" 31 #include "amdgpu_i2c.h" 32 #include "vid.h" 33 #include "atom.h" 34 #include "amdgpu_atombios.h" 35 #include "atombios_crtc.h" 36 #include "atombios_encoders.h" 37 #include "amdgpu_pll.h" 38 #include "amdgpu_connectors.h" 39 #include "amdgpu_display.h" 40 #include "dce_v11_0.h" 41 42 #include "dce/dce_11_0_d.h" 43 #include "dce/dce_11_0_sh_mask.h" 44 #include "dce/dce_11_0_enum.h" 45 #include "oss/oss_3_0_d.h" 46 #include "oss/oss_3_0_sh_mask.h" 47 #include "gmc/gmc_8_1_d.h" 48 #include "gmc/gmc_8_1_sh_mask.h" 49 50 #include "ivsrcid/ivsrcid_vislands30.h" 51 52 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 53 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 54 55 static const u32 crtc_offsets[] = 56 { 57 CRTC0_REGISTER_OFFSET, 58 CRTC1_REGISTER_OFFSET, 59 CRTC2_REGISTER_OFFSET, 60 CRTC3_REGISTER_OFFSET, 61 CRTC4_REGISTER_OFFSET, 62 CRTC5_REGISTER_OFFSET, 63 CRTC6_REGISTER_OFFSET 64 }; 65 66 static const u32 hpd_offsets[] = 67 { 68 HPD0_REGISTER_OFFSET, 69 HPD1_REGISTER_OFFSET, 70 HPD2_REGISTER_OFFSET, 71 HPD3_REGISTER_OFFSET, 72 HPD4_REGISTER_OFFSET, 73 HPD5_REGISTER_OFFSET 74 }; 75 76 static const uint32_t dig_offsets[] = { 77 DIG0_REGISTER_OFFSET, 78 DIG1_REGISTER_OFFSET, 79 DIG2_REGISTER_OFFSET, 80 DIG3_REGISTER_OFFSET, 81 DIG4_REGISTER_OFFSET, 82 DIG5_REGISTER_OFFSET, 83 DIG6_REGISTER_OFFSET, 84 DIG7_REGISTER_OFFSET, 85 DIG8_REGISTER_OFFSET 86 }; 87 88 static const struct { 89 uint32_t reg; 90 uint32_t vblank; 91 uint32_t vline; 92 uint32_t hpd; 93 94 } interrupt_status_offsets[] = { { 95 .reg = mmDISP_INTERRUPT_STATUS, 96 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 97 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 98 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 99 }, { 100 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 101 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 102 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 103 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 104 }, { 105 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 106 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 107 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 108 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 109 }, { 110 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 111 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 112 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 113 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 114 }, { 115 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 116 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 117 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 118 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 119 }, { 120 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 121 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 122 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 123 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 124 } }; 125 126 static const u32 cz_golden_settings_a11[] = 127 { 128 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 129 mmFBC_MISC, 0x1f311fff, 0x14300000, 130 }; 131 132 static const u32 cz_mgcg_cgcg_init[] = 133 { 134 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 135 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 136 }; 137 138 static const u32 stoney_golden_settings_a11[] = 139 { 140 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 141 mmFBC_MISC, 0x1f311fff, 0x14302000, 142 }; 143 144 static const u32 polaris11_golden_settings_a11[] = 145 { 146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 148 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 149 mmFBC_MISC, 0x9f313fff, 0x14302008, 150 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 151 }; 152 153 static const u32 polaris10_golden_settings_a11[] = 154 { 155 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 156 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 157 mmFBC_MISC, 0x9f313fff, 0x14302008, 158 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 159 }; 160 161 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 162 { 163 switch (adev->asic_type) { 164 case CHIP_CARRIZO: 165 amdgpu_device_program_register_sequence(adev, 166 cz_mgcg_cgcg_init, 167 ARRAY_SIZE(cz_mgcg_cgcg_init)); 168 amdgpu_device_program_register_sequence(adev, 169 cz_golden_settings_a11, 170 ARRAY_SIZE(cz_golden_settings_a11)); 171 break; 172 case CHIP_STONEY: 173 amdgpu_device_program_register_sequence(adev, 174 stoney_golden_settings_a11, 175 ARRAY_SIZE(stoney_golden_settings_a11)); 176 break; 177 case CHIP_POLARIS11: 178 case CHIP_POLARIS12: 179 amdgpu_device_program_register_sequence(adev, 180 polaris11_golden_settings_a11, 181 ARRAY_SIZE(polaris11_golden_settings_a11)); 182 break; 183 case CHIP_POLARIS10: 184 case CHIP_VEGAM: 185 amdgpu_device_program_register_sequence(adev, 186 polaris10_golden_settings_a11, 187 ARRAY_SIZE(polaris10_golden_settings_a11)); 188 break; 189 default: 190 break; 191 } 192 } 193 194 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 195 u32 block_offset, u32 reg) 196 { 197 unsigned long flags; 198 u32 r; 199 200 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 201 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 202 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 203 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 204 205 return r; 206 } 207 208 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 209 u32 block_offset, u32 reg, u32 v) 210 { 211 unsigned long flags; 212 213 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 214 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 215 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 216 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 217 } 218 219 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 220 { 221 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 222 return 0; 223 else 224 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 225 } 226 227 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 228 { 229 unsigned i; 230 231 /* Enable pflip interrupts */ 232 for (i = 0; i < adev->mode_info.num_crtc; i++) 233 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 234 } 235 236 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 237 { 238 unsigned i; 239 240 /* Disable pflip interrupts */ 241 for (i = 0; i < adev->mode_info.num_crtc; i++) 242 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 243 } 244 245 /** 246 * dce_v11_0_page_flip - pageflip callback. 247 * 248 * @adev: amdgpu_device pointer 249 * @crtc_id: crtc to cleanup pageflip on 250 * @crtc_base: new address of the crtc (GPU MC address) 251 * @async: asynchronous flip 252 * 253 * Triggers the actual pageflip by updating the primary 254 * surface base address. 255 */ 256 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 257 int crtc_id, u64 crtc_base, bool async) 258 { 259 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 260 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb; 261 u32 tmp; 262 263 /* flip immediate for async, default is vsync */ 264 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 265 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 266 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 267 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 268 /* update pitch */ 269 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, 270 fb->pitches[0] / fb->format->cpp[0]); 271 /* update the scanout addresses */ 272 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 273 upper_32_bits(crtc_base)); 274 /* writing to the low address triggers the update */ 275 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 276 lower_32_bits(crtc_base)); 277 /* post the write */ 278 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 279 } 280 281 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 282 u32 *vbl, u32 *position) 283 { 284 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 285 return -EINVAL; 286 287 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 288 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 289 290 return 0; 291 } 292 293 /** 294 * dce_v11_0_hpd_sense - hpd sense callback. 295 * 296 * @adev: amdgpu_device pointer 297 * @hpd: hpd (hotplug detect) pin 298 * 299 * Checks if a digital monitor is connected (evergreen+). 300 * Returns true if connected, false if not connected. 301 */ 302 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 303 enum amdgpu_hpd_id hpd) 304 { 305 bool connected = false; 306 307 if (hpd >= adev->mode_info.num_hpd) 308 return connected; 309 310 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 311 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 312 connected = true; 313 314 return connected; 315 } 316 317 /** 318 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 319 * 320 * @adev: amdgpu_device pointer 321 * @hpd: hpd (hotplug detect) pin 322 * 323 * Set the polarity of the hpd pin (evergreen+). 324 */ 325 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 326 enum amdgpu_hpd_id hpd) 327 { 328 u32 tmp; 329 bool connected = dce_v11_0_hpd_sense(adev, hpd); 330 331 if (hpd >= adev->mode_info.num_hpd) 332 return; 333 334 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 335 if (connected) 336 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 337 else 338 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 339 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 340 } 341 342 /** 343 * dce_v11_0_hpd_init - hpd setup callback. 344 * 345 * @adev: amdgpu_device pointer 346 * 347 * Setup the hpd pins used by the card (evergreen+). 348 * Enable the pin, set the polarity, and enable the hpd interrupts. 349 */ 350 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 351 { 352 struct drm_device *dev = adev_to_drm(adev); 353 struct drm_connector *connector; 354 struct drm_connector_list_iter iter; 355 u32 tmp; 356 357 drm_connector_list_iter_begin(dev, &iter); 358 drm_for_each_connector_iter(connector, &iter) { 359 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 360 361 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 362 continue; 363 364 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 365 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 366 /* don't try to enable hpd on eDP or LVDS avoid breaking the 367 * aux dp channel on imac and help (but not completely fix) 368 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 369 * also avoid interrupt storms during dpms. 370 */ 371 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 372 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 373 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 374 continue; 375 } 376 377 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 378 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 379 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 380 381 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 382 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 383 DC_HPD_CONNECT_INT_DELAY, 384 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 385 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 386 DC_HPD_DISCONNECT_INT_DELAY, 387 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 388 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 389 390 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 391 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 392 } 393 drm_connector_list_iter_end(&iter); 394 } 395 396 /** 397 * dce_v11_0_hpd_fini - hpd tear down callback. 398 * 399 * @adev: amdgpu_device pointer 400 * 401 * Tear down the hpd pins used by the card (evergreen+). 402 * Disable the hpd interrupts. 403 */ 404 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 405 { 406 struct drm_device *dev = adev_to_drm(adev); 407 struct drm_connector *connector; 408 struct drm_connector_list_iter iter; 409 u32 tmp; 410 411 drm_connector_list_iter_begin(dev, &iter); 412 drm_for_each_connector_iter(connector, &iter) { 413 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 414 415 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 416 continue; 417 418 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 419 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 420 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 421 422 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 423 } 424 drm_connector_list_iter_end(&iter); 425 } 426 427 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 428 { 429 return mmDC_GPIO_HPD_A; 430 } 431 432 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 433 { 434 u32 crtc_hung = 0; 435 u32 crtc_status[6]; 436 u32 i, j, tmp; 437 438 for (i = 0; i < adev->mode_info.num_crtc; i++) { 439 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 440 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 441 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 442 crtc_hung |= (1 << i); 443 } 444 } 445 446 for (j = 0; j < 10; j++) { 447 for (i = 0; i < adev->mode_info.num_crtc; i++) { 448 if (crtc_hung & (1 << i)) { 449 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 450 if (tmp != crtc_status[i]) 451 crtc_hung &= ~(1 << i); 452 } 453 } 454 if (crtc_hung == 0) 455 return false; 456 udelay(100); 457 } 458 459 return true; 460 } 461 462 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 463 bool render) 464 { 465 u32 tmp; 466 467 /* Lockout access through VGA aperture*/ 468 tmp = RREG32(mmVGA_HDP_CONTROL); 469 if (render) 470 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 471 else 472 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 473 WREG32(mmVGA_HDP_CONTROL, tmp); 474 475 /* disable VGA render */ 476 tmp = RREG32(mmVGA_RENDER_CONTROL); 477 if (render) 478 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 479 else 480 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 481 WREG32(mmVGA_RENDER_CONTROL, tmp); 482 } 483 484 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) 485 { 486 int num_crtc = 0; 487 488 switch (adev->asic_type) { 489 case CHIP_CARRIZO: 490 num_crtc = 3; 491 break; 492 case CHIP_STONEY: 493 num_crtc = 2; 494 break; 495 case CHIP_POLARIS10: 496 case CHIP_VEGAM: 497 num_crtc = 6; 498 break; 499 case CHIP_POLARIS11: 500 case CHIP_POLARIS12: 501 num_crtc = 5; 502 break; 503 default: 504 num_crtc = 0; 505 } 506 return num_crtc; 507 } 508 509 void dce_v11_0_disable_dce(struct amdgpu_device *adev) 510 { 511 /*Disable VGA render and enabled crtc, if has DCE engine*/ 512 if (amdgpu_atombios_has_dce_engine_info(adev)) { 513 u32 tmp; 514 int crtc_enabled, i; 515 516 dce_v11_0_set_vga_render_state(adev, false); 517 518 /*Disable crtc*/ 519 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { 520 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 521 CRTC_CONTROL, CRTC_MASTER_EN); 522 if (crtc_enabled) { 523 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 525 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 526 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 527 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 528 } 529 } 530 } 531 } 532 533 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 534 { 535 struct drm_device *dev = encoder->dev; 536 struct amdgpu_device *adev = drm_to_adev(dev); 537 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 538 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 539 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 540 int bpc = 0; 541 u32 tmp = 0; 542 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 543 544 if (connector) { 545 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 546 bpc = amdgpu_connector_get_monitor_bpc(connector); 547 dither = amdgpu_connector->dither; 548 } 549 550 /* LVDS/eDP FMT is set up by atom */ 551 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 552 return; 553 554 /* not needed for analog */ 555 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 556 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 557 return; 558 559 if (bpc == 0) 560 return; 561 562 switch (bpc) { 563 case 6: 564 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 565 /* XXX sort out optimal dither settings */ 566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 570 } else { 571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 573 } 574 break; 575 case 8: 576 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 577 /* XXX sort out optimal dither settings */ 578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 583 } else { 584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 585 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 586 } 587 break; 588 case 10: 589 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 590 /* XXX sort out optimal dither settings */ 591 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 592 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 593 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 596 } else { 597 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 598 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 599 } 600 break; 601 default: 602 /* not needed */ 603 break; 604 } 605 606 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 607 } 608 609 610 /* display watermark setup */ 611 /** 612 * dce_v11_0_line_buffer_adjust - Set up the line buffer 613 * 614 * @adev: amdgpu_device pointer 615 * @amdgpu_crtc: the selected display controller 616 * @mode: the current display mode on the selected display 617 * controller 618 * 619 * Setup up the line buffer allocation for 620 * the selected display controller (CIK). 621 * Returns the line buffer size in pixels. 622 */ 623 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 624 struct amdgpu_crtc *amdgpu_crtc, 625 struct drm_display_mode *mode) 626 { 627 u32 tmp, buffer_alloc, i, mem_cfg; 628 u32 pipe_offset = amdgpu_crtc->crtc_id; 629 /* 630 * Line Buffer Setup 631 * There are 6 line buffers, one for each display controllers. 632 * There are 3 partitions per LB. Select the number of partitions 633 * to enable based on the display width. For display widths larger 634 * than 4096, you need use to use 2 display controllers and combine 635 * them using the stereo blender. 636 */ 637 if (amdgpu_crtc->base.enabled && mode) { 638 if (mode->crtc_hdisplay < 1920) { 639 mem_cfg = 1; 640 buffer_alloc = 2; 641 } else if (mode->crtc_hdisplay < 2560) { 642 mem_cfg = 2; 643 buffer_alloc = 2; 644 } else if (mode->crtc_hdisplay < 4096) { 645 mem_cfg = 0; 646 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 647 } else { 648 DRM_DEBUG_KMS("Mode too big for LB!\n"); 649 mem_cfg = 0; 650 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 651 } 652 } else { 653 mem_cfg = 1; 654 buffer_alloc = 0; 655 } 656 657 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 658 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 659 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 660 661 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 662 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 663 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 664 665 for (i = 0; i < adev->usec_timeout; i++) { 666 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 667 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 668 break; 669 udelay(1); 670 } 671 672 if (amdgpu_crtc->base.enabled && mode) { 673 switch (mem_cfg) { 674 case 0: 675 default: 676 return 4096 * 2; 677 case 1: 678 return 1920 * 2; 679 case 2: 680 return 2560 * 2; 681 } 682 } 683 684 /* controller not enabled, so no lb used */ 685 return 0; 686 } 687 688 /** 689 * cik_get_number_of_dram_channels - get the number of dram channels 690 * 691 * @adev: amdgpu_device pointer 692 * 693 * Look up the number of video ram channels (CIK). 694 * Used for display watermark bandwidth calculations 695 * Returns the number of dram channels 696 */ 697 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 698 { 699 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 700 701 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 702 case 0: 703 default: 704 return 1; 705 case 1: 706 return 2; 707 case 2: 708 return 4; 709 case 3: 710 return 8; 711 case 4: 712 return 3; 713 case 5: 714 return 6; 715 case 6: 716 return 10; 717 case 7: 718 return 12; 719 case 8: 720 return 16; 721 } 722 } 723 724 struct dce10_wm_params { 725 u32 dram_channels; /* number of dram channels */ 726 u32 yclk; /* bandwidth per dram data pin in kHz */ 727 u32 sclk; /* engine clock in kHz */ 728 u32 disp_clk; /* display clock in kHz */ 729 u32 src_width; /* viewport width */ 730 u32 active_time; /* active display time in ns */ 731 u32 blank_time; /* blank time in ns */ 732 bool interlaced; /* mode is interlaced */ 733 fixed20_12 vsc; /* vertical scale ratio */ 734 u32 num_heads; /* number of active crtcs */ 735 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 736 u32 lb_size; /* line buffer allocated to pipe */ 737 u32 vtaps; /* vertical scaler taps */ 738 }; 739 740 /** 741 * dce_v11_0_dram_bandwidth - get the dram bandwidth 742 * 743 * @wm: watermark calculation data 744 * 745 * Calculate the raw dram bandwidth (CIK). 746 * Used for display watermark bandwidth calculations 747 * Returns the dram bandwidth in MBytes/s 748 */ 749 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 750 { 751 /* Calculate raw DRAM Bandwidth */ 752 fixed20_12 dram_efficiency; /* 0.7 */ 753 fixed20_12 yclk, dram_channels, bandwidth; 754 fixed20_12 a; 755 756 a.full = dfixed_const(1000); 757 yclk.full = dfixed_const(wm->yclk); 758 yclk.full = dfixed_div(yclk, a); 759 dram_channels.full = dfixed_const(wm->dram_channels * 4); 760 a.full = dfixed_const(10); 761 dram_efficiency.full = dfixed_const(7); 762 dram_efficiency.full = dfixed_div(dram_efficiency, a); 763 bandwidth.full = dfixed_mul(dram_channels, yclk); 764 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 765 766 return dfixed_trunc(bandwidth); 767 } 768 769 /** 770 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 771 * 772 * @wm: watermark calculation data 773 * 774 * Calculate the dram bandwidth used for display (CIK). 775 * Used for display watermark bandwidth calculations 776 * Returns the dram bandwidth for display in MBytes/s 777 */ 778 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 779 { 780 /* Calculate DRAM Bandwidth and the part allocated to display. */ 781 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 782 fixed20_12 yclk, dram_channels, bandwidth; 783 fixed20_12 a; 784 785 a.full = dfixed_const(1000); 786 yclk.full = dfixed_const(wm->yclk); 787 yclk.full = dfixed_div(yclk, a); 788 dram_channels.full = dfixed_const(wm->dram_channels * 4); 789 a.full = dfixed_const(10); 790 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 791 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 792 bandwidth.full = dfixed_mul(dram_channels, yclk); 793 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 794 795 return dfixed_trunc(bandwidth); 796 } 797 798 /** 799 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 800 * 801 * @wm: watermark calculation data 802 * 803 * Calculate the data return bandwidth used for display (CIK). 804 * Used for display watermark bandwidth calculations 805 * Returns the data return bandwidth in MBytes/s 806 */ 807 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 808 { 809 /* Calculate the display Data return Bandwidth */ 810 fixed20_12 return_efficiency; /* 0.8 */ 811 fixed20_12 sclk, bandwidth; 812 fixed20_12 a; 813 814 a.full = dfixed_const(1000); 815 sclk.full = dfixed_const(wm->sclk); 816 sclk.full = dfixed_div(sclk, a); 817 a.full = dfixed_const(10); 818 return_efficiency.full = dfixed_const(8); 819 return_efficiency.full = dfixed_div(return_efficiency, a); 820 a.full = dfixed_const(32); 821 bandwidth.full = dfixed_mul(a, sclk); 822 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 823 824 return dfixed_trunc(bandwidth); 825 } 826 827 /** 828 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 829 * 830 * @wm: watermark calculation data 831 * 832 * Calculate the dmif bandwidth used for display (CIK). 833 * Used for display watermark bandwidth calculations 834 * Returns the dmif bandwidth in MBytes/s 835 */ 836 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 837 { 838 /* Calculate the DMIF Request Bandwidth */ 839 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 840 fixed20_12 disp_clk, bandwidth; 841 fixed20_12 a, b; 842 843 a.full = dfixed_const(1000); 844 disp_clk.full = dfixed_const(wm->disp_clk); 845 disp_clk.full = dfixed_div(disp_clk, a); 846 a.full = dfixed_const(32); 847 b.full = dfixed_mul(a, disp_clk); 848 849 a.full = dfixed_const(10); 850 disp_clk_request_efficiency.full = dfixed_const(8); 851 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 852 853 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 854 855 return dfixed_trunc(bandwidth); 856 } 857 858 /** 859 * dce_v11_0_available_bandwidth - get the min available bandwidth 860 * 861 * @wm: watermark calculation data 862 * 863 * Calculate the min available bandwidth used for display (CIK). 864 * Used for display watermark bandwidth calculations 865 * Returns the min available bandwidth in MBytes/s 866 */ 867 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 868 { 869 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 870 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 871 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 872 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 873 874 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 875 } 876 877 /** 878 * dce_v11_0_average_bandwidth - get the average available bandwidth 879 * 880 * @wm: watermark calculation data 881 * 882 * Calculate the average available bandwidth used for display (CIK). 883 * Used for display watermark bandwidth calculations 884 * Returns the average available bandwidth in MBytes/s 885 */ 886 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 887 { 888 /* Calculate the display mode Average Bandwidth 889 * DisplayMode should contain the source and destination dimensions, 890 * timing, etc. 891 */ 892 fixed20_12 bpp; 893 fixed20_12 line_time; 894 fixed20_12 src_width; 895 fixed20_12 bandwidth; 896 fixed20_12 a; 897 898 a.full = dfixed_const(1000); 899 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 900 line_time.full = dfixed_div(line_time, a); 901 bpp.full = dfixed_const(wm->bytes_per_pixel); 902 src_width.full = dfixed_const(wm->src_width); 903 bandwidth.full = dfixed_mul(src_width, bpp); 904 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 905 bandwidth.full = dfixed_div(bandwidth, line_time); 906 907 return dfixed_trunc(bandwidth); 908 } 909 910 /** 911 * dce_v11_0_latency_watermark - get the latency watermark 912 * 913 * @wm: watermark calculation data 914 * 915 * Calculate the latency watermark (CIK). 916 * Used for display watermark bandwidth calculations 917 * Returns the latency watermark in ns 918 */ 919 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 920 { 921 /* First calculate the latency in ns */ 922 u32 mc_latency = 2000; /* 2000 ns. */ 923 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 924 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 925 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 926 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 927 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 928 (wm->num_heads * cursor_line_pair_return_time); 929 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 930 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 931 u32 tmp, dmif_size = 12288; 932 fixed20_12 a, b, c; 933 934 if (wm->num_heads == 0) 935 return 0; 936 937 a.full = dfixed_const(2); 938 b.full = dfixed_const(1); 939 if ((wm->vsc.full > a.full) || 940 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 941 (wm->vtaps >= 5) || 942 ((wm->vsc.full >= a.full) && wm->interlaced)) 943 max_src_lines_per_dst_line = 4; 944 else 945 max_src_lines_per_dst_line = 2; 946 947 a.full = dfixed_const(available_bandwidth); 948 b.full = dfixed_const(wm->num_heads); 949 a.full = dfixed_div(a, b); 950 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 951 tmp = min(dfixed_trunc(a), tmp); 952 953 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 954 955 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 956 b.full = dfixed_const(1000); 957 c.full = dfixed_const(lb_fill_bw); 958 b.full = dfixed_div(c, b); 959 a.full = dfixed_div(a, b); 960 line_fill_time = dfixed_trunc(a); 961 962 if (line_fill_time < wm->active_time) 963 return latency; 964 else 965 return latency + (line_fill_time - wm->active_time); 966 967 } 968 969 /** 970 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 971 * average and available dram bandwidth 972 * 973 * @wm: watermark calculation data 974 * 975 * Check if the display average bandwidth fits in the display 976 * dram bandwidth (CIK). 977 * Used for display watermark bandwidth calculations 978 * Returns true if the display fits, false if not. 979 */ 980 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 981 { 982 if (dce_v11_0_average_bandwidth(wm) <= 983 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 984 return true; 985 else 986 return false; 987 } 988 989 /** 990 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 991 * average and available bandwidth 992 * 993 * @wm: watermark calculation data 994 * 995 * Check if the display average bandwidth fits in the display 996 * available bandwidth (CIK). 997 * Used for display watermark bandwidth calculations 998 * Returns true if the display fits, false if not. 999 */ 1000 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1001 { 1002 if (dce_v11_0_average_bandwidth(wm) <= 1003 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1004 return true; 1005 else 1006 return false; 1007 } 1008 1009 /** 1010 * dce_v11_0_check_latency_hiding - check latency hiding 1011 * 1012 * @wm: watermark calculation data 1013 * 1014 * Check latency hiding (CIK). 1015 * Used for display watermark bandwidth calculations 1016 * Returns true if the display fits, false if not. 1017 */ 1018 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1019 { 1020 u32 lb_partitions = wm->lb_size / wm->src_width; 1021 u32 line_time = wm->active_time + wm->blank_time; 1022 u32 latency_tolerant_lines; 1023 u32 latency_hiding; 1024 fixed20_12 a; 1025 1026 a.full = dfixed_const(1); 1027 if (wm->vsc.full > a.full) 1028 latency_tolerant_lines = 1; 1029 else { 1030 if (lb_partitions <= (wm->vtaps + 1)) 1031 latency_tolerant_lines = 1; 1032 else 1033 latency_tolerant_lines = 2; 1034 } 1035 1036 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1037 1038 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1039 return true; 1040 else 1041 return false; 1042 } 1043 1044 /** 1045 * dce_v11_0_program_watermarks - program display watermarks 1046 * 1047 * @adev: amdgpu_device pointer 1048 * @amdgpu_crtc: the selected display controller 1049 * @lb_size: line buffer size 1050 * @num_heads: number of display controllers in use 1051 * 1052 * Calculate and program the display watermarks for the 1053 * selected display controller (CIK). 1054 */ 1055 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1056 struct amdgpu_crtc *amdgpu_crtc, 1057 u32 lb_size, u32 num_heads) 1058 { 1059 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1060 struct dce10_wm_params wm_low, wm_high; 1061 u32 active_time; 1062 u32 line_time = 0; 1063 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1064 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1065 1066 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1067 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1068 (u32)mode->clock); 1069 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1070 (u32)mode->clock); 1071 line_time = min(line_time, (u32)65535); 1072 1073 /* watermark for high clocks */ 1074 if (adev->pm.dpm_enabled) { 1075 wm_high.yclk = 1076 amdgpu_dpm_get_mclk(adev, false) * 10; 1077 wm_high.sclk = 1078 amdgpu_dpm_get_sclk(adev, false) * 10; 1079 } else { 1080 wm_high.yclk = adev->pm.current_mclk * 10; 1081 wm_high.sclk = adev->pm.current_sclk * 10; 1082 } 1083 1084 wm_high.disp_clk = mode->clock; 1085 wm_high.src_width = mode->crtc_hdisplay; 1086 wm_high.active_time = active_time; 1087 wm_high.blank_time = line_time - wm_high.active_time; 1088 wm_high.interlaced = false; 1089 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1090 wm_high.interlaced = true; 1091 wm_high.vsc = amdgpu_crtc->vsc; 1092 wm_high.vtaps = 1; 1093 if (amdgpu_crtc->rmx_type != RMX_OFF) 1094 wm_high.vtaps = 2; 1095 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1096 wm_high.lb_size = lb_size; 1097 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1098 wm_high.num_heads = num_heads; 1099 1100 /* set for high clocks */ 1101 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1102 1103 /* possibly force display priority to high */ 1104 /* should really do this at mode validation time... */ 1105 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1106 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1107 !dce_v11_0_check_latency_hiding(&wm_high) || 1108 (adev->mode_info.disp_priority == 2)) { 1109 DRM_DEBUG_KMS("force priority to high\n"); 1110 } 1111 1112 /* watermark for low clocks */ 1113 if (adev->pm.dpm_enabled) { 1114 wm_low.yclk = 1115 amdgpu_dpm_get_mclk(adev, true) * 10; 1116 wm_low.sclk = 1117 amdgpu_dpm_get_sclk(adev, true) * 10; 1118 } else { 1119 wm_low.yclk = adev->pm.current_mclk * 10; 1120 wm_low.sclk = adev->pm.current_sclk * 10; 1121 } 1122 1123 wm_low.disp_clk = mode->clock; 1124 wm_low.src_width = mode->crtc_hdisplay; 1125 wm_low.active_time = active_time; 1126 wm_low.blank_time = line_time - wm_low.active_time; 1127 wm_low.interlaced = false; 1128 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1129 wm_low.interlaced = true; 1130 wm_low.vsc = amdgpu_crtc->vsc; 1131 wm_low.vtaps = 1; 1132 if (amdgpu_crtc->rmx_type != RMX_OFF) 1133 wm_low.vtaps = 2; 1134 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1135 wm_low.lb_size = lb_size; 1136 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1137 wm_low.num_heads = num_heads; 1138 1139 /* set for low clocks */ 1140 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1141 1142 /* possibly force display priority to high */ 1143 /* should really do this at mode validation time... */ 1144 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1145 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1146 !dce_v11_0_check_latency_hiding(&wm_low) || 1147 (adev->mode_info.disp_priority == 2)) { 1148 DRM_DEBUG_KMS("force priority to high\n"); 1149 } 1150 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1151 } 1152 1153 /* select wm A */ 1154 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1155 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1156 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1157 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1158 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1159 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1160 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1161 /* select wm B */ 1162 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1163 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1164 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1165 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1166 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1167 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1168 /* restore original selection */ 1169 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1170 1171 /* save values for DPM */ 1172 amdgpu_crtc->line_time = line_time; 1173 amdgpu_crtc->wm_high = latency_watermark_a; 1174 amdgpu_crtc->wm_low = latency_watermark_b; 1175 /* Save number of lines the linebuffer leads before the scanout */ 1176 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1177 } 1178 1179 /** 1180 * dce_v11_0_bandwidth_update - program display watermarks 1181 * 1182 * @adev: amdgpu_device pointer 1183 * 1184 * Calculate and program the display watermarks and line 1185 * buffer allocation (CIK). 1186 */ 1187 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1188 { 1189 struct drm_display_mode *mode = NULL; 1190 u32 num_heads = 0, lb_size; 1191 int i; 1192 1193 amdgpu_display_update_priority(adev); 1194 1195 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1196 if (adev->mode_info.crtcs[i]->base.enabled) 1197 num_heads++; 1198 } 1199 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1200 mode = &adev->mode_info.crtcs[i]->base.mode; 1201 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1202 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1203 lb_size, num_heads); 1204 } 1205 } 1206 1207 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1208 { 1209 int i; 1210 u32 offset, tmp; 1211 1212 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1213 offset = adev->mode_info.audio.pin[i].offset; 1214 tmp = RREG32_AUDIO_ENDPT(offset, 1215 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1216 if (((tmp & 1217 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1218 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1219 adev->mode_info.audio.pin[i].connected = false; 1220 else 1221 adev->mode_info.audio.pin[i].connected = true; 1222 } 1223 } 1224 1225 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1226 { 1227 int i; 1228 1229 dce_v11_0_audio_get_connected_pins(adev); 1230 1231 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1232 if (adev->mode_info.audio.pin[i].connected) 1233 return &adev->mode_info.audio.pin[i]; 1234 } 1235 DRM_ERROR("No connected audio pins found!\n"); 1236 return NULL; 1237 } 1238 1239 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1240 { 1241 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 1242 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1243 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1244 u32 tmp; 1245 1246 if (!dig || !dig->afmt || !dig->afmt->pin) 1247 return; 1248 1249 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1250 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1251 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1252 } 1253 1254 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1255 struct drm_display_mode *mode) 1256 { 1257 struct drm_device *dev = encoder->dev; 1258 struct amdgpu_device *adev = drm_to_adev(dev); 1259 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1260 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1261 struct drm_connector *connector; 1262 struct drm_connector_list_iter iter; 1263 struct amdgpu_connector *amdgpu_connector = NULL; 1264 u32 tmp; 1265 int interlace = 0; 1266 1267 if (!dig || !dig->afmt || !dig->afmt->pin) 1268 return; 1269 1270 drm_connector_list_iter_begin(dev, &iter); 1271 drm_for_each_connector_iter(connector, &iter) { 1272 if (connector->encoder == encoder) { 1273 amdgpu_connector = to_amdgpu_connector(connector); 1274 break; 1275 } 1276 } 1277 drm_connector_list_iter_end(&iter); 1278 1279 if (!amdgpu_connector) { 1280 DRM_ERROR("Couldn't find encoder's connector\n"); 1281 return; 1282 } 1283 1284 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1285 interlace = 1; 1286 if (connector->latency_present[interlace]) { 1287 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1288 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1289 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1290 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1291 } else { 1292 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1293 VIDEO_LIPSYNC, 0); 1294 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1295 AUDIO_LIPSYNC, 0); 1296 } 1297 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1298 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1299 } 1300 1301 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1302 { 1303 struct drm_device *dev = encoder->dev; 1304 struct amdgpu_device *adev = drm_to_adev(dev); 1305 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1306 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1307 struct drm_connector *connector; 1308 struct drm_connector_list_iter iter; 1309 struct amdgpu_connector *amdgpu_connector = NULL; 1310 u32 tmp; 1311 u8 *sadb = NULL; 1312 int sad_count; 1313 1314 if (!dig || !dig->afmt || !dig->afmt->pin) 1315 return; 1316 1317 drm_connector_list_iter_begin(dev, &iter); 1318 drm_for_each_connector_iter(connector, &iter) { 1319 if (connector->encoder == encoder) { 1320 amdgpu_connector = to_amdgpu_connector(connector); 1321 break; 1322 } 1323 } 1324 drm_connector_list_iter_end(&iter); 1325 1326 if (!amdgpu_connector) { 1327 DRM_ERROR("Couldn't find encoder's connector\n"); 1328 return; 1329 } 1330 1331 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1332 if (sad_count < 0) { 1333 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1334 sad_count = 0; 1335 } 1336 1337 /* program the speaker allocation */ 1338 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1339 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1340 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1341 DP_CONNECTION, 0); 1342 /* set HDMI mode */ 1343 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1344 HDMI_CONNECTION, 1); 1345 if (sad_count) 1346 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1347 SPEAKER_ALLOCATION, sadb[0]); 1348 else 1349 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1350 SPEAKER_ALLOCATION, 5); /* stereo */ 1351 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1352 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1353 1354 kfree(sadb); 1355 } 1356 1357 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1358 { 1359 struct drm_device *dev = encoder->dev; 1360 struct amdgpu_device *adev = drm_to_adev(dev); 1361 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1362 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1363 struct drm_connector *connector; 1364 struct drm_connector_list_iter iter; 1365 struct amdgpu_connector *amdgpu_connector = NULL; 1366 struct cea_sad *sads; 1367 int i, sad_count; 1368 1369 static const u16 eld_reg_to_type[][2] = { 1370 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1371 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1379 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1380 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1381 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1382 }; 1383 1384 if (!dig || !dig->afmt || !dig->afmt->pin) 1385 return; 1386 1387 drm_connector_list_iter_begin(dev, &iter); 1388 drm_for_each_connector_iter(connector, &iter) { 1389 if (connector->encoder == encoder) { 1390 amdgpu_connector = to_amdgpu_connector(connector); 1391 break; 1392 } 1393 } 1394 drm_connector_list_iter_end(&iter); 1395 1396 if (!amdgpu_connector) { 1397 DRM_ERROR("Couldn't find encoder's connector\n"); 1398 return; 1399 } 1400 1401 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1402 if (sad_count < 0) 1403 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1404 if (sad_count <= 0) 1405 return; 1406 BUG_ON(!sads); 1407 1408 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1409 u32 tmp = 0; 1410 u8 stereo_freqs = 0; 1411 int max_channels = -1; 1412 int j; 1413 1414 for (j = 0; j < sad_count; j++) { 1415 struct cea_sad *sad = &sads[j]; 1416 1417 if (sad->format == eld_reg_to_type[i][1]) { 1418 if (sad->channels > max_channels) { 1419 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1420 MAX_CHANNELS, sad->channels); 1421 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1422 DESCRIPTOR_BYTE_2, sad->byte2); 1423 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1424 SUPPORTED_FREQUENCIES, sad->freq); 1425 max_channels = sad->channels; 1426 } 1427 1428 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1429 stereo_freqs |= sad->freq; 1430 else 1431 break; 1432 } 1433 } 1434 1435 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1436 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1437 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1438 } 1439 1440 kfree(sads); 1441 } 1442 1443 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1444 struct amdgpu_audio_pin *pin, 1445 bool enable) 1446 { 1447 if (!pin) 1448 return; 1449 1450 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1451 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1452 } 1453 1454 static const u32 pin_offsets[] = 1455 { 1456 AUD0_REGISTER_OFFSET, 1457 AUD1_REGISTER_OFFSET, 1458 AUD2_REGISTER_OFFSET, 1459 AUD3_REGISTER_OFFSET, 1460 AUD4_REGISTER_OFFSET, 1461 AUD5_REGISTER_OFFSET, 1462 AUD6_REGISTER_OFFSET, 1463 AUD7_REGISTER_OFFSET, 1464 }; 1465 1466 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1467 { 1468 int i; 1469 1470 if (!amdgpu_audio) 1471 return 0; 1472 1473 adev->mode_info.audio.enabled = true; 1474 1475 switch (adev->asic_type) { 1476 case CHIP_CARRIZO: 1477 case CHIP_STONEY: 1478 adev->mode_info.audio.num_pins = 7; 1479 break; 1480 case CHIP_POLARIS10: 1481 case CHIP_VEGAM: 1482 adev->mode_info.audio.num_pins = 8; 1483 break; 1484 case CHIP_POLARIS11: 1485 case CHIP_POLARIS12: 1486 adev->mode_info.audio.num_pins = 6; 1487 break; 1488 default: 1489 return -EINVAL; 1490 } 1491 1492 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1493 adev->mode_info.audio.pin[i].channels = -1; 1494 adev->mode_info.audio.pin[i].rate = -1; 1495 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1496 adev->mode_info.audio.pin[i].status_bits = 0; 1497 adev->mode_info.audio.pin[i].category_code = 0; 1498 adev->mode_info.audio.pin[i].connected = false; 1499 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1500 adev->mode_info.audio.pin[i].id = i; 1501 /* disable audio. it will be set up later */ 1502 /* XXX remove once we switch to ip funcs */ 1503 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1504 } 1505 1506 return 0; 1507 } 1508 1509 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1510 { 1511 int i; 1512 1513 if (!amdgpu_audio) 1514 return; 1515 1516 if (!adev->mode_info.audio.enabled) 1517 return; 1518 1519 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1520 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1521 1522 adev->mode_info.audio.enabled = false; 1523 } 1524 1525 /* 1526 * update the N and CTS parameters for a given pixel clock rate 1527 */ 1528 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1529 { 1530 struct drm_device *dev = encoder->dev; 1531 struct amdgpu_device *adev = drm_to_adev(dev); 1532 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1533 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1534 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1535 u32 tmp; 1536 1537 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1538 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1539 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1540 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1541 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1542 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1543 1544 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1545 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1546 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1547 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1548 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1549 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1550 1551 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1552 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1553 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1554 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1555 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1556 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1557 1558 } 1559 1560 /* 1561 * build a HDMI Video Info Frame 1562 */ 1563 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1564 void *buffer, size_t size) 1565 { 1566 struct drm_device *dev = encoder->dev; 1567 struct amdgpu_device *adev = drm_to_adev(dev); 1568 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1569 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1570 uint8_t *frame = buffer + 3; 1571 uint8_t *header = buffer; 1572 1573 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1574 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1575 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1576 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1577 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1578 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1579 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1580 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1581 } 1582 1583 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1584 { 1585 struct drm_device *dev = encoder->dev; 1586 struct amdgpu_device *adev = drm_to_adev(dev); 1587 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1588 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1589 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1590 u32 dto_phase = 24 * 1000; 1591 u32 dto_modulo = clock; 1592 u32 tmp; 1593 1594 if (!dig || !dig->afmt) 1595 return; 1596 1597 /* XXX two dtos; generally use dto0 for hdmi */ 1598 /* Express [24MHz / target pixel clock] as an exact rational 1599 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1600 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1601 */ 1602 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1603 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1604 amdgpu_crtc->crtc_id); 1605 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1606 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1607 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1608 } 1609 1610 /* 1611 * update the info frames with the data from the current display mode 1612 */ 1613 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1614 struct drm_display_mode *mode) 1615 { 1616 struct drm_device *dev = encoder->dev; 1617 struct amdgpu_device *adev = drm_to_adev(dev); 1618 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1619 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1620 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1621 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1622 struct hdmi_avi_infoframe frame; 1623 ssize_t err; 1624 u32 tmp; 1625 int bpc = 8; 1626 1627 if (!dig || !dig->afmt) 1628 return; 1629 1630 /* Silent, r600_hdmi_enable will raise WARN for us */ 1631 if (!dig->afmt->enabled) 1632 return; 1633 1634 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1635 if (encoder->crtc) { 1636 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1637 bpc = amdgpu_crtc->bpc; 1638 } 1639 1640 /* disable audio prior to setting up hw */ 1641 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1642 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1643 1644 dce_v11_0_audio_set_dto(encoder, mode->clock); 1645 1646 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1647 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1648 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1649 1650 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1651 1652 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1653 switch (bpc) { 1654 case 0: 1655 case 6: 1656 case 8: 1657 case 16: 1658 default: 1659 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1660 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1661 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1662 connector->name, bpc); 1663 break; 1664 case 10: 1665 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1666 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1667 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1668 connector->name); 1669 break; 1670 case 12: 1671 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1672 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1673 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1674 connector->name); 1675 break; 1676 } 1677 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1678 1679 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1680 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1681 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1682 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1683 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1684 1685 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1686 /* enable audio info frames (frames won't be set until audio is enabled) */ 1687 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1688 /* required for audio info values to be updated */ 1689 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1690 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1691 1692 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1693 /* required for audio info values to be updated */ 1694 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1695 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1696 1697 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1698 /* anything other than 0 */ 1699 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1700 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1701 1702 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1703 1704 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1705 /* set the default audio delay */ 1706 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1707 /* should be suffient for all audio modes and small enough for all hblanks */ 1708 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1709 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1710 1711 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1712 /* allow 60958 channel status fields to be updated */ 1713 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1714 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1715 1716 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1717 if (bpc > 8) 1718 /* clear SW CTS value */ 1719 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1720 else 1721 /* select SW CTS value */ 1722 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1723 /* allow hw to sent ACR packets when required */ 1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1725 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1726 1727 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1728 1729 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1730 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1731 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1732 1733 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1734 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1735 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1736 1737 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1738 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1739 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1741 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1742 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1743 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1744 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1745 1746 dce_v11_0_audio_write_speaker_allocation(encoder); 1747 1748 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1749 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1750 1751 dce_v11_0_afmt_audio_select_pin(encoder); 1752 dce_v11_0_audio_write_sad_regs(encoder); 1753 dce_v11_0_audio_write_latency_fields(encoder, mode); 1754 1755 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1756 if (err < 0) { 1757 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1758 return; 1759 } 1760 1761 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1762 if (err < 0) { 1763 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1764 return; 1765 } 1766 1767 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1768 1769 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1770 /* enable AVI info frames */ 1771 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1772 /* required for audio info values to be updated */ 1773 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1774 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1775 1776 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1777 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1778 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1779 1780 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1781 /* send audio packets */ 1782 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1783 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1784 1785 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1786 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1787 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1788 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1789 1790 /* enable audio after to setting up hw */ 1791 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1792 } 1793 1794 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1795 { 1796 struct drm_device *dev = encoder->dev; 1797 struct amdgpu_device *adev = drm_to_adev(dev); 1798 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1799 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1800 1801 if (!dig || !dig->afmt) 1802 return; 1803 1804 /* Silent, r600_hdmi_enable will raise WARN for us */ 1805 if (enable && dig->afmt->enabled) 1806 return; 1807 if (!enable && !dig->afmt->enabled) 1808 return; 1809 1810 if (!enable && dig->afmt->pin) { 1811 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1812 dig->afmt->pin = NULL; 1813 } 1814 1815 dig->afmt->enabled = enable; 1816 1817 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1818 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1819 } 1820 1821 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1822 { 1823 int i; 1824 1825 for (i = 0; i < adev->mode_info.num_dig; i++) 1826 adev->mode_info.afmt[i] = NULL; 1827 1828 /* DCE11 has audio blocks tied to DIG encoders */ 1829 for (i = 0; i < adev->mode_info.num_dig; i++) { 1830 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1831 if (adev->mode_info.afmt[i]) { 1832 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1833 adev->mode_info.afmt[i]->id = i; 1834 } else { 1835 int j; 1836 for (j = 0; j < i; j++) { 1837 kfree(adev->mode_info.afmt[j]); 1838 adev->mode_info.afmt[j] = NULL; 1839 } 1840 return -ENOMEM; 1841 } 1842 } 1843 return 0; 1844 } 1845 1846 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1847 { 1848 int i; 1849 1850 for (i = 0; i < adev->mode_info.num_dig; i++) { 1851 kfree(adev->mode_info.afmt[i]); 1852 adev->mode_info.afmt[i] = NULL; 1853 } 1854 } 1855 1856 static const u32 vga_control_regs[6] = 1857 { 1858 mmD1VGA_CONTROL, 1859 mmD2VGA_CONTROL, 1860 mmD3VGA_CONTROL, 1861 mmD4VGA_CONTROL, 1862 mmD5VGA_CONTROL, 1863 mmD6VGA_CONTROL, 1864 }; 1865 1866 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1867 { 1868 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1869 struct drm_device *dev = crtc->dev; 1870 struct amdgpu_device *adev = drm_to_adev(dev); 1871 u32 vga_control; 1872 1873 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1874 if (enable) 1875 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1876 else 1877 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1878 } 1879 1880 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1881 { 1882 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1883 struct drm_device *dev = crtc->dev; 1884 struct amdgpu_device *adev = drm_to_adev(dev); 1885 1886 if (enable) 1887 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1888 else 1889 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1890 } 1891 1892 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 1893 struct drm_framebuffer *fb, 1894 int x, int y, int atomic) 1895 { 1896 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1897 struct drm_device *dev = crtc->dev; 1898 struct amdgpu_device *adev = drm_to_adev(dev); 1899 struct drm_framebuffer *target_fb; 1900 struct drm_gem_object *obj; 1901 struct amdgpu_bo *abo; 1902 uint64_t fb_location, tiling_flags; 1903 uint32_t fb_format, fb_pitch_pixels; 1904 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1905 u32 pipe_config; 1906 u32 tmp, viewport_w, viewport_h; 1907 int r; 1908 bool bypass_lut = false; 1909 1910 /* no fb bound */ 1911 if (!atomic && !crtc->primary->fb) { 1912 DRM_DEBUG_KMS("No FB bound\n"); 1913 return 0; 1914 } 1915 1916 if (atomic) 1917 target_fb = fb; 1918 else 1919 target_fb = crtc->primary->fb; 1920 1921 /* If atomic, assume fb object is pinned & idle & fenced and 1922 * just update base pointers 1923 */ 1924 obj = target_fb->obj[0]; 1925 abo = gem_to_amdgpu_bo(obj); 1926 r = amdgpu_bo_reserve(abo, false); 1927 if (unlikely(r != 0)) 1928 return r; 1929 1930 if (!atomic) { 1931 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1932 if (unlikely(r != 0)) { 1933 amdgpu_bo_unreserve(abo); 1934 return -EINVAL; 1935 } 1936 } 1937 fb_location = amdgpu_bo_gpu_offset(abo); 1938 1939 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1940 amdgpu_bo_unreserve(abo); 1941 1942 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1943 1944 switch (target_fb->format->format) { 1945 case DRM_FORMAT_C8: 1946 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1947 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1948 break; 1949 case DRM_FORMAT_XRGB4444: 1950 case DRM_FORMAT_ARGB4444: 1951 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1952 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1953 #ifdef __BIG_ENDIAN 1954 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1955 ENDIAN_8IN16); 1956 #endif 1957 break; 1958 case DRM_FORMAT_XRGB1555: 1959 case DRM_FORMAT_ARGB1555: 1960 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1961 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1962 #ifdef __BIG_ENDIAN 1963 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1964 ENDIAN_8IN16); 1965 #endif 1966 break; 1967 case DRM_FORMAT_BGRX5551: 1968 case DRM_FORMAT_BGRA5551: 1969 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1970 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1971 #ifdef __BIG_ENDIAN 1972 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1973 ENDIAN_8IN16); 1974 #endif 1975 break; 1976 case DRM_FORMAT_RGB565: 1977 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1978 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1979 #ifdef __BIG_ENDIAN 1980 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1981 ENDIAN_8IN16); 1982 #endif 1983 break; 1984 case DRM_FORMAT_XRGB8888: 1985 case DRM_FORMAT_ARGB8888: 1986 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1987 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1988 #ifdef __BIG_ENDIAN 1989 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1990 ENDIAN_8IN32); 1991 #endif 1992 break; 1993 case DRM_FORMAT_XRGB2101010: 1994 case DRM_FORMAT_ARGB2101010: 1995 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1996 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1997 #ifdef __BIG_ENDIAN 1998 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1999 ENDIAN_8IN32); 2000 #endif 2001 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2002 bypass_lut = true; 2003 break; 2004 case DRM_FORMAT_BGRX1010102: 2005 case DRM_FORMAT_BGRA1010102: 2006 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2008 #ifdef __BIG_ENDIAN 2009 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2010 ENDIAN_8IN32); 2011 #endif 2012 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2013 bypass_lut = true; 2014 break; 2015 case DRM_FORMAT_XBGR8888: 2016 case DRM_FORMAT_ABGR8888: 2017 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2018 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2019 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); 2020 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); 2021 #ifdef __BIG_ENDIAN 2022 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2023 ENDIAN_8IN32); 2024 #endif 2025 break; 2026 default: 2027 DRM_ERROR("Unsupported screen format %p4cc\n", 2028 &target_fb->format->format); 2029 return -EINVAL; 2030 } 2031 2032 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2033 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2034 2035 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2036 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2037 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2038 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2039 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2040 2041 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2042 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2043 ARRAY_2D_TILED_THIN1); 2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2045 tile_split); 2046 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2047 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2048 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2049 mtaspect); 2050 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2051 ADDR_SURF_MICRO_TILING_DISPLAY); 2052 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2053 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2054 ARRAY_1D_TILED_THIN1); 2055 } 2056 2057 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2058 pipe_config); 2059 2060 dce_v11_0_vga_enable(crtc, false); 2061 2062 /* Make sure surface address is updated at vertical blank rather than 2063 * horizontal blank 2064 */ 2065 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2066 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2067 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2068 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2069 2070 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2071 upper_32_bits(fb_location)); 2072 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2073 upper_32_bits(fb_location)); 2074 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2075 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2076 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2077 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2078 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2079 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2080 2081 /* 2082 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2083 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2084 * retain the full precision throughout the pipeline. 2085 */ 2086 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2087 if (bypass_lut) 2088 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2089 else 2090 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2091 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2092 2093 if (bypass_lut) 2094 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2095 2096 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2097 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2098 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2099 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2100 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2101 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2102 2103 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2104 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2105 2106 dce_v11_0_grph_enable(crtc, true); 2107 2108 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2109 target_fb->height); 2110 2111 x &= ~3; 2112 y &= ~1; 2113 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2114 (x << 16) | y); 2115 viewport_w = crtc->mode.hdisplay; 2116 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2117 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2118 (viewport_w << 16) | viewport_h); 2119 2120 /* set pageflip to happen anywhere in vblank interval */ 2121 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2122 2123 if (!atomic && fb && fb != crtc->primary->fb) { 2124 abo = gem_to_amdgpu_bo(fb->obj[0]); 2125 r = amdgpu_bo_reserve(abo, true); 2126 if (unlikely(r != 0)) 2127 return r; 2128 amdgpu_bo_unpin(abo); 2129 amdgpu_bo_unreserve(abo); 2130 } 2131 2132 /* Bytes per pixel may have changed */ 2133 dce_v11_0_bandwidth_update(adev); 2134 2135 return 0; 2136 } 2137 2138 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2139 struct drm_display_mode *mode) 2140 { 2141 struct drm_device *dev = crtc->dev; 2142 struct amdgpu_device *adev = drm_to_adev(dev); 2143 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2144 u32 tmp; 2145 2146 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2147 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2148 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2149 else 2150 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2151 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2152 } 2153 2154 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2155 { 2156 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2157 struct drm_device *dev = crtc->dev; 2158 struct amdgpu_device *adev = drm_to_adev(dev); 2159 u16 *r, *g, *b; 2160 int i; 2161 u32 tmp; 2162 2163 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2164 2165 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2166 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2167 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2168 2169 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2170 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2171 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2172 2173 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2174 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2175 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2176 2177 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2178 2179 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2180 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2181 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2182 2183 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2184 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2185 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2186 2187 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2188 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2189 2190 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2191 r = crtc->gamma_store; 2192 g = r + crtc->gamma_size; 2193 b = g + crtc->gamma_size; 2194 for (i = 0; i < 256; i++) { 2195 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2196 ((*r++ & 0xffc0) << 14) | 2197 ((*g++ & 0xffc0) << 4) | 2198 (*b++ >> 6)); 2199 } 2200 2201 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2202 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2203 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2204 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2205 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2206 2207 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2208 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2209 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2210 2211 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2212 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2213 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2214 2215 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2216 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2217 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2218 2219 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2220 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2221 /* XXX this only needs to be programmed once per crtc at startup, 2222 * not sure where the best place for it is 2223 */ 2224 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2225 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2226 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2227 } 2228 2229 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2230 { 2231 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2232 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2233 2234 switch (amdgpu_encoder->encoder_id) { 2235 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2236 if (dig->linkb) 2237 return 1; 2238 else 2239 return 0; 2240 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2241 if (dig->linkb) 2242 return 3; 2243 else 2244 return 2; 2245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2246 if (dig->linkb) 2247 return 5; 2248 else 2249 return 4; 2250 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2251 return 6; 2252 default: 2253 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2254 return 0; 2255 } 2256 } 2257 2258 /** 2259 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2260 * 2261 * @crtc: drm crtc 2262 * 2263 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2264 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2265 * monitors a dedicated PPLL must be used. If a particular board has 2266 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2267 * as there is no need to program the PLL itself. If we are not able to 2268 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2269 * avoid messing up an existing monitor. 2270 * 2271 * Asic specific PLL information 2272 * 2273 * DCE 10.x 2274 * Tonga 2275 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2276 * CI 2277 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2278 * 2279 */ 2280 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2281 { 2282 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2283 struct drm_device *dev = crtc->dev; 2284 struct amdgpu_device *adev = drm_to_adev(dev); 2285 u32 pll_in_use; 2286 int pll; 2287 2288 if ((adev->asic_type == CHIP_POLARIS10) || 2289 (adev->asic_type == CHIP_POLARIS11) || 2290 (adev->asic_type == CHIP_POLARIS12) || 2291 (adev->asic_type == CHIP_VEGAM)) { 2292 struct amdgpu_encoder *amdgpu_encoder = 2293 to_amdgpu_encoder(amdgpu_crtc->encoder); 2294 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2295 2296 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2297 return ATOM_DP_DTO; 2298 2299 switch (amdgpu_encoder->encoder_id) { 2300 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2301 if (dig->linkb) 2302 return ATOM_COMBOPHY_PLL1; 2303 else 2304 return ATOM_COMBOPHY_PLL0; 2305 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2306 if (dig->linkb) 2307 return ATOM_COMBOPHY_PLL3; 2308 else 2309 return ATOM_COMBOPHY_PLL2; 2310 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2311 if (dig->linkb) 2312 return ATOM_COMBOPHY_PLL5; 2313 else 2314 return ATOM_COMBOPHY_PLL4; 2315 default: 2316 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2317 return ATOM_PPLL_INVALID; 2318 } 2319 } 2320 2321 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2322 if (adev->clock.dp_extclk) 2323 /* skip PPLL programming if using ext clock */ 2324 return ATOM_PPLL_INVALID; 2325 else { 2326 /* use the same PPLL for all DP monitors */ 2327 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2328 if (pll != ATOM_PPLL_INVALID) 2329 return pll; 2330 } 2331 } else { 2332 /* use the same PPLL for all monitors with the same clock */ 2333 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2334 if (pll != ATOM_PPLL_INVALID) 2335 return pll; 2336 } 2337 2338 /* XXX need to determine what plls are available on each DCE11 part */ 2339 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2340 if (adev->flags & AMD_IS_APU) { 2341 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2342 return ATOM_PPLL1; 2343 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2344 return ATOM_PPLL0; 2345 DRM_ERROR("unable to allocate a PPLL\n"); 2346 return ATOM_PPLL_INVALID; 2347 } else { 2348 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2349 return ATOM_PPLL2; 2350 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2351 return ATOM_PPLL1; 2352 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2353 return ATOM_PPLL0; 2354 DRM_ERROR("unable to allocate a PPLL\n"); 2355 return ATOM_PPLL_INVALID; 2356 } 2357 return ATOM_PPLL_INVALID; 2358 } 2359 2360 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2361 { 2362 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2363 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2364 uint32_t cur_lock; 2365 2366 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2367 if (lock) 2368 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2369 else 2370 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2371 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2372 } 2373 2374 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2375 { 2376 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2377 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2378 u32 tmp; 2379 2380 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2381 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2382 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2383 } 2384 2385 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2386 { 2387 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2388 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2389 u32 tmp; 2390 2391 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2392 upper_32_bits(amdgpu_crtc->cursor_addr)); 2393 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2394 lower_32_bits(amdgpu_crtc->cursor_addr)); 2395 2396 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2397 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2398 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2399 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2400 } 2401 2402 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2403 int x, int y) 2404 { 2405 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2406 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 2407 int xorigin = 0, yorigin = 0; 2408 2409 amdgpu_crtc->cursor_x = x; 2410 amdgpu_crtc->cursor_y = y; 2411 2412 /* avivo cursor are offset into the total surface */ 2413 x += crtc->x; 2414 y += crtc->y; 2415 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2416 2417 if (x < 0) { 2418 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2419 x = 0; 2420 } 2421 if (y < 0) { 2422 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2423 y = 0; 2424 } 2425 2426 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2427 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2428 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2429 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2430 2431 return 0; 2432 } 2433 2434 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2435 int x, int y) 2436 { 2437 int ret; 2438 2439 dce_v11_0_lock_cursor(crtc, true); 2440 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2441 dce_v11_0_lock_cursor(crtc, false); 2442 2443 return ret; 2444 } 2445 2446 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2447 struct drm_file *file_priv, 2448 uint32_t handle, 2449 uint32_t width, 2450 uint32_t height, 2451 int32_t hot_x, 2452 int32_t hot_y) 2453 { 2454 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2455 struct drm_gem_object *obj; 2456 struct amdgpu_bo *aobj; 2457 int ret; 2458 2459 if (!handle) { 2460 /* turn off cursor */ 2461 dce_v11_0_hide_cursor(crtc); 2462 obj = NULL; 2463 goto unpin; 2464 } 2465 2466 if ((width > amdgpu_crtc->max_cursor_width) || 2467 (height > amdgpu_crtc->max_cursor_height)) { 2468 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2469 return -EINVAL; 2470 } 2471 2472 obj = drm_gem_object_lookup(file_priv, handle); 2473 if (!obj) { 2474 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2475 return -ENOENT; 2476 } 2477 2478 aobj = gem_to_amdgpu_bo(obj); 2479 ret = amdgpu_bo_reserve(aobj, false); 2480 if (ret != 0) { 2481 drm_gem_object_put(obj); 2482 return ret; 2483 } 2484 2485 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2486 amdgpu_bo_unreserve(aobj); 2487 if (ret) { 2488 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2489 drm_gem_object_put(obj); 2490 return ret; 2491 } 2492 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2493 2494 dce_v11_0_lock_cursor(crtc, true); 2495 2496 if (width != amdgpu_crtc->cursor_width || 2497 height != amdgpu_crtc->cursor_height || 2498 hot_x != amdgpu_crtc->cursor_hot_x || 2499 hot_y != amdgpu_crtc->cursor_hot_y) { 2500 int x, y; 2501 2502 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2503 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2504 2505 dce_v11_0_cursor_move_locked(crtc, x, y); 2506 2507 amdgpu_crtc->cursor_width = width; 2508 amdgpu_crtc->cursor_height = height; 2509 amdgpu_crtc->cursor_hot_x = hot_x; 2510 amdgpu_crtc->cursor_hot_y = hot_y; 2511 } 2512 2513 dce_v11_0_show_cursor(crtc); 2514 dce_v11_0_lock_cursor(crtc, false); 2515 2516 unpin: 2517 if (amdgpu_crtc->cursor_bo) { 2518 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2519 ret = amdgpu_bo_reserve(aobj, true); 2520 if (likely(ret == 0)) { 2521 amdgpu_bo_unpin(aobj); 2522 amdgpu_bo_unreserve(aobj); 2523 } 2524 drm_gem_object_put(amdgpu_crtc->cursor_bo); 2525 } 2526 2527 amdgpu_crtc->cursor_bo = obj; 2528 return 0; 2529 } 2530 2531 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2532 { 2533 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2534 2535 if (amdgpu_crtc->cursor_bo) { 2536 dce_v11_0_lock_cursor(crtc, true); 2537 2538 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2539 amdgpu_crtc->cursor_y); 2540 2541 dce_v11_0_show_cursor(crtc); 2542 2543 dce_v11_0_lock_cursor(crtc, false); 2544 } 2545 } 2546 2547 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2548 u16 *blue, uint32_t size, 2549 struct drm_modeset_acquire_ctx *ctx) 2550 { 2551 dce_v11_0_crtc_load_lut(crtc); 2552 2553 return 0; 2554 } 2555 2556 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2557 { 2558 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2559 2560 drm_crtc_cleanup(crtc); 2561 kfree(amdgpu_crtc); 2562 } 2563 2564 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2565 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2566 .cursor_move = dce_v11_0_crtc_cursor_move, 2567 .gamma_set = dce_v11_0_crtc_gamma_set, 2568 .set_config = amdgpu_display_crtc_set_config, 2569 .destroy = dce_v11_0_crtc_destroy, 2570 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2571 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 2572 .enable_vblank = amdgpu_enable_vblank_kms, 2573 .disable_vblank = amdgpu_disable_vblank_kms, 2574 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 2575 }; 2576 2577 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2578 { 2579 struct drm_device *dev = crtc->dev; 2580 struct amdgpu_device *adev = drm_to_adev(dev); 2581 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2582 unsigned type; 2583 2584 switch (mode) { 2585 case DRM_MODE_DPMS_ON: 2586 amdgpu_crtc->enabled = true; 2587 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2588 dce_v11_0_vga_enable(crtc, true); 2589 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2590 dce_v11_0_vga_enable(crtc, false); 2591 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2592 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2593 amdgpu_crtc->crtc_id); 2594 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2595 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2596 drm_crtc_vblank_on(crtc); 2597 dce_v11_0_crtc_load_lut(crtc); 2598 break; 2599 case DRM_MODE_DPMS_STANDBY: 2600 case DRM_MODE_DPMS_SUSPEND: 2601 case DRM_MODE_DPMS_OFF: 2602 drm_crtc_vblank_off(crtc); 2603 if (amdgpu_crtc->enabled) { 2604 dce_v11_0_vga_enable(crtc, true); 2605 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2606 dce_v11_0_vga_enable(crtc, false); 2607 } 2608 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2609 amdgpu_crtc->enabled = false; 2610 break; 2611 } 2612 /* adjust pm to dpms */ 2613 amdgpu_dpm_compute_clocks(adev); 2614 } 2615 2616 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2617 { 2618 /* disable crtc pair power gating before programming */ 2619 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2620 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2621 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2622 } 2623 2624 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2625 { 2626 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2627 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2628 } 2629 2630 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2631 { 2632 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2633 struct drm_device *dev = crtc->dev; 2634 struct amdgpu_device *adev = drm_to_adev(dev); 2635 struct amdgpu_atom_ss ss; 2636 int i; 2637 2638 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2639 if (crtc->primary->fb) { 2640 int r; 2641 struct amdgpu_bo *abo; 2642 2643 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2644 r = amdgpu_bo_reserve(abo, true); 2645 if (unlikely(r)) 2646 DRM_ERROR("failed to reserve abo before unpin\n"); 2647 else { 2648 amdgpu_bo_unpin(abo); 2649 amdgpu_bo_unreserve(abo); 2650 } 2651 } 2652 /* disable the GRPH */ 2653 dce_v11_0_grph_enable(crtc, false); 2654 2655 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2656 2657 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2658 if (adev->mode_info.crtcs[i] && 2659 adev->mode_info.crtcs[i]->enabled && 2660 i != amdgpu_crtc->crtc_id && 2661 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2662 /* one other crtc is using this pll don't turn 2663 * off the pll 2664 */ 2665 goto done; 2666 } 2667 } 2668 2669 switch (amdgpu_crtc->pll_id) { 2670 case ATOM_PPLL0: 2671 case ATOM_PPLL1: 2672 case ATOM_PPLL2: 2673 /* disable the ppll */ 2674 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2675 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2676 break; 2677 case ATOM_COMBOPHY_PLL0: 2678 case ATOM_COMBOPHY_PLL1: 2679 case ATOM_COMBOPHY_PLL2: 2680 case ATOM_COMBOPHY_PLL3: 2681 case ATOM_COMBOPHY_PLL4: 2682 case ATOM_COMBOPHY_PLL5: 2683 /* disable the ppll */ 2684 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2685 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2686 break; 2687 default: 2688 break; 2689 } 2690 done: 2691 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2692 amdgpu_crtc->adjusted_clock = 0; 2693 amdgpu_crtc->encoder = NULL; 2694 amdgpu_crtc->connector = NULL; 2695 } 2696 2697 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2698 struct drm_display_mode *mode, 2699 struct drm_display_mode *adjusted_mode, 2700 int x, int y, struct drm_framebuffer *old_fb) 2701 { 2702 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2703 struct drm_device *dev = crtc->dev; 2704 struct amdgpu_device *adev = drm_to_adev(dev); 2705 2706 if (!amdgpu_crtc->adjusted_clock) 2707 return -EINVAL; 2708 2709 if ((adev->asic_type == CHIP_POLARIS10) || 2710 (adev->asic_type == CHIP_POLARIS11) || 2711 (adev->asic_type == CHIP_POLARIS12) || 2712 (adev->asic_type == CHIP_VEGAM)) { 2713 struct amdgpu_encoder *amdgpu_encoder = 2714 to_amdgpu_encoder(amdgpu_crtc->encoder); 2715 int encoder_mode = 2716 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2717 2718 /* SetPixelClock calculates the plls and ss values now */ 2719 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2720 amdgpu_crtc->pll_id, 2721 encoder_mode, amdgpu_encoder->encoder_id, 2722 adjusted_mode->clock, 0, 0, 0, 0, 2723 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2724 } else { 2725 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2726 } 2727 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2728 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2729 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2730 amdgpu_atombios_crtc_scaler_setup(crtc); 2731 dce_v11_0_cursor_reset(crtc); 2732 /* update the hw version fpr dpm */ 2733 amdgpu_crtc->hw_mode = *adjusted_mode; 2734 2735 return 0; 2736 } 2737 2738 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2739 const struct drm_display_mode *mode, 2740 struct drm_display_mode *adjusted_mode) 2741 { 2742 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2743 struct drm_device *dev = crtc->dev; 2744 struct drm_encoder *encoder; 2745 2746 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2747 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2748 if (encoder->crtc == crtc) { 2749 amdgpu_crtc->encoder = encoder; 2750 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2751 break; 2752 } 2753 } 2754 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2755 amdgpu_crtc->encoder = NULL; 2756 amdgpu_crtc->connector = NULL; 2757 return false; 2758 } 2759 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2760 return false; 2761 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2762 return false; 2763 /* pick pll */ 2764 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2765 /* if we can't get a PPLL for a non-DP encoder, fail */ 2766 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2767 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2768 return false; 2769 2770 return true; 2771 } 2772 2773 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2774 struct drm_framebuffer *old_fb) 2775 { 2776 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2777 } 2778 2779 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2780 struct drm_framebuffer *fb, 2781 int x, int y, enum mode_set_atomic state) 2782 { 2783 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2784 } 2785 2786 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2787 .dpms = dce_v11_0_crtc_dpms, 2788 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2789 .mode_set = dce_v11_0_crtc_mode_set, 2790 .mode_set_base = dce_v11_0_crtc_set_base, 2791 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2792 .prepare = dce_v11_0_crtc_prepare, 2793 .commit = dce_v11_0_crtc_commit, 2794 .disable = dce_v11_0_crtc_disable, 2795 .get_scanout_position = amdgpu_crtc_get_scanout_position, 2796 }; 2797 2798 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2799 { 2800 struct amdgpu_crtc *amdgpu_crtc; 2801 2802 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2803 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2804 if (amdgpu_crtc == NULL) 2805 return -ENOMEM; 2806 2807 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2808 2809 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2810 amdgpu_crtc->crtc_id = index; 2811 adev->mode_info.crtcs[index] = amdgpu_crtc; 2812 2813 amdgpu_crtc->max_cursor_width = 128; 2814 amdgpu_crtc->max_cursor_height = 128; 2815 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2816 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2817 2818 switch (amdgpu_crtc->crtc_id) { 2819 case 0: 2820 default: 2821 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2822 break; 2823 case 1: 2824 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2825 break; 2826 case 2: 2827 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2828 break; 2829 case 3: 2830 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2831 break; 2832 case 4: 2833 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2834 break; 2835 case 5: 2836 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2837 break; 2838 } 2839 2840 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2841 amdgpu_crtc->adjusted_clock = 0; 2842 amdgpu_crtc->encoder = NULL; 2843 amdgpu_crtc->connector = NULL; 2844 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2845 2846 return 0; 2847 } 2848 2849 static int dce_v11_0_early_init(void *handle) 2850 { 2851 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2852 2853 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2854 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2855 2856 dce_v11_0_set_display_funcs(adev); 2857 2858 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); 2859 2860 switch (adev->asic_type) { 2861 case CHIP_CARRIZO: 2862 adev->mode_info.num_hpd = 6; 2863 adev->mode_info.num_dig = 9; 2864 break; 2865 case CHIP_STONEY: 2866 adev->mode_info.num_hpd = 6; 2867 adev->mode_info.num_dig = 9; 2868 break; 2869 case CHIP_POLARIS10: 2870 case CHIP_VEGAM: 2871 adev->mode_info.num_hpd = 6; 2872 adev->mode_info.num_dig = 6; 2873 break; 2874 case CHIP_POLARIS11: 2875 case CHIP_POLARIS12: 2876 adev->mode_info.num_hpd = 5; 2877 adev->mode_info.num_dig = 5; 2878 break; 2879 default: 2880 /* FIXME: not supported yet */ 2881 return -EINVAL; 2882 } 2883 2884 dce_v11_0_set_irq_funcs(adev); 2885 2886 return 0; 2887 } 2888 2889 static int dce_v11_0_sw_init(void *handle) 2890 { 2891 int r, i; 2892 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2893 2894 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2895 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2896 if (r) 2897 return r; 2898 } 2899 2900 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { 2901 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2902 if (r) 2903 return r; 2904 } 2905 2906 /* HPD hotplug */ 2907 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2908 if (r) 2909 return r; 2910 2911 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs; 2912 2913 adev_to_drm(adev)->mode_config.async_page_flip = true; 2914 2915 adev_to_drm(adev)->mode_config.max_width = 16384; 2916 adev_to_drm(adev)->mode_config.max_height = 16384; 2917 2918 adev_to_drm(adev)->mode_config.preferred_depth = 24; 2919 adev_to_drm(adev)->mode_config.prefer_shadow = 1; 2920 2921 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; 2922 2923 r = amdgpu_display_modeset_create_props(adev); 2924 if (r) 2925 return r; 2926 2927 adev_to_drm(adev)->mode_config.max_width = 16384; 2928 adev_to_drm(adev)->mode_config.max_height = 16384; 2929 2930 2931 /* allocate crtcs */ 2932 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2933 r = dce_v11_0_crtc_init(adev, i); 2934 if (r) 2935 return r; 2936 } 2937 2938 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2939 amdgpu_display_print_display_setup(adev_to_drm(adev)); 2940 else 2941 return -EINVAL; 2942 2943 /* setup afmt */ 2944 r = dce_v11_0_afmt_init(adev); 2945 if (r) 2946 return r; 2947 2948 r = dce_v11_0_audio_init(adev); 2949 if (r) 2950 return r; 2951 2952 /* Disable vblank IRQs aggressively for power-saving */ 2953 /* XXX: can this be enabled for DC? */ 2954 adev_to_drm(adev)->vblank_disable_immediate = true; 2955 2956 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc); 2957 if (r) 2958 return r; 2959 2960 INIT_DELAYED_WORK(&adev->hotplug_work, 2961 amdgpu_display_hotplug_work_func); 2962 2963 drm_kms_helper_poll_init(adev_to_drm(adev)); 2964 2965 adev->mode_info.mode_config_initialized = true; 2966 return 0; 2967 } 2968 2969 static int dce_v11_0_sw_fini(void *handle) 2970 { 2971 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2972 2973 kfree(adev->mode_info.bios_hardcoded_edid); 2974 2975 drm_kms_helper_poll_fini(adev_to_drm(adev)); 2976 2977 dce_v11_0_audio_fini(adev); 2978 2979 dce_v11_0_afmt_fini(adev); 2980 2981 drm_mode_config_cleanup(adev_to_drm(adev)); 2982 adev->mode_info.mode_config_initialized = false; 2983 2984 return 0; 2985 } 2986 2987 static int dce_v11_0_hw_init(void *handle) 2988 { 2989 int i; 2990 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2991 2992 dce_v11_0_init_golden_registers(adev); 2993 2994 /* disable vga render */ 2995 dce_v11_0_set_vga_render_state(adev, false); 2996 /* init dig PHYs, disp eng pll */ 2997 amdgpu_atombios_crtc_powergate_init(adev); 2998 amdgpu_atombios_encoder_init_dig(adev); 2999 if ((adev->asic_type == CHIP_POLARIS10) || 3000 (adev->asic_type == CHIP_POLARIS11) || 3001 (adev->asic_type == CHIP_POLARIS12) || 3002 (adev->asic_type == CHIP_VEGAM)) { 3003 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 3004 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 3005 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 3006 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 3007 } else { 3008 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3009 } 3010 3011 /* initialize hpd */ 3012 dce_v11_0_hpd_init(adev); 3013 3014 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3015 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3016 } 3017 3018 dce_v11_0_pageflip_interrupt_init(adev); 3019 3020 return 0; 3021 } 3022 3023 static int dce_v11_0_hw_fini(void *handle) 3024 { 3025 int i; 3026 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3027 3028 dce_v11_0_hpd_fini(adev); 3029 3030 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3031 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3032 } 3033 3034 dce_v11_0_pageflip_interrupt_fini(adev); 3035 3036 flush_delayed_work(&adev->hotplug_work); 3037 3038 return 0; 3039 } 3040 3041 static int dce_v11_0_suspend(void *handle) 3042 { 3043 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3044 int r; 3045 3046 r = amdgpu_display_suspend_helper(adev); 3047 if (r) 3048 return r; 3049 3050 adev->mode_info.bl_level = 3051 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 3052 3053 return dce_v11_0_hw_fini(handle); 3054 } 3055 3056 static int dce_v11_0_resume(void *handle) 3057 { 3058 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3059 int ret; 3060 3061 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 3062 adev->mode_info.bl_level); 3063 3064 ret = dce_v11_0_hw_init(handle); 3065 3066 /* turn on the BL */ 3067 if (adev->mode_info.bl_encoder) { 3068 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3069 adev->mode_info.bl_encoder); 3070 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3071 bl_level); 3072 } 3073 if (ret) 3074 return ret; 3075 3076 return amdgpu_display_resume_helper(adev); 3077 } 3078 3079 static bool dce_v11_0_is_idle(void *handle) 3080 { 3081 return true; 3082 } 3083 3084 static int dce_v11_0_wait_for_idle(void *handle) 3085 { 3086 return 0; 3087 } 3088 3089 static int dce_v11_0_soft_reset(void *handle) 3090 { 3091 u32 srbm_soft_reset = 0, tmp; 3092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3093 3094 if (dce_v11_0_is_display_hung(adev)) 3095 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3096 3097 if (srbm_soft_reset) { 3098 tmp = RREG32(mmSRBM_SOFT_RESET); 3099 tmp |= srbm_soft_reset; 3100 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3101 WREG32(mmSRBM_SOFT_RESET, tmp); 3102 tmp = RREG32(mmSRBM_SOFT_RESET); 3103 3104 udelay(50); 3105 3106 tmp &= ~srbm_soft_reset; 3107 WREG32(mmSRBM_SOFT_RESET, tmp); 3108 tmp = RREG32(mmSRBM_SOFT_RESET); 3109 3110 /* Wait a little for things to settle down */ 3111 udelay(50); 3112 } 3113 return 0; 3114 } 3115 3116 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3117 int crtc, 3118 enum amdgpu_interrupt_state state) 3119 { 3120 u32 lb_interrupt_mask; 3121 3122 if (crtc >= adev->mode_info.num_crtc) { 3123 DRM_DEBUG("invalid crtc %d\n", crtc); 3124 return; 3125 } 3126 3127 switch (state) { 3128 case AMDGPU_IRQ_STATE_DISABLE: 3129 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3130 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3131 VBLANK_INTERRUPT_MASK, 0); 3132 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3133 break; 3134 case AMDGPU_IRQ_STATE_ENABLE: 3135 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3136 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3137 VBLANK_INTERRUPT_MASK, 1); 3138 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3139 break; 3140 default: 3141 break; 3142 } 3143 } 3144 3145 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3146 int crtc, 3147 enum amdgpu_interrupt_state state) 3148 { 3149 u32 lb_interrupt_mask; 3150 3151 if (crtc >= adev->mode_info.num_crtc) { 3152 DRM_DEBUG("invalid crtc %d\n", crtc); 3153 return; 3154 } 3155 3156 switch (state) { 3157 case AMDGPU_IRQ_STATE_DISABLE: 3158 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3159 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3160 VLINE_INTERRUPT_MASK, 0); 3161 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3162 break; 3163 case AMDGPU_IRQ_STATE_ENABLE: 3164 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3165 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3166 VLINE_INTERRUPT_MASK, 1); 3167 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3168 break; 3169 default: 3170 break; 3171 } 3172 } 3173 3174 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3175 struct amdgpu_irq_src *source, 3176 unsigned hpd, 3177 enum amdgpu_interrupt_state state) 3178 { 3179 u32 tmp; 3180 3181 if (hpd >= adev->mode_info.num_hpd) { 3182 DRM_DEBUG("invalid hdp %d\n", hpd); 3183 return 0; 3184 } 3185 3186 switch (state) { 3187 case AMDGPU_IRQ_STATE_DISABLE: 3188 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3189 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3190 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3191 break; 3192 case AMDGPU_IRQ_STATE_ENABLE: 3193 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3194 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3195 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3196 break; 3197 default: 3198 break; 3199 } 3200 3201 return 0; 3202 } 3203 3204 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3205 struct amdgpu_irq_src *source, 3206 unsigned type, 3207 enum amdgpu_interrupt_state state) 3208 { 3209 switch (type) { 3210 case AMDGPU_CRTC_IRQ_VBLANK1: 3211 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3212 break; 3213 case AMDGPU_CRTC_IRQ_VBLANK2: 3214 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3215 break; 3216 case AMDGPU_CRTC_IRQ_VBLANK3: 3217 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3218 break; 3219 case AMDGPU_CRTC_IRQ_VBLANK4: 3220 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3221 break; 3222 case AMDGPU_CRTC_IRQ_VBLANK5: 3223 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3224 break; 3225 case AMDGPU_CRTC_IRQ_VBLANK6: 3226 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3227 break; 3228 case AMDGPU_CRTC_IRQ_VLINE1: 3229 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3230 break; 3231 case AMDGPU_CRTC_IRQ_VLINE2: 3232 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3233 break; 3234 case AMDGPU_CRTC_IRQ_VLINE3: 3235 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3236 break; 3237 case AMDGPU_CRTC_IRQ_VLINE4: 3238 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3239 break; 3240 case AMDGPU_CRTC_IRQ_VLINE5: 3241 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3242 break; 3243 case AMDGPU_CRTC_IRQ_VLINE6: 3244 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3245 break; 3246 default: 3247 break; 3248 } 3249 return 0; 3250 } 3251 3252 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3253 struct amdgpu_irq_src *src, 3254 unsigned type, 3255 enum amdgpu_interrupt_state state) 3256 { 3257 u32 reg; 3258 3259 if (type >= adev->mode_info.num_crtc) { 3260 DRM_ERROR("invalid pageflip crtc %d\n", type); 3261 return -EINVAL; 3262 } 3263 3264 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3265 if (state == AMDGPU_IRQ_STATE_DISABLE) 3266 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3267 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3268 else 3269 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3270 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3271 3272 return 0; 3273 } 3274 3275 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3276 struct amdgpu_irq_src *source, 3277 struct amdgpu_iv_entry *entry) 3278 { 3279 unsigned long flags; 3280 unsigned crtc_id; 3281 struct amdgpu_crtc *amdgpu_crtc; 3282 struct amdgpu_flip_work *works; 3283 3284 crtc_id = (entry->src_id - 8) >> 1; 3285 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3286 3287 if (crtc_id >= adev->mode_info.num_crtc) { 3288 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3289 return -EINVAL; 3290 } 3291 3292 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3293 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3294 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3295 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3296 3297 /* IRQ could occur when in initial stage */ 3298 if(amdgpu_crtc == NULL) 3299 return 0; 3300 3301 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); 3302 works = amdgpu_crtc->pflip_works; 3303 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3304 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3305 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3306 amdgpu_crtc->pflip_status, 3307 AMDGPU_FLIP_SUBMITTED); 3308 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3309 return 0; 3310 } 3311 3312 /* page flip completed. clean up */ 3313 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3314 amdgpu_crtc->pflip_works = NULL; 3315 3316 /* wakeup usersapce */ 3317 if(works->event) 3318 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3319 3320 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags); 3321 3322 drm_crtc_vblank_put(&amdgpu_crtc->base); 3323 schedule_work(&works->unpin_work); 3324 3325 return 0; 3326 } 3327 3328 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3329 int hpd) 3330 { 3331 u32 tmp; 3332 3333 if (hpd >= adev->mode_info.num_hpd) { 3334 DRM_DEBUG("invalid hdp %d\n", hpd); 3335 return; 3336 } 3337 3338 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3339 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3340 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3341 } 3342 3343 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3344 int crtc) 3345 { 3346 u32 tmp; 3347 3348 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3349 DRM_DEBUG("invalid crtc %d\n", crtc); 3350 return; 3351 } 3352 3353 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3354 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3355 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3356 } 3357 3358 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3359 int crtc) 3360 { 3361 u32 tmp; 3362 3363 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3364 DRM_DEBUG("invalid crtc %d\n", crtc); 3365 return; 3366 } 3367 3368 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3369 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3370 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3371 } 3372 3373 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3374 struct amdgpu_irq_src *source, 3375 struct amdgpu_iv_entry *entry) 3376 { 3377 unsigned crtc = entry->src_id - 1; 3378 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3379 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3380 crtc); 3381 3382 switch (entry->src_data[0]) { 3383 case 0: /* vblank */ 3384 if (disp_int & interrupt_status_offsets[crtc].vblank) 3385 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3386 else 3387 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3388 3389 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3390 drm_handle_vblank(adev_to_drm(adev), crtc); 3391 } 3392 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3393 3394 break; 3395 case 1: /* vline */ 3396 if (disp_int & interrupt_status_offsets[crtc].vline) 3397 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3398 else 3399 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3400 3401 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3402 3403 break; 3404 default: 3405 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3406 break; 3407 } 3408 3409 return 0; 3410 } 3411 3412 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3413 struct amdgpu_irq_src *source, 3414 struct amdgpu_iv_entry *entry) 3415 { 3416 uint32_t disp_int, mask; 3417 unsigned hpd; 3418 3419 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3420 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3421 return 0; 3422 } 3423 3424 hpd = entry->src_data[0]; 3425 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3426 mask = interrupt_status_offsets[hpd].hpd; 3427 3428 if (disp_int & mask) { 3429 dce_v11_0_hpd_int_ack(adev, hpd); 3430 schedule_delayed_work(&adev->hotplug_work, 0); 3431 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3432 } 3433 3434 return 0; 3435 } 3436 3437 static int dce_v11_0_set_clockgating_state(void *handle, 3438 enum amd_clockgating_state state) 3439 { 3440 return 0; 3441 } 3442 3443 static int dce_v11_0_set_powergating_state(void *handle, 3444 enum amd_powergating_state state) 3445 { 3446 return 0; 3447 } 3448 3449 static const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3450 .name = "dce_v11_0", 3451 .early_init = dce_v11_0_early_init, 3452 .late_init = NULL, 3453 .sw_init = dce_v11_0_sw_init, 3454 .sw_fini = dce_v11_0_sw_fini, 3455 .hw_init = dce_v11_0_hw_init, 3456 .hw_fini = dce_v11_0_hw_fini, 3457 .suspend = dce_v11_0_suspend, 3458 .resume = dce_v11_0_resume, 3459 .is_idle = dce_v11_0_is_idle, 3460 .wait_for_idle = dce_v11_0_wait_for_idle, 3461 .soft_reset = dce_v11_0_soft_reset, 3462 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3463 .set_powergating_state = dce_v11_0_set_powergating_state, 3464 }; 3465 3466 static void 3467 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3468 struct drm_display_mode *mode, 3469 struct drm_display_mode *adjusted_mode) 3470 { 3471 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3472 3473 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3474 3475 /* need to call this here rather than in prepare() since we need some crtc info */ 3476 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3477 3478 /* set scaler clears this on some chips */ 3479 dce_v11_0_set_interleave(encoder->crtc, mode); 3480 3481 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3482 dce_v11_0_afmt_enable(encoder, true); 3483 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3484 } 3485 } 3486 3487 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3488 { 3489 struct amdgpu_device *adev = drm_to_adev(encoder->dev); 3490 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3491 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3492 3493 if ((amdgpu_encoder->active_device & 3494 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3495 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3496 ENCODER_OBJECT_ID_NONE)) { 3497 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3498 if (dig) { 3499 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3500 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3501 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3502 } 3503 } 3504 3505 amdgpu_atombios_scratch_regs_lock(adev, true); 3506 3507 if (connector) { 3508 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3509 3510 /* select the clock/data port if it uses a router */ 3511 if (amdgpu_connector->router.cd_valid) 3512 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3513 3514 /* turn eDP panel on for mode set */ 3515 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3516 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3517 ATOM_TRANSMITTER_ACTION_POWER_ON); 3518 } 3519 3520 /* this is needed for the pll/ss setup to work correctly in some cases */ 3521 amdgpu_atombios_encoder_set_crtc_source(encoder); 3522 /* set up the FMT blocks */ 3523 dce_v11_0_program_fmt(encoder); 3524 } 3525 3526 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3527 { 3528 struct drm_device *dev = encoder->dev; 3529 struct amdgpu_device *adev = drm_to_adev(dev); 3530 3531 /* need to call this here as we need the crtc set up */ 3532 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3533 amdgpu_atombios_scratch_regs_lock(adev, false); 3534 } 3535 3536 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3537 { 3538 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3539 struct amdgpu_encoder_atom_dig *dig; 3540 3541 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3542 3543 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3544 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3545 dce_v11_0_afmt_enable(encoder, false); 3546 dig = amdgpu_encoder->enc_priv; 3547 dig->dig_encoder = -1; 3548 } 3549 amdgpu_encoder->active_device = 0; 3550 } 3551 3552 /* these are handled by the primary encoders */ 3553 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3554 { 3555 3556 } 3557 3558 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3559 { 3560 3561 } 3562 3563 static void 3564 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3565 struct drm_display_mode *mode, 3566 struct drm_display_mode *adjusted_mode) 3567 { 3568 3569 } 3570 3571 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3572 { 3573 3574 } 3575 3576 static void 3577 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3578 { 3579 3580 } 3581 3582 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3583 .dpms = dce_v11_0_ext_dpms, 3584 .prepare = dce_v11_0_ext_prepare, 3585 .mode_set = dce_v11_0_ext_mode_set, 3586 .commit = dce_v11_0_ext_commit, 3587 .disable = dce_v11_0_ext_disable, 3588 /* no detect for TMDS/LVDS yet */ 3589 }; 3590 3591 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3592 .dpms = amdgpu_atombios_encoder_dpms, 3593 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3594 .prepare = dce_v11_0_encoder_prepare, 3595 .mode_set = dce_v11_0_encoder_mode_set, 3596 .commit = dce_v11_0_encoder_commit, 3597 .disable = dce_v11_0_encoder_disable, 3598 .detect = amdgpu_atombios_encoder_dig_detect, 3599 }; 3600 3601 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3602 .dpms = amdgpu_atombios_encoder_dpms, 3603 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3604 .prepare = dce_v11_0_encoder_prepare, 3605 .mode_set = dce_v11_0_encoder_mode_set, 3606 .commit = dce_v11_0_encoder_commit, 3607 .detect = amdgpu_atombios_encoder_dac_detect, 3608 }; 3609 3610 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3611 { 3612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3613 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3614 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3615 kfree(amdgpu_encoder->enc_priv); 3616 drm_encoder_cleanup(encoder); 3617 kfree(amdgpu_encoder); 3618 } 3619 3620 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3621 .destroy = dce_v11_0_encoder_destroy, 3622 }; 3623 3624 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3625 uint32_t encoder_enum, 3626 uint32_t supported_device, 3627 u16 caps) 3628 { 3629 struct drm_device *dev = adev_to_drm(adev); 3630 struct drm_encoder *encoder; 3631 struct amdgpu_encoder *amdgpu_encoder; 3632 3633 /* see if we already added it */ 3634 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3635 amdgpu_encoder = to_amdgpu_encoder(encoder); 3636 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3637 amdgpu_encoder->devices |= supported_device; 3638 return; 3639 } 3640 3641 } 3642 3643 /* add a new one */ 3644 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3645 if (!amdgpu_encoder) 3646 return; 3647 3648 encoder = &amdgpu_encoder->base; 3649 switch (adev->mode_info.num_crtc) { 3650 case 1: 3651 encoder->possible_crtcs = 0x1; 3652 break; 3653 case 2: 3654 default: 3655 encoder->possible_crtcs = 0x3; 3656 break; 3657 case 3: 3658 encoder->possible_crtcs = 0x7; 3659 break; 3660 case 4: 3661 encoder->possible_crtcs = 0xf; 3662 break; 3663 case 5: 3664 encoder->possible_crtcs = 0x1f; 3665 break; 3666 case 6: 3667 encoder->possible_crtcs = 0x3f; 3668 break; 3669 } 3670 3671 amdgpu_encoder->enc_priv = NULL; 3672 3673 amdgpu_encoder->encoder_enum = encoder_enum; 3674 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3675 amdgpu_encoder->devices = supported_device; 3676 amdgpu_encoder->rmx_type = RMX_OFF; 3677 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3678 amdgpu_encoder->is_ext_encoder = false; 3679 amdgpu_encoder->caps = caps; 3680 3681 switch (amdgpu_encoder->encoder_id) { 3682 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3683 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3684 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3685 DRM_MODE_ENCODER_DAC, NULL); 3686 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3687 break; 3688 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3689 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3690 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3691 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3692 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3693 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3694 amdgpu_encoder->rmx_type = RMX_FULL; 3695 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3696 DRM_MODE_ENCODER_LVDS, NULL); 3697 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3698 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3699 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3700 DRM_MODE_ENCODER_DAC, NULL); 3701 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3702 } else { 3703 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3704 DRM_MODE_ENCODER_TMDS, NULL); 3705 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3706 } 3707 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3708 break; 3709 case ENCODER_OBJECT_ID_SI170B: 3710 case ENCODER_OBJECT_ID_CH7303: 3711 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3712 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3713 case ENCODER_OBJECT_ID_TITFP513: 3714 case ENCODER_OBJECT_ID_VT1623: 3715 case ENCODER_OBJECT_ID_HDMI_SI1930: 3716 case ENCODER_OBJECT_ID_TRAVIS: 3717 case ENCODER_OBJECT_ID_NUTMEG: 3718 /* these are handled by the primary encoders */ 3719 amdgpu_encoder->is_ext_encoder = true; 3720 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3721 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3722 DRM_MODE_ENCODER_LVDS, NULL); 3723 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3724 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3725 DRM_MODE_ENCODER_DAC, NULL); 3726 else 3727 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3728 DRM_MODE_ENCODER_TMDS, NULL); 3729 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3730 break; 3731 } 3732 } 3733 3734 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3735 .bandwidth_update = &dce_v11_0_bandwidth_update, 3736 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3737 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3738 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3739 .hpd_sense = &dce_v11_0_hpd_sense, 3740 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3741 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3742 .page_flip = &dce_v11_0_page_flip, 3743 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3744 .add_encoder = &dce_v11_0_encoder_add, 3745 .add_connector = &amdgpu_connector_add, 3746 }; 3747 3748 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3749 { 3750 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3751 } 3752 3753 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3754 .set = dce_v11_0_set_crtc_irq_state, 3755 .process = dce_v11_0_crtc_irq, 3756 }; 3757 3758 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3759 .set = dce_v11_0_set_pageflip_irq_state, 3760 .process = dce_v11_0_pageflip_irq, 3761 }; 3762 3763 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3764 .set = dce_v11_0_set_hpd_irq_state, 3765 .process = dce_v11_0_hpd_irq, 3766 }; 3767 3768 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3769 { 3770 if (adev->mode_info.num_crtc > 0) 3771 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3772 else 3773 adev->crtc_irq.num_types = 0; 3774 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3775 3776 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3777 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3778 3779 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3780 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3781 } 3782 3783 const struct amdgpu_ip_block_version dce_v11_0_ip_block = 3784 { 3785 .type = AMD_IP_BLOCK_TYPE_DCE, 3786 .major = 11, 3787 .minor = 0, 3788 .rev = 0, 3789 .funcs = &dce_v11_0_ip_funcs, 3790 }; 3791 3792 const struct amdgpu_ip_block_version dce_v11_2_ip_block = 3793 { 3794 .type = AMD_IP_BLOCK_TYPE_DCE, 3795 .major = 11, 3796 .minor = 2, 3797 .rev = 0, 3798 .funcs = &dce_v11_0_ip_funcs, 3799 }; 3800