1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 #include "dce/dce_11_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET, 75 DIG7_REGISTER_OFFSET, 76 DIG8_REGISTER_OFFSET 77 }; 78 79 static const struct { 80 uint32_t reg; 81 uint32_t vblank; 82 uint32_t vline; 83 uint32_t hpd; 84 85 } interrupt_status_offsets[] = { { 86 .reg = mmDISP_INTERRUPT_STATUS, 87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 } }; 116 117 static const u32 cz_golden_settings_a11[] = 118 { 119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000, 121 }; 122 123 static const u32 cz_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 stoney_golden_settings_a11[] = 130 { 131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 132 mmFBC_MISC, 0x1f311fff, 0x14302000, 133 }; 134 135 136 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 137 { 138 switch (adev->asic_type) { 139 case CHIP_CARRIZO: 140 amdgpu_program_register_sequence(adev, 141 cz_mgcg_cgcg_init, 142 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 143 amdgpu_program_register_sequence(adev, 144 cz_golden_settings_a11, 145 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 146 break; 147 case CHIP_STONEY: 148 amdgpu_program_register_sequence(adev, 149 stoney_golden_settings_a11, 150 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 151 break; 152 default: 153 break; 154 } 155 } 156 157 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 158 u32 block_offset, u32 reg) 159 { 160 unsigned long flags; 161 u32 r; 162 163 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 164 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 165 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 166 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 167 168 return r; 169 } 170 171 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 172 u32 block_offset, u32 reg, u32 v) 173 { 174 unsigned long flags; 175 176 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 177 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 178 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 179 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 180 } 181 182 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 183 { 184 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 185 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 186 return true; 187 else 188 return false; 189 } 190 191 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 192 { 193 u32 pos1, pos2; 194 195 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 196 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 197 198 if (pos1 != pos2) 199 return true; 200 else 201 return false; 202 } 203 204 /** 205 * dce_v11_0_vblank_wait - vblank wait asic callback. 206 * 207 * @adev: amdgpu_device pointer 208 * @crtc: crtc to wait for vblank on 209 * 210 * Wait for vblank on the requested crtc (evergreen+). 211 */ 212 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 213 { 214 unsigned i = 100; 215 216 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 217 return; 218 219 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 220 return; 221 222 /* depending on when we hit vblank, we may be close to active; if so, 223 * wait for another frame. 224 */ 225 while (dce_v11_0_is_in_vblank(adev, crtc)) { 226 if (i++ == 100) { 227 i = 0; 228 if (!dce_v11_0_is_counter_moving(adev, crtc)) 229 break; 230 } 231 } 232 233 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 234 if (i++ == 100) { 235 i = 0; 236 if (!dce_v11_0_is_counter_moving(adev, crtc)) 237 break; 238 } 239 } 240 } 241 242 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 243 { 244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 245 return 0; 246 else 247 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 248 } 249 250 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 251 { 252 unsigned i; 253 254 /* Enable pflip interrupts */ 255 for (i = 0; i < adev->mode_info.num_crtc; i++) 256 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 257 } 258 259 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 260 { 261 unsigned i; 262 263 /* Disable pflip interrupts */ 264 for (i = 0; i < adev->mode_info.num_crtc; i++) 265 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 266 } 267 268 /** 269 * dce_v11_0_page_flip - pageflip callback. 270 * 271 * @adev: amdgpu_device pointer 272 * @crtc_id: crtc to cleanup pageflip on 273 * @crtc_base: new address of the crtc (GPU MC address) 274 * 275 * Triggers the actual pageflip by updating the primary 276 * surface base address. 277 */ 278 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 279 int crtc_id, u64 crtc_base) 280 { 281 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 282 283 /* update the scanout addresses */ 284 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 285 upper_32_bits(crtc_base)); 286 /* writing to the low address triggers the update */ 287 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 288 lower_32_bits(crtc_base)); 289 /* post the write */ 290 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 291 } 292 293 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 294 u32 *vbl, u32 *position) 295 { 296 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 297 return -EINVAL; 298 299 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 300 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 301 302 return 0; 303 } 304 305 /** 306 * dce_v11_0_hpd_sense - hpd sense callback. 307 * 308 * @adev: amdgpu_device pointer 309 * @hpd: hpd (hotplug detect) pin 310 * 311 * Checks if a digital monitor is connected (evergreen+). 312 * Returns true if connected, false if not connected. 313 */ 314 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 315 enum amdgpu_hpd_id hpd) 316 { 317 int idx; 318 bool connected = false; 319 320 switch (hpd) { 321 case AMDGPU_HPD_1: 322 idx = 0; 323 break; 324 case AMDGPU_HPD_2: 325 idx = 1; 326 break; 327 case AMDGPU_HPD_3: 328 idx = 2; 329 break; 330 case AMDGPU_HPD_4: 331 idx = 3; 332 break; 333 case AMDGPU_HPD_5: 334 idx = 4; 335 break; 336 case AMDGPU_HPD_6: 337 idx = 5; 338 break; 339 default: 340 return connected; 341 } 342 343 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 344 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 345 connected = true; 346 347 return connected; 348 } 349 350 /** 351 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 352 * 353 * @adev: amdgpu_device pointer 354 * @hpd: hpd (hotplug detect) pin 355 * 356 * Set the polarity of the hpd pin (evergreen+). 357 */ 358 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 359 enum amdgpu_hpd_id hpd) 360 { 361 u32 tmp; 362 bool connected = dce_v11_0_hpd_sense(adev, hpd); 363 int idx; 364 365 switch (hpd) { 366 case AMDGPU_HPD_1: 367 idx = 0; 368 break; 369 case AMDGPU_HPD_2: 370 idx = 1; 371 break; 372 case AMDGPU_HPD_3: 373 idx = 2; 374 break; 375 case AMDGPU_HPD_4: 376 idx = 3; 377 break; 378 case AMDGPU_HPD_5: 379 idx = 4; 380 break; 381 case AMDGPU_HPD_6: 382 idx = 5; 383 break; 384 default: 385 return; 386 } 387 388 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 389 if (connected) 390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 391 else 392 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 393 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 394 } 395 396 /** 397 * dce_v11_0_hpd_init - hpd setup callback. 398 * 399 * @adev: amdgpu_device pointer 400 * 401 * Setup the hpd pins used by the card (evergreen+). 402 * Enable the pin, set the polarity, and enable the hpd interrupts. 403 */ 404 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 405 { 406 struct drm_device *dev = adev->ddev; 407 struct drm_connector *connector; 408 u32 tmp; 409 int idx; 410 411 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 412 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 413 414 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 415 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 416 /* don't try to enable hpd on eDP or LVDS avoid breaking the 417 * aux dp channel on imac and help (but not completely fix) 418 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 419 * also avoid interrupt storms during dpms. 420 */ 421 continue; 422 } 423 424 switch (amdgpu_connector->hpd.hpd) { 425 case AMDGPU_HPD_1: 426 idx = 0; 427 break; 428 case AMDGPU_HPD_2: 429 idx = 1; 430 break; 431 case AMDGPU_HPD_3: 432 idx = 2; 433 break; 434 case AMDGPU_HPD_4: 435 idx = 3; 436 break; 437 case AMDGPU_HPD_5: 438 idx = 4; 439 break; 440 case AMDGPU_HPD_6: 441 idx = 5; 442 break; 443 default: 444 continue; 445 } 446 447 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 448 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 449 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 450 451 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 452 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 453 DC_HPD_CONNECT_INT_DELAY, 454 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 455 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 456 DC_HPD_DISCONNECT_INT_DELAY, 457 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 458 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 459 460 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 461 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 462 } 463 } 464 465 /** 466 * dce_v11_0_hpd_fini - hpd tear down callback. 467 * 468 * @adev: amdgpu_device pointer 469 * 470 * Tear down the hpd pins used by the card (evergreen+). 471 * Disable the hpd interrupts. 472 */ 473 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 474 { 475 struct drm_device *dev = adev->ddev; 476 struct drm_connector *connector; 477 u32 tmp; 478 int idx; 479 480 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 481 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 482 483 switch (amdgpu_connector->hpd.hpd) { 484 case AMDGPU_HPD_1: 485 idx = 0; 486 break; 487 case AMDGPU_HPD_2: 488 idx = 1; 489 break; 490 case AMDGPU_HPD_3: 491 idx = 2; 492 break; 493 case AMDGPU_HPD_4: 494 idx = 3; 495 break; 496 case AMDGPU_HPD_5: 497 idx = 4; 498 break; 499 case AMDGPU_HPD_6: 500 idx = 5; 501 break; 502 default: 503 continue; 504 } 505 506 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 507 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 508 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 509 510 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 511 } 512 } 513 514 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 515 { 516 return mmDC_GPIO_HPD_A; 517 } 518 519 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 520 { 521 u32 crtc_hung = 0; 522 u32 crtc_status[6]; 523 u32 i, j, tmp; 524 525 for (i = 0; i < adev->mode_info.num_crtc; i++) { 526 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 527 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 528 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 529 crtc_hung |= (1 << i); 530 } 531 } 532 533 for (j = 0; j < 10; j++) { 534 for (i = 0; i < adev->mode_info.num_crtc; i++) { 535 if (crtc_hung & (1 << i)) { 536 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 537 if (tmp != crtc_status[i]) 538 crtc_hung &= ~(1 << i); 539 } 540 } 541 if (crtc_hung == 0) 542 return false; 543 udelay(100); 544 } 545 546 return true; 547 } 548 549 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 550 struct amdgpu_mode_mc_save *save) 551 { 552 u32 crtc_enabled, tmp; 553 int i; 554 555 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 556 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 557 558 /* disable VGA render */ 559 tmp = RREG32(mmVGA_RENDER_CONTROL); 560 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 561 WREG32(mmVGA_RENDER_CONTROL, tmp); 562 563 /* blank the display controllers */ 564 for (i = 0; i < adev->mode_info.num_crtc; i++) { 565 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 566 CRTC_CONTROL, CRTC_MASTER_EN); 567 if (crtc_enabled) { 568 #if 0 569 u32 frame_count; 570 int j; 571 572 save->crtc_enabled[i] = true; 573 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 574 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 575 amdgpu_display_vblank_wait(adev, i); 576 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 577 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 578 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 579 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 580 } 581 /* wait for the next frame */ 582 frame_count = amdgpu_display_vblank_get_counter(adev, i); 583 for (j = 0; j < adev->usec_timeout; j++) { 584 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 585 break; 586 udelay(1); 587 } 588 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 589 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 590 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 591 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 592 } 593 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); 594 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 595 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 596 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 597 } 598 #else 599 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 600 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 601 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 602 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 603 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 604 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 605 save->crtc_enabled[i] = false; 606 /* ***** */ 607 #endif 608 } else { 609 save->crtc_enabled[i] = false; 610 } 611 } 612 } 613 614 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 615 struct amdgpu_mode_mc_save *save) 616 { 617 u32 tmp, frame_count; 618 int i, j; 619 620 /* update crtc base addresses */ 621 for (i = 0; i < adev->mode_info.num_crtc; i++) { 622 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 623 upper_32_bits(adev->mc.vram_start)); 624 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 625 upper_32_bits(adev->mc.vram_start)); 626 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 627 (u32)adev->mc.vram_start); 628 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 629 (u32)adev->mc.vram_start); 630 631 if (save->crtc_enabled[i]) { 632 tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); 633 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { 634 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); 635 WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); 636 } 637 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 638 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 639 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 640 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 641 } 642 tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); 643 if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 644 tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 645 WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 646 } 647 for (j = 0; j < adev->usec_timeout; j++) { 648 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 649 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 650 break; 651 udelay(1); 652 } 653 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 654 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 655 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 656 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 657 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 658 /* wait for the next frame */ 659 frame_count = amdgpu_display_vblank_get_counter(adev, i); 660 for (j = 0; j < adev->usec_timeout; j++) { 661 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 662 break; 663 udelay(1); 664 } 665 } 666 } 667 668 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 669 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 670 671 /* Unlock vga access */ 672 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 673 mdelay(1); 674 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 675 } 676 677 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 678 bool render) 679 { 680 u32 tmp; 681 682 /* Lockout access through VGA aperture*/ 683 tmp = RREG32(mmVGA_HDP_CONTROL); 684 if (render) 685 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 686 else 687 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 688 WREG32(mmVGA_HDP_CONTROL, tmp); 689 690 /* disable VGA render */ 691 tmp = RREG32(mmVGA_RENDER_CONTROL); 692 if (render) 693 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 694 else 695 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 696 WREG32(mmVGA_RENDER_CONTROL, tmp); 697 } 698 699 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 700 { 701 struct drm_device *dev = encoder->dev; 702 struct amdgpu_device *adev = dev->dev_private; 703 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 704 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 705 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 706 int bpc = 0; 707 u32 tmp = 0; 708 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 709 710 if (connector) { 711 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 712 bpc = amdgpu_connector_get_monitor_bpc(connector); 713 dither = amdgpu_connector->dither; 714 } 715 716 /* LVDS/eDP FMT is set up by atom */ 717 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 718 return; 719 720 /* not needed for analog */ 721 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 722 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 723 return; 724 725 if (bpc == 0) 726 return; 727 728 switch (bpc) { 729 case 6: 730 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 731 /* XXX sort out optimal dither settings */ 732 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 733 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 734 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 736 } else { 737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 739 } 740 break; 741 case 8: 742 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 743 /* XXX sort out optimal dither settings */ 744 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 745 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 746 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 747 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 748 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 749 } else { 750 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 751 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 752 } 753 break; 754 case 10: 755 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 756 /* XXX sort out optimal dither settings */ 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 760 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 762 } else { 763 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 764 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 765 } 766 break; 767 default: 768 /* not needed */ 769 break; 770 } 771 772 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 773 } 774 775 776 /* display watermark setup */ 777 /** 778 * dce_v11_0_line_buffer_adjust - Set up the line buffer 779 * 780 * @adev: amdgpu_device pointer 781 * @amdgpu_crtc: the selected display controller 782 * @mode: the current display mode on the selected display 783 * controller 784 * 785 * Setup up the line buffer allocation for 786 * the selected display controller (CIK). 787 * Returns the line buffer size in pixels. 788 */ 789 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 790 struct amdgpu_crtc *amdgpu_crtc, 791 struct drm_display_mode *mode) 792 { 793 u32 tmp, buffer_alloc, i, mem_cfg; 794 u32 pipe_offset = amdgpu_crtc->crtc_id; 795 /* 796 * Line Buffer Setup 797 * There are 6 line buffers, one for each display controllers. 798 * There are 3 partitions per LB. Select the number of partitions 799 * to enable based on the display width. For display widths larger 800 * than 4096, you need use to use 2 display controllers and combine 801 * them using the stereo blender. 802 */ 803 if (amdgpu_crtc->base.enabled && mode) { 804 if (mode->crtc_hdisplay < 1920) { 805 mem_cfg = 1; 806 buffer_alloc = 2; 807 } else if (mode->crtc_hdisplay < 2560) { 808 mem_cfg = 2; 809 buffer_alloc = 2; 810 } else if (mode->crtc_hdisplay < 4096) { 811 mem_cfg = 0; 812 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 813 } else { 814 DRM_DEBUG_KMS("Mode too big for LB!\n"); 815 mem_cfg = 0; 816 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 817 } 818 } else { 819 mem_cfg = 1; 820 buffer_alloc = 0; 821 } 822 823 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 824 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 825 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 826 827 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 828 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 829 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 830 831 for (i = 0; i < adev->usec_timeout; i++) { 832 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 833 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 834 break; 835 udelay(1); 836 } 837 838 if (amdgpu_crtc->base.enabled && mode) { 839 switch (mem_cfg) { 840 case 0: 841 default: 842 return 4096 * 2; 843 case 1: 844 return 1920 * 2; 845 case 2: 846 return 2560 * 2; 847 } 848 } 849 850 /* controller not enabled, so no lb used */ 851 return 0; 852 } 853 854 /** 855 * cik_get_number_of_dram_channels - get the number of dram channels 856 * 857 * @adev: amdgpu_device pointer 858 * 859 * Look up the number of video ram channels (CIK). 860 * Used for display watermark bandwidth calculations 861 * Returns the number of dram channels 862 */ 863 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 864 { 865 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 866 867 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 868 case 0: 869 default: 870 return 1; 871 case 1: 872 return 2; 873 case 2: 874 return 4; 875 case 3: 876 return 8; 877 case 4: 878 return 3; 879 case 5: 880 return 6; 881 case 6: 882 return 10; 883 case 7: 884 return 12; 885 case 8: 886 return 16; 887 } 888 } 889 890 struct dce10_wm_params { 891 u32 dram_channels; /* number of dram channels */ 892 u32 yclk; /* bandwidth per dram data pin in kHz */ 893 u32 sclk; /* engine clock in kHz */ 894 u32 disp_clk; /* display clock in kHz */ 895 u32 src_width; /* viewport width */ 896 u32 active_time; /* active display time in ns */ 897 u32 blank_time; /* blank time in ns */ 898 bool interlaced; /* mode is interlaced */ 899 fixed20_12 vsc; /* vertical scale ratio */ 900 u32 num_heads; /* number of active crtcs */ 901 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 902 u32 lb_size; /* line buffer allocated to pipe */ 903 u32 vtaps; /* vertical scaler taps */ 904 }; 905 906 /** 907 * dce_v11_0_dram_bandwidth - get the dram bandwidth 908 * 909 * @wm: watermark calculation data 910 * 911 * Calculate the raw dram bandwidth (CIK). 912 * Used for display watermark bandwidth calculations 913 * Returns the dram bandwidth in MBytes/s 914 */ 915 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 916 { 917 /* Calculate raw DRAM Bandwidth */ 918 fixed20_12 dram_efficiency; /* 0.7 */ 919 fixed20_12 yclk, dram_channels, bandwidth; 920 fixed20_12 a; 921 922 a.full = dfixed_const(1000); 923 yclk.full = dfixed_const(wm->yclk); 924 yclk.full = dfixed_div(yclk, a); 925 dram_channels.full = dfixed_const(wm->dram_channels * 4); 926 a.full = dfixed_const(10); 927 dram_efficiency.full = dfixed_const(7); 928 dram_efficiency.full = dfixed_div(dram_efficiency, a); 929 bandwidth.full = dfixed_mul(dram_channels, yclk); 930 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 931 932 return dfixed_trunc(bandwidth); 933 } 934 935 /** 936 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 937 * 938 * @wm: watermark calculation data 939 * 940 * Calculate the dram bandwidth used for display (CIK). 941 * Used for display watermark bandwidth calculations 942 * Returns the dram bandwidth for display in MBytes/s 943 */ 944 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 945 { 946 /* Calculate DRAM Bandwidth and the part allocated to display. */ 947 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 948 fixed20_12 yclk, dram_channels, bandwidth; 949 fixed20_12 a; 950 951 a.full = dfixed_const(1000); 952 yclk.full = dfixed_const(wm->yclk); 953 yclk.full = dfixed_div(yclk, a); 954 dram_channels.full = dfixed_const(wm->dram_channels * 4); 955 a.full = dfixed_const(10); 956 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 957 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 958 bandwidth.full = dfixed_mul(dram_channels, yclk); 959 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 960 961 return dfixed_trunc(bandwidth); 962 } 963 964 /** 965 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 966 * 967 * @wm: watermark calculation data 968 * 969 * Calculate the data return bandwidth used for display (CIK). 970 * Used for display watermark bandwidth calculations 971 * Returns the data return bandwidth in MBytes/s 972 */ 973 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 974 { 975 /* Calculate the display Data return Bandwidth */ 976 fixed20_12 return_efficiency; /* 0.8 */ 977 fixed20_12 sclk, bandwidth; 978 fixed20_12 a; 979 980 a.full = dfixed_const(1000); 981 sclk.full = dfixed_const(wm->sclk); 982 sclk.full = dfixed_div(sclk, a); 983 a.full = dfixed_const(10); 984 return_efficiency.full = dfixed_const(8); 985 return_efficiency.full = dfixed_div(return_efficiency, a); 986 a.full = dfixed_const(32); 987 bandwidth.full = dfixed_mul(a, sclk); 988 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 989 990 return dfixed_trunc(bandwidth); 991 } 992 993 /** 994 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 995 * 996 * @wm: watermark calculation data 997 * 998 * Calculate the dmif bandwidth used for display (CIK). 999 * Used for display watermark bandwidth calculations 1000 * Returns the dmif bandwidth in MBytes/s 1001 */ 1002 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 1003 { 1004 /* Calculate the DMIF Request Bandwidth */ 1005 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 1006 fixed20_12 disp_clk, bandwidth; 1007 fixed20_12 a, b; 1008 1009 a.full = dfixed_const(1000); 1010 disp_clk.full = dfixed_const(wm->disp_clk); 1011 disp_clk.full = dfixed_div(disp_clk, a); 1012 a.full = dfixed_const(32); 1013 b.full = dfixed_mul(a, disp_clk); 1014 1015 a.full = dfixed_const(10); 1016 disp_clk_request_efficiency.full = dfixed_const(8); 1017 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1018 1019 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1020 1021 return dfixed_trunc(bandwidth); 1022 } 1023 1024 /** 1025 * dce_v11_0_available_bandwidth - get the min available bandwidth 1026 * 1027 * @wm: watermark calculation data 1028 * 1029 * Calculate the min available bandwidth used for display (CIK). 1030 * Used for display watermark bandwidth calculations 1031 * Returns the min available bandwidth in MBytes/s 1032 */ 1033 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 1034 { 1035 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1036 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 1037 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 1038 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 1039 1040 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1041 } 1042 1043 /** 1044 * dce_v11_0_average_bandwidth - get the average available bandwidth 1045 * 1046 * @wm: watermark calculation data 1047 * 1048 * Calculate the average available bandwidth used for display (CIK). 1049 * Used for display watermark bandwidth calculations 1050 * Returns the average available bandwidth in MBytes/s 1051 */ 1052 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 1053 { 1054 /* Calculate the display mode Average Bandwidth 1055 * DisplayMode should contain the source and destination dimensions, 1056 * timing, etc. 1057 */ 1058 fixed20_12 bpp; 1059 fixed20_12 line_time; 1060 fixed20_12 src_width; 1061 fixed20_12 bandwidth; 1062 fixed20_12 a; 1063 1064 a.full = dfixed_const(1000); 1065 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1066 line_time.full = dfixed_div(line_time, a); 1067 bpp.full = dfixed_const(wm->bytes_per_pixel); 1068 src_width.full = dfixed_const(wm->src_width); 1069 bandwidth.full = dfixed_mul(src_width, bpp); 1070 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1071 bandwidth.full = dfixed_div(bandwidth, line_time); 1072 1073 return dfixed_trunc(bandwidth); 1074 } 1075 1076 /** 1077 * dce_v11_0_latency_watermark - get the latency watermark 1078 * 1079 * @wm: watermark calculation data 1080 * 1081 * Calculate the latency watermark (CIK). 1082 * Used for display watermark bandwidth calculations 1083 * Returns the latency watermark in ns 1084 */ 1085 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1086 { 1087 /* First calculate the latency in ns */ 1088 u32 mc_latency = 2000; /* 2000 ns. */ 1089 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1090 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1091 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1092 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1093 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1094 (wm->num_heads * cursor_line_pair_return_time); 1095 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1096 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1097 u32 tmp, dmif_size = 12288; 1098 fixed20_12 a, b, c; 1099 1100 if (wm->num_heads == 0) 1101 return 0; 1102 1103 a.full = dfixed_const(2); 1104 b.full = dfixed_const(1); 1105 if ((wm->vsc.full > a.full) || 1106 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1107 (wm->vtaps >= 5) || 1108 ((wm->vsc.full >= a.full) && wm->interlaced)) 1109 max_src_lines_per_dst_line = 4; 1110 else 1111 max_src_lines_per_dst_line = 2; 1112 1113 a.full = dfixed_const(available_bandwidth); 1114 b.full = dfixed_const(wm->num_heads); 1115 a.full = dfixed_div(a, b); 1116 1117 b.full = dfixed_const(mc_latency + 512); 1118 c.full = dfixed_const(wm->disp_clk); 1119 b.full = dfixed_div(b, c); 1120 1121 c.full = dfixed_const(dmif_size); 1122 b.full = dfixed_div(c, b); 1123 1124 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1125 1126 b.full = dfixed_const(1000); 1127 c.full = dfixed_const(wm->disp_clk); 1128 b.full = dfixed_div(c, b); 1129 c.full = dfixed_const(wm->bytes_per_pixel); 1130 b.full = dfixed_mul(b, c); 1131 1132 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1133 1134 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1135 b.full = dfixed_const(1000); 1136 c.full = dfixed_const(lb_fill_bw); 1137 b.full = dfixed_div(c, b); 1138 a.full = dfixed_div(a, b); 1139 line_fill_time = dfixed_trunc(a); 1140 1141 if (line_fill_time < wm->active_time) 1142 return latency; 1143 else 1144 return latency + (line_fill_time - wm->active_time); 1145 1146 } 1147 1148 /** 1149 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1150 * average and available dram bandwidth 1151 * 1152 * @wm: watermark calculation data 1153 * 1154 * Check if the display average bandwidth fits in the display 1155 * dram bandwidth (CIK). 1156 * Used for display watermark bandwidth calculations 1157 * Returns true if the display fits, false if not. 1158 */ 1159 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1160 { 1161 if (dce_v11_0_average_bandwidth(wm) <= 1162 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1163 return true; 1164 else 1165 return false; 1166 } 1167 1168 /** 1169 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1170 * average and available bandwidth 1171 * 1172 * @wm: watermark calculation data 1173 * 1174 * Check if the display average bandwidth fits in the display 1175 * available bandwidth (CIK). 1176 * Used for display watermark bandwidth calculations 1177 * Returns true if the display fits, false if not. 1178 */ 1179 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1180 { 1181 if (dce_v11_0_average_bandwidth(wm) <= 1182 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1183 return true; 1184 else 1185 return false; 1186 } 1187 1188 /** 1189 * dce_v11_0_check_latency_hiding - check latency hiding 1190 * 1191 * @wm: watermark calculation data 1192 * 1193 * Check latency hiding (CIK). 1194 * Used for display watermark bandwidth calculations 1195 * Returns true if the display fits, false if not. 1196 */ 1197 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1198 { 1199 u32 lb_partitions = wm->lb_size / wm->src_width; 1200 u32 line_time = wm->active_time + wm->blank_time; 1201 u32 latency_tolerant_lines; 1202 u32 latency_hiding; 1203 fixed20_12 a; 1204 1205 a.full = dfixed_const(1); 1206 if (wm->vsc.full > a.full) 1207 latency_tolerant_lines = 1; 1208 else { 1209 if (lb_partitions <= (wm->vtaps + 1)) 1210 latency_tolerant_lines = 1; 1211 else 1212 latency_tolerant_lines = 2; 1213 } 1214 1215 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1216 1217 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1218 return true; 1219 else 1220 return false; 1221 } 1222 1223 /** 1224 * dce_v11_0_program_watermarks - program display watermarks 1225 * 1226 * @adev: amdgpu_device pointer 1227 * @amdgpu_crtc: the selected display controller 1228 * @lb_size: line buffer size 1229 * @num_heads: number of display controllers in use 1230 * 1231 * Calculate and program the display watermarks for the 1232 * selected display controller (CIK). 1233 */ 1234 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1235 struct amdgpu_crtc *amdgpu_crtc, 1236 u32 lb_size, u32 num_heads) 1237 { 1238 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1239 struct dce10_wm_params wm_low, wm_high; 1240 u32 pixel_period; 1241 u32 line_time = 0; 1242 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1243 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1244 1245 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1246 pixel_period = 1000000 / (u32)mode->clock; 1247 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1248 1249 /* watermark for high clocks */ 1250 if (adev->pm.dpm_enabled) { 1251 wm_high.yclk = 1252 amdgpu_dpm_get_mclk(adev, false) * 10; 1253 wm_high.sclk = 1254 amdgpu_dpm_get_sclk(adev, false) * 10; 1255 } else { 1256 wm_high.yclk = adev->pm.current_mclk * 10; 1257 wm_high.sclk = adev->pm.current_sclk * 10; 1258 } 1259 1260 wm_high.disp_clk = mode->clock; 1261 wm_high.src_width = mode->crtc_hdisplay; 1262 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1263 wm_high.blank_time = line_time - wm_high.active_time; 1264 wm_high.interlaced = false; 1265 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1266 wm_high.interlaced = true; 1267 wm_high.vsc = amdgpu_crtc->vsc; 1268 wm_high.vtaps = 1; 1269 if (amdgpu_crtc->rmx_type != RMX_OFF) 1270 wm_high.vtaps = 2; 1271 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1272 wm_high.lb_size = lb_size; 1273 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1274 wm_high.num_heads = num_heads; 1275 1276 /* set for high clocks */ 1277 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1278 1279 /* possibly force display priority to high */ 1280 /* should really do this at mode validation time... */ 1281 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1282 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1283 !dce_v11_0_check_latency_hiding(&wm_high) || 1284 (adev->mode_info.disp_priority == 2)) { 1285 DRM_DEBUG_KMS("force priority to high\n"); 1286 } 1287 1288 /* watermark for low clocks */ 1289 if (adev->pm.dpm_enabled) { 1290 wm_low.yclk = 1291 amdgpu_dpm_get_mclk(adev, true) * 10; 1292 wm_low.sclk = 1293 amdgpu_dpm_get_sclk(adev, true) * 10; 1294 } else { 1295 wm_low.yclk = adev->pm.current_mclk * 10; 1296 wm_low.sclk = adev->pm.current_sclk * 10; 1297 } 1298 1299 wm_low.disp_clk = mode->clock; 1300 wm_low.src_width = mode->crtc_hdisplay; 1301 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1302 wm_low.blank_time = line_time - wm_low.active_time; 1303 wm_low.interlaced = false; 1304 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1305 wm_low.interlaced = true; 1306 wm_low.vsc = amdgpu_crtc->vsc; 1307 wm_low.vtaps = 1; 1308 if (amdgpu_crtc->rmx_type != RMX_OFF) 1309 wm_low.vtaps = 2; 1310 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1311 wm_low.lb_size = lb_size; 1312 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1313 wm_low.num_heads = num_heads; 1314 1315 /* set for low clocks */ 1316 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1317 1318 /* possibly force display priority to high */ 1319 /* should really do this at mode validation time... */ 1320 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1321 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1322 !dce_v11_0_check_latency_hiding(&wm_low) || 1323 (adev->mode_info.disp_priority == 2)) { 1324 DRM_DEBUG_KMS("force priority to high\n"); 1325 } 1326 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1327 } 1328 1329 /* select wm A */ 1330 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1331 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1332 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1333 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1334 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1335 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1336 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1337 /* select wm B */ 1338 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1339 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1340 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1341 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1342 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1343 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1344 /* restore original selection */ 1345 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1346 1347 /* save values for DPM */ 1348 amdgpu_crtc->line_time = line_time; 1349 amdgpu_crtc->wm_high = latency_watermark_a; 1350 amdgpu_crtc->wm_low = latency_watermark_b; 1351 /* Save number of lines the linebuffer leads before the scanout */ 1352 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1353 } 1354 1355 /** 1356 * dce_v11_0_bandwidth_update - program display watermarks 1357 * 1358 * @adev: amdgpu_device pointer 1359 * 1360 * Calculate and program the display watermarks and line 1361 * buffer allocation (CIK). 1362 */ 1363 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1364 { 1365 struct drm_display_mode *mode = NULL; 1366 u32 num_heads = 0, lb_size; 1367 int i; 1368 1369 amdgpu_update_display_priority(adev); 1370 1371 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1372 if (adev->mode_info.crtcs[i]->base.enabled) 1373 num_heads++; 1374 } 1375 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1376 mode = &adev->mode_info.crtcs[i]->base.mode; 1377 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1378 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1379 lb_size, num_heads); 1380 } 1381 } 1382 1383 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1384 { 1385 int i; 1386 u32 offset, tmp; 1387 1388 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1389 offset = adev->mode_info.audio.pin[i].offset; 1390 tmp = RREG32_AUDIO_ENDPT(offset, 1391 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1392 if (((tmp & 1393 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1394 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1395 adev->mode_info.audio.pin[i].connected = false; 1396 else 1397 adev->mode_info.audio.pin[i].connected = true; 1398 } 1399 } 1400 1401 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1402 { 1403 int i; 1404 1405 dce_v11_0_audio_get_connected_pins(adev); 1406 1407 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1408 if (adev->mode_info.audio.pin[i].connected) 1409 return &adev->mode_info.audio.pin[i]; 1410 } 1411 DRM_ERROR("No connected audio pins found!\n"); 1412 return NULL; 1413 } 1414 1415 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1416 { 1417 struct amdgpu_device *adev = encoder->dev->dev_private; 1418 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1419 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1420 u32 tmp; 1421 1422 if (!dig || !dig->afmt || !dig->afmt->pin) 1423 return; 1424 1425 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1426 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1427 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1428 } 1429 1430 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1431 struct drm_display_mode *mode) 1432 { 1433 struct amdgpu_device *adev = encoder->dev->dev_private; 1434 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1435 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1436 struct drm_connector *connector; 1437 struct amdgpu_connector *amdgpu_connector = NULL; 1438 u32 tmp; 1439 int interlace = 0; 1440 1441 if (!dig || !dig->afmt || !dig->afmt->pin) 1442 return; 1443 1444 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1445 if (connector->encoder == encoder) { 1446 amdgpu_connector = to_amdgpu_connector(connector); 1447 break; 1448 } 1449 } 1450 1451 if (!amdgpu_connector) { 1452 DRM_ERROR("Couldn't find encoder's connector\n"); 1453 return; 1454 } 1455 1456 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1457 interlace = 1; 1458 if (connector->latency_present[interlace]) { 1459 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1460 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1461 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1462 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1463 } else { 1464 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1465 VIDEO_LIPSYNC, 0); 1466 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1467 AUDIO_LIPSYNC, 0); 1468 } 1469 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1470 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1471 } 1472 1473 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1474 { 1475 struct amdgpu_device *adev = encoder->dev->dev_private; 1476 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1477 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1478 struct drm_connector *connector; 1479 struct amdgpu_connector *amdgpu_connector = NULL; 1480 u32 tmp; 1481 u8 *sadb = NULL; 1482 int sad_count; 1483 1484 if (!dig || !dig->afmt || !dig->afmt->pin) 1485 return; 1486 1487 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1488 if (connector->encoder == encoder) { 1489 amdgpu_connector = to_amdgpu_connector(connector); 1490 break; 1491 } 1492 } 1493 1494 if (!amdgpu_connector) { 1495 DRM_ERROR("Couldn't find encoder's connector\n"); 1496 return; 1497 } 1498 1499 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1500 if (sad_count < 0) { 1501 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1502 sad_count = 0; 1503 } 1504 1505 /* program the speaker allocation */ 1506 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1507 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1508 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1509 DP_CONNECTION, 0); 1510 /* set HDMI mode */ 1511 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1512 HDMI_CONNECTION, 1); 1513 if (sad_count) 1514 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1515 SPEAKER_ALLOCATION, sadb[0]); 1516 else 1517 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1518 SPEAKER_ALLOCATION, 5); /* stereo */ 1519 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1520 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1521 1522 kfree(sadb); 1523 } 1524 1525 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1526 { 1527 struct amdgpu_device *adev = encoder->dev->dev_private; 1528 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1529 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1530 struct drm_connector *connector; 1531 struct amdgpu_connector *amdgpu_connector = NULL; 1532 struct cea_sad *sads; 1533 int i, sad_count; 1534 1535 static const u16 eld_reg_to_type[][2] = { 1536 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1537 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1538 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1539 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1540 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1541 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1542 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1543 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1544 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1545 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1546 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1547 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1548 }; 1549 1550 if (!dig || !dig->afmt || !dig->afmt->pin) 1551 return; 1552 1553 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1554 if (connector->encoder == encoder) { 1555 amdgpu_connector = to_amdgpu_connector(connector); 1556 break; 1557 } 1558 } 1559 1560 if (!amdgpu_connector) { 1561 DRM_ERROR("Couldn't find encoder's connector\n"); 1562 return; 1563 } 1564 1565 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1566 if (sad_count <= 0) { 1567 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1568 return; 1569 } 1570 BUG_ON(!sads); 1571 1572 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1573 u32 tmp = 0; 1574 u8 stereo_freqs = 0; 1575 int max_channels = -1; 1576 int j; 1577 1578 for (j = 0; j < sad_count; j++) { 1579 struct cea_sad *sad = &sads[j]; 1580 1581 if (sad->format == eld_reg_to_type[i][1]) { 1582 if (sad->channels > max_channels) { 1583 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1584 MAX_CHANNELS, sad->channels); 1585 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1586 DESCRIPTOR_BYTE_2, sad->byte2); 1587 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1588 SUPPORTED_FREQUENCIES, sad->freq); 1589 max_channels = sad->channels; 1590 } 1591 1592 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1593 stereo_freqs |= sad->freq; 1594 else 1595 break; 1596 } 1597 } 1598 1599 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1600 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1601 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1602 } 1603 1604 kfree(sads); 1605 } 1606 1607 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1608 struct amdgpu_audio_pin *pin, 1609 bool enable) 1610 { 1611 if (!pin) 1612 return; 1613 1614 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1615 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1616 } 1617 1618 static const u32 pin_offsets[] = 1619 { 1620 AUD0_REGISTER_OFFSET, 1621 AUD1_REGISTER_OFFSET, 1622 AUD2_REGISTER_OFFSET, 1623 AUD3_REGISTER_OFFSET, 1624 AUD4_REGISTER_OFFSET, 1625 AUD5_REGISTER_OFFSET, 1626 AUD6_REGISTER_OFFSET, 1627 }; 1628 1629 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1630 { 1631 int i; 1632 1633 if (!amdgpu_audio) 1634 return 0; 1635 1636 adev->mode_info.audio.enabled = true; 1637 1638 adev->mode_info.audio.num_pins = 7; 1639 1640 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1641 adev->mode_info.audio.pin[i].channels = -1; 1642 adev->mode_info.audio.pin[i].rate = -1; 1643 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1644 adev->mode_info.audio.pin[i].status_bits = 0; 1645 adev->mode_info.audio.pin[i].category_code = 0; 1646 adev->mode_info.audio.pin[i].connected = false; 1647 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1648 adev->mode_info.audio.pin[i].id = i; 1649 /* disable audio. it will be set up later */ 1650 /* XXX remove once we switch to ip funcs */ 1651 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1652 } 1653 1654 return 0; 1655 } 1656 1657 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1658 { 1659 int i; 1660 1661 if (!amdgpu_audio) 1662 return; 1663 1664 if (!adev->mode_info.audio.enabled) 1665 return; 1666 1667 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1668 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1669 1670 adev->mode_info.audio.enabled = false; 1671 } 1672 1673 /* 1674 * update the N and CTS parameters for a given pixel clock rate 1675 */ 1676 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1677 { 1678 struct drm_device *dev = encoder->dev; 1679 struct amdgpu_device *adev = dev->dev_private; 1680 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1681 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1682 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1683 u32 tmp; 1684 1685 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1686 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1687 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1688 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1689 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1690 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1691 1692 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1693 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1694 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1695 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1696 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1697 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1698 1699 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1700 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1701 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1702 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1703 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1704 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1705 1706 } 1707 1708 /* 1709 * build a HDMI Video Info Frame 1710 */ 1711 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1712 void *buffer, size_t size) 1713 { 1714 struct drm_device *dev = encoder->dev; 1715 struct amdgpu_device *adev = dev->dev_private; 1716 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1717 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1718 uint8_t *frame = buffer + 3; 1719 uint8_t *header = buffer; 1720 1721 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1722 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1723 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1724 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1725 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1726 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1727 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1728 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1729 } 1730 1731 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1732 { 1733 struct drm_device *dev = encoder->dev; 1734 struct amdgpu_device *adev = dev->dev_private; 1735 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1736 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1737 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1738 u32 dto_phase = 24 * 1000; 1739 u32 dto_modulo = clock; 1740 u32 tmp; 1741 1742 if (!dig || !dig->afmt) 1743 return; 1744 1745 /* XXX two dtos; generally use dto0 for hdmi */ 1746 /* Express [24MHz / target pixel clock] as an exact rational 1747 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1748 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1749 */ 1750 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1751 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1752 amdgpu_crtc->crtc_id); 1753 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1754 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1755 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1756 } 1757 1758 /* 1759 * update the info frames with the data from the current display mode 1760 */ 1761 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1762 struct drm_display_mode *mode) 1763 { 1764 struct drm_device *dev = encoder->dev; 1765 struct amdgpu_device *adev = dev->dev_private; 1766 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1767 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1768 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1769 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1770 struct hdmi_avi_infoframe frame; 1771 ssize_t err; 1772 u32 tmp; 1773 int bpc = 8; 1774 1775 if (!dig || !dig->afmt) 1776 return; 1777 1778 /* Silent, r600_hdmi_enable will raise WARN for us */ 1779 if (!dig->afmt->enabled) 1780 return; 1781 1782 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1783 if (encoder->crtc) { 1784 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1785 bpc = amdgpu_crtc->bpc; 1786 } 1787 1788 /* disable audio prior to setting up hw */ 1789 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1790 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1791 1792 dce_v11_0_audio_set_dto(encoder, mode->clock); 1793 1794 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1795 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1796 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1797 1798 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1799 1800 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1801 switch (bpc) { 1802 case 0: 1803 case 6: 1804 case 8: 1805 case 16: 1806 default: 1807 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1808 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1809 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1810 connector->name, bpc); 1811 break; 1812 case 10: 1813 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1814 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1815 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1816 connector->name); 1817 break; 1818 case 12: 1819 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1820 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1821 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1822 connector->name); 1823 break; 1824 } 1825 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1826 1827 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1828 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1829 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1830 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1831 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1832 1833 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1834 /* enable audio info frames (frames won't be set until audio is enabled) */ 1835 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1836 /* required for audio info values to be updated */ 1837 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1838 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1839 1840 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1841 /* required for audio info values to be updated */ 1842 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1843 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1844 1845 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1846 /* anything other than 0 */ 1847 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1848 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1849 1850 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1851 1852 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1853 /* set the default audio delay */ 1854 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1855 /* should be suffient for all audio modes and small enough for all hblanks */ 1856 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1857 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1858 1859 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1860 /* allow 60958 channel status fields to be updated */ 1861 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1862 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1863 1864 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1865 if (bpc > 8) 1866 /* clear SW CTS value */ 1867 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1868 else 1869 /* select SW CTS value */ 1870 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1871 /* allow hw to sent ACR packets when required */ 1872 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1873 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1874 1875 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1876 1877 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1878 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1879 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1880 1881 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1883 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1884 1885 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1886 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1887 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1888 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1889 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1890 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1891 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1892 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1893 1894 dce_v11_0_audio_write_speaker_allocation(encoder); 1895 1896 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1897 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1898 1899 dce_v11_0_afmt_audio_select_pin(encoder); 1900 dce_v11_0_audio_write_sad_regs(encoder); 1901 dce_v11_0_audio_write_latency_fields(encoder, mode); 1902 1903 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1904 if (err < 0) { 1905 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1906 return; 1907 } 1908 1909 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1910 if (err < 0) { 1911 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1912 return; 1913 } 1914 1915 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1916 1917 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1918 /* enable AVI info frames */ 1919 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1920 /* required for audio info values to be updated */ 1921 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1922 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1923 1924 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1925 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1926 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1927 1928 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1929 /* send audio packets */ 1930 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1931 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1932 1933 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1934 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1935 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1936 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1937 1938 /* enable audio after to setting up hw */ 1939 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1940 } 1941 1942 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1943 { 1944 struct drm_device *dev = encoder->dev; 1945 struct amdgpu_device *adev = dev->dev_private; 1946 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1947 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1948 1949 if (!dig || !dig->afmt) 1950 return; 1951 1952 /* Silent, r600_hdmi_enable will raise WARN for us */ 1953 if (enable && dig->afmt->enabled) 1954 return; 1955 if (!enable && !dig->afmt->enabled) 1956 return; 1957 1958 if (!enable && dig->afmt->pin) { 1959 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1960 dig->afmt->pin = NULL; 1961 } 1962 1963 dig->afmt->enabled = enable; 1964 1965 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1966 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1967 } 1968 1969 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1970 { 1971 int i; 1972 1973 for (i = 0; i < adev->mode_info.num_dig; i++) 1974 adev->mode_info.afmt[i] = NULL; 1975 1976 /* DCE11 has audio blocks tied to DIG encoders */ 1977 for (i = 0; i < adev->mode_info.num_dig; i++) { 1978 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1979 if (adev->mode_info.afmt[i]) { 1980 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1981 adev->mode_info.afmt[i]->id = i; 1982 } else { 1983 int j; 1984 for (j = 0; j < i; j++) { 1985 kfree(adev->mode_info.afmt[j]); 1986 adev->mode_info.afmt[j] = NULL; 1987 } 1988 return -ENOMEM; 1989 } 1990 } 1991 return 0; 1992 } 1993 1994 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1995 { 1996 int i; 1997 1998 for (i = 0; i < adev->mode_info.num_dig; i++) { 1999 kfree(adev->mode_info.afmt[i]); 2000 adev->mode_info.afmt[i] = NULL; 2001 } 2002 } 2003 2004 static const u32 vga_control_regs[6] = 2005 { 2006 mmD1VGA_CONTROL, 2007 mmD2VGA_CONTROL, 2008 mmD3VGA_CONTROL, 2009 mmD4VGA_CONTROL, 2010 mmD5VGA_CONTROL, 2011 mmD6VGA_CONTROL, 2012 }; 2013 2014 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 2015 { 2016 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2017 struct drm_device *dev = crtc->dev; 2018 struct amdgpu_device *adev = dev->dev_private; 2019 u32 vga_control; 2020 2021 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2022 if (enable) 2023 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2024 else 2025 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2026 } 2027 2028 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 2029 { 2030 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2031 struct drm_device *dev = crtc->dev; 2032 struct amdgpu_device *adev = dev->dev_private; 2033 2034 if (enable) 2035 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2036 else 2037 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2038 } 2039 2040 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 2041 struct drm_framebuffer *fb, 2042 int x, int y, int atomic) 2043 { 2044 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2045 struct drm_device *dev = crtc->dev; 2046 struct amdgpu_device *adev = dev->dev_private; 2047 struct amdgpu_framebuffer *amdgpu_fb; 2048 struct drm_framebuffer *target_fb; 2049 struct drm_gem_object *obj; 2050 struct amdgpu_bo *rbo; 2051 uint64_t fb_location, tiling_flags; 2052 uint32_t fb_format, fb_pitch_pixels; 2053 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2054 u32 pipe_config; 2055 u32 tmp, viewport_w, viewport_h; 2056 int r; 2057 bool bypass_lut = false; 2058 2059 /* no fb bound */ 2060 if (!atomic && !crtc->primary->fb) { 2061 DRM_DEBUG_KMS("No FB bound\n"); 2062 return 0; 2063 } 2064 2065 if (atomic) { 2066 amdgpu_fb = to_amdgpu_framebuffer(fb); 2067 target_fb = fb; 2068 } else { 2069 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2070 target_fb = crtc->primary->fb; 2071 } 2072 2073 /* If atomic, assume fb object is pinned & idle & fenced and 2074 * just update base pointers 2075 */ 2076 obj = amdgpu_fb->obj; 2077 rbo = gem_to_amdgpu_bo(obj); 2078 r = amdgpu_bo_reserve(rbo, false); 2079 if (unlikely(r != 0)) 2080 return r; 2081 2082 if (atomic) { 2083 fb_location = amdgpu_bo_gpu_offset(rbo); 2084 } else { 2085 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2086 if (unlikely(r != 0)) { 2087 amdgpu_bo_unreserve(rbo); 2088 return -EINVAL; 2089 } 2090 } 2091 2092 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2093 amdgpu_bo_unreserve(rbo); 2094 2095 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2096 2097 switch (target_fb->pixel_format) { 2098 case DRM_FORMAT_C8: 2099 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2100 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2101 break; 2102 case DRM_FORMAT_XRGB4444: 2103 case DRM_FORMAT_ARGB4444: 2104 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2105 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2106 #ifdef __BIG_ENDIAN 2107 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2108 ENDIAN_8IN16); 2109 #endif 2110 break; 2111 case DRM_FORMAT_XRGB1555: 2112 case DRM_FORMAT_ARGB1555: 2113 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2114 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2115 #ifdef __BIG_ENDIAN 2116 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2117 ENDIAN_8IN16); 2118 #endif 2119 break; 2120 case DRM_FORMAT_BGRX5551: 2121 case DRM_FORMAT_BGRA5551: 2122 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2123 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2124 #ifdef __BIG_ENDIAN 2125 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2126 ENDIAN_8IN16); 2127 #endif 2128 break; 2129 case DRM_FORMAT_RGB565: 2130 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2131 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2132 #ifdef __BIG_ENDIAN 2133 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2134 ENDIAN_8IN16); 2135 #endif 2136 break; 2137 case DRM_FORMAT_XRGB8888: 2138 case DRM_FORMAT_ARGB8888: 2139 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2140 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2141 #ifdef __BIG_ENDIAN 2142 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2143 ENDIAN_8IN32); 2144 #endif 2145 break; 2146 case DRM_FORMAT_XRGB2101010: 2147 case DRM_FORMAT_ARGB2101010: 2148 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2149 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2150 #ifdef __BIG_ENDIAN 2151 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2152 ENDIAN_8IN32); 2153 #endif 2154 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2155 bypass_lut = true; 2156 break; 2157 case DRM_FORMAT_BGRX1010102: 2158 case DRM_FORMAT_BGRA1010102: 2159 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2160 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2161 #ifdef __BIG_ENDIAN 2162 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2163 ENDIAN_8IN32); 2164 #endif 2165 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2166 bypass_lut = true; 2167 break; 2168 default: 2169 DRM_ERROR("Unsupported screen format %s\n", 2170 drm_get_format_name(target_fb->pixel_format)); 2171 return -EINVAL; 2172 } 2173 2174 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2175 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2176 2177 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2178 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2179 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2180 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2181 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2182 2183 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2184 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2185 ARRAY_2D_TILED_THIN1); 2186 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2187 tile_split); 2188 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2189 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2190 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2191 mtaspect); 2192 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2193 ADDR_SURF_MICRO_TILING_DISPLAY); 2194 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2195 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2196 ARRAY_1D_TILED_THIN1); 2197 } 2198 2199 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2200 pipe_config); 2201 2202 dce_v11_0_vga_enable(crtc, false); 2203 2204 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2205 upper_32_bits(fb_location)); 2206 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2207 upper_32_bits(fb_location)); 2208 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2209 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2210 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2211 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2212 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2213 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2214 2215 /* 2216 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2217 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2218 * retain the full precision throughout the pipeline. 2219 */ 2220 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2221 if (bypass_lut) 2222 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2223 else 2224 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2225 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2226 2227 if (bypass_lut) 2228 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2229 2230 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2231 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2232 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2233 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2234 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2235 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2236 2237 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2238 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2239 2240 dce_v11_0_grph_enable(crtc, true); 2241 2242 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2243 target_fb->height); 2244 2245 x &= ~3; 2246 y &= ~1; 2247 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2248 (x << 16) | y); 2249 viewport_w = crtc->mode.hdisplay; 2250 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2251 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2252 (viewport_w << 16) | viewport_h); 2253 2254 /* pageflip setup */ 2255 /* make sure flip is at vb rather than hb */ 2256 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2257 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2258 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2259 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2260 2261 /* set pageflip to happen only at start of vblank interval (front porch) */ 2262 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2263 2264 if (!atomic && fb && fb != crtc->primary->fb) { 2265 amdgpu_fb = to_amdgpu_framebuffer(fb); 2266 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2267 r = amdgpu_bo_reserve(rbo, false); 2268 if (unlikely(r != 0)) 2269 return r; 2270 amdgpu_bo_unpin(rbo); 2271 amdgpu_bo_unreserve(rbo); 2272 } 2273 2274 /* Bytes per pixel may have changed */ 2275 dce_v11_0_bandwidth_update(adev); 2276 2277 return 0; 2278 } 2279 2280 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2281 struct drm_display_mode *mode) 2282 { 2283 struct drm_device *dev = crtc->dev; 2284 struct amdgpu_device *adev = dev->dev_private; 2285 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2286 u32 tmp; 2287 2288 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2289 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2290 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2291 else 2292 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2293 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2294 } 2295 2296 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2297 { 2298 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2299 struct drm_device *dev = crtc->dev; 2300 struct amdgpu_device *adev = dev->dev_private; 2301 int i; 2302 u32 tmp; 2303 2304 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2305 2306 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2307 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2308 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2309 2310 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2311 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2312 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2313 2314 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2315 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2316 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2317 2318 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2319 2320 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2321 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2322 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2323 2324 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2325 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2326 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2327 2328 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2329 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2330 2331 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2332 for (i = 0; i < 256; i++) { 2333 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2334 (amdgpu_crtc->lut_r[i] << 20) | 2335 (amdgpu_crtc->lut_g[i] << 10) | 2336 (amdgpu_crtc->lut_b[i] << 0)); 2337 } 2338 2339 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2340 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2341 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2342 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2343 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2344 2345 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2346 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2347 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2348 2349 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2350 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2351 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2352 2353 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2354 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2355 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2356 2357 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2358 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2359 /* XXX this only needs to be programmed once per crtc at startup, 2360 * not sure where the best place for it is 2361 */ 2362 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2363 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2364 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2365 } 2366 2367 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2368 { 2369 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2370 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2371 2372 switch (amdgpu_encoder->encoder_id) { 2373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2374 if (dig->linkb) 2375 return 1; 2376 else 2377 return 0; 2378 break; 2379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2380 if (dig->linkb) 2381 return 3; 2382 else 2383 return 2; 2384 break; 2385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2386 if (dig->linkb) 2387 return 5; 2388 else 2389 return 4; 2390 break; 2391 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2392 return 6; 2393 break; 2394 default: 2395 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2396 return 0; 2397 } 2398 } 2399 2400 /** 2401 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2402 * 2403 * @crtc: drm crtc 2404 * 2405 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2406 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2407 * monitors a dedicated PPLL must be used. If a particular board has 2408 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2409 * as there is no need to program the PLL itself. If we are not able to 2410 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2411 * avoid messing up an existing monitor. 2412 * 2413 * Asic specific PLL information 2414 * 2415 * DCE 10.x 2416 * Tonga 2417 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2418 * CI 2419 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2420 * 2421 */ 2422 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2423 { 2424 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2425 struct drm_device *dev = crtc->dev; 2426 struct amdgpu_device *adev = dev->dev_private; 2427 u32 pll_in_use; 2428 int pll; 2429 2430 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2431 if (adev->clock.dp_extclk) 2432 /* skip PPLL programming if using ext clock */ 2433 return ATOM_PPLL_INVALID; 2434 else { 2435 /* use the same PPLL for all DP monitors */ 2436 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2437 if (pll != ATOM_PPLL_INVALID) 2438 return pll; 2439 } 2440 } else { 2441 /* use the same PPLL for all monitors with the same clock */ 2442 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2443 if (pll != ATOM_PPLL_INVALID) 2444 return pll; 2445 } 2446 2447 /* XXX need to determine what plls are available on each DCE11 part */ 2448 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2449 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2450 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2451 return ATOM_PPLL1; 2452 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2453 return ATOM_PPLL0; 2454 DRM_ERROR("unable to allocate a PPLL\n"); 2455 return ATOM_PPLL_INVALID; 2456 } else { 2457 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2458 return ATOM_PPLL2; 2459 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2460 return ATOM_PPLL1; 2461 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2462 return ATOM_PPLL0; 2463 DRM_ERROR("unable to allocate a PPLL\n"); 2464 return ATOM_PPLL_INVALID; 2465 } 2466 return ATOM_PPLL_INVALID; 2467 } 2468 2469 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2470 { 2471 struct amdgpu_device *adev = crtc->dev->dev_private; 2472 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2473 uint32_t cur_lock; 2474 2475 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2476 if (lock) 2477 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2478 else 2479 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2480 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2481 } 2482 2483 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2484 { 2485 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2486 struct amdgpu_device *adev = crtc->dev->dev_private; 2487 u32 tmp; 2488 2489 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2490 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2491 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2492 } 2493 2494 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2495 { 2496 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2497 struct amdgpu_device *adev = crtc->dev->dev_private; 2498 u32 tmp; 2499 2500 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2501 upper_32_bits(amdgpu_crtc->cursor_addr)); 2502 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2503 lower_32_bits(amdgpu_crtc->cursor_addr)); 2504 2505 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2506 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2507 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2508 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2509 } 2510 2511 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2512 int x, int y) 2513 { 2514 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2515 struct amdgpu_device *adev = crtc->dev->dev_private; 2516 int xorigin = 0, yorigin = 0; 2517 2518 /* avivo cursor are offset into the total surface */ 2519 x += crtc->x; 2520 y += crtc->y; 2521 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2522 2523 if (x < 0) { 2524 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2525 x = 0; 2526 } 2527 if (y < 0) { 2528 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2529 y = 0; 2530 } 2531 2532 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2533 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2534 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2535 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2536 2537 amdgpu_crtc->cursor_x = x; 2538 amdgpu_crtc->cursor_y = y; 2539 2540 return 0; 2541 } 2542 2543 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2544 int x, int y) 2545 { 2546 int ret; 2547 2548 dce_v11_0_lock_cursor(crtc, true); 2549 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2550 dce_v11_0_lock_cursor(crtc, false); 2551 2552 return ret; 2553 } 2554 2555 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2556 struct drm_file *file_priv, 2557 uint32_t handle, 2558 uint32_t width, 2559 uint32_t height, 2560 int32_t hot_x, 2561 int32_t hot_y) 2562 { 2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2564 struct drm_gem_object *obj; 2565 struct amdgpu_bo *aobj; 2566 int ret; 2567 2568 if (!handle) { 2569 /* turn off cursor */ 2570 dce_v11_0_hide_cursor(crtc); 2571 obj = NULL; 2572 goto unpin; 2573 } 2574 2575 if ((width > amdgpu_crtc->max_cursor_width) || 2576 (height > amdgpu_crtc->max_cursor_height)) { 2577 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2578 return -EINVAL; 2579 } 2580 2581 obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); 2582 if (!obj) { 2583 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2584 return -ENOENT; 2585 } 2586 2587 aobj = gem_to_amdgpu_bo(obj); 2588 ret = amdgpu_bo_reserve(aobj, false); 2589 if (ret != 0) { 2590 drm_gem_object_unreference_unlocked(obj); 2591 return ret; 2592 } 2593 2594 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2595 amdgpu_bo_unreserve(aobj); 2596 if (ret) { 2597 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2598 drm_gem_object_unreference_unlocked(obj); 2599 return ret; 2600 } 2601 2602 amdgpu_crtc->cursor_width = width; 2603 amdgpu_crtc->cursor_height = height; 2604 2605 dce_v11_0_lock_cursor(crtc, true); 2606 2607 if (hot_x != amdgpu_crtc->cursor_hot_x || 2608 hot_y != amdgpu_crtc->cursor_hot_y) { 2609 int x, y; 2610 2611 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2612 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2613 2614 dce_v11_0_cursor_move_locked(crtc, x, y); 2615 2616 amdgpu_crtc->cursor_hot_x = hot_x; 2617 amdgpu_crtc->cursor_hot_y = hot_y; 2618 } 2619 2620 dce_v11_0_show_cursor(crtc); 2621 dce_v11_0_lock_cursor(crtc, false); 2622 2623 unpin: 2624 if (amdgpu_crtc->cursor_bo) { 2625 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2626 ret = amdgpu_bo_reserve(aobj, false); 2627 if (likely(ret == 0)) { 2628 amdgpu_bo_unpin(aobj); 2629 amdgpu_bo_unreserve(aobj); 2630 } 2631 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2632 } 2633 2634 amdgpu_crtc->cursor_bo = obj; 2635 return 0; 2636 } 2637 2638 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2639 { 2640 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2641 2642 if (amdgpu_crtc->cursor_bo) { 2643 dce_v11_0_lock_cursor(crtc, true); 2644 2645 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2646 amdgpu_crtc->cursor_y); 2647 2648 dce_v11_0_show_cursor(crtc); 2649 2650 dce_v11_0_lock_cursor(crtc, false); 2651 } 2652 } 2653 2654 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2655 u16 *blue, uint32_t start, uint32_t size) 2656 { 2657 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2658 int end = (start + size > 256) ? 256 : start + size, i; 2659 2660 /* userspace palettes are always correct as is */ 2661 for (i = start; i < end; i++) { 2662 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2663 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2664 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2665 } 2666 dce_v11_0_crtc_load_lut(crtc); 2667 } 2668 2669 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2670 { 2671 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2672 2673 drm_crtc_cleanup(crtc); 2674 kfree(amdgpu_crtc); 2675 } 2676 2677 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2678 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2679 .cursor_move = dce_v11_0_crtc_cursor_move, 2680 .gamma_set = dce_v11_0_crtc_gamma_set, 2681 .set_config = amdgpu_crtc_set_config, 2682 .destroy = dce_v11_0_crtc_destroy, 2683 .page_flip = amdgpu_crtc_page_flip, 2684 }; 2685 2686 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2687 { 2688 struct drm_device *dev = crtc->dev; 2689 struct amdgpu_device *adev = dev->dev_private; 2690 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2691 unsigned type; 2692 2693 switch (mode) { 2694 case DRM_MODE_DPMS_ON: 2695 amdgpu_crtc->enabled = true; 2696 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2697 dce_v11_0_vga_enable(crtc, true); 2698 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2699 dce_v11_0_vga_enable(crtc, false); 2700 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2701 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2702 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2703 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2704 drm_vblank_on(dev, amdgpu_crtc->crtc_id); 2705 dce_v11_0_crtc_load_lut(crtc); 2706 break; 2707 case DRM_MODE_DPMS_STANDBY: 2708 case DRM_MODE_DPMS_SUSPEND: 2709 case DRM_MODE_DPMS_OFF: 2710 drm_vblank_off(dev, amdgpu_crtc->crtc_id); 2711 if (amdgpu_crtc->enabled) { 2712 dce_v11_0_vga_enable(crtc, true); 2713 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2714 dce_v11_0_vga_enable(crtc, false); 2715 } 2716 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2717 amdgpu_crtc->enabled = false; 2718 break; 2719 } 2720 /* adjust pm to dpms */ 2721 amdgpu_pm_compute_clocks(adev); 2722 } 2723 2724 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2725 { 2726 /* disable crtc pair power gating before programming */ 2727 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2728 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2729 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2730 } 2731 2732 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2733 { 2734 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2735 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2736 } 2737 2738 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2739 { 2740 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2741 struct drm_device *dev = crtc->dev; 2742 struct amdgpu_device *adev = dev->dev_private; 2743 struct amdgpu_atom_ss ss; 2744 int i; 2745 2746 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2747 if (crtc->primary->fb) { 2748 int r; 2749 struct amdgpu_framebuffer *amdgpu_fb; 2750 struct amdgpu_bo *rbo; 2751 2752 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2753 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2754 r = amdgpu_bo_reserve(rbo, false); 2755 if (unlikely(r)) 2756 DRM_ERROR("failed to reserve rbo before unpin\n"); 2757 else { 2758 amdgpu_bo_unpin(rbo); 2759 amdgpu_bo_unreserve(rbo); 2760 } 2761 } 2762 /* disable the GRPH */ 2763 dce_v11_0_grph_enable(crtc, false); 2764 2765 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2766 2767 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2768 if (adev->mode_info.crtcs[i] && 2769 adev->mode_info.crtcs[i]->enabled && 2770 i != amdgpu_crtc->crtc_id && 2771 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2772 /* one other crtc is using this pll don't turn 2773 * off the pll 2774 */ 2775 goto done; 2776 } 2777 } 2778 2779 switch (amdgpu_crtc->pll_id) { 2780 case ATOM_PPLL0: 2781 case ATOM_PPLL1: 2782 case ATOM_PPLL2: 2783 /* disable the ppll */ 2784 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2785 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2786 break; 2787 default: 2788 break; 2789 } 2790 done: 2791 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2792 amdgpu_crtc->adjusted_clock = 0; 2793 amdgpu_crtc->encoder = NULL; 2794 amdgpu_crtc->connector = NULL; 2795 } 2796 2797 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2798 struct drm_display_mode *mode, 2799 struct drm_display_mode *adjusted_mode, 2800 int x, int y, struct drm_framebuffer *old_fb) 2801 { 2802 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2803 2804 if (!amdgpu_crtc->adjusted_clock) 2805 return -EINVAL; 2806 2807 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2808 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2809 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2810 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2811 amdgpu_atombios_crtc_scaler_setup(crtc); 2812 dce_v11_0_cursor_reset(crtc); 2813 /* update the hw version fpr dpm */ 2814 amdgpu_crtc->hw_mode = *adjusted_mode; 2815 2816 return 0; 2817 } 2818 2819 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2820 const struct drm_display_mode *mode, 2821 struct drm_display_mode *adjusted_mode) 2822 { 2823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2824 struct drm_device *dev = crtc->dev; 2825 struct drm_encoder *encoder; 2826 2827 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2828 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2829 if (encoder->crtc == crtc) { 2830 amdgpu_crtc->encoder = encoder; 2831 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2832 break; 2833 } 2834 } 2835 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2836 amdgpu_crtc->encoder = NULL; 2837 amdgpu_crtc->connector = NULL; 2838 return false; 2839 } 2840 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2841 return false; 2842 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2843 return false; 2844 /* pick pll */ 2845 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2846 /* if we can't get a PPLL for a non-DP encoder, fail */ 2847 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2848 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2849 return false; 2850 2851 return true; 2852 } 2853 2854 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2855 struct drm_framebuffer *old_fb) 2856 { 2857 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2858 } 2859 2860 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2861 struct drm_framebuffer *fb, 2862 int x, int y, enum mode_set_atomic state) 2863 { 2864 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2865 } 2866 2867 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2868 .dpms = dce_v11_0_crtc_dpms, 2869 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2870 .mode_set = dce_v11_0_crtc_mode_set, 2871 .mode_set_base = dce_v11_0_crtc_set_base, 2872 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2873 .prepare = dce_v11_0_crtc_prepare, 2874 .commit = dce_v11_0_crtc_commit, 2875 .load_lut = dce_v11_0_crtc_load_lut, 2876 .disable = dce_v11_0_crtc_disable, 2877 }; 2878 2879 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2880 { 2881 struct amdgpu_crtc *amdgpu_crtc; 2882 int i; 2883 2884 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2885 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2886 if (amdgpu_crtc == NULL) 2887 return -ENOMEM; 2888 2889 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2890 2891 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2892 amdgpu_crtc->crtc_id = index; 2893 adev->mode_info.crtcs[index] = amdgpu_crtc; 2894 2895 amdgpu_crtc->max_cursor_width = 128; 2896 amdgpu_crtc->max_cursor_height = 128; 2897 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2898 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2899 2900 for (i = 0; i < 256; i++) { 2901 amdgpu_crtc->lut_r[i] = i << 2; 2902 amdgpu_crtc->lut_g[i] = i << 2; 2903 amdgpu_crtc->lut_b[i] = i << 2; 2904 } 2905 2906 switch (amdgpu_crtc->crtc_id) { 2907 case 0: 2908 default: 2909 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2910 break; 2911 case 1: 2912 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2913 break; 2914 case 2: 2915 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2916 break; 2917 case 3: 2918 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2919 break; 2920 case 4: 2921 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2922 break; 2923 case 5: 2924 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2925 break; 2926 } 2927 2928 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2929 amdgpu_crtc->adjusted_clock = 0; 2930 amdgpu_crtc->encoder = NULL; 2931 amdgpu_crtc->connector = NULL; 2932 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2933 2934 return 0; 2935 } 2936 2937 static int dce_v11_0_early_init(void *handle) 2938 { 2939 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2940 2941 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2942 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2943 2944 dce_v11_0_set_display_funcs(adev); 2945 dce_v11_0_set_irq_funcs(adev); 2946 2947 switch (adev->asic_type) { 2948 case CHIP_CARRIZO: 2949 adev->mode_info.num_crtc = 3; 2950 adev->mode_info.num_hpd = 6; 2951 adev->mode_info.num_dig = 9; 2952 break; 2953 case CHIP_STONEY: 2954 adev->mode_info.num_crtc = 2; 2955 adev->mode_info.num_hpd = 6; 2956 adev->mode_info.num_dig = 9; 2957 break; 2958 default: 2959 /* FIXME: not supported yet */ 2960 return -EINVAL; 2961 } 2962 2963 return 0; 2964 } 2965 2966 static int dce_v11_0_sw_init(void *handle) 2967 { 2968 int r, i; 2969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2970 2971 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2972 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 2973 if (r) 2974 return r; 2975 } 2976 2977 for (i = 8; i < 20; i += 2) { 2978 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 2979 if (r) 2980 return r; 2981 } 2982 2983 /* HPD hotplug */ 2984 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 2985 if (r) 2986 return r; 2987 2988 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2989 2990 adev->ddev->mode_config.max_width = 16384; 2991 adev->ddev->mode_config.max_height = 16384; 2992 2993 adev->ddev->mode_config.preferred_depth = 24; 2994 adev->ddev->mode_config.prefer_shadow = 1; 2995 2996 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 2997 2998 r = amdgpu_modeset_create_props(adev); 2999 if (r) 3000 return r; 3001 3002 adev->ddev->mode_config.max_width = 16384; 3003 adev->ddev->mode_config.max_height = 16384; 3004 3005 3006 /* allocate crtcs */ 3007 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3008 r = dce_v11_0_crtc_init(adev, i); 3009 if (r) 3010 return r; 3011 } 3012 3013 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3014 amdgpu_print_display_setup(adev->ddev); 3015 else 3016 return -EINVAL; 3017 3018 /* setup afmt */ 3019 r = dce_v11_0_afmt_init(adev); 3020 if (r) 3021 return r; 3022 3023 r = dce_v11_0_audio_init(adev); 3024 if (r) 3025 return r; 3026 3027 drm_kms_helper_poll_init(adev->ddev); 3028 3029 adev->mode_info.mode_config_initialized = true; 3030 return 0; 3031 } 3032 3033 static int dce_v11_0_sw_fini(void *handle) 3034 { 3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3036 3037 kfree(adev->mode_info.bios_hardcoded_edid); 3038 3039 drm_kms_helper_poll_fini(adev->ddev); 3040 3041 dce_v11_0_audio_fini(adev); 3042 3043 dce_v11_0_afmt_fini(adev); 3044 3045 adev->mode_info.mode_config_initialized = false; 3046 3047 return 0; 3048 } 3049 3050 static int dce_v11_0_hw_init(void *handle) 3051 { 3052 int i; 3053 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3054 3055 dce_v11_0_init_golden_registers(adev); 3056 3057 /* init dig PHYs, disp eng pll */ 3058 amdgpu_atombios_crtc_powergate_init(adev); 3059 amdgpu_atombios_encoder_init_dig(adev); 3060 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3061 3062 /* initialize hpd */ 3063 dce_v11_0_hpd_init(adev); 3064 3065 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3066 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3067 } 3068 3069 dce_v11_0_pageflip_interrupt_init(adev); 3070 3071 return 0; 3072 } 3073 3074 static int dce_v11_0_hw_fini(void *handle) 3075 { 3076 int i; 3077 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3078 3079 dce_v11_0_hpd_fini(adev); 3080 3081 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3082 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3083 } 3084 3085 dce_v11_0_pageflip_interrupt_fini(adev); 3086 3087 return 0; 3088 } 3089 3090 static int dce_v11_0_suspend(void *handle) 3091 { 3092 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3093 3094 amdgpu_atombios_scratch_regs_save(adev); 3095 3096 return dce_v11_0_hw_fini(handle); 3097 } 3098 3099 static int dce_v11_0_resume(void *handle) 3100 { 3101 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3102 int ret; 3103 3104 ret = dce_v11_0_hw_init(handle); 3105 3106 amdgpu_atombios_scratch_regs_restore(adev); 3107 3108 /* turn on the BL */ 3109 if (adev->mode_info.bl_encoder) { 3110 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3111 adev->mode_info.bl_encoder); 3112 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3113 bl_level); 3114 } 3115 3116 return ret; 3117 } 3118 3119 static bool dce_v11_0_is_idle(void *handle) 3120 { 3121 return true; 3122 } 3123 3124 static int dce_v11_0_wait_for_idle(void *handle) 3125 { 3126 return 0; 3127 } 3128 3129 static void dce_v11_0_print_status(void *handle) 3130 { 3131 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3132 3133 dev_info(adev->dev, "DCE 10.x registers\n"); 3134 /* XXX todo */ 3135 } 3136 3137 static int dce_v11_0_soft_reset(void *handle) 3138 { 3139 u32 srbm_soft_reset = 0, tmp; 3140 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3141 3142 if (dce_v11_0_is_display_hung(adev)) 3143 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3144 3145 if (srbm_soft_reset) { 3146 dce_v11_0_print_status((void *)adev); 3147 3148 tmp = RREG32(mmSRBM_SOFT_RESET); 3149 tmp |= srbm_soft_reset; 3150 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3151 WREG32(mmSRBM_SOFT_RESET, tmp); 3152 tmp = RREG32(mmSRBM_SOFT_RESET); 3153 3154 udelay(50); 3155 3156 tmp &= ~srbm_soft_reset; 3157 WREG32(mmSRBM_SOFT_RESET, tmp); 3158 tmp = RREG32(mmSRBM_SOFT_RESET); 3159 3160 /* Wait a little for things to settle down */ 3161 udelay(50); 3162 dce_v11_0_print_status((void *)adev); 3163 } 3164 return 0; 3165 } 3166 3167 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3168 int crtc, 3169 enum amdgpu_interrupt_state state) 3170 { 3171 u32 lb_interrupt_mask; 3172 3173 if (crtc >= adev->mode_info.num_crtc) { 3174 DRM_DEBUG("invalid crtc %d\n", crtc); 3175 return; 3176 } 3177 3178 switch (state) { 3179 case AMDGPU_IRQ_STATE_DISABLE: 3180 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3181 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3182 VBLANK_INTERRUPT_MASK, 0); 3183 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3184 break; 3185 case AMDGPU_IRQ_STATE_ENABLE: 3186 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3187 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3188 VBLANK_INTERRUPT_MASK, 1); 3189 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3190 break; 3191 default: 3192 break; 3193 } 3194 } 3195 3196 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3197 int crtc, 3198 enum amdgpu_interrupt_state state) 3199 { 3200 u32 lb_interrupt_mask; 3201 3202 if (crtc >= adev->mode_info.num_crtc) { 3203 DRM_DEBUG("invalid crtc %d\n", crtc); 3204 return; 3205 } 3206 3207 switch (state) { 3208 case AMDGPU_IRQ_STATE_DISABLE: 3209 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3210 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3211 VLINE_INTERRUPT_MASK, 0); 3212 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3213 break; 3214 case AMDGPU_IRQ_STATE_ENABLE: 3215 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3216 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3217 VLINE_INTERRUPT_MASK, 1); 3218 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3219 break; 3220 default: 3221 break; 3222 } 3223 } 3224 3225 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3226 struct amdgpu_irq_src *source, 3227 unsigned hpd, 3228 enum amdgpu_interrupt_state state) 3229 { 3230 u32 tmp; 3231 3232 if (hpd >= adev->mode_info.num_hpd) { 3233 DRM_DEBUG("invalid hdp %d\n", hpd); 3234 return 0; 3235 } 3236 3237 switch (state) { 3238 case AMDGPU_IRQ_STATE_DISABLE: 3239 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3240 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3241 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3242 break; 3243 case AMDGPU_IRQ_STATE_ENABLE: 3244 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3245 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3246 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3247 break; 3248 default: 3249 break; 3250 } 3251 3252 return 0; 3253 } 3254 3255 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3256 struct amdgpu_irq_src *source, 3257 unsigned type, 3258 enum amdgpu_interrupt_state state) 3259 { 3260 switch (type) { 3261 case AMDGPU_CRTC_IRQ_VBLANK1: 3262 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3263 break; 3264 case AMDGPU_CRTC_IRQ_VBLANK2: 3265 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3266 break; 3267 case AMDGPU_CRTC_IRQ_VBLANK3: 3268 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3269 break; 3270 case AMDGPU_CRTC_IRQ_VBLANK4: 3271 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3272 break; 3273 case AMDGPU_CRTC_IRQ_VBLANK5: 3274 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3275 break; 3276 case AMDGPU_CRTC_IRQ_VBLANK6: 3277 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3278 break; 3279 case AMDGPU_CRTC_IRQ_VLINE1: 3280 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3281 break; 3282 case AMDGPU_CRTC_IRQ_VLINE2: 3283 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3284 break; 3285 case AMDGPU_CRTC_IRQ_VLINE3: 3286 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3287 break; 3288 case AMDGPU_CRTC_IRQ_VLINE4: 3289 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3290 break; 3291 case AMDGPU_CRTC_IRQ_VLINE5: 3292 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3293 break; 3294 case AMDGPU_CRTC_IRQ_VLINE6: 3295 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3296 break; 3297 default: 3298 break; 3299 } 3300 return 0; 3301 } 3302 3303 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3304 struct amdgpu_irq_src *src, 3305 unsigned type, 3306 enum amdgpu_interrupt_state state) 3307 { 3308 u32 reg; 3309 3310 if (type >= adev->mode_info.num_crtc) { 3311 DRM_ERROR("invalid pageflip crtc %d\n", type); 3312 return -EINVAL; 3313 } 3314 3315 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3316 if (state == AMDGPU_IRQ_STATE_DISABLE) 3317 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3318 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3319 else 3320 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3321 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3322 3323 return 0; 3324 } 3325 3326 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3327 struct amdgpu_irq_src *source, 3328 struct amdgpu_iv_entry *entry) 3329 { 3330 unsigned long flags; 3331 unsigned crtc_id; 3332 struct amdgpu_crtc *amdgpu_crtc; 3333 struct amdgpu_flip_work *works; 3334 3335 crtc_id = (entry->src_id - 8) >> 1; 3336 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3337 3338 if (crtc_id >= adev->mode_info.num_crtc) { 3339 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3340 return -EINVAL; 3341 } 3342 3343 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3344 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3345 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3346 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3347 3348 /* IRQ could occur when in initial stage */ 3349 if(amdgpu_crtc == NULL) 3350 return 0; 3351 3352 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3353 works = amdgpu_crtc->pflip_works; 3354 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3355 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3356 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3357 amdgpu_crtc->pflip_status, 3358 AMDGPU_FLIP_SUBMITTED); 3359 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3360 return 0; 3361 } 3362 3363 /* page flip completed. clean up */ 3364 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3365 amdgpu_crtc->pflip_works = NULL; 3366 3367 /* wakeup usersapce */ 3368 if(works->event) 3369 drm_send_vblank_event(adev->ddev, crtc_id, works->event); 3370 3371 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3372 3373 drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); 3374 schedule_work(&works->unpin_work); 3375 3376 return 0; 3377 } 3378 3379 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3380 int hpd) 3381 { 3382 u32 tmp; 3383 3384 if (hpd >= adev->mode_info.num_hpd) { 3385 DRM_DEBUG("invalid hdp %d\n", hpd); 3386 return; 3387 } 3388 3389 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3390 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3391 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3392 } 3393 3394 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3395 int crtc) 3396 { 3397 u32 tmp; 3398 3399 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3400 DRM_DEBUG("invalid crtc %d\n", crtc); 3401 return; 3402 } 3403 3404 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3405 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3406 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3407 } 3408 3409 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3410 int crtc) 3411 { 3412 u32 tmp; 3413 3414 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3415 DRM_DEBUG("invalid crtc %d\n", crtc); 3416 return; 3417 } 3418 3419 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3420 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3421 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3422 } 3423 3424 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3425 struct amdgpu_irq_src *source, 3426 struct amdgpu_iv_entry *entry) 3427 { 3428 unsigned crtc = entry->src_id - 1; 3429 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3430 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3431 3432 switch (entry->src_data) { 3433 case 0: /* vblank */ 3434 if (disp_int & interrupt_status_offsets[crtc].vblank) 3435 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3436 else 3437 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3438 3439 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3440 drm_handle_vblank(adev->ddev, crtc); 3441 } 3442 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3443 3444 break; 3445 case 1: /* vline */ 3446 if (disp_int & interrupt_status_offsets[crtc].vline) 3447 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3448 else 3449 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3450 3451 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3452 3453 break; 3454 default: 3455 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3456 break; 3457 } 3458 3459 return 0; 3460 } 3461 3462 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3463 struct amdgpu_irq_src *source, 3464 struct amdgpu_iv_entry *entry) 3465 { 3466 uint32_t disp_int, mask; 3467 unsigned hpd; 3468 3469 if (entry->src_data >= adev->mode_info.num_hpd) { 3470 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3471 return 0; 3472 } 3473 3474 hpd = entry->src_data; 3475 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3476 mask = interrupt_status_offsets[hpd].hpd; 3477 3478 if (disp_int & mask) { 3479 dce_v11_0_hpd_int_ack(adev, hpd); 3480 schedule_work(&adev->hotplug_work); 3481 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3482 } 3483 3484 return 0; 3485 } 3486 3487 static int dce_v11_0_set_clockgating_state(void *handle, 3488 enum amd_clockgating_state state) 3489 { 3490 return 0; 3491 } 3492 3493 static int dce_v11_0_set_powergating_state(void *handle, 3494 enum amd_powergating_state state) 3495 { 3496 return 0; 3497 } 3498 3499 const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3500 .early_init = dce_v11_0_early_init, 3501 .late_init = NULL, 3502 .sw_init = dce_v11_0_sw_init, 3503 .sw_fini = dce_v11_0_sw_fini, 3504 .hw_init = dce_v11_0_hw_init, 3505 .hw_fini = dce_v11_0_hw_fini, 3506 .suspend = dce_v11_0_suspend, 3507 .resume = dce_v11_0_resume, 3508 .is_idle = dce_v11_0_is_idle, 3509 .wait_for_idle = dce_v11_0_wait_for_idle, 3510 .soft_reset = dce_v11_0_soft_reset, 3511 .print_status = dce_v11_0_print_status, 3512 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3513 .set_powergating_state = dce_v11_0_set_powergating_state, 3514 }; 3515 3516 static void 3517 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3518 struct drm_display_mode *mode, 3519 struct drm_display_mode *adjusted_mode) 3520 { 3521 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3522 3523 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3524 3525 /* need to call this here rather than in prepare() since we need some crtc info */ 3526 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3527 3528 /* set scaler clears this on some chips */ 3529 dce_v11_0_set_interleave(encoder->crtc, mode); 3530 3531 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3532 dce_v11_0_afmt_enable(encoder, true); 3533 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3534 } 3535 } 3536 3537 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3538 { 3539 struct amdgpu_device *adev = encoder->dev->dev_private; 3540 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3541 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3542 3543 if ((amdgpu_encoder->active_device & 3544 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3545 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3546 ENCODER_OBJECT_ID_NONE)) { 3547 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3548 if (dig) { 3549 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3550 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3551 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3552 } 3553 } 3554 3555 amdgpu_atombios_scratch_regs_lock(adev, true); 3556 3557 if (connector) { 3558 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3559 3560 /* select the clock/data port if it uses a router */ 3561 if (amdgpu_connector->router.cd_valid) 3562 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3563 3564 /* turn eDP panel on for mode set */ 3565 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3566 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3567 ATOM_TRANSMITTER_ACTION_POWER_ON); 3568 } 3569 3570 /* this is needed for the pll/ss setup to work correctly in some cases */ 3571 amdgpu_atombios_encoder_set_crtc_source(encoder); 3572 /* set up the FMT blocks */ 3573 dce_v11_0_program_fmt(encoder); 3574 } 3575 3576 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3577 { 3578 struct drm_device *dev = encoder->dev; 3579 struct amdgpu_device *adev = dev->dev_private; 3580 3581 /* need to call this here as we need the crtc set up */ 3582 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3583 amdgpu_atombios_scratch_regs_lock(adev, false); 3584 } 3585 3586 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3587 { 3588 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3589 struct amdgpu_encoder_atom_dig *dig; 3590 3591 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3592 3593 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3594 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3595 dce_v11_0_afmt_enable(encoder, false); 3596 dig = amdgpu_encoder->enc_priv; 3597 dig->dig_encoder = -1; 3598 } 3599 amdgpu_encoder->active_device = 0; 3600 } 3601 3602 /* these are handled by the primary encoders */ 3603 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3604 { 3605 3606 } 3607 3608 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3609 { 3610 3611 } 3612 3613 static void 3614 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3615 struct drm_display_mode *mode, 3616 struct drm_display_mode *adjusted_mode) 3617 { 3618 3619 } 3620 3621 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3622 { 3623 3624 } 3625 3626 static void 3627 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3628 { 3629 3630 } 3631 3632 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3633 .dpms = dce_v11_0_ext_dpms, 3634 .prepare = dce_v11_0_ext_prepare, 3635 .mode_set = dce_v11_0_ext_mode_set, 3636 .commit = dce_v11_0_ext_commit, 3637 .disable = dce_v11_0_ext_disable, 3638 /* no detect for TMDS/LVDS yet */ 3639 }; 3640 3641 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3642 .dpms = amdgpu_atombios_encoder_dpms, 3643 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3644 .prepare = dce_v11_0_encoder_prepare, 3645 .mode_set = dce_v11_0_encoder_mode_set, 3646 .commit = dce_v11_0_encoder_commit, 3647 .disable = dce_v11_0_encoder_disable, 3648 .detect = amdgpu_atombios_encoder_dig_detect, 3649 }; 3650 3651 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3652 .dpms = amdgpu_atombios_encoder_dpms, 3653 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3654 .prepare = dce_v11_0_encoder_prepare, 3655 .mode_set = dce_v11_0_encoder_mode_set, 3656 .commit = dce_v11_0_encoder_commit, 3657 .detect = amdgpu_atombios_encoder_dac_detect, 3658 }; 3659 3660 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3661 { 3662 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3663 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3664 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3665 kfree(amdgpu_encoder->enc_priv); 3666 drm_encoder_cleanup(encoder); 3667 kfree(amdgpu_encoder); 3668 } 3669 3670 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3671 .destroy = dce_v11_0_encoder_destroy, 3672 }; 3673 3674 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3675 uint32_t encoder_enum, 3676 uint32_t supported_device, 3677 u16 caps) 3678 { 3679 struct drm_device *dev = adev->ddev; 3680 struct drm_encoder *encoder; 3681 struct amdgpu_encoder *amdgpu_encoder; 3682 3683 /* see if we already added it */ 3684 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3685 amdgpu_encoder = to_amdgpu_encoder(encoder); 3686 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3687 amdgpu_encoder->devices |= supported_device; 3688 return; 3689 } 3690 3691 } 3692 3693 /* add a new one */ 3694 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3695 if (!amdgpu_encoder) 3696 return; 3697 3698 encoder = &amdgpu_encoder->base; 3699 switch (adev->mode_info.num_crtc) { 3700 case 1: 3701 encoder->possible_crtcs = 0x1; 3702 break; 3703 case 2: 3704 default: 3705 encoder->possible_crtcs = 0x3; 3706 break; 3707 case 4: 3708 encoder->possible_crtcs = 0xf; 3709 break; 3710 case 6: 3711 encoder->possible_crtcs = 0x3f; 3712 break; 3713 } 3714 3715 amdgpu_encoder->enc_priv = NULL; 3716 3717 amdgpu_encoder->encoder_enum = encoder_enum; 3718 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3719 amdgpu_encoder->devices = supported_device; 3720 amdgpu_encoder->rmx_type = RMX_OFF; 3721 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3722 amdgpu_encoder->is_ext_encoder = false; 3723 amdgpu_encoder->caps = caps; 3724 3725 switch (amdgpu_encoder->encoder_id) { 3726 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3727 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3728 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3729 DRM_MODE_ENCODER_DAC, NULL); 3730 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3731 break; 3732 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3733 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3734 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3735 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3736 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3737 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3738 amdgpu_encoder->rmx_type = RMX_FULL; 3739 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3740 DRM_MODE_ENCODER_LVDS, NULL); 3741 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3742 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3743 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3744 DRM_MODE_ENCODER_DAC, NULL); 3745 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3746 } else { 3747 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3748 DRM_MODE_ENCODER_TMDS, NULL); 3749 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3750 } 3751 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3752 break; 3753 case ENCODER_OBJECT_ID_SI170B: 3754 case ENCODER_OBJECT_ID_CH7303: 3755 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3756 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3757 case ENCODER_OBJECT_ID_TITFP513: 3758 case ENCODER_OBJECT_ID_VT1623: 3759 case ENCODER_OBJECT_ID_HDMI_SI1930: 3760 case ENCODER_OBJECT_ID_TRAVIS: 3761 case ENCODER_OBJECT_ID_NUTMEG: 3762 /* these are handled by the primary encoders */ 3763 amdgpu_encoder->is_ext_encoder = true; 3764 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3765 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3766 DRM_MODE_ENCODER_LVDS, NULL); 3767 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3768 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3769 DRM_MODE_ENCODER_DAC, NULL); 3770 else 3771 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3772 DRM_MODE_ENCODER_TMDS, NULL); 3773 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3774 break; 3775 } 3776 } 3777 3778 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3779 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3780 .bandwidth_update = &dce_v11_0_bandwidth_update, 3781 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3782 .vblank_wait = &dce_v11_0_vblank_wait, 3783 .is_display_hung = &dce_v11_0_is_display_hung, 3784 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3785 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3786 .hpd_sense = &dce_v11_0_hpd_sense, 3787 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3788 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3789 .page_flip = &dce_v11_0_page_flip, 3790 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3791 .add_encoder = &dce_v11_0_encoder_add, 3792 .add_connector = &amdgpu_connector_add, 3793 .stop_mc_access = &dce_v11_0_stop_mc_access, 3794 .resume_mc_access = &dce_v11_0_resume_mc_access, 3795 }; 3796 3797 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3798 { 3799 if (adev->mode_info.funcs == NULL) 3800 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3801 } 3802 3803 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3804 .set = dce_v11_0_set_crtc_irq_state, 3805 .process = dce_v11_0_crtc_irq, 3806 }; 3807 3808 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3809 .set = dce_v11_0_set_pageflip_irq_state, 3810 .process = dce_v11_0_pageflip_irq, 3811 }; 3812 3813 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3814 .set = dce_v11_0_set_hpd_irq_state, 3815 .process = dce_v11_0_hpd_irq, 3816 }; 3817 3818 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3819 { 3820 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3821 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3822 3823 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3824 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3825 3826 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3827 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3828 } 3829