1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 #include "dce/dce_11_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET, 75 DIG7_REGISTER_OFFSET, 76 DIG8_REGISTER_OFFSET 77 }; 78 79 static const struct { 80 uint32_t reg; 81 uint32_t vblank; 82 uint32_t vline; 83 uint32_t hpd; 84 85 } interrupt_status_offsets[] = { { 86 .reg = mmDISP_INTERRUPT_STATUS, 87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 } }; 116 117 static const u32 cz_golden_settings_a11[] = 118 { 119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000, 121 }; 122 123 static const u32 cz_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 stoney_golden_settings_a11[] = 130 { 131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 132 mmFBC_MISC, 0x1f311fff, 0x14302000, 133 }; 134 135 static const u32 polaris11_golden_settings_a11[] = 136 { 137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 139 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 140 mmFBC_MISC, 0x9f313fff, 0x14302008, 141 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 142 }; 143 144 static const u32 polaris10_golden_settings_a11[] = 145 { 146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 148 mmFBC_MISC, 0x9f313fff, 0x14302008, 149 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 150 }; 151 152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 153 { 154 switch (adev->asic_type) { 155 case CHIP_CARRIZO: 156 amdgpu_program_register_sequence(adev, 157 cz_mgcg_cgcg_init, 158 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 159 amdgpu_program_register_sequence(adev, 160 cz_golden_settings_a11, 161 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 162 break; 163 case CHIP_STONEY: 164 amdgpu_program_register_sequence(adev, 165 stoney_golden_settings_a11, 166 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 167 break; 168 case CHIP_POLARIS11: 169 amdgpu_program_register_sequence(adev, 170 polaris11_golden_settings_a11, 171 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); 172 break; 173 case CHIP_POLARIS10: 174 amdgpu_program_register_sequence(adev, 175 polaris10_golden_settings_a11, 176 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); 177 break; 178 default: 179 break; 180 } 181 } 182 183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 184 u32 block_offset, u32 reg) 185 { 186 unsigned long flags; 187 u32 r; 188 189 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 191 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 192 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 193 194 return r; 195 } 196 197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 198 u32 block_offset, u32 reg, u32 v) 199 { 200 unsigned long flags; 201 202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 206 } 207 208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 209 { 210 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 212 return true; 213 else 214 return false; 215 } 216 217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 218 { 219 u32 pos1, pos2; 220 221 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 222 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 223 224 if (pos1 != pos2) 225 return true; 226 else 227 return false; 228 } 229 230 /** 231 * dce_v11_0_vblank_wait - vblank wait asic callback. 232 * 233 * @adev: amdgpu_device pointer 234 * @crtc: crtc to wait for vblank on 235 * 236 * Wait for vblank on the requested crtc (evergreen+). 237 */ 238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 239 { 240 unsigned i = 100; 241 242 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 243 return; 244 245 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 246 return; 247 248 /* depending on when we hit vblank, we may be close to active; if so, 249 * wait for another frame. 250 */ 251 while (dce_v11_0_is_in_vblank(adev, crtc)) { 252 if (i++ == 100) { 253 i = 0; 254 if (!dce_v11_0_is_counter_moving(adev, crtc)) 255 break; 256 } 257 } 258 259 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 260 if (i++ == 100) { 261 i = 0; 262 if (!dce_v11_0_is_counter_moving(adev, crtc)) 263 break; 264 } 265 } 266 } 267 268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 269 { 270 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 271 return 0; 272 else 273 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 274 } 275 276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 277 { 278 unsigned i; 279 280 /* Enable pflip interrupts */ 281 for (i = 0; i < adev->mode_info.num_crtc; i++) 282 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 283 } 284 285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 286 { 287 unsigned i; 288 289 /* Disable pflip interrupts */ 290 for (i = 0; i < adev->mode_info.num_crtc; i++) 291 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 292 } 293 294 /** 295 * dce_v11_0_page_flip - pageflip callback. 296 * 297 * @adev: amdgpu_device pointer 298 * @crtc_id: crtc to cleanup pageflip on 299 * @crtc_base: new address of the crtc (GPU MC address) 300 * 301 * Triggers the actual pageflip by updating the primary 302 * surface base address. 303 */ 304 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 305 int crtc_id, u64 crtc_base, bool async) 306 { 307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 308 u32 tmp; 309 310 /* flip immediate for async, default is vsync */ 311 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 312 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 313 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 314 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 315 /* update the scanout addresses */ 316 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 317 upper_32_bits(crtc_base)); 318 /* writing to the low address triggers the update */ 319 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 320 lower_32_bits(crtc_base)); 321 /* post the write */ 322 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 323 } 324 325 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 326 u32 *vbl, u32 *position) 327 { 328 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 329 return -EINVAL; 330 331 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 332 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 333 334 return 0; 335 } 336 337 /** 338 * dce_v11_0_hpd_sense - hpd sense callback. 339 * 340 * @adev: amdgpu_device pointer 341 * @hpd: hpd (hotplug detect) pin 342 * 343 * Checks if a digital monitor is connected (evergreen+). 344 * Returns true if connected, false if not connected. 345 */ 346 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 347 enum amdgpu_hpd_id hpd) 348 { 349 int idx; 350 bool connected = false; 351 352 switch (hpd) { 353 case AMDGPU_HPD_1: 354 idx = 0; 355 break; 356 case AMDGPU_HPD_2: 357 idx = 1; 358 break; 359 case AMDGPU_HPD_3: 360 idx = 2; 361 break; 362 case AMDGPU_HPD_4: 363 idx = 3; 364 break; 365 case AMDGPU_HPD_5: 366 idx = 4; 367 break; 368 case AMDGPU_HPD_6: 369 idx = 5; 370 break; 371 default: 372 return connected; 373 } 374 375 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 376 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 377 connected = true; 378 379 return connected; 380 } 381 382 /** 383 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 384 * 385 * @adev: amdgpu_device pointer 386 * @hpd: hpd (hotplug detect) pin 387 * 388 * Set the polarity of the hpd pin (evergreen+). 389 */ 390 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 391 enum amdgpu_hpd_id hpd) 392 { 393 u32 tmp; 394 bool connected = dce_v11_0_hpd_sense(adev, hpd); 395 int idx; 396 397 switch (hpd) { 398 case AMDGPU_HPD_1: 399 idx = 0; 400 break; 401 case AMDGPU_HPD_2: 402 idx = 1; 403 break; 404 case AMDGPU_HPD_3: 405 idx = 2; 406 break; 407 case AMDGPU_HPD_4: 408 idx = 3; 409 break; 410 case AMDGPU_HPD_5: 411 idx = 4; 412 break; 413 case AMDGPU_HPD_6: 414 idx = 5; 415 break; 416 default: 417 return; 418 } 419 420 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 421 if (connected) 422 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 423 else 424 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 425 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 426 } 427 428 /** 429 * dce_v11_0_hpd_init - hpd setup callback. 430 * 431 * @adev: amdgpu_device pointer 432 * 433 * Setup the hpd pins used by the card (evergreen+). 434 * Enable the pin, set the polarity, and enable the hpd interrupts. 435 */ 436 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 437 { 438 struct drm_device *dev = adev->ddev; 439 struct drm_connector *connector; 440 u32 tmp; 441 int idx; 442 443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 444 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 445 446 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 447 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 448 /* don't try to enable hpd on eDP or LVDS avoid breaking the 449 * aux dp channel on imac and help (but not completely fix) 450 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 451 * also avoid interrupt storms during dpms. 452 */ 453 continue; 454 } 455 456 switch (amdgpu_connector->hpd.hpd) { 457 case AMDGPU_HPD_1: 458 idx = 0; 459 break; 460 case AMDGPU_HPD_2: 461 idx = 1; 462 break; 463 case AMDGPU_HPD_3: 464 idx = 2; 465 break; 466 case AMDGPU_HPD_4: 467 idx = 3; 468 break; 469 case AMDGPU_HPD_5: 470 idx = 4; 471 break; 472 case AMDGPU_HPD_6: 473 idx = 5; 474 break; 475 default: 476 continue; 477 } 478 479 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 480 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 481 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 482 483 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 484 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 485 DC_HPD_CONNECT_INT_DELAY, 486 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 487 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 488 DC_HPD_DISCONNECT_INT_DELAY, 489 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 490 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 491 492 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 493 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 494 } 495 } 496 497 /** 498 * dce_v11_0_hpd_fini - hpd tear down callback. 499 * 500 * @adev: amdgpu_device pointer 501 * 502 * Tear down the hpd pins used by the card (evergreen+). 503 * Disable the hpd interrupts. 504 */ 505 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 506 { 507 struct drm_device *dev = adev->ddev; 508 struct drm_connector *connector; 509 u32 tmp; 510 int idx; 511 512 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 513 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 514 515 switch (amdgpu_connector->hpd.hpd) { 516 case AMDGPU_HPD_1: 517 idx = 0; 518 break; 519 case AMDGPU_HPD_2: 520 idx = 1; 521 break; 522 case AMDGPU_HPD_3: 523 idx = 2; 524 break; 525 case AMDGPU_HPD_4: 526 idx = 3; 527 break; 528 case AMDGPU_HPD_5: 529 idx = 4; 530 break; 531 case AMDGPU_HPD_6: 532 idx = 5; 533 break; 534 default: 535 continue; 536 } 537 538 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 539 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 540 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 541 542 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 543 } 544 } 545 546 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 547 { 548 return mmDC_GPIO_HPD_A; 549 } 550 551 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 552 { 553 u32 crtc_hung = 0; 554 u32 crtc_status[6]; 555 u32 i, j, tmp; 556 557 for (i = 0; i < adev->mode_info.num_crtc; i++) { 558 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 559 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 560 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 561 crtc_hung |= (1 << i); 562 } 563 } 564 565 for (j = 0; j < 10; j++) { 566 for (i = 0; i < adev->mode_info.num_crtc; i++) { 567 if (crtc_hung & (1 << i)) { 568 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 569 if (tmp != crtc_status[i]) 570 crtc_hung &= ~(1 << i); 571 } 572 } 573 if (crtc_hung == 0) 574 return false; 575 udelay(100); 576 } 577 578 return true; 579 } 580 581 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 582 struct amdgpu_mode_mc_save *save) 583 { 584 u32 crtc_enabled, tmp; 585 int i; 586 587 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 588 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 589 590 /* disable VGA render */ 591 tmp = RREG32(mmVGA_RENDER_CONTROL); 592 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 593 WREG32(mmVGA_RENDER_CONTROL, tmp); 594 595 /* blank the display controllers */ 596 for (i = 0; i < adev->mode_info.num_crtc; i++) { 597 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 598 CRTC_CONTROL, CRTC_MASTER_EN); 599 if (crtc_enabled) { 600 #if 1 601 save->crtc_enabled[i] = true; 602 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 603 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 604 /*it is correct only for RGB ; black is 0*/ 605 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 606 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 607 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 608 } 609 #else 610 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 611 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 612 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 613 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 614 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 615 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 616 save->crtc_enabled[i] = false; 617 /* ***** */ 618 #endif 619 } else { 620 save->crtc_enabled[i] = false; 621 } 622 } 623 } 624 625 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 626 struct amdgpu_mode_mc_save *save) 627 { 628 u32 tmp; 629 int i; 630 631 /* update crtc base addresses */ 632 for (i = 0; i < adev->mode_info.num_crtc; i++) { 633 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 634 upper_32_bits(adev->mc.vram_start)); 635 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 636 (u32)adev->mc.vram_start); 637 638 if (save->crtc_enabled[i]) { 639 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 640 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 641 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 642 } 643 } 644 645 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 646 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 647 648 /* Unlock vga access */ 649 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 650 mdelay(1); 651 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 652 } 653 654 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 655 bool render) 656 { 657 u32 tmp; 658 659 /* Lockout access through VGA aperture*/ 660 tmp = RREG32(mmVGA_HDP_CONTROL); 661 if (render) 662 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 663 else 664 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 665 WREG32(mmVGA_HDP_CONTROL, tmp); 666 667 /* disable VGA render */ 668 tmp = RREG32(mmVGA_RENDER_CONTROL); 669 if (render) 670 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 671 else 672 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 673 WREG32(mmVGA_RENDER_CONTROL, tmp); 674 } 675 676 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 677 { 678 struct drm_device *dev = encoder->dev; 679 struct amdgpu_device *adev = dev->dev_private; 680 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 682 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 683 int bpc = 0; 684 u32 tmp = 0; 685 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 686 687 if (connector) { 688 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 689 bpc = amdgpu_connector_get_monitor_bpc(connector); 690 dither = amdgpu_connector->dither; 691 } 692 693 /* LVDS/eDP FMT is set up by atom */ 694 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 695 return; 696 697 /* not needed for analog */ 698 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 699 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 700 return; 701 702 if (bpc == 0) 703 return; 704 705 switch (bpc) { 706 case 6: 707 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 708 /* XXX sort out optimal dither settings */ 709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 711 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 712 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 713 } else { 714 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 715 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 716 } 717 break; 718 case 8: 719 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 720 /* XXX sort out optimal dither settings */ 721 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 722 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 723 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 724 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 725 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 726 } else { 727 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 728 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 729 } 730 break; 731 case 10: 732 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 733 /* XXX sort out optimal dither settings */ 734 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 735 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 736 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 737 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 738 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 739 } else { 740 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 741 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 742 } 743 break; 744 default: 745 /* not needed */ 746 break; 747 } 748 749 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 750 } 751 752 753 /* display watermark setup */ 754 /** 755 * dce_v11_0_line_buffer_adjust - Set up the line buffer 756 * 757 * @adev: amdgpu_device pointer 758 * @amdgpu_crtc: the selected display controller 759 * @mode: the current display mode on the selected display 760 * controller 761 * 762 * Setup up the line buffer allocation for 763 * the selected display controller (CIK). 764 * Returns the line buffer size in pixels. 765 */ 766 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 767 struct amdgpu_crtc *amdgpu_crtc, 768 struct drm_display_mode *mode) 769 { 770 u32 tmp, buffer_alloc, i, mem_cfg; 771 u32 pipe_offset = amdgpu_crtc->crtc_id; 772 /* 773 * Line Buffer Setup 774 * There are 6 line buffers, one for each display controllers. 775 * There are 3 partitions per LB. Select the number of partitions 776 * to enable based on the display width. For display widths larger 777 * than 4096, you need use to use 2 display controllers and combine 778 * them using the stereo blender. 779 */ 780 if (amdgpu_crtc->base.enabled && mode) { 781 if (mode->crtc_hdisplay < 1920) { 782 mem_cfg = 1; 783 buffer_alloc = 2; 784 } else if (mode->crtc_hdisplay < 2560) { 785 mem_cfg = 2; 786 buffer_alloc = 2; 787 } else if (mode->crtc_hdisplay < 4096) { 788 mem_cfg = 0; 789 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 790 } else { 791 DRM_DEBUG_KMS("Mode too big for LB!\n"); 792 mem_cfg = 0; 793 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 794 } 795 } else { 796 mem_cfg = 1; 797 buffer_alloc = 0; 798 } 799 800 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 801 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 802 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 803 804 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 805 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 806 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 807 808 for (i = 0; i < adev->usec_timeout; i++) { 809 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 810 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 811 break; 812 udelay(1); 813 } 814 815 if (amdgpu_crtc->base.enabled && mode) { 816 switch (mem_cfg) { 817 case 0: 818 default: 819 return 4096 * 2; 820 case 1: 821 return 1920 * 2; 822 case 2: 823 return 2560 * 2; 824 } 825 } 826 827 /* controller not enabled, so no lb used */ 828 return 0; 829 } 830 831 /** 832 * cik_get_number_of_dram_channels - get the number of dram channels 833 * 834 * @adev: amdgpu_device pointer 835 * 836 * Look up the number of video ram channels (CIK). 837 * Used for display watermark bandwidth calculations 838 * Returns the number of dram channels 839 */ 840 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 841 { 842 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 843 844 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 845 case 0: 846 default: 847 return 1; 848 case 1: 849 return 2; 850 case 2: 851 return 4; 852 case 3: 853 return 8; 854 case 4: 855 return 3; 856 case 5: 857 return 6; 858 case 6: 859 return 10; 860 case 7: 861 return 12; 862 case 8: 863 return 16; 864 } 865 } 866 867 struct dce10_wm_params { 868 u32 dram_channels; /* number of dram channels */ 869 u32 yclk; /* bandwidth per dram data pin in kHz */ 870 u32 sclk; /* engine clock in kHz */ 871 u32 disp_clk; /* display clock in kHz */ 872 u32 src_width; /* viewport width */ 873 u32 active_time; /* active display time in ns */ 874 u32 blank_time; /* blank time in ns */ 875 bool interlaced; /* mode is interlaced */ 876 fixed20_12 vsc; /* vertical scale ratio */ 877 u32 num_heads; /* number of active crtcs */ 878 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 879 u32 lb_size; /* line buffer allocated to pipe */ 880 u32 vtaps; /* vertical scaler taps */ 881 }; 882 883 /** 884 * dce_v11_0_dram_bandwidth - get the dram bandwidth 885 * 886 * @wm: watermark calculation data 887 * 888 * Calculate the raw dram bandwidth (CIK). 889 * Used for display watermark bandwidth calculations 890 * Returns the dram bandwidth in MBytes/s 891 */ 892 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 893 { 894 /* Calculate raw DRAM Bandwidth */ 895 fixed20_12 dram_efficiency; /* 0.7 */ 896 fixed20_12 yclk, dram_channels, bandwidth; 897 fixed20_12 a; 898 899 a.full = dfixed_const(1000); 900 yclk.full = dfixed_const(wm->yclk); 901 yclk.full = dfixed_div(yclk, a); 902 dram_channels.full = dfixed_const(wm->dram_channels * 4); 903 a.full = dfixed_const(10); 904 dram_efficiency.full = dfixed_const(7); 905 dram_efficiency.full = dfixed_div(dram_efficiency, a); 906 bandwidth.full = dfixed_mul(dram_channels, yclk); 907 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 908 909 return dfixed_trunc(bandwidth); 910 } 911 912 /** 913 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 914 * 915 * @wm: watermark calculation data 916 * 917 * Calculate the dram bandwidth used for display (CIK). 918 * Used for display watermark bandwidth calculations 919 * Returns the dram bandwidth for display in MBytes/s 920 */ 921 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 922 { 923 /* Calculate DRAM Bandwidth and the part allocated to display. */ 924 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 925 fixed20_12 yclk, dram_channels, bandwidth; 926 fixed20_12 a; 927 928 a.full = dfixed_const(1000); 929 yclk.full = dfixed_const(wm->yclk); 930 yclk.full = dfixed_div(yclk, a); 931 dram_channels.full = dfixed_const(wm->dram_channels * 4); 932 a.full = dfixed_const(10); 933 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 934 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 935 bandwidth.full = dfixed_mul(dram_channels, yclk); 936 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 937 938 return dfixed_trunc(bandwidth); 939 } 940 941 /** 942 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 943 * 944 * @wm: watermark calculation data 945 * 946 * Calculate the data return bandwidth used for display (CIK). 947 * Used for display watermark bandwidth calculations 948 * Returns the data return bandwidth in MBytes/s 949 */ 950 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 951 { 952 /* Calculate the display Data return Bandwidth */ 953 fixed20_12 return_efficiency; /* 0.8 */ 954 fixed20_12 sclk, bandwidth; 955 fixed20_12 a; 956 957 a.full = dfixed_const(1000); 958 sclk.full = dfixed_const(wm->sclk); 959 sclk.full = dfixed_div(sclk, a); 960 a.full = dfixed_const(10); 961 return_efficiency.full = dfixed_const(8); 962 return_efficiency.full = dfixed_div(return_efficiency, a); 963 a.full = dfixed_const(32); 964 bandwidth.full = dfixed_mul(a, sclk); 965 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 966 967 return dfixed_trunc(bandwidth); 968 } 969 970 /** 971 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 972 * 973 * @wm: watermark calculation data 974 * 975 * Calculate the dmif bandwidth used for display (CIK). 976 * Used for display watermark bandwidth calculations 977 * Returns the dmif bandwidth in MBytes/s 978 */ 979 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 980 { 981 /* Calculate the DMIF Request Bandwidth */ 982 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 983 fixed20_12 disp_clk, bandwidth; 984 fixed20_12 a, b; 985 986 a.full = dfixed_const(1000); 987 disp_clk.full = dfixed_const(wm->disp_clk); 988 disp_clk.full = dfixed_div(disp_clk, a); 989 a.full = dfixed_const(32); 990 b.full = dfixed_mul(a, disp_clk); 991 992 a.full = dfixed_const(10); 993 disp_clk_request_efficiency.full = dfixed_const(8); 994 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 995 996 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 997 998 return dfixed_trunc(bandwidth); 999 } 1000 1001 /** 1002 * dce_v11_0_available_bandwidth - get the min available bandwidth 1003 * 1004 * @wm: watermark calculation data 1005 * 1006 * Calculate the min available bandwidth used for display (CIK). 1007 * Used for display watermark bandwidth calculations 1008 * Returns the min available bandwidth in MBytes/s 1009 */ 1010 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 1011 { 1012 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1013 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 1014 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 1015 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 1016 1017 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1018 } 1019 1020 /** 1021 * dce_v11_0_average_bandwidth - get the average available bandwidth 1022 * 1023 * @wm: watermark calculation data 1024 * 1025 * Calculate the average available bandwidth used for display (CIK). 1026 * Used for display watermark bandwidth calculations 1027 * Returns the average available bandwidth in MBytes/s 1028 */ 1029 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 1030 { 1031 /* Calculate the display mode Average Bandwidth 1032 * DisplayMode should contain the source and destination dimensions, 1033 * timing, etc. 1034 */ 1035 fixed20_12 bpp; 1036 fixed20_12 line_time; 1037 fixed20_12 src_width; 1038 fixed20_12 bandwidth; 1039 fixed20_12 a; 1040 1041 a.full = dfixed_const(1000); 1042 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1043 line_time.full = dfixed_div(line_time, a); 1044 bpp.full = dfixed_const(wm->bytes_per_pixel); 1045 src_width.full = dfixed_const(wm->src_width); 1046 bandwidth.full = dfixed_mul(src_width, bpp); 1047 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1048 bandwidth.full = dfixed_div(bandwidth, line_time); 1049 1050 return dfixed_trunc(bandwidth); 1051 } 1052 1053 /** 1054 * dce_v11_0_latency_watermark - get the latency watermark 1055 * 1056 * @wm: watermark calculation data 1057 * 1058 * Calculate the latency watermark (CIK). 1059 * Used for display watermark bandwidth calculations 1060 * Returns the latency watermark in ns 1061 */ 1062 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1063 { 1064 /* First calculate the latency in ns */ 1065 u32 mc_latency = 2000; /* 2000 ns. */ 1066 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1067 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1068 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1069 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1070 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1071 (wm->num_heads * cursor_line_pair_return_time); 1072 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1073 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1074 u32 tmp, dmif_size = 12288; 1075 fixed20_12 a, b, c; 1076 1077 if (wm->num_heads == 0) 1078 return 0; 1079 1080 a.full = dfixed_const(2); 1081 b.full = dfixed_const(1); 1082 if ((wm->vsc.full > a.full) || 1083 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1084 (wm->vtaps >= 5) || 1085 ((wm->vsc.full >= a.full) && wm->interlaced)) 1086 max_src_lines_per_dst_line = 4; 1087 else 1088 max_src_lines_per_dst_line = 2; 1089 1090 a.full = dfixed_const(available_bandwidth); 1091 b.full = dfixed_const(wm->num_heads); 1092 a.full = dfixed_div(a, b); 1093 1094 b.full = dfixed_const(mc_latency + 512); 1095 c.full = dfixed_const(wm->disp_clk); 1096 b.full = dfixed_div(b, c); 1097 1098 c.full = dfixed_const(dmif_size); 1099 b.full = dfixed_div(c, b); 1100 1101 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1102 1103 b.full = dfixed_const(1000); 1104 c.full = dfixed_const(wm->disp_clk); 1105 b.full = dfixed_div(c, b); 1106 c.full = dfixed_const(wm->bytes_per_pixel); 1107 b.full = dfixed_mul(b, c); 1108 1109 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1110 1111 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1112 b.full = dfixed_const(1000); 1113 c.full = dfixed_const(lb_fill_bw); 1114 b.full = dfixed_div(c, b); 1115 a.full = dfixed_div(a, b); 1116 line_fill_time = dfixed_trunc(a); 1117 1118 if (line_fill_time < wm->active_time) 1119 return latency; 1120 else 1121 return latency + (line_fill_time - wm->active_time); 1122 1123 } 1124 1125 /** 1126 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1127 * average and available dram bandwidth 1128 * 1129 * @wm: watermark calculation data 1130 * 1131 * Check if the display average bandwidth fits in the display 1132 * dram bandwidth (CIK). 1133 * Used for display watermark bandwidth calculations 1134 * Returns true if the display fits, false if not. 1135 */ 1136 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1137 { 1138 if (dce_v11_0_average_bandwidth(wm) <= 1139 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1140 return true; 1141 else 1142 return false; 1143 } 1144 1145 /** 1146 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1147 * average and available bandwidth 1148 * 1149 * @wm: watermark calculation data 1150 * 1151 * Check if the display average bandwidth fits in the display 1152 * available bandwidth (CIK). 1153 * Used for display watermark bandwidth calculations 1154 * Returns true if the display fits, false if not. 1155 */ 1156 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1157 { 1158 if (dce_v11_0_average_bandwidth(wm) <= 1159 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1160 return true; 1161 else 1162 return false; 1163 } 1164 1165 /** 1166 * dce_v11_0_check_latency_hiding - check latency hiding 1167 * 1168 * @wm: watermark calculation data 1169 * 1170 * Check latency hiding (CIK). 1171 * Used for display watermark bandwidth calculations 1172 * Returns true if the display fits, false if not. 1173 */ 1174 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1175 { 1176 u32 lb_partitions = wm->lb_size / wm->src_width; 1177 u32 line_time = wm->active_time + wm->blank_time; 1178 u32 latency_tolerant_lines; 1179 u32 latency_hiding; 1180 fixed20_12 a; 1181 1182 a.full = dfixed_const(1); 1183 if (wm->vsc.full > a.full) 1184 latency_tolerant_lines = 1; 1185 else { 1186 if (lb_partitions <= (wm->vtaps + 1)) 1187 latency_tolerant_lines = 1; 1188 else 1189 latency_tolerant_lines = 2; 1190 } 1191 1192 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1193 1194 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1195 return true; 1196 else 1197 return false; 1198 } 1199 1200 /** 1201 * dce_v11_0_program_watermarks - program display watermarks 1202 * 1203 * @adev: amdgpu_device pointer 1204 * @amdgpu_crtc: the selected display controller 1205 * @lb_size: line buffer size 1206 * @num_heads: number of display controllers in use 1207 * 1208 * Calculate and program the display watermarks for the 1209 * selected display controller (CIK). 1210 */ 1211 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1212 struct amdgpu_crtc *amdgpu_crtc, 1213 u32 lb_size, u32 num_heads) 1214 { 1215 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1216 struct dce10_wm_params wm_low, wm_high; 1217 u32 pixel_period; 1218 u32 line_time = 0; 1219 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1220 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1221 1222 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1223 pixel_period = 1000000 / (u32)mode->clock; 1224 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1225 1226 /* watermark for high clocks */ 1227 if (adev->pm.dpm_enabled) { 1228 wm_high.yclk = 1229 amdgpu_dpm_get_mclk(adev, false) * 10; 1230 wm_high.sclk = 1231 amdgpu_dpm_get_sclk(adev, false) * 10; 1232 } else { 1233 wm_high.yclk = adev->pm.current_mclk * 10; 1234 wm_high.sclk = adev->pm.current_sclk * 10; 1235 } 1236 1237 wm_high.disp_clk = mode->clock; 1238 wm_high.src_width = mode->crtc_hdisplay; 1239 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1240 wm_high.blank_time = line_time - wm_high.active_time; 1241 wm_high.interlaced = false; 1242 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1243 wm_high.interlaced = true; 1244 wm_high.vsc = amdgpu_crtc->vsc; 1245 wm_high.vtaps = 1; 1246 if (amdgpu_crtc->rmx_type != RMX_OFF) 1247 wm_high.vtaps = 2; 1248 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1249 wm_high.lb_size = lb_size; 1250 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1251 wm_high.num_heads = num_heads; 1252 1253 /* set for high clocks */ 1254 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1255 1256 /* possibly force display priority to high */ 1257 /* should really do this at mode validation time... */ 1258 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1259 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1260 !dce_v11_0_check_latency_hiding(&wm_high) || 1261 (adev->mode_info.disp_priority == 2)) { 1262 DRM_DEBUG_KMS("force priority to high\n"); 1263 } 1264 1265 /* watermark for low clocks */ 1266 if (adev->pm.dpm_enabled) { 1267 wm_low.yclk = 1268 amdgpu_dpm_get_mclk(adev, true) * 10; 1269 wm_low.sclk = 1270 amdgpu_dpm_get_sclk(adev, true) * 10; 1271 } else { 1272 wm_low.yclk = adev->pm.current_mclk * 10; 1273 wm_low.sclk = adev->pm.current_sclk * 10; 1274 } 1275 1276 wm_low.disp_clk = mode->clock; 1277 wm_low.src_width = mode->crtc_hdisplay; 1278 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1279 wm_low.blank_time = line_time - wm_low.active_time; 1280 wm_low.interlaced = false; 1281 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1282 wm_low.interlaced = true; 1283 wm_low.vsc = amdgpu_crtc->vsc; 1284 wm_low.vtaps = 1; 1285 if (amdgpu_crtc->rmx_type != RMX_OFF) 1286 wm_low.vtaps = 2; 1287 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1288 wm_low.lb_size = lb_size; 1289 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1290 wm_low.num_heads = num_heads; 1291 1292 /* set for low clocks */ 1293 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1294 1295 /* possibly force display priority to high */ 1296 /* should really do this at mode validation time... */ 1297 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1298 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1299 !dce_v11_0_check_latency_hiding(&wm_low) || 1300 (adev->mode_info.disp_priority == 2)) { 1301 DRM_DEBUG_KMS("force priority to high\n"); 1302 } 1303 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1304 } 1305 1306 /* select wm A */ 1307 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1308 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1309 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1310 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1311 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1312 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1313 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1314 /* select wm B */ 1315 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1316 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1317 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1318 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1319 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1320 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1321 /* restore original selection */ 1322 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1323 1324 /* save values for DPM */ 1325 amdgpu_crtc->line_time = line_time; 1326 amdgpu_crtc->wm_high = latency_watermark_a; 1327 amdgpu_crtc->wm_low = latency_watermark_b; 1328 /* Save number of lines the linebuffer leads before the scanout */ 1329 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1330 } 1331 1332 /** 1333 * dce_v11_0_bandwidth_update - program display watermarks 1334 * 1335 * @adev: amdgpu_device pointer 1336 * 1337 * Calculate and program the display watermarks and line 1338 * buffer allocation (CIK). 1339 */ 1340 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1341 { 1342 struct drm_display_mode *mode = NULL; 1343 u32 num_heads = 0, lb_size; 1344 int i; 1345 1346 amdgpu_update_display_priority(adev); 1347 1348 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1349 if (adev->mode_info.crtcs[i]->base.enabled) 1350 num_heads++; 1351 } 1352 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1353 mode = &adev->mode_info.crtcs[i]->base.mode; 1354 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1355 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1356 lb_size, num_heads); 1357 } 1358 } 1359 1360 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1361 { 1362 int i; 1363 u32 offset, tmp; 1364 1365 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1366 offset = adev->mode_info.audio.pin[i].offset; 1367 tmp = RREG32_AUDIO_ENDPT(offset, 1368 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1369 if (((tmp & 1370 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1371 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1372 adev->mode_info.audio.pin[i].connected = false; 1373 else 1374 adev->mode_info.audio.pin[i].connected = true; 1375 } 1376 } 1377 1378 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1379 { 1380 int i; 1381 1382 dce_v11_0_audio_get_connected_pins(adev); 1383 1384 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1385 if (adev->mode_info.audio.pin[i].connected) 1386 return &adev->mode_info.audio.pin[i]; 1387 } 1388 DRM_ERROR("No connected audio pins found!\n"); 1389 return NULL; 1390 } 1391 1392 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1393 { 1394 struct amdgpu_device *adev = encoder->dev->dev_private; 1395 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1396 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1397 u32 tmp; 1398 1399 if (!dig || !dig->afmt || !dig->afmt->pin) 1400 return; 1401 1402 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1403 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1404 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1405 } 1406 1407 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1408 struct drm_display_mode *mode) 1409 { 1410 struct amdgpu_device *adev = encoder->dev->dev_private; 1411 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1412 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1413 struct drm_connector *connector; 1414 struct amdgpu_connector *amdgpu_connector = NULL; 1415 u32 tmp; 1416 int interlace = 0; 1417 1418 if (!dig || !dig->afmt || !dig->afmt->pin) 1419 return; 1420 1421 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1422 if (connector->encoder == encoder) { 1423 amdgpu_connector = to_amdgpu_connector(connector); 1424 break; 1425 } 1426 } 1427 1428 if (!amdgpu_connector) { 1429 DRM_ERROR("Couldn't find encoder's connector\n"); 1430 return; 1431 } 1432 1433 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1434 interlace = 1; 1435 if (connector->latency_present[interlace]) { 1436 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1437 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1438 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1439 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1440 } else { 1441 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1442 VIDEO_LIPSYNC, 0); 1443 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1444 AUDIO_LIPSYNC, 0); 1445 } 1446 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1447 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1448 } 1449 1450 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1451 { 1452 struct amdgpu_device *adev = encoder->dev->dev_private; 1453 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1454 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1455 struct drm_connector *connector; 1456 struct amdgpu_connector *amdgpu_connector = NULL; 1457 u32 tmp; 1458 u8 *sadb = NULL; 1459 int sad_count; 1460 1461 if (!dig || !dig->afmt || !dig->afmt->pin) 1462 return; 1463 1464 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1465 if (connector->encoder == encoder) { 1466 amdgpu_connector = to_amdgpu_connector(connector); 1467 break; 1468 } 1469 } 1470 1471 if (!amdgpu_connector) { 1472 DRM_ERROR("Couldn't find encoder's connector\n"); 1473 return; 1474 } 1475 1476 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1477 if (sad_count < 0) { 1478 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1479 sad_count = 0; 1480 } 1481 1482 /* program the speaker allocation */ 1483 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1484 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1485 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1486 DP_CONNECTION, 0); 1487 /* set HDMI mode */ 1488 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1489 HDMI_CONNECTION, 1); 1490 if (sad_count) 1491 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1492 SPEAKER_ALLOCATION, sadb[0]); 1493 else 1494 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1495 SPEAKER_ALLOCATION, 5); /* stereo */ 1496 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1497 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1498 1499 kfree(sadb); 1500 } 1501 1502 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1503 { 1504 struct amdgpu_device *adev = encoder->dev->dev_private; 1505 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1506 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1507 struct drm_connector *connector; 1508 struct amdgpu_connector *amdgpu_connector = NULL; 1509 struct cea_sad *sads; 1510 int i, sad_count; 1511 1512 static const u16 eld_reg_to_type[][2] = { 1513 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1514 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1515 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1516 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1517 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1518 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1519 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1520 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1521 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1522 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1523 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1524 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1525 }; 1526 1527 if (!dig || !dig->afmt || !dig->afmt->pin) 1528 return; 1529 1530 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1531 if (connector->encoder == encoder) { 1532 amdgpu_connector = to_amdgpu_connector(connector); 1533 break; 1534 } 1535 } 1536 1537 if (!amdgpu_connector) { 1538 DRM_ERROR("Couldn't find encoder's connector\n"); 1539 return; 1540 } 1541 1542 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1543 if (sad_count <= 0) { 1544 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1545 return; 1546 } 1547 BUG_ON(!sads); 1548 1549 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1550 u32 tmp = 0; 1551 u8 stereo_freqs = 0; 1552 int max_channels = -1; 1553 int j; 1554 1555 for (j = 0; j < sad_count; j++) { 1556 struct cea_sad *sad = &sads[j]; 1557 1558 if (sad->format == eld_reg_to_type[i][1]) { 1559 if (sad->channels > max_channels) { 1560 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1561 MAX_CHANNELS, sad->channels); 1562 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1563 DESCRIPTOR_BYTE_2, sad->byte2); 1564 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1565 SUPPORTED_FREQUENCIES, sad->freq); 1566 max_channels = sad->channels; 1567 } 1568 1569 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1570 stereo_freqs |= sad->freq; 1571 else 1572 break; 1573 } 1574 } 1575 1576 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1577 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1578 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1579 } 1580 1581 kfree(sads); 1582 } 1583 1584 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1585 struct amdgpu_audio_pin *pin, 1586 bool enable) 1587 { 1588 if (!pin) 1589 return; 1590 1591 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1592 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1593 } 1594 1595 static const u32 pin_offsets[] = 1596 { 1597 AUD0_REGISTER_OFFSET, 1598 AUD1_REGISTER_OFFSET, 1599 AUD2_REGISTER_OFFSET, 1600 AUD3_REGISTER_OFFSET, 1601 AUD4_REGISTER_OFFSET, 1602 AUD5_REGISTER_OFFSET, 1603 AUD6_REGISTER_OFFSET, 1604 AUD7_REGISTER_OFFSET, 1605 }; 1606 1607 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1608 { 1609 int i; 1610 1611 if (!amdgpu_audio) 1612 return 0; 1613 1614 adev->mode_info.audio.enabled = true; 1615 1616 switch (adev->asic_type) { 1617 case CHIP_CARRIZO: 1618 case CHIP_STONEY: 1619 adev->mode_info.audio.num_pins = 7; 1620 break; 1621 case CHIP_POLARIS10: 1622 adev->mode_info.audio.num_pins = 8; 1623 break; 1624 case CHIP_POLARIS11: 1625 adev->mode_info.audio.num_pins = 6; 1626 break; 1627 default: 1628 return -EINVAL; 1629 } 1630 1631 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1632 adev->mode_info.audio.pin[i].channels = -1; 1633 adev->mode_info.audio.pin[i].rate = -1; 1634 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1635 adev->mode_info.audio.pin[i].status_bits = 0; 1636 adev->mode_info.audio.pin[i].category_code = 0; 1637 adev->mode_info.audio.pin[i].connected = false; 1638 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1639 adev->mode_info.audio.pin[i].id = i; 1640 /* disable audio. it will be set up later */ 1641 /* XXX remove once we switch to ip funcs */ 1642 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1643 } 1644 1645 return 0; 1646 } 1647 1648 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1649 { 1650 int i; 1651 1652 if (!amdgpu_audio) 1653 return; 1654 1655 if (!adev->mode_info.audio.enabled) 1656 return; 1657 1658 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1659 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1660 1661 adev->mode_info.audio.enabled = false; 1662 } 1663 1664 /* 1665 * update the N and CTS parameters for a given pixel clock rate 1666 */ 1667 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1668 { 1669 struct drm_device *dev = encoder->dev; 1670 struct amdgpu_device *adev = dev->dev_private; 1671 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1672 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1673 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1674 u32 tmp; 1675 1676 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1677 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1678 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1679 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1680 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1681 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1682 1683 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1684 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1685 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1686 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1687 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1688 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1689 1690 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1691 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1692 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1693 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1694 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1695 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1696 1697 } 1698 1699 /* 1700 * build a HDMI Video Info Frame 1701 */ 1702 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1703 void *buffer, size_t size) 1704 { 1705 struct drm_device *dev = encoder->dev; 1706 struct amdgpu_device *adev = dev->dev_private; 1707 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1708 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1709 uint8_t *frame = buffer + 3; 1710 uint8_t *header = buffer; 1711 1712 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1713 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1714 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1715 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1716 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1717 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1718 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1719 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1720 } 1721 1722 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1723 { 1724 struct drm_device *dev = encoder->dev; 1725 struct amdgpu_device *adev = dev->dev_private; 1726 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1727 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1728 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1729 u32 dto_phase = 24 * 1000; 1730 u32 dto_modulo = clock; 1731 u32 tmp; 1732 1733 if (!dig || !dig->afmt) 1734 return; 1735 1736 /* XXX two dtos; generally use dto0 for hdmi */ 1737 /* Express [24MHz / target pixel clock] as an exact rational 1738 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1739 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1740 */ 1741 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1742 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1743 amdgpu_crtc->crtc_id); 1744 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1745 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1746 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1747 } 1748 1749 /* 1750 * update the info frames with the data from the current display mode 1751 */ 1752 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1753 struct drm_display_mode *mode) 1754 { 1755 struct drm_device *dev = encoder->dev; 1756 struct amdgpu_device *adev = dev->dev_private; 1757 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1758 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1759 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1760 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1761 struct hdmi_avi_infoframe frame; 1762 ssize_t err; 1763 u32 tmp; 1764 int bpc = 8; 1765 1766 if (!dig || !dig->afmt) 1767 return; 1768 1769 /* Silent, r600_hdmi_enable will raise WARN for us */ 1770 if (!dig->afmt->enabled) 1771 return; 1772 1773 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1774 if (encoder->crtc) { 1775 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1776 bpc = amdgpu_crtc->bpc; 1777 } 1778 1779 /* disable audio prior to setting up hw */ 1780 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1781 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1782 1783 dce_v11_0_audio_set_dto(encoder, mode->clock); 1784 1785 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1786 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1787 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1788 1789 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1790 1791 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1792 switch (bpc) { 1793 case 0: 1794 case 6: 1795 case 8: 1796 case 16: 1797 default: 1798 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1799 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1800 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1801 connector->name, bpc); 1802 break; 1803 case 10: 1804 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1805 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1806 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1807 connector->name); 1808 break; 1809 case 12: 1810 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1811 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1812 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1813 connector->name); 1814 break; 1815 } 1816 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1817 1818 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1819 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1820 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1821 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1822 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1823 1824 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1825 /* enable audio info frames (frames won't be set until audio is enabled) */ 1826 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1827 /* required for audio info values to be updated */ 1828 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1829 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1830 1831 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1832 /* required for audio info values to be updated */ 1833 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1834 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1835 1836 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1837 /* anything other than 0 */ 1838 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1839 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1840 1841 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1842 1843 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1844 /* set the default audio delay */ 1845 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1846 /* should be suffient for all audio modes and small enough for all hblanks */ 1847 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1848 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1849 1850 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1851 /* allow 60958 channel status fields to be updated */ 1852 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1853 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1854 1855 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1856 if (bpc > 8) 1857 /* clear SW CTS value */ 1858 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1859 else 1860 /* select SW CTS value */ 1861 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1862 /* allow hw to sent ACR packets when required */ 1863 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1864 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1865 1866 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1867 1868 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1869 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1870 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1871 1872 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1873 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1874 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1875 1876 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1877 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1878 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1879 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1880 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1881 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1882 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1883 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1884 1885 dce_v11_0_audio_write_speaker_allocation(encoder); 1886 1887 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1888 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1889 1890 dce_v11_0_afmt_audio_select_pin(encoder); 1891 dce_v11_0_audio_write_sad_regs(encoder); 1892 dce_v11_0_audio_write_latency_fields(encoder, mode); 1893 1894 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1895 if (err < 0) { 1896 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1897 return; 1898 } 1899 1900 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1901 if (err < 0) { 1902 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1903 return; 1904 } 1905 1906 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1907 1908 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1909 /* enable AVI info frames */ 1910 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1911 /* required for audio info values to be updated */ 1912 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1913 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1914 1915 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1916 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1917 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1918 1919 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1920 /* send audio packets */ 1921 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1922 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1923 1924 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1925 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1926 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1927 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1928 1929 /* enable audio after to setting up hw */ 1930 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1931 } 1932 1933 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1934 { 1935 struct drm_device *dev = encoder->dev; 1936 struct amdgpu_device *adev = dev->dev_private; 1937 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1938 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1939 1940 if (!dig || !dig->afmt) 1941 return; 1942 1943 /* Silent, r600_hdmi_enable will raise WARN for us */ 1944 if (enable && dig->afmt->enabled) 1945 return; 1946 if (!enable && !dig->afmt->enabled) 1947 return; 1948 1949 if (!enable && dig->afmt->pin) { 1950 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1951 dig->afmt->pin = NULL; 1952 } 1953 1954 dig->afmt->enabled = enable; 1955 1956 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1957 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1958 } 1959 1960 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1961 { 1962 int i; 1963 1964 for (i = 0; i < adev->mode_info.num_dig; i++) 1965 adev->mode_info.afmt[i] = NULL; 1966 1967 /* DCE11 has audio blocks tied to DIG encoders */ 1968 for (i = 0; i < adev->mode_info.num_dig; i++) { 1969 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1970 if (adev->mode_info.afmt[i]) { 1971 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1972 adev->mode_info.afmt[i]->id = i; 1973 } else { 1974 int j; 1975 for (j = 0; j < i; j++) { 1976 kfree(adev->mode_info.afmt[j]); 1977 adev->mode_info.afmt[j] = NULL; 1978 } 1979 return -ENOMEM; 1980 } 1981 } 1982 return 0; 1983 } 1984 1985 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1986 { 1987 int i; 1988 1989 for (i = 0; i < adev->mode_info.num_dig; i++) { 1990 kfree(adev->mode_info.afmt[i]); 1991 adev->mode_info.afmt[i] = NULL; 1992 } 1993 } 1994 1995 static const u32 vga_control_regs[6] = 1996 { 1997 mmD1VGA_CONTROL, 1998 mmD2VGA_CONTROL, 1999 mmD3VGA_CONTROL, 2000 mmD4VGA_CONTROL, 2001 mmD5VGA_CONTROL, 2002 mmD6VGA_CONTROL, 2003 }; 2004 2005 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 2006 { 2007 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2008 struct drm_device *dev = crtc->dev; 2009 struct amdgpu_device *adev = dev->dev_private; 2010 u32 vga_control; 2011 2012 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2013 if (enable) 2014 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2015 else 2016 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2017 } 2018 2019 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 2020 { 2021 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2022 struct drm_device *dev = crtc->dev; 2023 struct amdgpu_device *adev = dev->dev_private; 2024 2025 if (enable) 2026 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2027 else 2028 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2029 } 2030 2031 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 2032 struct drm_framebuffer *fb, 2033 int x, int y, int atomic) 2034 { 2035 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2036 struct drm_device *dev = crtc->dev; 2037 struct amdgpu_device *adev = dev->dev_private; 2038 struct amdgpu_framebuffer *amdgpu_fb; 2039 struct drm_framebuffer *target_fb; 2040 struct drm_gem_object *obj; 2041 struct amdgpu_bo *rbo; 2042 uint64_t fb_location, tiling_flags; 2043 uint32_t fb_format, fb_pitch_pixels; 2044 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2045 u32 pipe_config; 2046 u32 tmp, viewport_w, viewport_h; 2047 int r; 2048 bool bypass_lut = false; 2049 char *format_name; 2050 2051 /* no fb bound */ 2052 if (!atomic && !crtc->primary->fb) { 2053 DRM_DEBUG_KMS("No FB bound\n"); 2054 return 0; 2055 } 2056 2057 if (atomic) { 2058 amdgpu_fb = to_amdgpu_framebuffer(fb); 2059 target_fb = fb; 2060 } else { 2061 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2062 target_fb = crtc->primary->fb; 2063 } 2064 2065 /* If atomic, assume fb object is pinned & idle & fenced and 2066 * just update base pointers 2067 */ 2068 obj = amdgpu_fb->obj; 2069 rbo = gem_to_amdgpu_bo(obj); 2070 r = amdgpu_bo_reserve(rbo, false); 2071 if (unlikely(r != 0)) 2072 return r; 2073 2074 if (atomic) { 2075 fb_location = amdgpu_bo_gpu_offset(rbo); 2076 } else { 2077 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2078 if (unlikely(r != 0)) { 2079 amdgpu_bo_unreserve(rbo); 2080 return -EINVAL; 2081 } 2082 } 2083 2084 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2085 amdgpu_bo_unreserve(rbo); 2086 2087 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2088 2089 switch (target_fb->pixel_format) { 2090 case DRM_FORMAT_C8: 2091 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2092 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2093 break; 2094 case DRM_FORMAT_XRGB4444: 2095 case DRM_FORMAT_ARGB4444: 2096 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2097 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2098 #ifdef __BIG_ENDIAN 2099 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2100 ENDIAN_8IN16); 2101 #endif 2102 break; 2103 case DRM_FORMAT_XRGB1555: 2104 case DRM_FORMAT_ARGB1555: 2105 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2106 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2107 #ifdef __BIG_ENDIAN 2108 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2109 ENDIAN_8IN16); 2110 #endif 2111 break; 2112 case DRM_FORMAT_BGRX5551: 2113 case DRM_FORMAT_BGRA5551: 2114 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2115 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2116 #ifdef __BIG_ENDIAN 2117 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2118 ENDIAN_8IN16); 2119 #endif 2120 break; 2121 case DRM_FORMAT_RGB565: 2122 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2123 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2124 #ifdef __BIG_ENDIAN 2125 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2126 ENDIAN_8IN16); 2127 #endif 2128 break; 2129 case DRM_FORMAT_XRGB8888: 2130 case DRM_FORMAT_ARGB8888: 2131 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2132 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2133 #ifdef __BIG_ENDIAN 2134 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2135 ENDIAN_8IN32); 2136 #endif 2137 break; 2138 case DRM_FORMAT_XRGB2101010: 2139 case DRM_FORMAT_ARGB2101010: 2140 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2142 #ifdef __BIG_ENDIAN 2143 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2144 ENDIAN_8IN32); 2145 #endif 2146 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2147 bypass_lut = true; 2148 break; 2149 case DRM_FORMAT_BGRX1010102: 2150 case DRM_FORMAT_BGRA1010102: 2151 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2153 #ifdef __BIG_ENDIAN 2154 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2155 ENDIAN_8IN32); 2156 #endif 2157 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2158 bypass_lut = true; 2159 break; 2160 default: 2161 format_name = drm_get_format_name(target_fb->pixel_format); 2162 DRM_ERROR("Unsupported screen format %s\n", format_name); 2163 kfree(format_name); 2164 return -EINVAL; 2165 } 2166 2167 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2168 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2169 2170 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2171 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2172 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2173 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2174 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2175 2176 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2177 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2178 ARRAY_2D_TILED_THIN1); 2179 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2180 tile_split); 2181 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2182 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2183 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2184 mtaspect); 2185 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2186 ADDR_SURF_MICRO_TILING_DISPLAY); 2187 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2188 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2189 ARRAY_1D_TILED_THIN1); 2190 } 2191 2192 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2193 pipe_config); 2194 2195 dce_v11_0_vga_enable(crtc, false); 2196 2197 /* Make sure surface address is updated at vertical blank rather than 2198 * horizontal blank 2199 */ 2200 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2201 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2202 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2203 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2204 2205 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2206 upper_32_bits(fb_location)); 2207 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2208 upper_32_bits(fb_location)); 2209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2210 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2211 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2212 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2213 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2214 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2215 2216 /* 2217 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2218 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2219 * retain the full precision throughout the pipeline. 2220 */ 2221 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2222 if (bypass_lut) 2223 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2224 else 2225 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2226 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2227 2228 if (bypass_lut) 2229 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2230 2231 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2232 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2233 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2234 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2235 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2236 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2237 2238 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2239 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2240 2241 dce_v11_0_grph_enable(crtc, true); 2242 2243 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2244 target_fb->height); 2245 2246 x &= ~3; 2247 y &= ~1; 2248 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2249 (x << 16) | y); 2250 viewport_w = crtc->mode.hdisplay; 2251 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2252 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2253 (viewport_w << 16) | viewport_h); 2254 2255 /* set pageflip to happen only at start of vblank interval (front porch) */ 2256 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2257 2258 if (!atomic && fb && fb != crtc->primary->fb) { 2259 amdgpu_fb = to_amdgpu_framebuffer(fb); 2260 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2261 r = amdgpu_bo_reserve(rbo, false); 2262 if (unlikely(r != 0)) 2263 return r; 2264 amdgpu_bo_unpin(rbo); 2265 amdgpu_bo_unreserve(rbo); 2266 } 2267 2268 /* Bytes per pixel may have changed */ 2269 dce_v11_0_bandwidth_update(adev); 2270 2271 return 0; 2272 } 2273 2274 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2275 struct drm_display_mode *mode) 2276 { 2277 struct drm_device *dev = crtc->dev; 2278 struct amdgpu_device *adev = dev->dev_private; 2279 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2280 u32 tmp; 2281 2282 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2283 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2284 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2285 else 2286 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2287 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2288 } 2289 2290 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2291 { 2292 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2293 struct drm_device *dev = crtc->dev; 2294 struct amdgpu_device *adev = dev->dev_private; 2295 int i; 2296 u32 tmp; 2297 2298 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2299 2300 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2301 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2302 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2303 2304 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2305 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2306 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2307 2308 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2309 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2310 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2311 2312 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2313 2314 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2315 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2316 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2317 2318 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2319 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2320 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2321 2322 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2323 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2324 2325 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2326 for (i = 0; i < 256; i++) { 2327 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2328 (amdgpu_crtc->lut_r[i] << 20) | 2329 (amdgpu_crtc->lut_g[i] << 10) | 2330 (amdgpu_crtc->lut_b[i] << 0)); 2331 } 2332 2333 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2334 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2335 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2336 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2337 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2338 2339 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2340 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2341 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2342 2343 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2344 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2345 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2346 2347 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2348 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2349 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2350 2351 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2352 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2353 /* XXX this only needs to be programmed once per crtc at startup, 2354 * not sure where the best place for it is 2355 */ 2356 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2357 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2358 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2359 } 2360 2361 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2362 { 2363 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2364 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2365 2366 switch (amdgpu_encoder->encoder_id) { 2367 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2368 if (dig->linkb) 2369 return 1; 2370 else 2371 return 0; 2372 break; 2373 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2374 if (dig->linkb) 2375 return 3; 2376 else 2377 return 2; 2378 break; 2379 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2380 if (dig->linkb) 2381 return 5; 2382 else 2383 return 4; 2384 break; 2385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2386 return 6; 2387 break; 2388 default: 2389 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2390 return 0; 2391 } 2392 } 2393 2394 /** 2395 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2396 * 2397 * @crtc: drm crtc 2398 * 2399 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2400 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2401 * monitors a dedicated PPLL must be used. If a particular board has 2402 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2403 * as there is no need to program the PLL itself. If we are not able to 2404 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2405 * avoid messing up an existing monitor. 2406 * 2407 * Asic specific PLL information 2408 * 2409 * DCE 10.x 2410 * Tonga 2411 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2412 * CI 2413 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2414 * 2415 */ 2416 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2417 { 2418 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2419 struct drm_device *dev = crtc->dev; 2420 struct amdgpu_device *adev = dev->dev_private; 2421 u32 pll_in_use; 2422 int pll; 2423 2424 if ((adev->asic_type == CHIP_POLARIS10) || 2425 (adev->asic_type == CHIP_POLARIS11)) { 2426 struct amdgpu_encoder *amdgpu_encoder = 2427 to_amdgpu_encoder(amdgpu_crtc->encoder); 2428 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2429 2430 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2431 return ATOM_DP_DTO; 2432 2433 switch (amdgpu_encoder->encoder_id) { 2434 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2435 if (dig->linkb) 2436 return ATOM_COMBOPHY_PLL1; 2437 else 2438 return ATOM_COMBOPHY_PLL0; 2439 break; 2440 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2441 if (dig->linkb) 2442 return ATOM_COMBOPHY_PLL3; 2443 else 2444 return ATOM_COMBOPHY_PLL2; 2445 break; 2446 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2447 if (dig->linkb) 2448 return ATOM_COMBOPHY_PLL5; 2449 else 2450 return ATOM_COMBOPHY_PLL4; 2451 break; 2452 default: 2453 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2454 return ATOM_PPLL_INVALID; 2455 } 2456 } 2457 2458 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2459 if (adev->clock.dp_extclk) 2460 /* skip PPLL programming if using ext clock */ 2461 return ATOM_PPLL_INVALID; 2462 else { 2463 /* use the same PPLL for all DP monitors */ 2464 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2465 if (pll != ATOM_PPLL_INVALID) 2466 return pll; 2467 } 2468 } else { 2469 /* use the same PPLL for all monitors with the same clock */ 2470 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2471 if (pll != ATOM_PPLL_INVALID) 2472 return pll; 2473 } 2474 2475 /* XXX need to determine what plls are available on each DCE11 part */ 2476 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2477 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2478 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2479 return ATOM_PPLL1; 2480 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2481 return ATOM_PPLL0; 2482 DRM_ERROR("unable to allocate a PPLL\n"); 2483 return ATOM_PPLL_INVALID; 2484 } else { 2485 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2486 return ATOM_PPLL2; 2487 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2488 return ATOM_PPLL1; 2489 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2490 return ATOM_PPLL0; 2491 DRM_ERROR("unable to allocate a PPLL\n"); 2492 return ATOM_PPLL_INVALID; 2493 } 2494 return ATOM_PPLL_INVALID; 2495 } 2496 2497 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2498 { 2499 struct amdgpu_device *adev = crtc->dev->dev_private; 2500 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2501 uint32_t cur_lock; 2502 2503 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2504 if (lock) 2505 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2506 else 2507 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2508 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2509 } 2510 2511 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2512 { 2513 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2514 struct amdgpu_device *adev = crtc->dev->dev_private; 2515 u32 tmp; 2516 2517 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2518 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2519 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2520 } 2521 2522 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2523 { 2524 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2525 struct amdgpu_device *adev = crtc->dev->dev_private; 2526 u32 tmp; 2527 2528 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2529 upper_32_bits(amdgpu_crtc->cursor_addr)); 2530 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2531 lower_32_bits(amdgpu_crtc->cursor_addr)); 2532 2533 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2534 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2535 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2536 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2537 } 2538 2539 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2540 int x, int y) 2541 { 2542 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2543 struct amdgpu_device *adev = crtc->dev->dev_private; 2544 int xorigin = 0, yorigin = 0; 2545 2546 /* avivo cursor are offset into the total surface */ 2547 x += crtc->x; 2548 y += crtc->y; 2549 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2550 2551 if (x < 0) { 2552 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2553 x = 0; 2554 } 2555 if (y < 0) { 2556 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2557 y = 0; 2558 } 2559 2560 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2561 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2562 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2563 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2564 2565 amdgpu_crtc->cursor_x = x; 2566 amdgpu_crtc->cursor_y = y; 2567 2568 return 0; 2569 } 2570 2571 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2572 int x, int y) 2573 { 2574 int ret; 2575 2576 dce_v11_0_lock_cursor(crtc, true); 2577 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2578 dce_v11_0_lock_cursor(crtc, false); 2579 2580 return ret; 2581 } 2582 2583 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2584 struct drm_file *file_priv, 2585 uint32_t handle, 2586 uint32_t width, 2587 uint32_t height, 2588 int32_t hot_x, 2589 int32_t hot_y) 2590 { 2591 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2592 struct drm_gem_object *obj; 2593 struct amdgpu_bo *aobj; 2594 int ret; 2595 2596 if (!handle) { 2597 /* turn off cursor */ 2598 dce_v11_0_hide_cursor(crtc); 2599 obj = NULL; 2600 goto unpin; 2601 } 2602 2603 if ((width > amdgpu_crtc->max_cursor_width) || 2604 (height > amdgpu_crtc->max_cursor_height)) { 2605 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2606 return -EINVAL; 2607 } 2608 2609 obj = drm_gem_object_lookup(file_priv, handle); 2610 if (!obj) { 2611 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2612 return -ENOENT; 2613 } 2614 2615 aobj = gem_to_amdgpu_bo(obj); 2616 ret = amdgpu_bo_reserve(aobj, false); 2617 if (ret != 0) { 2618 drm_gem_object_unreference_unlocked(obj); 2619 return ret; 2620 } 2621 2622 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2623 amdgpu_bo_unreserve(aobj); 2624 if (ret) { 2625 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2626 drm_gem_object_unreference_unlocked(obj); 2627 return ret; 2628 } 2629 2630 amdgpu_crtc->cursor_width = width; 2631 amdgpu_crtc->cursor_height = height; 2632 2633 dce_v11_0_lock_cursor(crtc, true); 2634 2635 if (hot_x != amdgpu_crtc->cursor_hot_x || 2636 hot_y != amdgpu_crtc->cursor_hot_y) { 2637 int x, y; 2638 2639 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2640 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2641 2642 dce_v11_0_cursor_move_locked(crtc, x, y); 2643 2644 amdgpu_crtc->cursor_hot_x = hot_x; 2645 amdgpu_crtc->cursor_hot_y = hot_y; 2646 } 2647 2648 dce_v11_0_show_cursor(crtc); 2649 dce_v11_0_lock_cursor(crtc, false); 2650 2651 unpin: 2652 if (amdgpu_crtc->cursor_bo) { 2653 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2654 ret = amdgpu_bo_reserve(aobj, false); 2655 if (likely(ret == 0)) { 2656 amdgpu_bo_unpin(aobj); 2657 amdgpu_bo_unreserve(aobj); 2658 } 2659 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2660 } 2661 2662 amdgpu_crtc->cursor_bo = obj; 2663 return 0; 2664 } 2665 2666 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2667 { 2668 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2669 2670 if (amdgpu_crtc->cursor_bo) { 2671 dce_v11_0_lock_cursor(crtc, true); 2672 2673 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2674 amdgpu_crtc->cursor_y); 2675 2676 dce_v11_0_show_cursor(crtc); 2677 2678 dce_v11_0_lock_cursor(crtc, false); 2679 } 2680 } 2681 2682 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2683 u16 *blue, uint32_t size) 2684 { 2685 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2686 int i; 2687 2688 /* userspace palettes are always correct as is */ 2689 for (i = 0; i < size; i++) { 2690 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2691 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2692 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2693 } 2694 dce_v11_0_crtc_load_lut(crtc); 2695 2696 return 0; 2697 } 2698 2699 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2700 { 2701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2702 2703 drm_crtc_cleanup(crtc); 2704 kfree(amdgpu_crtc); 2705 } 2706 2707 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2708 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2709 .cursor_move = dce_v11_0_crtc_cursor_move, 2710 .gamma_set = dce_v11_0_crtc_gamma_set, 2711 .set_config = amdgpu_crtc_set_config, 2712 .destroy = dce_v11_0_crtc_destroy, 2713 .page_flip = amdgpu_crtc_page_flip, 2714 }; 2715 2716 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2717 { 2718 struct drm_device *dev = crtc->dev; 2719 struct amdgpu_device *adev = dev->dev_private; 2720 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2721 unsigned type; 2722 2723 switch (mode) { 2724 case DRM_MODE_DPMS_ON: 2725 amdgpu_crtc->enabled = true; 2726 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2727 dce_v11_0_vga_enable(crtc, true); 2728 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2729 dce_v11_0_vga_enable(crtc, false); 2730 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2731 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2732 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2733 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2734 drm_crtc_vblank_on(crtc); 2735 dce_v11_0_crtc_load_lut(crtc); 2736 break; 2737 case DRM_MODE_DPMS_STANDBY: 2738 case DRM_MODE_DPMS_SUSPEND: 2739 case DRM_MODE_DPMS_OFF: 2740 drm_crtc_vblank_off(crtc); 2741 if (amdgpu_crtc->enabled) { 2742 dce_v11_0_vga_enable(crtc, true); 2743 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2744 dce_v11_0_vga_enable(crtc, false); 2745 } 2746 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2747 amdgpu_crtc->enabled = false; 2748 break; 2749 } 2750 /* adjust pm to dpms */ 2751 amdgpu_pm_compute_clocks(adev); 2752 } 2753 2754 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2755 { 2756 /* disable crtc pair power gating before programming */ 2757 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2758 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2759 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2760 } 2761 2762 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2763 { 2764 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2765 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2766 } 2767 2768 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2769 { 2770 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2771 struct drm_device *dev = crtc->dev; 2772 struct amdgpu_device *adev = dev->dev_private; 2773 struct amdgpu_atom_ss ss; 2774 int i; 2775 2776 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2777 if (crtc->primary->fb) { 2778 int r; 2779 struct amdgpu_framebuffer *amdgpu_fb; 2780 struct amdgpu_bo *rbo; 2781 2782 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2783 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2784 r = amdgpu_bo_reserve(rbo, false); 2785 if (unlikely(r)) 2786 DRM_ERROR("failed to reserve rbo before unpin\n"); 2787 else { 2788 amdgpu_bo_unpin(rbo); 2789 amdgpu_bo_unreserve(rbo); 2790 } 2791 } 2792 /* disable the GRPH */ 2793 dce_v11_0_grph_enable(crtc, false); 2794 2795 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2796 2797 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2798 if (adev->mode_info.crtcs[i] && 2799 adev->mode_info.crtcs[i]->enabled && 2800 i != amdgpu_crtc->crtc_id && 2801 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2802 /* one other crtc is using this pll don't turn 2803 * off the pll 2804 */ 2805 goto done; 2806 } 2807 } 2808 2809 switch (amdgpu_crtc->pll_id) { 2810 case ATOM_PPLL0: 2811 case ATOM_PPLL1: 2812 case ATOM_PPLL2: 2813 /* disable the ppll */ 2814 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2815 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2816 break; 2817 case ATOM_COMBOPHY_PLL0: 2818 case ATOM_COMBOPHY_PLL1: 2819 case ATOM_COMBOPHY_PLL2: 2820 case ATOM_COMBOPHY_PLL3: 2821 case ATOM_COMBOPHY_PLL4: 2822 case ATOM_COMBOPHY_PLL5: 2823 /* disable the ppll */ 2824 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2825 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2826 break; 2827 default: 2828 break; 2829 } 2830 done: 2831 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2832 amdgpu_crtc->adjusted_clock = 0; 2833 amdgpu_crtc->encoder = NULL; 2834 amdgpu_crtc->connector = NULL; 2835 } 2836 2837 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2838 struct drm_display_mode *mode, 2839 struct drm_display_mode *adjusted_mode, 2840 int x, int y, struct drm_framebuffer *old_fb) 2841 { 2842 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2843 struct drm_device *dev = crtc->dev; 2844 struct amdgpu_device *adev = dev->dev_private; 2845 2846 if (!amdgpu_crtc->adjusted_clock) 2847 return -EINVAL; 2848 2849 if ((adev->asic_type == CHIP_POLARIS10) || 2850 (adev->asic_type == CHIP_POLARIS11)) { 2851 struct amdgpu_encoder *amdgpu_encoder = 2852 to_amdgpu_encoder(amdgpu_crtc->encoder); 2853 int encoder_mode = 2854 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2855 2856 /* SetPixelClock calculates the plls and ss values now */ 2857 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2858 amdgpu_crtc->pll_id, 2859 encoder_mode, amdgpu_encoder->encoder_id, 2860 adjusted_mode->clock, 0, 0, 0, 0, 2861 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2862 } else { 2863 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2864 } 2865 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2866 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2867 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2868 amdgpu_atombios_crtc_scaler_setup(crtc); 2869 dce_v11_0_cursor_reset(crtc); 2870 /* update the hw version fpr dpm */ 2871 amdgpu_crtc->hw_mode = *adjusted_mode; 2872 2873 return 0; 2874 } 2875 2876 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2877 const struct drm_display_mode *mode, 2878 struct drm_display_mode *adjusted_mode) 2879 { 2880 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2881 struct drm_device *dev = crtc->dev; 2882 struct drm_encoder *encoder; 2883 2884 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2885 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2886 if (encoder->crtc == crtc) { 2887 amdgpu_crtc->encoder = encoder; 2888 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2889 break; 2890 } 2891 } 2892 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2893 amdgpu_crtc->encoder = NULL; 2894 amdgpu_crtc->connector = NULL; 2895 return false; 2896 } 2897 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2898 return false; 2899 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2900 return false; 2901 /* pick pll */ 2902 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2903 /* if we can't get a PPLL for a non-DP encoder, fail */ 2904 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2905 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2906 return false; 2907 2908 return true; 2909 } 2910 2911 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2912 struct drm_framebuffer *old_fb) 2913 { 2914 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2915 } 2916 2917 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2918 struct drm_framebuffer *fb, 2919 int x, int y, enum mode_set_atomic state) 2920 { 2921 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2922 } 2923 2924 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2925 .dpms = dce_v11_0_crtc_dpms, 2926 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2927 .mode_set = dce_v11_0_crtc_mode_set, 2928 .mode_set_base = dce_v11_0_crtc_set_base, 2929 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2930 .prepare = dce_v11_0_crtc_prepare, 2931 .commit = dce_v11_0_crtc_commit, 2932 .load_lut = dce_v11_0_crtc_load_lut, 2933 .disable = dce_v11_0_crtc_disable, 2934 }; 2935 2936 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2937 { 2938 struct amdgpu_crtc *amdgpu_crtc; 2939 int i; 2940 2941 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2942 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2943 if (amdgpu_crtc == NULL) 2944 return -ENOMEM; 2945 2946 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2947 2948 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2949 amdgpu_crtc->crtc_id = index; 2950 adev->mode_info.crtcs[index] = amdgpu_crtc; 2951 2952 amdgpu_crtc->max_cursor_width = 128; 2953 amdgpu_crtc->max_cursor_height = 128; 2954 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2955 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2956 2957 for (i = 0; i < 256; i++) { 2958 amdgpu_crtc->lut_r[i] = i << 2; 2959 amdgpu_crtc->lut_g[i] = i << 2; 2960 amdgpu_crtc->lut_b[i] = i << 2; 2961 } 2962 2963 switch (amdgpu_crtc->crtc_id) { 2964 case 0: 2965 default: 2966 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2967 break; 2968 case 1: 2969 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2970 break; 2971 case 2: 2972 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2973 break; 2974 case 3: 2975 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2976 break; 2977 case 4: 2978 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2979 break; 2980 case 5: 2981 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2982 break; 2983 } 2984 2985 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2986 amdgpu_crtc->adjusted_clock = 0; 2987 amdgpu_crtc->encoder = NULL; 2988 amdgpu_crtc->connector = NULL; 2989 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2990 2991 return 0; 2992 } 2993 2994 static int dce_v11_0_early_init(void *handle) 2995 { 2996 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2997 2998 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2999 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 3000 3001 dce_v11_0_set_display_funcs(adev); 3002 dce_v11_0_set_irq_funcs(adev); 3003 3004 switch (adev->asic_type) { 3005 case CHIP_CARRIZO: 3006 adev->mode_info.num_crtc = 3; 3007 adev->mode_info.num_hpd = 6; 3008 adev->mode_info.num_dig = 9; 3009 break; 3010 case CHIP_STONEY: 3011 adev->mode_info.num_crtc = 2; 3012 adev->mode_info.num_hpd = 6; 3013 adev->mode_info.num_dig = 9; 3014 break; 3015 case CHIP_POLARIS10: 3016 adev->mode_info.num_crtc = 6; 3017 adev->mode_info.num_hpd = 6; 3018 adev->mode_info.num_dig = 6; 3019 break; 3020 case CHIP_POLARIS11: 3021 adev->mode_info.num_crtc = 5; 3022 adev->mode_info.num_hpd = 5; 3023 adev->mode_info.num_dig = 5; 3024 break; 3025 default: 3026 /* FIXME: not supported yet */ 3027 return -EINVAL; 3028 } 3029 3030 return 0; 3031 } 3032 3033 static int dce_v11_0_sw_init(void *handle) 3034 { 3035 int r, i; 3036 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3037 3038 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3039 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 3040 if (r) 3041 return r; 3042 } 3043 3044 for (i = 8; i < 20; i += 2) { 3045 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 3046 if (r) 3047 return r; 3048 } 3049 3050 /* HPD hotplug */ 3051 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 3052 if (r) 3053 return r; 3054 3055 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 3056 3057 adev->ddev->mode_config.async_page_flip = true; 3058 3059 adev->ddev->mode_config.max_width = 16384; 3060 adev->ddev->mode_config.max_height = 16384; 3061 3062 adev->ddev->mode_config.preferred_depth = 24; 3063 adev->ddev->mode_config.prefer_shadow = 1; 3064 3065 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 3066 3067 r = amdgpu_modeset_create_props(adev); 3068 if (r) 3069 return r; 3070 3071 adev->ddev->mode_config.max_width = 16384; 3072 adev->ddev->mode_config.max_height = 16384; 3073 3074 3075 /* allocate crtcs */ 3076 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3077 r = dce_v11_0_crtc_init(adev, i); 3078 if (r) 3079 return r; 3080 } 3081 3082 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3083 amdgpu_print_display_setup(adev->ddev); 3084 else 3085 return -EINVAL; 3086 3087 /* setup afmt */ 3088 r = dce_v11_0_afmt_init(adev); 3089 if (r) 3090 return r; 3091 3092 r = dce_v11_0_audio_init(adev); 3093 if (r) 3094 return r; 3095 3096 drm_kms_helper_poll_init(adev->ddev); 3097 3098 adev->mode_info.mode_config_initialized = true; 3099 return 0; 3100 } 3101 3102 static int dce_v11_0_sw_fini(void *handle) 3103 { 3104 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3105 3106 kfree(adev->mode_info.bios_hardcoded_edid); 3107 3108 drm_kms_helper_poll_fini(adev->ddev); 3109 3110 dce_v11_0_audio_fini(adev); 3111 3112 dce_v11_0_afmt_fini(adev); 3113 3114 adev->mode_info.mode_config_initialized = false; 3115 3116 return 0; 3117 } 3118 3119 static int dce_v11_0_hw_init(void *handle) 3120 { 3121 int i; 3122 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3123 3124 dce_v11_0_init_golden_registers(adev); 3125 3126 /* init dig PHYs, disp eng pll */ 3127 amdgpu_atombios_crtc_powergate_init(adev); 3128 amdgpu_atombios_encoder_init_dig(adev); 3129 if ((adev->asic_type == CHIP_POLARIS10) || 3130 (adev->asic_type == CHIP_POLARIS11)) { 3131 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 3132 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 3133 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 3134 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 3135 } else { 3136 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3137 } 3138 3139 /* initialize hpd */ 3140 dce_v11_0_hpd_init(adev); 3141 3142 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3143 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3144 } 3145 3146 dce_v11_0_pageflip_interrupt_init(adev); 3147 3148 return 0; 3149 } 3150 3151 static int dce_v11_0_hw_fini(void *handle) 3152 { 3153 int i; 3154 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3155 3156 dce_v11_0_hpd_fini(adev); 3157 3158 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3159 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3160 } 3161 3162 dce_v11_0_pageflip_interrupt_fini(adev); 3163 3164 return 0; 3165 } 3166 3167 static int dce_v11_0_suspend(void *handle) 3168 { 3169 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3170 3171 amdgpu_atombios_scratch_regs_save(adev); 3172 3173 return dce_v11_0_hw_fini(handle); 3174 } 3175 3176 static int dce_v11_0_resume(void *handle) 3177 { 3178 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3179 int ret; 3180 3181 ret = dce_v11_0_hw_init(handle); 3182 3183 amdgpu_atombios_scratch_regs_restore(adev); 3184 3185 /* turn on the BL */ 3186 if (adev->mode_info.bl_encoder) { 3187 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3188 adev->mode_info.bl_encoder); 3189 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3190 bl_level); 3191 } 3192 3193 return ret; 3194 } 3195 3196 static bool dce_v11_0_is_idle(void *handle) 3197 { 3198 return true; 3199 } 3200 3201 static int dce_v11_0_wait_for_idle(void *handle) 3202 { 3203 return 0; 3204 } 3205 3206 static int dce_v11_0_soft_reset(void *handle) 3207 { 3208 u32 srbm_soft_reset = 0, tmp; 3209 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3210 3211 if (dce_v11_0_is_display_hung(adev)) 3212 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3213 3214 if (srbm_soft_reset) { 3215 tmp = RREG32(mmSRBM_SOFT_RESET); 3216 tmp |= srbm_soft_reset; 3217 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3218 WREG32(mmSRBM_SOFT_RESET, tmp); 3219 tmp = RREG32(mmSRBM_SOFT_RESET); 3220 3221 udelay(50); 3222 3223 tmp &= ~srbm_soft_reset; 3224 WREG32(mmSRBM_SOFT_RESET, tmp); 3225 tmp = RREG32(mmSRBM_SOFT_RESET); 3226 3227 /* Wait a little for things to settle down */ 3228 udelay(50); 3229 } 3230 return 0; 3231 } 3232 3233 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3234 int crtc, 3235 enum amdgpu_interrupt_state state) 3236 { 3237 u32 lb_interrupt_mask; 3238 3239 if (crtc >= adev->mode_info.num_crtc) { 3240 DRM_DEBUG("invalid crtc %d\n", crtc); 3241 return; 3242 } 3243 3244 switch (state) { 3245 case AMDGPU_IRQ_STATE_DISABLE: 3246 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3247 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3248 VBLANK_INTERRUPT_MASK, 0); 3249 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3250 break; 3251 case AMDGPU_IRQ_STATE_ENABLE: 3252 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3253 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3254 VBLANK_INTERRUPT_MASK, 1); 3255 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3256 break; 3257 default: 3258 break; 3259 } 3260 } 3261 3262 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3263 int crtc, 3264 enum amdgpu_interrupt_state state) 3265 { 3266 u32 lb_interrupt_mask; 3267 3268 if (crtc >= adev->mode_info.num_crtc) { 3269 DRM_DEBUG("invalid crtc %d\n", crtc); 3270 return; 3271 } 3272 3273 switch (state) { 3274 case AMDGPU_IRQ_STATE_DISABLE: 3275 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3276 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3277 VLINE_INTERRUPT_MASK, 0); 3278 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3279 break; 3280 case AMDGPU_IRQ_STATE_ENABLE: 3281 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3282 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3283 VLINE_INTERRUPT_MASK, 1); 3284 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3285 break; 3286 default: 3287 break; 3288 } 3289 } 3290 3291 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3292 struct amdgpu_irq_src *source, 3293 unsigned hpd, 3294 enum amdgpu_interrupt_state state) 3295 { 3296 u32 tmp; 3297 3298 if (hpd >= adev->mode_info.num_hpd) { 3299 DRM_DEBUG("invalid hdp %d\n", hpd); 3300 return 0; 3301 } 3302 3303 switch (state) { 3304 case AMDGPU_IRQ_STATE_DISABLE: 3305 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3306 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3307 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3308 break; 3309 case AMDGPU_IRQ_STATE_ENABLE: 3310 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3311 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3312 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3313 break; 3314 default: 3315 break; 3316 } 3317 3318 return 0; 3319 } 3320 3321 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3322 struct amdgpu_irq_src *source, 3323 unsigned type, 3324 enum amdgpu_interrupt_state state) 3325 { 3326 switch (type) { 3327 case AMDGPU_CRTC_IRQ_VBLANK1: 3328 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3329 break; 3330 case AMDGPU_CRTC_IRQ_VBLANK2: 3331 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3332 break; 3333 case AMDGPU_CRTC_IRQ_VBLANK3: 3334 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3335 break; 3336 case AMDGPU_CRTC_IRQ_VBLANK4: 3337 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3338 break; 3339 case AMDGPU_CRTC_IRQ_VBLANK5: 3340 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3341 break; 3342 case AMDGPU_CRTC_IRQ_VBLANK6: 3343 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3344 break; 3345 case AMDGPU_CRTC_IRQ_VLINE1: 3346 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3347 break; 3348 case AMDGPU_CRTC_IRQ_VLINE2: 3349 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3350 break; 3351 case AMDGPU_CRTC_IRQ_VLINE3: 3352 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3353 break; 3354 case AMDGPU_CRTC_IRQ_VLINE4: 3355 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3356 break; 3357 case AMDGPU_CRTC_IRQ_VLINE5: 3358 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3359 break; 3360 case AMDGPU_CRTC_IRQ_VLINE6: 3361 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3362 break; 3363 default: 3364 break; 3365 } 3366 return 0; 3367 } 3368 3369 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3370 struct amdgpu_irq_src *src, 3371 unsigned type, 3372 enum amdgpu_interrupt_state state) 3373 { 3374 u32 reg; 3375 3376 if (type >= adev->mode_info.num_crtc) { 3377 DRM_ERROR("invalid pageflip crtc %d\n", type); 3378 return -EINVAL; 3379 } 3380 3381 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3382 if (state == AMDGPU_IRQ_STATE_DISABLE) 3383 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3384 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3385 else 3386 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3387 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3388 3389 return 0; 3390 } 3391 3392 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3393 struct amdgpu_irq_src *source, 3394 struct amdgpu_iv_entry *entry) 3395 { 3396 unsigned long flags; 3397 unsigned crtc_id; 3398 struct amdgpu_crtc *amdgpu_crtc; 3399 struct amdgpu_flip_work *works; 3400 3401 crtc_id = (entry->src_id - 8) >> 1; 3402 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3403 3404 if (crtc_id >= adev->mode_info.num_crtc) { 3405 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3406 return -EINVAL; 3407 } 3408 3409 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3410 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3411 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3412 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3413 3414 /* IRQ could occur when in initial stage */ 3415 if(amdgpu_crtc == NULL) 3416 return 0; 3417 3418 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3419 works = amdgpu_crtc->pflip_works; 3420 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3421 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3422 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3423 amdgpu_crtc->pflip_status, 3424 AMDGPU_FLIP_SUBMITTED); 3425 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3426 return 0; 3427 } 3428 3429 /* page flip completed. clean up */ 3430 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3431 amdgpu_crtc->pflip_works = NULL; 3432 3433 /* wakeup usersapce */ 3434 if(works->event) 3435 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3436 3437 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3438 3439 drm_crtc_vblank_put(&amdgpu_crtc->base); 3440 schedule_work(&works->unpin_work); 3441 3442 return 0; 3443 } 3444 3445 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3446 int hpd) 3447 { 3448 u32 tmp; 3449 3450 if (hpd >= adev->mode_info.num_hpd) { 3451 DRM_DEBUG("invalid hdp %d\n", hpd); 3452 return; 3453 } 3454 3455 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3456 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3457 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3458 } 3459 3460 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3461 int crtc) 3462 { 3463 u32 tmp; 3464 3465 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3466 DRM_DEBUG("invalid crtc %d\n", crtc); 3467 return; 3468 } 3469 3470 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3471 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3472 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3473 } 3474 3475 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3476 int crtc) 3477 { 3478 u32 tmp; 3479 3480 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3481 DRM_DEBUG("invalid crtc %d\n", crtc); 3482 return; 3483 } 3484 3485 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3486 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3487 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3488 } 3489 3490 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3491 struct amdgpu_irq_src *source, 3492 struct amdgpu_iv_entry *entry) 3493 { 3494 unsigned crtc = entry->src_id - 1; 3495 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3496 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3497 3498 switch (entry->src_data) { 3499 case 0: /* vblank */ 3500 if (disp_int & interrupt_status_offsets[crtc].vblank) 3501 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3502 else 3503 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3504 3505 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3506 drm_handle_vblank(adev->ddev, crtc); 3507 } 3508 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3509 3510 break; 3511 case 1: /* vline */ 3512 if (disp_int & interrupt_status_offsets[crtc].vline) 3513 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3514 else 3515 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3516 3517 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3518 3519 break; 3520 default: 3521 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3522 break; 3523 } 3524 3525 return 0; 3526 } 3527 3528 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3529 struct amdgpu_irq_src *source, 3530 struct amdgpu_iv_entry *entry) 3531 { 3532 uint32_t disp_int, mask; 3533 unsigned hpd; 3534 3535 if (entry->src_data >= adev->mode_info.num_hpd) { 3536 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3537 return 0; 3538 } 3539 3540 hpd = entry->src_data; 3541 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3542 mask = interrupt_status_offsets[hpd].hpd; 3543 3544 if (disp_int & mask) { 3545 dce_v11_0_hpd_int_ack(adev, hpd); 3546 schedule_work(&adev->hotplug_work); 3547 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3548 } 3549 3550 return 0; 3551 } 3552 3553 static int dce_v11_0_set_clockgating_state(void *handle, 3554 enum amd_clockgating_state state) 3555 { 3556 return 0; 3557 } 3558 3559 static int dce_v11_0_set_powergating_state(void *handle, 3560 enum amd_powergating_state state) 3561 { 3562 return 0; 3563 } 3564 3565 const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3566 .name = "dce_v11_0", 3567 .early_init = dce_v11_0_early_init, 3568 .late_init = NULL, 3569 .sw_init = dce_v11_0_sw_init, 3570 .sw_fini = dce_v11_0_sw_fini, 3571 .hw_init = dce_v11_0_hw_init, 3572 .hw_fini = dce_v11_0_hw_fini, 3573 .suspend = dce_v11_0_suspend, 3574 .resume = dce_v11_0_resume, 3575 .is_idle = dce_v11_0_is_idle, 3576 .wait_for_idle = dce_v11_0_wait_for_idle, 3577 .soft_reset = dce_v11_0_soft_reset, 3578 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3579 .set_powergating_state = dce_v11_0_set_powergating_state, 3580 }; 3581 3582 static void 3583 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3584 struct drm_display_mode *mode, 3585 struct drm_display_mode *adjusted_mode) 3586 { 3587 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3588 3589 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3590 3591 /* need to call this here rather than in prepare() since we need some crtc info */ 3592 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3593 3594 /* set scaler clears this on some chips */ 3595 dce_v11_0_set_interleave(encoder->crtc, mode); 3596 3597 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3598 dce_v11_0_afmt_enable(encoder, true); 3599 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3600 } 3601 } 3602 3603 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3604 { 3605 struct amdgpu_device *adev = encoder->dev->dev_private; 3606 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3607 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3608 3609 if ((amdgpu_encoder->active_device & 3610 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3611 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3612 ENCODER_OBJECT_ID_NONE)) { 3613 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3614 if (dig) { 3615 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3616 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3617 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3618 } 3619 } 3620 3621 amdgpu_atombios_scratch_regs_lock(adev, true); 3622 3623 if (connector) { 3624 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3625 3626 /* select the clock/data port if it uses a router */ 3627 if (amdgpu_connector->router.cd_valid) 3628 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3629 3630 /* turn eDP panel on for mode set */ 3631 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3632 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3633 ATOM_TRANSMITTER_ACTION_POWER_ON); 3634 } 3635 3636 /* this is needed for the pll/ss setup to work correctly in some cases */ 3637 amdgpu_atombios_encoder_set_crtc_source(encoder); 3638 /* set up the FMT blocks */ 3639 dce_v11_0_program_fmt(encoder); 3640 } 3641 3642 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3643 { 3644 struct drm_device *dev = encoder->dev; 3645 struct amdgpu_device *adev = dev->dev_private; 3646 3647 /* need to call this here as we need the crtc set up */ 3648 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3649 amdgpu_atombios_scratch_regs_lock(adev, false); 3650 } 3651 3652 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3653 { 3654 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3655 struct amdgpu_encoder_atom_dig *dig; 3656 3657 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3658 3659 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3660 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3661 dce_v11_0_afmt_enable(encoder, false); 3662 dig = amdgpu_encoder->enc_priv; 3663 dig->dig_encoder = -1; 3664 } 3665 amdgpu_encoder->active_device = 0; 3666 } 3667 3668 /* these are handled by the primary encoders */ 3669 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3670 { 3671 3672 } 3673 3674 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3675 { 3676 3677 } 3678 3679 static void 3680 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3681 struct drm_display_mode *mode, 3682 struct drm_display_mode *adjusted_mode) 3683 { 3684 3685 } 3686 3687 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3688 { 3689 3690 } 3691 3692 static void 3693 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3694 { 3695 3696 } 3697 3698 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3699 .dpms = dce_v11_0_ext_dpms, 3700 .prepare = dce_v11_0_ext_prepare, 3701 .mode_set = dce_v11_0_ext_mode_set, 3702 .commit = dce_v11_0_ext_commit, 3703 .disable = dce_v11_0_ext_disable, 3704 /* no detect for TMDS/LVDS yet */ 3705 }; 3706 3707 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3708 .dpms = amdgpu_atombios_encoder_dpms, 3709 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3710 .prepare = dce_v11_0_encoder_prepare, 3711 .mode_set = dce_v11_0_encoder_mode_set, 3712 .commit = dce_v11_0_encoder_commit, 3713 .disable = dce_v11_0_encoder_disable, 3714 .detect = amdgpu_atombios_encoder_dig_detect, 3715 }; 3716 3717 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3718 .dpms = amdgpu_atombios_encoder_dpms, 3719 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3720 .prepare = dce_v11_0_encoder_prepare, 3721 .mode_set = dce_v11_0_encoder_mode_set, 3722 .commit = dce_v11_0_encoder_commit, 3723 .detect = amdgpu_atombios_encoder_dac_detect, 3724 }; 3725 3726 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3727 { 3728 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3729 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3730 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3731 kfree(amdgpu_encoder->enc_priv); 3732 drm_encoder_cleanup(encoder); 3733 kfree(amdgpu_encoder); 3734 } 3735 3736 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3737 .destroy = dce_v11_0_encoder_destroy, 3738 }; 3739 3740 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3741 uint32_t encoder_enum, 3742 uint32_t supported_device, 3743 u16 caps) 3744 { 3745 struct drm_device *dev = adev->ddev; 3746 struct drm_encoder *encoder; 3747 struct amdgpu_encoder *amdgpu_encoder; 3748 3749 /* see if we already added it */ 3750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3751 amdgpu_encoder = to_amdgpu_encoder(encoder); 3752 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3753 amdgpu_encoder->devices |= supported_device; 3754 return; 3755 } 3756 3757 } 3758 3759 /* add a new one */ 3760 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3761 if (!amdgpu_encoder) 3762 return; 3763 3764 encoder = &amdgpu_encoder->base; 3765 switch (adev->mode_info.num_crtc) { 3766 case 1: 3767 encoder->possible_crtcs = 0x1; 3768 break; 3769 case 2: 3770 default: 3771 encoder->possible_crtcs = 0x3; 3772 break; 3773 case 4: 3774 encoder->possible_crtcs = 0xf; 3775 break; 3776 case 6: 3777 encoder->possible_crtcs = 0x3f; 3778 break; 3779 } 3780 3781 amdgpu_encoder->enc_priv = NULL; 3782 3783 amdgpu_encoder->encoder_enum = encoder_enum; 3784 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3785 amdgpu_encoder->devices = supported_device; 3786 amdgpu_encoder->rmx_type = RMX_OFF; 3787 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3788 amdgpu_encoder->is_ext_encoder = false; 3789 amdgpu_encoder->caps = caps; 3790 3791 switch (amdgpu_encoder->encoder_id) { 3792 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3793 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3794 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3795 DRM_MODE_ENCODER_DAC, NULL); 3796 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3797 break; 3798 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3799 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3800 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3801 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3802 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3803 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3804 amdgpu_encoder->rmx_type = RMX_FULL; 3805 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3806 DRM_MODE_ENCODER_LVDS, NULL); 3807 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3808 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3809 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3810 DRM_MODE_ENCODER_DAC, NULL); 3811 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3812 } else { 3813 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3814 DRM_MODE_ENCODER_TMDS, NULL); 3815 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3816 } 3817 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3818 break; 3819 case ENCODER_OBJECT_ID_SI170B: 3820 case ENCODER_OBJECT_ID_CH7303: 3821 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3822 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3823 case ENCODER_OBJECT_ID_TITFP513: 3824 case ENCODER_OBJECT_ID_VT1623: 3825 case ENCODER_OBJECT_ID_HDMI_SI1930: 3826 case ENCODER_OBJECT_ID_TRAVIS: 3827 case ENCODER_OBJECT_ID_NUTMEG: 3828 /* these are handled by the primary encoders */ 3829 amdgpu_encoder->is_ext_encoder = true; 3830 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3831 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3832 DRM_MODE_ENCODER_LVDS, NULL); 3833 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3834 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3835 DRM_MODE_ENCODER_DAC, NULL); 3836 else 3837 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3838 DRM_MODE_ENCODER_TMDS, NULL); 3839 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3840 break; 3841 } 3842 } 3843 3844 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3845 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3846 .bandwidth_update = &dce_v11_0_bandwidth_update, 3847 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3848 .vblank_wait = &dce_v11_0_vblank_wait, 3849 .is_display_hung = &dce_v11_0_is_display_hung, 3850 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3851 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3852 .hpd_sense = &dce_v11_0_hpd_sense, 3853 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3854 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3855 .page_flip = &dce_v11_0_page_flip, 3856 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3857 .add_encoder = &dce_v11_0_encoder_add, 3858 .add_connector = &amdgpu_connector_add, 3859 .stop_mc_access = &dce_v11_0_stop_mc_access, 3860 .resume_mc_access = &dce_v11_0_resume_mc_access, 3861 }; 3862 3863 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3864 { 3865 if (adev->mode_info.funcs == NULL) 3866 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3867 } 3868 3869 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3870 .set = dce_v11_0_set_crtc_irq_state, 3871 .process = dce_v11_0_crtc_irq, 3872 }; 3873 3874 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3875 .set = dce_v11_0_set_pageflip_irq_state, 3876 .process = dce_v11_0_pageflip_irq, 3877 }; 3878 3879 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3880 .set = dce_v11_0_set_hpd_irq_state, 3881 .process = dce_v11_0_hpd_irq, 3882 }; 3883 3884 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3885 { 3886 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3887 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3888 3889 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3890 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3891 3892 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3893 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3894 } 3895