1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <drm/drm_fourcc.h> 25 #include <drm/drm_vblank.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_pm.h" 29 #include "amdgpu_i2c.h" 30 #include "vid.h" 31 #include "atom.h" 32 #include "amdgpu_atombios.h" 33 #include "atombios_crtc.h" 34 #include "atombios_encoders.h" 35 #include "amdgpu_pll.h" 36 #include "amdgpu_connectors.h" 37 #include "amdgpu_display.h" 38 #include "dce_v11_0.h" 39 40 #include "dce/dce_11_0_d.h" 41 #include "dce/dce_11_0_sh_mask.h" 42 #include "dce/dce_11_0_enum.h" 43 #include "oss/oss_3_0_d.h" 44 #include "oss/oss_3_0_sh_mask.h" 45 #include "gmc/gmc_8_1_d.h" 46 #include "gmc/gmc_8_1_sh_mask.h" 47 48 #include "ivsrcid/ivsrcid_vislands30.h" 49 50 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 51 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 52 53 static const u32 crtc_offsets[] = 54 { 55 CRTC0_REGISTER_OFFSET, 56 CRTC1_REGISTER_OFFSET, 57 CRTC2_REGISTER_OFFSET, 58 CRTC3_REGISTER_OFFSET, 59 CRTC4_REGISTER_OFFSET, 60 CRTC5_REGISTER_OFFSET, 61 CRTC6_REGISTER_OFFSET 62 }; 63 64 static const u32 hpd_offsets[] = 65 { 66 HPD0_REGISTER_OFFSET, 67 HPD1_REGISTER_OFFSET, 68 HPD2_REGISTER_OFFSET, 69 HPD3_REGISTER_OFFSET, 70 HPD4_REGISTER_OFFSET, 71 HPD5_REGISTER_OFFSET 72 }; 73 74 static const uint32_t dig_offsets[] = { 75 DIG0_REGISTER_OFFSET, 76 DIG1_REGISTER_OFFSET, 77 DIG2_REGISTER_OFFSET, 78 DIG3_REGISTER_OFFSET, 79 DIG4_REGISTER_OFFSET, 80 DIG5_REGISTER_OFFSET, 81 DIG6_REGISTER_OFFSET, 82 DIG7_REGISTER_OFFSET, 83 DIG8_REGISTER_OFFSET 84 }; 85 86 static const struct { 87 uint32_t reg; 88 uint32_t vblank; 89 uint32_t vline; 90 uint32_t hpd; 91 92 } interrupt_status_offsets[] = { { 93 .reg = mmDISP_INTERRUPT_STATUS, 94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 97 }, { 98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 102 }, { 103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 107 }, { 108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 112 }, { 113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 117 }, { 118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 122 } }; 123 124 static const u32 cz_golden_settings_a11[] = 125 { 126 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 127 mmFBC_MISC, 0x1f311fff, 0x14300000, 128 }; 129 130 static const u32 cz_mgcg_cgcg_init[] = 131 { 132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 134 }; 135 136 static const u32 stoney_golden_settings_a11[] = 137 { 138 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 139 mmFBC_MISC, 0x1f311fff, 0x14302000, 140 }; 141 142 static const u32 polaris11_golden_settings_a11[] = 143 { 144 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 145 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 146 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 147 mmFBC_MISC, 0x9f313fff, 0x14302008, 148 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 149 }; 150 151 static const u32 polaris10_golden_settings_a11[] = 152 { 153 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 154 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 155 mmFBC_MISC, 0x9f313fff, 0x14302008, 156 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 157 }; 158 159 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 160 { 161 switch (adev->asic_type) { 162 case CHIP_CARRIZO: 163 amdgpu_device_program_register_sequence(adev, 164 cz_mgcg_cgcg_init, 165 ARRAY_SIZE(cz_mgcg_cgcg_init)); 166 amdgpu_device_program_register_sequence(adev, 167 cz_golden_settings_a11, 168 ARRAY_SIZE(cz_golden_settings_a11)); 169 break; 170 case CHIP_STONEY: 171 amdgpu_device_program_register_sequence(adev, 172 stoney_golden_settings_a11, 173 ARRAY_SIZE(stoney_golden_settings_a11)); 174 break; 175 case CHIP_POLARIS11: 176 case CHIP_POLARIS12: 177 amdgpu_device_program_register_sequence(adev, 178 polaris11_golden_settings_a11, 179 ARRAY_SIZE(polaris11_golden_settings_a11)); 180 break; 181 case CHIP_POLARIS10: 182 case CHIP_VEGAM: 183 amdgpu_device_program_register_sequence(adev, 184 polaris10_golden_settings_a11, 185 ARRAY_SIZE(polaris10_golden_settings_a11)); 186 break; 187 default: 188 break; 189 } 190 } 191 192 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 193 u32 block_offset, u32 reg) 194 { 195 unsigned long flags; 196 u32 r; 197 198 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 200 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 201 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 202 203 return r; 204 } 205 206 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 207 u32 block_offset, u32 reg, u32 v) 208 { 209 unsigned long flags; 210 211 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 212 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 213 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 214 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 215 } 216 217 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 218 { 219 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 220 return 0; 221 else 222 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 223 } 224 225 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 226 { 227 unsigned i; 228 229 /* Enable pflip interrupts */ 230 for (i = 0; i < adev->mode_info.num_crtc; i++) 231 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 232 } 233 234 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 235 { 236 unsigned i; 237 238 /* Disable pflip interrupts */ 239 for (i = 0; i < adev->mode_info.num_crtc; i++) 240 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 241 } 242 243 /** 244 * dce_v11_0_page_flip - pageflip callback. 245 * 246 * @adev: amdgpu_device pointer 247 * @crtc_id: crtc to cleanup pageflip on 248 * @crtc_base: new address of the crtc (GPU MC address) 249 * 250 * Triggers the actual pageflip by updating the primary 251 * surface base address. 252 */ 253 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 254 int crtc_id, u64 crtc_base, bool async) 255 { 256 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 257 u32 tmp; 258 259 /* flip immediate for async, default is vsync */ 260 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 261 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 262 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 263 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 264 /* update the scanout addresses */ 265 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 266 upper_32_bits(crtc_base)); 267 /* writing to the low address triggers the update */ 268 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 269 lower_32_bits(crtc_base)); 270 /* post the write */ 271 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 272 } 273 274 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 275 u32 *vbl, u32 *position) 276 { 277 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 278 return -EINVAL; 279 280 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 281 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 282 283 return 0; 284 } 285 286 /** 287 * dce_v11_0_hpd_sense - hpd sense callback. 288 * 289 * @adev: amdgpu_device pointer 290 * @hpd: hpd (hotplug detect) pin 291 * 292 * Checks if a digital monitor is connected (evergreen+). 293 * Returns true if connected, false if not connected. 294 */ 295 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 296 enum amdgpu_hpd_id hpd) 297 { 298 bool connected = false; 299 300 if (hpd >= adev->mode_info.num_hpd) 301 return connected; 302 303 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 304 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 305 connected = true; 306 307 return connected; 308 } 309 310 /** 311 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 312 * 313 * @adev: amdgpu_device pointer 314 * @hpd: hpd (hotplug detect) pin 315 * 316 * Set the polarity of the hpd pin (evergreen+). 317 */ 318 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 319 enum amdgpu_hpd_id hpd) 320 { 321 u32 tmp; 322 bool connected = dce_v11_0_hpd_sense(adev, hpd); 323 324 if (hpd >= adev->mode_info.num_hpd) 325 return; 326 327 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 328 if (connected) 329 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 330 else 331 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 332 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 333 } 334 335 /** 336 * dce_v11_0_hpd_init - hpd setup callback. 337 * 338 * @adev: amdgpu_device pointer 339 * 340 * Setup the hpd pins used by the card (evergreen+). 341 * Enable the pin, set the polarity, and enable the hpd interrupts. 342 */ 343 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 344 { 345 struct drm_device *dev = adev->ddev; 346 struct drm_connector *connector; 347 u32 tmp; 348 349 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 350 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 351 352 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 353 continue; 354 355 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 356 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 357 /* don't try to enable hpd on eDP or LVDS avoid breaking the 358 * aux dp channel on imac and help (but not completely fix) 359 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 360 * also avoid interrupt storms during dpms. 361 */ 362 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 363 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 364 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 365 continue; 366 } 367 368 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 369 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 370 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 371 372 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 373 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 374 DC_HPD_CONNECT_INT_DELAY, 375 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 376 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 377 DC_HPD_DISCONNECT_INT_DELAY, 378 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 379 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 380 381 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 382 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 383 } 384 } 385 386 /** 387 * dce_v11_0_hpd_fini - hpd tear down callback. 388 * 389 * @adev: amdgpu_device pointer 390 * 391 * Tear down the hpd pins used by the card (evergreen+). 392 * Disable the hpd interrupts. 393 */ 394 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 395 { 396 struct drm_device *dev = adev->ddev; 397 struct drm_connector *connector; 398 u32 tmp; 399 400 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 401 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 402 403 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 404 continue; 405 406 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 407 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 408 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 409 410 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 411 } 412 } 413 414 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 415 { 416 return mmDC_GPIO_HPD_A; 417 } 418 419 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 420 { 421 u32 crtc_hung = 0; 422 u32 crtc_status[6]; 423 u32 i, j, tmp; 424 425 for (i = 0; i < adev->mode_info.num_crtc; i++) { 426 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 427 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 428 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 429 crtc_hung |= (1 << i); 430 } 431 } 432 433 for (j = 0; j < 10; j++) { 434 for (i = 0; i < adev->mode_info.num_crtc; i++) { 435 if (crtc_hung & (1 << i)) { 436 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 437 if (tmp != crtc_status[i]) 438 crtc_hung &= ~(1 << i); 439 } 440 } 441 if (crtc_hung == 0) 442 return false; 443 udelay(100); 444 } 445 446 return true; 447 } 448 449 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 450 bool render) 451 { 452 u32 tmp; 453 454 /* Lockout access through VGA aperture*/ 455 tmp = RREG32(mmVGA_HDP_CONTROL); 456 if (render) 457 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 458 else 459 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 460 WREG32(mmVGA_HDP_CONTROL, tmp); 461 462 /* disable VGA render */ 463 tmp = RREG32(mmVGA_RENDER_CONTROL); 464 if (render) 465 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 466 else 467 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 468 WREG32(mmVGA_RENDER_CONTROL, tmp); 469 } 470 471 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) 472 { 473 int num_crtc = 0; 474 475 switch (adev->asic_type) { 476 case CHIP_CARRIZO: 477 num_crtc = 3; 478 break; 479 case CHIP_STONEY: 480 num_crtc = 2; 481 break; 482 case CHIP_POLARIS10: 483 case CHIP_VEGAM: 484 num_crtc = 6; 485 break; 486 case CHIP_POLARIS11: 487 case CHIP_POLARIS12: 488 num_crtc = 5; 489 break; 490 default: 491 num_crtc = 0; 492 } 493 return num_crtc; 494 } 495 496 void dce_v11_0_disable_dce(struct amdgpu_device *adev) 497 { 498 /*Disable VGA render and enabled crtc, if has DCE engine*/ 499 if (amdgpu_atombios_has_dce_engine_info(adev)) { 500 u32 tmp; 501 int crtc_enabled, i; 502 503 dce_v11_0_set_vga_render_state(adev, false); 504 505 /*Disable crtc*/ 506 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { 507 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 508 CRTC_CONTROL, CRTC_MASTER_EN); 509 if (crtc_enabled) { 510 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 511 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 512 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 513 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 514 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 515 } 516 } 517 } 518 } 519 520 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 521 { 522 struct drm_device *dev = encoder->dev; 523 struct amdgpu_device *adev = dev->dev_private; 524 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 526 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 527 int bpc = 0; 528 u32 tmp = 0; 529 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 530 531 if (connector) { 532 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 533 bpc = amdgpu_connector_get_monitor_bpc(connector); 534 dither = amdgpu_connector->dither; 535 } 536 537 /* LVDS/eDP FMT is set up by atom */ 538 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 539 return; 540 541 /* not needed for analog */ 542 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 543 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 544 return; 545 546 if (bpc == 0) 547 return; 548 549 switch (bpc) { 550 case 6: 551 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 552 /* XXX sort out optimal dither settings */ 553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 557 } else { 558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 559 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 560 } 561 break; 562 case 8: 563 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 564 /* XXX sort out optimal dither settings */ 565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 570 } else { 571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 573 } 574 break; 575 case 10: 576 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 577 /* XXX sort out optimal dither settings */ 578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 580 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 583 } else { 584 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 585 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 586 } 587 break; 588 default: 589 /* not needed */ 590 break; 591 } 592 593 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 594 } 595 596 597 /* display watermark setup */ 598 /** 599 * dce_v11_0_line_buffer_adjust - Set up the line buffer 600 * 601 * @adev: amdgpu_device pointer 602 * @amdgpu_crtc: the selected display controller 603 * @mode: the current display mode on the selected display 604 * controller 605 * 606 * Setup up the line buffer allocation for 607 * the selected display controller (CIK). 608 * Returns the line buffer size in pixels. 609 */ 610 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 611 struct amdgpu_crtc *amdgpu_crtc, 612 struct drm_display_mode *mode) 613 { 614 u32 tmp, buffer_alloc, i, mem_cfg; 615 u32 pipe_offset = amdgpu_crtc->crtc_id; 616 /* 617 * Line Buffer Setup 618 * There are 6 line buffers, one for each display controllers. 619 * There are 3 partitions per LB. Select the number of partitions 620 * to enable based on the display width. For display widths larger 621 * than 4096, you need use to use 2 display controllers and combine 622 * them using the stereo blender. 623 */ 624 if (amdgpu_crtc->base.enabled && mode) { 625 if (mode->crtc_hdisplay < 1920) { 626 mem_cfg = 1; 627 buffer_alloc = 2; 628 } else if (mode->crtc_hdisplay < 2560) { 629 mem_cfg = 2; 630 buffer_alloc = 2; 631 } else if (mode->crtc_hdisplay < 4096) { 632 mem_cfg = 0; 633 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 634 } else { 635 DRM_DEBUG_KMS("Mode too big for LB!\n"); 636 mem_cfg = 0; 637 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 638 } 639 } else { 640 mem_cfg = 1; 641 buffer_alloc = 0; 642 } 643 644 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 645 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 646 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 647 648 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 649 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 650 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 651 652 for (i = 0; i < adev->usec_timeout; i++) { 653 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 654 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 655 break; 656 udelay(1); 657 } 658 659 if (amdgpu_crtc->base.enabled && mode) { 660 switch (mem_cfg) { 661 case 0: 662 default: 663 return 4096 * 2; 664 case 1: 665 return 1920 * 2; 666 case 2: 667 return 2560 * 2; 668 } 669 } 670 671 /* controller not enabled, so no lb used */ 672 return 0; 673 } 674 675 /** 676 * cik_get_number_of_dram_channels - get the number of dram channels 677 * 678 * @adev: amdgpu_device pointer 679 * 680 * Look up the number of video ram channels (CIK). 681 * Used for display watermark bandwidth calculations 682 * Returns the number of dram channels 683 */ 684 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 685 { 686 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 687 688 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 689 case 0: 690 default: 691 return 1; 692 case 1: 693 return 2; 694 case 2: 695 return 4; 696 case 3: 697 return 8; 698 case 4: 699 return 3; 700 case 5: 701 return 6; 702 case 6: 703 return 10; 704 case 7: 705 return 12; 706 case 8: 707 return 16; 708 } 709 } 710 711 struct dce10_wm_params { 712 u32 dram_channels; /* number of dram channels */ 713 u32 yclk; /* bandwidth per dram data pin in kHz */ 714 u32 sclk; /* engine clock in kHz */ 715 u32 disp_clk; /* display clock in kHz */ 716 u32 src_width; /* viewport width */ 717 u32 active_time; /* active display time in ns */ 718 u32 blank_time; /* blank time in ns */ 719 bool interlaced; /* mode is interlaced */ 720 fixed20_12 vsc; /* vertical scale ratio */ 721 u32 num_heads; /* number of active crtcs */ 722 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 723 u32 lb_size; /* line buffer allocated to pipe */ 724 u32 vtaps; /* vertical scaler taps */ 725 }; 726 727 /** 728 * dce_v11_0_dram_bandwidth - get the dram bandwidth 729 * 730 * @wm: watermark calculation data 731 * 732 * Calculate the raw dram bandwidth (CIK). 733 * Used for display watermark bandwidth calculations 734 * Returns the dram bandwidth in MBytes/s 735 */ 736 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 737 { 738 /* Calculate raw DRAM Bandwidth */ 739 fixed20_12 dram_efficiency; /* 0.7 */ 740 fixed20_12 yclk, dram_channels, bandwidth; 741 fixed20_12 a; 742 743 a.full = dfixed_const(1000); 744 yclk.full = dfixed_const(wm->yclk); 745 yclk.full = dfixed_div(yclk, a); 746 dram_channels.full = dfixed_const(wm->dram_channels * 4); 747 a.full = dfixed_const(10); 748 dram_efficiency.full = dfixed_const(7); 749 dram_efficiency.full = dfixed_div(dram_efficiency, a); 750 bandwidth.full = dfixed_mul(dram_channels, yclk); 751 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 752 753 return dfixed_trunc(bandwidth); 754 } 755 756 /** 757 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 758 * 759 * @wm: watermark calculation data 760 * 761 * Calculate the dram bandwidth used for display (CIK). 762 * Used for display watermark bandwidth calculations 763 * Returns the dram bandwidth for display in MBytes/s 764 */ 765 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 766 { 767 /* Calculate DRAM Bandwidth and the part allocated to display. */ 768 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 769 fixed20_12 yclk, dram_channels, bandwidth; 770 fixed20_12 a; 771 772 a.full = dfixed_const(1000); 773 yclk.full = dfixed_const(wm->yclk); 774 yclk.full = dfixed_div(yclk, a); 775 dram_channels.full = dfixed_const(wm->dram_channels * 4); 776 a.full = dfixed_const(10); 777 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 778 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 779 bandwidth.full = dfixed_mul(dram_channels, yclk); 780 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 781 782 return dfixed_trunc(bandwidth); 783 } 784 785 /** 786 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 787 * 788 * @wm: watermark calculation data 789 * 790 * Calculate the data return bandwidth used for display (CIK). 791 * Used for display watermark bandwidth calculations 792 * Returns the data return bandwidth in MBytes/s 793 */ 794 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 795 { 796 /* Calculate the display Data return Bandwidth */ 797 fixed20_12 return_efficiency; /* 0.8 */ 798 fixed20_12 sclk, bandwidth; 799 fixed20_12 a; 800 801 a.full = dfixed_const(1000); 802 sclk.full = dfixed_const(wm->sclk); 803 sclk.full = dfixed_div(sclk, a); 804 a.full = dfixed_const(10); 805 return_efficiency.full = dfixed_const(8); 806 return_efficiency.full = dfixed_div(return_efficiency, a); 807 a.full = dfixed_const(32); 808 bandwidth.full = dfixed_mul(a, sclk); 809 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 810 811 return dfixed_trunc(bandwidth); 812 } 813 814 /** 815 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 816 * 817 * @wm: watermark calculation data 818 * 819 * Calculate the dmif bandwidth used for display (CIK). 820 * Used for display watermark bandwidth calculations 821 * Returns the dmif bandwidth in MBytes/s 822 */ 823 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 824 { 825 /* Calculate the DMIF Request Bandwidth */ 826 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 827 fixed20_12 disp_clk, bandwidth; 828 fixed20_12 a, b; 829 830 a.full = dfixed_const(1000); 831 disp_clk.full = dfixed_const(wm->disp_clk); 832 disp_clk.full = dfixed_div(disp_clk, a); 833 a.full = dfixed_const(32); 834 b.full = dfixed_mul(a, disp_clk); 835 836 a.full = dfixed_const(10); 837 disp_clk_request_efficiency.full = dfixed_const(8); 838 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 839 840 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 841 842 return dfixed_trunc(bandwidth); 843 } 844 845 /** 846 * dce_v11_0_available_bandwidth - get the min available bandwidth 847 * 848 * @wm: watermark calculation data 849 * 850 * Calculate the min available bandwidth used for display (CIK). 851 * Used for display watermark bandwidth calculations 852 * Returns the min available bandwidth in MBytes/s 853 */ 854 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 855 { 856 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 857 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 858 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 859 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 860 861 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 862 } 863 864 /** 865 * dce_v11_0_average_bandwidth - get the average available bandwidth 866 * 867 * @wm: watermark calculation data 868 * 869 * Calculate the average available bandwidth used for display (CIK). 870 * Used for display watermark bandwidth calculations 871 * Returns the average available bandwidth in MBytes/s 872 */ 873 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 874 { 875 /* Calculate the display mode Average Bandwidth 876 * DisplayMode should contain the source and destination dimensions, 877 * timing, etc. 878 */ 879 fixed20_12 bpp; 880 fixed20_12 line_time; 881 fixed20_12 src_width; 882 fixed20_12 bandwidth; 883 fixed20_12 a; 884 885 a.full = dfixed_const(1000); 886 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 887 line_time.full = dfixed_div(line_time, a); 888 bpp.full = dfixed_const(wm->bytes_per_pixel); 889 src_width.full = dfixed_const(wm->src_width); 890 bandwidth.full = dfixed_mul(src_width, bpp); 891 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 892 bandwidth.full = dfixed_div(bandwidth, line_time); 893 894 return dfixed_trunc(bandwidth); 895 } 896 897 /** 898 * dce_v11_0_latency_watermark - get the latency watermark 899 * 900 * @wm: watermark calculation data 901 * 902 * Calculate the latency watermark (CIK). 903 * Used for display watermark bandwidth calculations 904 * Returns the latency watermark in ns 905 */ 906 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 907 { 908 /* First calculate the latency in ns */ 909 u32 mc_latency = 2000; /* 2000 ns. */ 910 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 911 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 912 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 913 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 914 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 915 (wm->num_heads * cursor_line_pair_return_time); 916 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 917 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 918 u32 tmp, dmif_size = 12288; 919 fixed20_12 a, b, c; 920 921 if (wm->num_heads == 0) 922 return 0; 923 924 a.full = dfixed_const(2); 925 b.full = dfixed_const(1); 926 if ((wm->vsc.full > a.full) || 927 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 928 (wm->vtaps >= 5) || 929 ((wm->vsc.full >= a.full) && wm->interlaced)) 930 max_src_lines_per_dst_line = 4; 931 else 932 max_src_lines_per_dst_line = 2; 933 934 a.full = dfixed_const(available_bandwidth); 935 b.full = dfixed_const(wm->num_heads); 936 a.full = dfixed_div(a, b); 937 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 938 tmp = min(dfixed_trunc(a), tmp); 939 940 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 941 942 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 943 b.full = dfixed_const(1000); 944 c.full = dfixed_const(lb_fill_bw); 945 b.full = dfixed_div(c, b); 946 a.full = dfixed_div(a, b); 947 line_fill_time = dfixed_trunc(a); 948 949 if (line_fill_time < wm->active_time) 950 return latency; 951 else 952 return latency + (line_fill_time - wm->active_time); 953 954 } 955 956 /** 957 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 958 * average and available dram bandwidth 959 * 960 * @wm: watermark calculation data 961 * 962 * Check if the display average bandwidth fits in the display 963 * dram bandwidth (CIK). 964 * Used for display watermark bandwidth calculations 965 * Returns true if the display fits, false if not. 966 */ 967 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 968 { 969 if (dce_v11_0_average_bandwidth(wm) <= 970 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 971 return true; 972 else 973 return false; 974 } 975 976 /** 977 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 978 * average and available bandwidth 979 * 980 * @wm: watermark calculation data 981 * 982 * Check if the display average bandwidth fits in the display 983 * available bandwidth (CIK). 984 * Used for display watermark bandwidth calculations 985 * Returns true if the display fits, false if not. 986 */ 987 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 988 { 989 if (dce_v11_0_average_bandwidth(wm) <= 990 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 991 return true; 992 else 993 return false; 994 } 995 996 /** 997 * dce_v11_0_check_latency_hiding - check latency hiding 998 * 999 * @wm: watermark calculation data 1000 * 1001 * Check latency hiding (CIK). 1002 * Used for display watermark bandwidth calculations 1003 * Returns true if the display fits, false if not. 1004 */ 1005 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1006 { 1007 u32 lb_partitions = wm->lb_size / wm->src_width; 1008 u32 line_time = wm->active_time + wm->blank_time; 1009 u32 latency_tolerant_lines; 1010 u32 latency_hiding; 1011 fixed20_12 a; 1012 1013 a.full = dfixed_const(1); 1014 if (wm->vsc.full > a.full) 1015 latency_tolerant_lines = 1; 1016 else { 1017 if (lb_partitions <= (wm->vtaps + 1)) 1018 latency_tolerant_lines = 1; 1019 else 1020 latency_tolerant_lines = 2; 1021 } 1022 1023 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1024 1025 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1026 return true; 1027 else 1028 return false; 1029 } 1030 1031 /** 1032 * dce_v11_0_program_watermarks - program display watermarks 1033 * 1034 * @adev: amdgpu_device pointer 1035 * @amdgpu_crtc: the selected display controller 1036 * @lb_size: line buffer size 1037 * @num_heads: number of display controllers in use 1038 * 1039 * Calculate and program the display watermarks for the 1040 * selected display controller (CIK). 1041 */ 1042 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1043 struct amdgpu_crtc *amdgpu_crtc, 1044 u32 lb_size, u32 num_heads) 1045 { 1046 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1047 struct dce10_wm_params wm_low, wm_high; 1048 u32 active_time; 1049 u32 line_time = 0; 1050 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1051 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1052 1053 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1054 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1055 (u32)mode->clock); 1056 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1057 (u32)mode->clock); 1058 line_time = min(line_time, (u32)65535); 1059 1060 /* watermark for high clocks */ 1061 if (adev->pm.dpm_enabled) { 1062 wm_high.yclk = 1063 amdgpu_dpm_get_mclk(adev, false) * 10; 1064 wm_high.sclk = 1065 amdgpu_dpm_get_sclk(adev, false) * 10; 1066 } else { 1067 wm_high.yclk = adev->pm.current_mclk * 10; 1068 wm_high.sclk = adev->pm.current_sclk * 10; 1069 } 1070 1071 wm_high.disp_clk = mode->clock; 1072 wm_high.src_width = mode->crtc_hdisplay; 1073 wm_high.active_time = active_time; 1074 wm_high.blank_time = line_time - wm_high.active_time; 1075 wm_high.interlaced = false; 1076 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1077 wm_high.interlaced = true; 1078 wm_high.vsc = amdgpu_crtc->vsc; 1079 wm_high.vtaps = 1; 1080 if (amdgpu_crtc->rmx_type != RMX_OFF) 1081 wm_high.vtaps = 2; 1082 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1083 wm_high.lb_size = lb_size; 1084 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1085 wm_high.num_heads = num_heads; 1086 1087 /* set for high clocks */ 1088 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1089 1090 /* possibly force display priority to high */ 1091 /* should really do this at mode validation time... */ 1092 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1093 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1094 !dce_v11_0_check_latency_hiding(&wm_high) || 1095 (adev->mode_info.disp_priority == 2)) { 1096 DRM_DEBUG_KMS("force priority to high\n"); 1097 } 1098 1099 /* watermark for low clocks */ 1100 if (adev->pm.dpm_enabled) { 1101 wm_low.yclk = 1102 amdgpu_dpm_get_mclk(adev, true) * 10; 1103 wm_low.sclk = 1104 amdgpu_dpm_get_sclk(adev, true) * 10; 1105 } else { 1106 wm_low.yclk = adev->pm.current_mclk * 10; 1107 wm_low.sclk = adev->pm.current_sclk * 10; 1108 } 1109 1110 wm_low.disp_clk = mode->clock; 1111 wm_low.src_width = mode->crtc_hdisplay; 1112 wm_low.active_time = active_time; 1113 wm_low.blank_time = line_time - wm_low.active_time; 1114 wm_low.interlaced = false; 1115 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1116 wm_low.interlaced = true; 1117 wm_low.vsc = amdgpu_crtc->vsc; 1118 wm_low.vtaps = 1; 1119 if (amdgpu_crtc->rmx_type != RMX_OFF) 1120 wm_low.vtaps = 2; 1121 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1122 wm_low.lb_size = lb_size; 1123 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1124 wm_low.num_heads = num_heads; 1125 1126 /* set for low clocks */ 1127 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1128 1129 /* possibly force display priority to high */ 1130 /* should really do this at mode validation time... */ 1131 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1132 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1133 !dce_v11_0_check_latency_hiding(&wm_low) || 1134 (adev->mode_info.disp_priority == 2)) { 1135 DRM_DEBUG_KMS("force priority to high\n"); 1136 } 1137 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1138 } 1139 1140 /* select wm A */ 1141 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1142 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1143 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1144 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1145 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1146 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1147 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1148 /* select wm B */ 1149 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1150 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1151 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1152 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1153 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1154 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1155 /* restore original selection */ 1156 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1157 1158 /* save values for DPM */ 1159 amdgpu_crtc->line_time = line_time; 1160 amdgpu_crtc->wm_high = latency_watermark_a; 1161 amdgpu_crtc->wm_low = latency_watermark_b; 1162 /* Save number of lines the linebuffer leads before the scanout */ 1163 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1164 } 1165 1166 /** 1167 * dce_v11_0_bandwidth_update - program display watermarks 1168 * 1169 * @adev: amdgpu_device pointer 1170 * 1171 * Calculate and program the display watermarks and line 1172 * buffer allocation (CIK). 1173 */ 1174 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1175 { 1176 struct drm_display_mode *mode = NULL; 1177 u32 num_heads = 0, lb_size; 1178 int i; 1179 1180 amdgpu_display_update_priority(adev); 1181 1182 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1183 if (adev->mode_info.crtcs[i]->base.enabled) 1184 num_heads++; 1185 } 1186 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1187 mode = &adev->mode_info.crtcs[i]->base.mode; 1188 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1189 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1190 lb_size, num_heads); 1191 } 1192 } 1193 1194 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1195 { 1196 int i; 1197 u32 offset, tmp; 1198 1199 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1200 offset = adev->mode_info.audio.pin[i].offset; 1201 tmp = RREG32_AUDIO_ENDPT(offset, 1202 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1203 if (((tmp & 1204 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1205 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1206 adev->mode_info.audio.pin[i].connected = false; 1207 else 1208 adev->mode_info.audio.pin[i].connected = true; 1209 } 1210 } 1211 1212 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1213 { 1214 int i; 1215 1216 dce_v11_0_audio_get_connected_pins(adev); 1217 1218 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1219 if (adev->mode_info.audio.pin[i].connected) 1220 return &adev->mode_info.audio.pin[i]; 1221 } 1222 DRM_ERROR("No connected audio pins found!\n"); 1223 return NULL; 1224 } 1225 1226 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1227 { 1228 struct amdgpu_device *adev = encoder->dev->dev_private; 1229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1231 u32 tmp; 1232 1233 if (!dig || !dig->afmt || !dig->afmt->pin) 1234 return; 1235 1236 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1237 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1238 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1239 } 1240 1241 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1242 struct drm_display_mode *mode) 1243 { 1244 struct amdgpu_device *adev = encoder->dev->dev_private; 1245 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1246 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1247 struct drm_connector *connector; 1248 struct amdgpu_connector *amdgpu_connector = NULL; 1249 u32 tmp; 1250 int interlace = 0; 1251 1252 if (!dig || !dig->afmt || !dig->afmt->pin) 1253 return; 1254 1255 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1256 if (connector->encoder == encoder) { 1257 amdgpu_connector = to_amdgpu_connector(connector); 1258 break; 1259 } 1260 } 1261 1262 if (!amdgpu_connector) { 1263 DRM_ERROR("Couldn't find encoder's connector\n"); 1264 return; 1265 } 1266 1267 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1268 interlace = 1; 1269 if (connector->latency_present[interlace]) { 1270 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1271 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1272 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1273 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1274 } else { 1275 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1276 VIDEO_LIPSYNC, 0); 1277 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1278 AUDIO_LIPSYNC, 0); 1279 } 1280 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1281 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1282 } 1283 1284 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1285 { 1286 struct amdgpu_device *adev = encoder->dev->dev_private; 1287 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1288 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1289 struct drm_connector *connector; 1290 struct amdgpu_connector *amdgpu_connector = NULL; 1291 u32 tmp; 1292 u8 *sadb = NULL; 1293 int sad_count; 1294 1295 if (!dig || !dig->afmt || !dig->afmt->pin) 1296 return; 1297 1298 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1299 if (connector->encoder == encoder) { 1300 amdgpu_connector = to_amdgpu_connector(connector); 1301 break; 1302 } 1303 } 1304 1305 if (!amdgpu_connector) { 1306 DRM_ERROR("Couldn't find encoder's connector\n"); 1307 return; 1308 } 1309 1310 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1311 if (sad_count < 0) { 1312 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1313 sad_count = 0; 1314 } 1315 1316 /* program the speaker allocation */ 1317 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1318 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1319 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1320 DP_CONNECTION, 0); 1321 /* set HDMI mode */ 1322 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1323 HDMI_CONNECTION, 1); 1324 if (sad_count) 1325 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1326 SPEAKER_ALLOCATION, sadb[0]); 1327 else 1328 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1329 SPEAKER_ALLOCATION, 5); /* stereo */ 1330 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1331 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1332 1333 kfree(sadb); 1334 } 1335 1336 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1337 { 1338 struct amdgpu_device *adev = encoder->dev->dev_private; 1339 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1340 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1341 struct drm_connector *connector; 1342 struct amdgpu_connector *amdgpu_connector = NULL; 1343 struct cea_sad *sads; 1344 int i, sad_count; 1345 1346 static const u16 eld_reg_to_type[][2] = { 1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1353 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1354 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1355 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1356 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1357 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1358 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1359 }; 1360 1361 if (!dig || !dig->afmt || !dig->afmt->pin) 1362 return; 1363 1364 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1365 if (connector->encoder == encoder) { 1366 amdgpu_connector = to_amdgpu_connector(connector); 1367 break; 1368 } 1369 } 1370 1371 if (!amdgpu_connector) { 1372 DRM_ERROR("Couldn't find encoder's connector\n"); 1373 return; 1374 } 1375 1376 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1377 if (sad_count <= 0) { 1378 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1379 return; 1380 } 1381 BUG_ON(!sads); 1382 1383 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1384 u32 tmp = 0; 1385 u8 stereo_freqs = 0; 1386 int max_channels = -1; 1387 int j; 1388 1389 for (j = 0; j < sad_count; j++) { 1390 struct cea_sad *sad = &sads[j]; 1391 1392 if (sad->format == eld_reg_to_type[i][1]) { 1393 if (sad->channels > max_channels) { 1394 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1395 MAX_CHANNELS, sad->channels); 1396 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1397 DESCRIPTOR_BYTE_2, sad->byte2); 1398 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1399 SUPPORTED_FREQUENCIES, sad->freq); 1400 max_channels = sad->channels; 1401 } 1402 1403 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1404 stereo_freqs |= sad->freq; 1405 else 1406 break; 1407 } 1408 } 1409 1410 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1411 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1412 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1413 } 1414 1415 kfree(sads); 1416 } 1417 1418 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1419 struct amdgpu_audio_pin *pin, 1420 bool enable) 1421 { 1422 if (!pin) 1423 return; 1424 1425 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1426 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1427 } 1428 1429 static const u32 pin_offsets[] = 1430 { 1431 AUD0_REGISTER_OFFSET, 1432 AUD1_REGISTER_OFFSET, 1433 AUD2_REGISTER_OFFSET, 1434 AUD3_REGISTER_OFFSET, 1435 AUD4_REGISTER_OFFSET, 1436 AUD5_REGISTER_OFFSET, 1437 AUD6_REGISTER_OFFSET, 1438 AUD7_REGISTER_OFFSET, 1439 }; 1440 1441 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1442 { 1443 int i; 1444 1445 if (!amdgpu_audio) 1446 return 0; 1447 1448 adev->mode_info.audio.enabled = true; 1449 1450 switch (adev->asic_type) { 1451 case CHIP_CARRIZO: 1452 case CHIP_STONEY: 1453 adev->mode_info.audio.num_pins = 7; 1454 break; 1455 case CHIP_POLARIS10: 1456 case CHIP_VEGAM: 1457 adev->mode_info.audio.num_pins = 8; 1458 break; 1459 case CHIP_POLARIS11: 1460 case CHIP_POLARIS12: 1461 adev->mode_info.audio.num_pins = 6; 1462 break; 1463 default: 1464 return -EINVAL; 1465 } 1466 1467 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1468 adev->mode_info.audio.pin[i].channels = -1; 1469 adev->mode_info.audio.pin[i].rate = -1; 1470 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1471 adev->mode_info.audio.pin[i].status_bits = 0; 1472 adev->mode_info.audio.pin[i].category_code = 0; 1473 adev->mode_info.audio.pin[i].connected = false; 1474 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1475 adev->mode_info.audio.pin[i].id = i; 1476 /* disable audio. it will be set up later */ 1477 /* XXX remove once we switch to ip funcs */ 1478 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1479 } 1480 1481 return 0; 1482 } 1483 1484 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1485 { 1486 int i; 1487 1488 if (!amdgpu_audio) 1489 return; 1490 1491 if (!adev->mode_info.audio.enabled) 1492 return; 1493 1494 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1495 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1496 1497 adev->mode_info.audio.enabled = false; 1498 } 1499 1500 /* 1501 * update the N and CTS parameters for a given pixel clock rate 1502 */ 1503 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1504 { 1505 struct drm_device *dev = encoder->dev; 1506 struct amdgpu_device *adev = dev->dev_private; 1507 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1508 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1509 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1510 u32 tmp; 1511 1512 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1513 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1514 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1515 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1516 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1517 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1518 1519 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1520 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1521 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1522 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1523 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1524 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1525 1526 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1527 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1528 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1529 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1530 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1531 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1532 1533 } 1534 1535 /* 1536 * build a HDMI Video Info Frame 1537 */ 1538 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1539 void *buffer, size_t size) 1540 { 1541 struct drm_device *dev = encoder->dev; 1542 struct amdgpu_device *adev = dev->dev_private; 1543 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1544 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1545 uint8_t *frame = buffer + 3; 1546 uint8_t *header = buffer; 1547 1548 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1549 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1550 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1551 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1552 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1553 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1554 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1555 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1556 } 1557 1558 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1559 { 1560 struct drm_device *dev = encoder->dev; 1561 struct amdgpu_device *adev = dev->dev_private; 1562 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1563 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1564 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1565 u32 dto_phase = 24 * 1000; 1566 u32 dto_modulo = clock; 1567 u32 tmp; 1568 1569 if (!dig || !dig->afmt) 1570 return; 1571 1572 /* XXX two dtos; generally use dto0 for hdmi */ 1573 /* Express [24MHz / target pixel clock] as an exact rational 1574 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1575 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1576 */ 1577 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1578 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1579 amdgpu_crtc->crtc_id); 1580 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1581 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1582 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1583 } 1584 1585 /* 1586 * update the info frames with the data from the current display mode 1587 */ 1588 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1589 struct drm_display_mode *mode) 1590 { 1591 struct drm_device *dev = encoder->dev; 1592 struct amdgpu_device *adev = dev->dev_private; 1593 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1594 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1595 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1596 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1597 struct hdmi_avi_infoframe frame; 1598 ssize_t err; 1599 u32 tmp; 1600 int bpc = 8; 1601 1602 if (!dig || !dig->afmt) 1603 return; 1604 1605 /* Silent, r600_hdmi_enable will raise WARN for us */ 1606 if (!dig->afmt->enabled) 1607 return; 1608 1609 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1610 if (encoder->crtc) { 1611 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1612 bpc = amdgpu_crtc->bpc; 1613 } 1614 1615 /* disable audio prior to setting up hw */ 1616 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1617 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1618 1619 dce_v11_0_audio_set_dto(encoder, mode->clock); 1620 1621 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1622 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1623 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1624 1625 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1626 1627 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1628 switch (bpc) { 1629 case 0: 1630 case 6: 1631 case 8: 1632 case 16: 1633 default: 1634 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1635 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1636 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1637 connector->name, bpc); 1638 break; 1639 case 10: 1640 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1641 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1642 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1643 connector->name); 1644 break; 1645 case 12: 1646 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1647 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1648 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1649 connector->name); 1650 break; 1651 } 1652 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1653 1654 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1655 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1656 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1657 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1658 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1659 1660 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1661 /* enable audio info frames (frames won't be set until audio is enabled) */ 1662 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1663 /* required for audio info values to be updated */ 1664 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1665 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1666 1667 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1668 /* required for audio info values to be updated */ 1669 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1670 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1671 1672 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1673 /* anything other than 0 */ 1674 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1675 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1676 1677 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1678 1679 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1680 /* set the default audio delay */ 1681 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1682 /* should be suffient for all audio modes and small enough for all hblanks */ 1683 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1684 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1685 1686 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1687 /* allow 60958 channel status fields to be updated */ 1688 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1689 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1690 1691 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1692 if (bpc > 8) 1693 /* clear SW CTS value */ 1694 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1695 else 1696 /* select SW CTS value */ 1697 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1698 /* allow hw to sent ACR packets when required */ 1699 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1700 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1701 1702 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1703 1704 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1705 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1706 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1707 1708 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1709 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1710 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1711 1712 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1713 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1714 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1715 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1716 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1717 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1718 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1719 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1720 1721 dce_v11_0_audio_write_speaker_allocation(encoder); 1722 1723 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1724 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1725 1726 dce_v11_0_afmt_audio_select_pin(encoder); 1727 dce_v11_0_audio_write_sad_regs(encoder); 1728 dce_v11_0_audio_write_latency_fields(encoder, mode); 1729 1730 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1731 if (err < 0) { 1732 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1733 return; 1734 } 1735 1736 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1737 if (err < 0) { 1738 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1739 return; 1740 } 1741 1742 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1743 1744 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1745 /* enable AVI info frames */ 1746 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1747 /* required for audio info values to be updated */ 1748 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1749 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1750 1751 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1752 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1753 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1754 1755 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1756 /* send audio packets */ 1757 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1758 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1759 1760 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1761 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1762 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1763 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1764 1765 /* enable audio after to setting up hw */ 1766 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1767 } 1768 1769 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1770 { 1771 struct drm_device *dev = encoder->dev; 1772 struct amdgpu_device *adev = dev->dev_private; 1773 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1774 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1775 1776 if (!dig || !dig->afmt) 1777 return; 1778 1779 /* Silent, r600_hdmi_enable will raise WARN for us */ 1780 if (enable && dig->afmt->enabled) 1781 return; 1782 if (!enable && !dig->afmt->enabled) 1783 return; 1784 1785 if (!enable && dig->afmt->pin) { 1786 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1787 dig->afmt->pin = NULL; 1788 } 1789 1790 dig->afmt->enabled = enable; 1791 1792 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1793 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1794 } 1795 1796 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1797 { 1798 int i; 1799 1800 for (i = 0; i < adev->mode_info.num_dig; i++) 1801 adev->mode_info.afmt[i] = NULL; 1802 1803 /* DCE11 has audio blocks tied to DIG encoders */ 1804 for (i = 0; i < adev->mode_info.num_dig; i++) { 1805 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1806 if (adev->mode_info.afmt[i]) { 1807 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1808 adev->mode_info.afmt[i]->id = i; 1809 } else { 1810 int j; 1811 for (j = 0; j < i; j++) { 1812 kfree(adev->mode_info.afmt[j]); 1813 adev->mode_info.afmt[j] = NULL; 1814 } 1815 return -ENOMEM; 1816 } 1817 } 1818 return 0; 1819 } 1820 1821 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1822 { 1823 int i; 1824 1825 for (i = 0; i < adev->mode_info.num_dig; i++) { 1826 kfree(adev->mode_info.afmt[i]); 1827 adev->mode_info.afmt[i] = NULL; 1828 } 1829 } 1830 1831 static const u32 vga_control_regs[6] = 1832 { 1833 mmD1VGA_CONTROL, 1834 mmD2VGA_CONTROL, 1835 mmD3VGA_CONTROL, 1836 mmD4VGA_CONTROL, 1837 mmD5VGA_CONTROL, 1838 mmD6VGA_CONTROL, 1839 }; 1840 1841 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1842 { 1843 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1844 struct drm_device *dev = crtc->dev; 1845 struct amdgpu_device *adev = dev->dev_private; 1846 u32 vga_control; 1847 1848 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1849 if (enable) 1850 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1851 else 1852 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1853 } 1854 1855 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1856 { 1857 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1858 struct drm_device *dev = crtc->dev; 1859 struct amdgpu_device *adev = dev->dev_private; 1860 1861 if (enable) 1862 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1863 else 1864 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1865 } 1866 1867 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 1868 struct drm_framebuffer *fb, 1869 int x, int y, int atomic) 1870 { 1871 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1872 struct drm_device *dev = crtc->dev; 1873 struct amdgpu_device *adev = dev->dev_private; 1874 struct drm_framebuffer *target_fb; 1875 struct drm_gem_object *obj; 1876 struct amdgpu_bo *abo; 1877 uint64_t fb_location, tiling_flags; 1878 uint32_t fb_format, fb_pitch_pixels; 1879 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1880 u32 pipe_config; 1881 u32 tmp, viewport_w, viewport_h; 1882 int r; 1883 bool bypass_lut = false; 1884 struct drm_format_name_buf format_name; 1885 1886 /* no fb bound */ 1887 if (!atomic && !crtc->primary->fb) { 1888 DRM_DEBUG_KMS("No FB bound\n"); 1889 return 0; 1890 } 1891 1892 if (atomic) 1893 target_fb = fb; 1894 else 1895 target_fb = crtc->primary->fb; 1896 1897 /* If atomic, assume fb object is pinned & idle & fenced and 1898 * just update base pointers 1899 */ 1900 obj = target_fb->obj[0]; 1901 abo = gem_to_amdgpu_bo(obj); 1902 r = amdgpu_bo_reserve(abo, false); 1903 if (unlikely(r != 0)) 1904 return r; 1905 1906 if (!atomic) { 1907 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); 1908 if (unlikely(r != 0)) { 1909 amdgpu_bo_unreserve(abo); 1910 return -EINVAL; 1911 } 1912 } 1913 fb_location = amdgpu_bo_gpu_offset(abo); 1914 1915 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1916 amdgpu_bo_unreserve(abo); 1917 1918 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1919 1920 switch (target_fb->format->format) { 1921 case DRM_FORMAT_C8: 1922 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1923 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1924 break; 1925 case DRM_FORMAT_XRGB4444: 1926 case DRM_FORMAT_ARGB4444: 1927 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1928 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1929 #ifdef __BIG_ENDIAN 1930 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1931 ENDIAN_8IN16); 1932 #endif 1933 break; 1934 case DRM_FORMAT_XRGB1555: 1935 case DRM_FORMAT_ARGB1555: 1936 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1937 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1938 #ifdef __BIG_ENDIAN 1939 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1940 ENDIAN_8IN16); 1941 #endif 1942 break; 1943 case DRM_FORMAT_BGRX5551: 1944 case DRM_FORMAT_BGRA5551: 1945 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1946 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1947 #ifdef __BIG_ENDIAN 1948 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1949 ENDIAN_8IN16); 1950 #endif 1951 break; 1952 case DRM_FORMAT_RGB565: 1953 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1954 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1955 #ifdef __BIG_ENDIAN 1956 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1957 ENDIAN_8IN16); 1958 #endif 1959 break; 1960 case DRM_FORMAT_XRGB8888: 1961 case DRM_FORMAT_ARGB8888: 1962 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1963 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1964 #ifdef __BIG_ENDIAN 1965 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1966 ENDIAN_8IN32); 1967 #endif 1968 break; 1969 case DRM_FORMAT_XRGB2101010: 1970 case DRM_FORMAT_ARGB2101010: 1971 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1972 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1973 #ifdef __BIG_ENDIAN 1974 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1975 ENDIAN_8IN32); 1976 #endif 1977 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1978 bypass_lut = true; 1979 break; 1980 case DRM_FORMAT_BGRX1010102: 1981 case DRM_FORMAT_BGRA1010102: 1982 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1983 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 1984 #ifdef __BIG_ENDIAN 1985 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1986 ENDIAN_8IN32); 1987 #endif 1988 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1989 bypass_lut = true; 1990 break; 1991 case DRM_FORMAT_XBGR8888: 1992 case DRM_FORMAT_ABGR8888: 1993 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1994 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1995 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2); 1996 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2); 1997 #ifdef __BIG_ENDIAN 1998 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1999 ENDIAN_8IN32); 2000 #endif 2001 break; 2002 default: 2003 DRM_ERROR("Unsupported screen format %s\n", 2004 drm_get_format_name(target_fb->format->format, &format_name)); 2005 return -EINVAL; 2006 } 2007 2008 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2009 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2010 2011 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2012 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2013 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2014 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2015 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2016 2017 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2018 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2019 ARRAY_2D_TILED_THIN1); 2020 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2021 tile_split); 2022 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2023 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2024 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2025 mtaspect); 2026 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2027 ADDR_SURF_MICRO_TILING_DISPLAY); 2028 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2029 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2030 ARRAY_1D_TILED_THIN1); 2031 } 2032 2033 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2034 pipe_config); 2035 2036 dce_v11_0_vga_enable(crtc, false); 2037 2038 /* Make sure surface address is updated at vertical blank rather than 2039 * horizontal blank 2040 */ 2041 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2042 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2043 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2044 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2045 2046 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2047 upper_32_bits(fb_location)); 2048 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2049 upper_32_bits(fb_location)); 2050 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2051 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2052 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2053 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2054 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2055 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2056 2057 /* 2058 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2059 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2060 * retain the full precision throughout the pipeline. 2061 */ 2062 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2063 if (bypass_lut) 2064 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2065 else 2066 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2067 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2068 2069 if (bypass_lut) 2070 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2071 2072 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2073 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2074 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2075 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2076 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2077 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2078 2079 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2080 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2081 2082 dce_v11_0_grph_enable(crtc, true); 2083 2084 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2085 target_fb->height); 2086 2087 x &= ~3; 2088 y &= ~1; 2089 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2090 (x << 16) | y); 2091 viewport_w = crtc->mode.hdisplay; 2092 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2093 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2094 (viewport_w << 16) | viewport_h); 2095 2096 /* set pageflip to happen anywhere in vblank interval */ 2097 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2098 2099 if (!atomic && fb && fb != crtc->primary->fb) { 2100 abo = gem_to_amdgpu_bo(fb->obj[0]); 2101 r = amdgpu_bo_reserve(abo, true); 2102 if (unlikely(r != 0)) 2103 return r; 2104 amdgpu_bo_unpin(abo); 2105 amdgpu_bo_unreserve(abo); 2106 } 2107 2108 /* Bytes per pixel may have changed */ 2109 dce_v11_0_bandwidth_update(adev); 2110 2111 return 0; 2112 } 2113 2114 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2115 struct drm_display_mode *mode) 2116 { 2117 struct drm_device *dev = crtc->dev; 2118 struct amdgpu_device *adev = dev->dev_private; 2119 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2120 u32 tmp; 2121 2122 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2123 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2124 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2125 else 2126 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2127 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2128 } 2129 2130 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2131 { 2132 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2133 struct drm_device *dev = crtc->dev; 2134 struct amdgpu_device *adev = dev->dev_private; 2135 u16 *r, *g, *b; 2136 int i; 2137 u32 tmp; 2138 2139 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2140 2141 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2142 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2143 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2144 2145 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2146 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2147 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2148 2149 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2150 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2151 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2152 2153 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2154 2155 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2156 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2157 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2158 2159 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2160 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2161 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2162 2163 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2164 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2165 2166 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2167 r = crtc->gamma_store; 2168 g = r + crtc->gamma_size; 2169 b = g + crtc->gamma_size; 2170 for (i = 0; i < 256; i++) { 2171 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2172 ((*r++ & 0xffc0) << 14) | 2173 ((*g++ & 0xffc0) << 4) | 2174 (*b++ >> 6)); 2175 } 2176 2177 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2178 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2179 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2180 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2181 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2182 2183 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2184 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2185 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2186 2187 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2188 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2189 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2190 2191 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2192 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2193 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2194 2195 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2196 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2197 /* XXX this only needs to be programmed once per crtc at startup, 2198 * not sure where the best place for it is 2199 */ 2200 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2201 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2202 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2203 } 2204 2205 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2206 { 2207 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2208 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2209 2210 switch (amdgpu_encoder->encoder_id) { 2211 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2212 if (dig->linkb) 2213 return 1; 2214 else 2215 return 0; 2216 break; 2217 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2218 if (dig->linkb) 2219 return 3; 2220 else 2221 return 2; 2222 break; 2223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2224 if (dig->linkb) 2225 return 5; 2226 else 2227 return 4; 2228 break; 2229 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2230 return 6; 2231 break; 2232 default: 2233 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2234 return 0; 2235 } 2236 } 2237 2238 /** 2239 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2240 * 2241 * @crtc: drm crtc 2242 * 2243 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2244 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2245 * monitors a dedicated PPLL must be used. If a particular board has 2246 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2247 * as there is no need to program the PLL itself. If we are not able to 2248 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2249 * avoid messing up an existing monitor. 2250 * 2251 * Asic specific PLL information 2252 * 2253 * DCE 10.x 2254 * Tonga 2255 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2256 * CI 2257 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2258 * 2259 */ 2260 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2261 { 2262 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2263 struct drm_device *dev = crtc->dev; 2264 struct amdgpu_device *adev = dev->dev_private; 2265 u32 pll_in_use; 2266 int pll; 2267 2268 if ((adev->asic_type == CHIP_POLARIS10) || 2269 (adev->asic_type == CHIP_POLARIS11) || 2270 (adev->asic_type == CHIP_POLARIS12) || 2271 (adev->asic_type == CHIP_VEGAM)) { 2272 struct amdgpu_encoder *amdgpu_encoder = 2273 to_amdgpu_encoder(amdgpu_crtc->encoder); 2274 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2275 2276 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2277 return ATOM_DP_DTO; 2278 2279 switch (amdgpu_encoder->encoder_id) { 2280 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2281 if (dig->linkb) 2282 return ATOM_COMBOPHY_PLL1; 2283 else 2284 return ATOM_COMBOPHY_PLL0; 2285 break; 2286 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2287 if (dig->linkb) 2288 return ATOM_COMBOPHY_PLL3; 2289 else 2290 return ATOM_COMBOPHY_PLL2; 2291 break; 2292 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2293 if (dig->linkb) 2294 return ATOM_COMBOPHY_PLL5; 2295 else 2296 return ATOM_COMBOPHY_PLL4; 2297 break; 2298 default: 2299 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2300 return ATOM_PPLL_INVALID; 2301 } 2302 } 2303 2304 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2305 if (adev->clock.dp_extclk) 2306 /* skip PPLL programming if using ext clock */ 2307 return ATOM_PPLL_INVALID; 2308 else { 2309 /* use the same PPLL for all DP monitors */ 2310 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2311 if (pll != ATOM_PPLL_INVALID) 2312 return pll; 2313 } 2314 } else { 2315 /* use the same PPLL for all monitors with the same clock */ 2316 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2317 if (pll != ATOM_PPLL_INVALID) 2318 return pll; 2319 } 2320 2321 /* XXX need to determine what plls are available on each DCE11 part */ 2322 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2323 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2324 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2325 return ATOM_PPLL1; 2326 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2327 return ATOM_PPLL0; 2328 DRM_ERROR("unable to allocate a PPLL\n"); 2329 return ATOM_PPLL_INVALID; 2330 } else { 2331 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2332 return ATOM_PPLL2; 2333 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2334 return ATOM_PPLL1; 2335 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2336 return ATOM_PPLL0; 2337 DRM_ERROR("unable to allocate a PPLL\n"); 2338 return ATOM_PPLL_INVALID; 2339 } 2340 return ATOM_PPLL_INVALID; 2341 } 2342 2343 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2344 { 2345 struct amdgpu_device *adev = crtc->dev->dev_private; 2346 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2347 uint32_t cur_lock; 2348 2349 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2350 if (lock) 2351 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2352 else 2353 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2354 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2355 } 2356 2357 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2358 { 2359 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2360 struct amdgpu_device *adev = crtc->dev->dev_private; 2361 u32 tmp; 2362 2363 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2364 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2365 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2366 } 2367 2368 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2369 { 2370 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2371 struct amdgpu_device *adev = crtc->dev->dev_private; 2372 u32 tmp; 2373 2374 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2375 upper_32_bits(amdgpu_crtc->cursor_addr)); 2376 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2377 lower_32_bits(amdgpu_crtc->cursor_addr)); 2378 2379 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2380 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2381 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2382 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2383 } 2384 2385 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2386 int x, int y) 2387 { 2388 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2389 struct amdgpu_device *adev = crtc->dev->dev_private; 2390 int xorigin = 0, yorigin = 0; 2391 2392 amdgpu_crtc->cursor_x = x; 2393 amdgpu_crtc->cursor_y = y; 2394 2395 /* avivo cursor are offset into the total surface */ 2396 x += crtc->x; 2397 y += crtc->y; 2398 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2399 2400 if (x < 0) { 2401 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2402 x = 0; 2403 } 2404 if (y < 0) { 2405 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2406 y = 0; 2407 } 2408 2409 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2410 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2411 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2412 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2413 2414 return 0; 2415 } 2416 2417 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2418 int x, int y) 2419 { 2420 int ret; 2421 2422 dce_v11_0_lock_cursor(crtc, true); 2423 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2424 dce_v11_0_lock_cursor(crtc, false); 2425 2426 return ret; 2427 } 2428 2429 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2430 struct drm_file *file_priv, 2431 uint32_t handle, 2432 uint32_t width, 2433 uint32_t height, 2434 int32_t hot_x, 2435 int32_t hot_y) 2436 { 2437 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2438 struct drm_gem_object *obj; 2439 struct amdgpu_bo *aobj; 2440 int ret; 2441 2442 if (!handle) { 2443 /* turn off cursor */ 2444 dce_v11_0_hide_cursor(crtc); 2445 obj = NULL; 2446 goto unpin; 2447 } 2448 2449 if ((width > amdgpu_crtc->max_cursor_width) || 2450 (height > amdgpu_crtc->max_cursor_height)) { 2451 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2452 return -EINVAL; 2453 } 2454 2455 obj = drm_gem_object_lookup(file_priv, handle); 2456 if (!obj) { 2457 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2458 return -ENOENT; 2459 } 2460 2461 aobj = gem_to_amdgpu_bo(obj); 2462 ret = amdgpu_bo_reserve(aobj, false); 2463 if (ret != 0) { 2464 drm_gem_object_put_unlocked(obj); 2465 return ret; 2466 } 2467 2468 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); 2469 amdgpu_bo_unreserve(aobj); 2470 if (ret) { 2471 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2472 drm_gem_object_put_unlocked(obj); 2473 return ret; 2474 } 2475 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj); 2476 2477 dce_v11_0_lock_cursor(crtc, true); 2478 2479 if (width != amdgpu_crtc->cursor_width || 2480 height != amdgpu_crtc->cursor_height || 2481 hot_x != amdgpu_crtc->cursor_hot_x || 2482 hot_y != amdgpu_crtc->cursor_hot_y) { 2483 int x, y; 2484 2485 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2486 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2487 2488 dce_v11_0_cursor_move_locked(crtc, x, y); 2489 2490 amdgpu_crtc->cursor_width = width; 2491 amdgpu_crtc->cursor_height = height; 2492 amdgpu_crtc->cursor_hot_x = hot_x; 2493 amdgpu_crtc->cursor_hot_y = hot_y; 2494 } 2495 2496 dce_v11_0_show_cursor(crtc); 2497 dce_v11_0_lock_cursor(crtc, false); 2498 2499 unpin: 2500 if (amdgpu_crtc->cursor_bo) { 2501 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2502 ret = amdgpu_bo_reserve(aobj, true); 2503 if (likely(ret == 0)) { 2504 amdgpu_bo_unpin(aobj); 2505 amdgpu_bo_unreserve(aobj); 2506 } 2507 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); 2508 } 2509 2510 amdgpu_crtc->cursor_bo = obj; 2511 return 0; 2512 } 2513 2514 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2515 { 2516 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2517 2518 if (amdgpu_crtc->cursor_bo) { 2519 dce_v11_0_lock_cursor(crtc, true); 2520 2521 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2522 amdgpu_crtc->cursor_y); 2523 2524 dce_v11_0_show_cursor(crtc); 2525 2526 dce_v11_0_lock_cursor(crtc, false); 2527 } 2528 } 2529 2530 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2531 u16 *blue, uint32_t size, 2532 struct drm_modeset_acquire_ctx *ctx) 2533 { 2534 dce_v11_0_crtc_load_lut(crtc); 2535 2536 return 0; 2537 } 2538 2539 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2540 { 2541 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2542 2543 drm_crtc_cleanup(crtc); 2544 kfree(amdgpu_crtc); 2545 } 2546 2547 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2548 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2549 .cursor_move = dce_v11_0_crtc_cursor_move, 2550 .gamma_set = dce_v11_0_crtc_gamma_set, 2551 .set_config = amdgpu_display_crtc_set_config, 2552 .destroy = dce_v11_0_crtc_destroy, 2553 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2554 }; 2555 2556 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2557 { 2558 struct drm_device *dev = crtc->dev; 2559 struct amdgpu_device *adev = dev->dev_private; 2560 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2561 unsigned type; 2562 2563 switch (mode) { 2564 case DRM_MODE_DPMS_ON: 2565 amdgpu_crtc->enabled = true; 2566 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2567 dce_v11_0_vga_enable(crtc, true); 2568 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2569 dce_v11_0_vga_enable(crtc, false); 2570 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2571 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2572 amdgpu_crtc->crtc_id); 2573 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2574 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2575 drm_crtc_vblank_on(crtc); 2576 dce_v11_0_crtc_load_lut(crtc); 2577 break; 2578 case DRM_MODE_DPMS_STANDBY: 2579 case DRM_MODE_DPMS_SUSPEND: 2580 case DRM_MODE_DPMS_OFF: 2581 drm_crtc_vblank_off(crtc); 2582 if (amdgpu_crtc->enabled) { 2583 dce_v11_0_vga_enable(crtc, true); 2584 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2585 dce_v11_0_vga_enable(crtc, false); 2586 } 2587 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2588 amdgpu_crtc->enabled = false; 2589 break; 2590 } 2591 /* adjust pm to dpms */ 2592 amdgpu_pm_compute_clocks(adev); 2593 } 2594 2595 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2596 { 2597 /* disable crtc pair power gating before programming */ 2598 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2599 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2600 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2601 } 2602 2603 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2604 { 2605 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2606 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2607 } 2608 2609 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2610 { 2611 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2612 struct drm_device *dev = crtc->dev; 2613 struct amdgpu_device *adev = dev->dev_private; 2614 struct amdgpu_atom_ss ss; 2615 int i; 2616 2617 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2618 if (crtc->primary->fb) { 2619 int r; 2620 struct amdgpu_bo *abo; 2621 2622 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2623 r = amdgpu_bo_reserve(abo, true); 2624 if (unlikely(r)) 2625 DRM_ERROR("failed to reserve abo before unpin\n"); 2626 else { 2627 amdgpu_bo_unpin(abo); 2628 amdgpu_bo_unreserve(abo); 2629 } 2630 } 2631 /* disable the GRPH */ 2632 dce_v11_0_grph_enable(crtc, false); 2633 2634 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2635 2636 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2637 if (adev->mode_info.crtcs[i] && 2638 adev->mode_info.crtcs[i]->enabled && 2639 i != amdgpu_crtc->crtc_id && 2640 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2641 /* one other crtc is using this pll don't turn 2642 * off the pll 2643 */ 2644 goto done; 2645 } 2646 } 2647 2648 switch (amdgpu_crtc->pll_id) { 2649 case ATOM_PPLL0: 2650 case ATOM_PPLL1: 2651 case ATOM_PPLL2: 2652 /* disable the ppll */ 2653 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2654 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2655 break; 2656 case ATOM_COMBOPHY_PLL0: 2657 case ATOM_COMBOPHY_PLL1: 2658 case ATOM_COMBOPHY_PLL2: 2659 case ATOM_COMBOPHY_PLL3: 2660 case ATOM_COMBOPHY_PLL4: 2661 case ATOM_COMBOPHY_PLL5: 2662 /* disable the ppll */ 2663 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2664 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2665 break; 2666 default: 2667 break; 2668 } 2669 done: 2670 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2671 amdgpu_crtc->adjusted_clock = 0; 2672 amdgpu_crtc->encoder = NULL; 2673 amdgpu_crtc->connector = NULL; 2674 } 2675 2676 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2677 struct drm_display_mode *mode, 2678 struct drm_display_mode *adjusted_mode, 2679 int x, int y, struct drm_framebuffer *old_fb) 2680 { 2681 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2682 struct drm_device *dev = crtc->dev; 2683 struct amdgpu_device *adev = dev->dev_private; 2684 2685 if (!amdgpu_crtc->adjusted_clock) 2686 return -EINVAL; 2687 2688 if ((adev->asic_type == CHIP_POLARIS10) || 2689 (adev->asic_type == CHIP_POLARIS11) || 2690 (adev->asic_type == CHIP_POLARIS12) || 2691 (adev->asic_type == CHIP_VEGAM)) { 2692 struct amdgpu_encoder *amdgpu_encoder = 2693 to_amdgpu_encoder(amdgpu_crtc->encoder); 2694 int encoder_mode = 2695 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2696 2697 /* SetPixelClock calculates the plls and ss values now */ 2698 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2699 amdgpu_crtc->pll_id, 2700 encoder_mode, amdgpu_encoder->encoder_id, 2701 adjusted_mode->clock, 0, 0, 0, 0, 2702 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2703 } else { 2704 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2705 } 2706 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2707 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2708 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2709 amdgpu_atombios_crtc_scaler_setup(crtc); 2710 dce_v11_0_cursor_reset(crtc); 2711 /* update the hw version fpr dpm */ 2712 amdgpu_crtc->hw_mode = *adjusted_mode; 2713 2714 return 0; 2715 } 2716 2717 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2718 const struct drm_display_mode *mode, 2719 struct drm_display_mode *adjusted_mode) 2720 { 2721 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2722 struct drm_device *dev = crtc->dev; 2723 struct drm_encoder *encoder; 2724 2725 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2726 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2727 if (encoder->crtc == crtc) { 2728 amdgpu_crtc->encoder = encoder; 2729 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2730 break; 2731 } 2732 } 2733 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2734 amdgpu_crtc->encoder = NULL; 2735 amdgpu_crtc->connector = NULL; 2736 return false; 2737 } 2738 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2739 return false; 2740 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2741 return false; 2742 /* pick pll */ 2743 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2744 /* if we can't get a PPLL for a non-DP encoder, fail */ 2745 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2746 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2747 return false; 2748 2749 return true; 2750 } 2751 2752 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2753 struct drm_framebuffer *old_fb) 2754 { 2755 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2756 } 2757 2758 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2759 struct drm_framebuffer *fb, 2760 int x, int y, enum mode_set_atomic state) 2761 { 2762 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2763 } 2764 2765 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2766 .dpms = dce_v11_0_crtc_dpms, 2767 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2768 .mode_set = dce_v11_0_crtc_mode_set, 2769 .mode_set_base = dce_v11_0_crtc_set_base, 2770 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2771 .prepare = dce_v11_0_crtc_prepare, 2772 .commit = dce_v11_0_crtc_commit, 2773 .disable = dce_v11_0_crtc_disable, 2774 }; 2775 2776 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2777 { 2778 struct amdgpu_crtc *amdgpu_crtc; 2779 2780 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2781 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2782 if (amdgpu_crtc == NULL) 2783 return -ENOMEM; 2784 2785 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2786 2787 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2788 amdgpu_crtc->crtc_id = index; 2789 adev->mode_info.crtcs[index] = amdgpu_crtc; 2790 2791 amdgpu_crtc->max_cursor_width = 128; 2792 amdgpu_crtc->max_cursor_height = 128; 2793 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2794 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2795 2796 switch (amdgpu_crtc->crtc_id) { 2797 case 0: 2798 default: 2799 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2800 break; 2801 case 1: 2802 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2803 break; 2804 case 2: 2805 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2806 break; 2807 case 3: 2808 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2809 break; 2810 case 4: 2811 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2812 break; 2813 case 5: 2814 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2815 break; 2816 } 2817 2818 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2819 amdgpu_crtc->adjusted_clock = 0; 2820 amdgpu_crtc->encoder = NULL; 2821 amdgpu_crtc->connector = NULL; 2822 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2823 2824 return 0; 2825 } 2826 2827 static int dce_v11_0_early_init(void *handle) 2828 { 2829 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2830 2831 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2832 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2833 2834 dce_v11_0_set_display_funcs(adev); 2835 2836 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); 2837 2838 switch (adev->asic_type) { 2839 case CHIP_CARRIZO: 2840 adev->mode_info.num_hpd = 6; 2841 adev->mode_info.num_dig = 9; 2842 break; 2843 case CHIP_STONEY: 2844 adev->mode_info.num_hpd = 6; 2845 adev->mode_info.num_dig = 9; 2846 break; 2847 case CHIP_POLARIS10: 2848 case CHIP_VEGAM: 2849 adev->mode_info.num_hpd = 6; 2850 adev->mode_info.num_dig = 6; 2851 break; 2852 case CHIP_POLARIS11: 2853 case CHIP_POLARIS12: 2854 adev->mode_info.num_hpd = 5; 2855 adev->mode_info.num_dig = 5; 2856 break; 2857 default: 2858 /* FIXME: not supported yet */ 2859 return -EINVAL; 2860 } 2861 2862 dce_v11_0_set_irq_funcs(adev); 2863 2864 return 0; 2865 } 2866 2867 static int dce_v11_0_sw_init(void *handle) 2868 { 2869 int r, i; 2870 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2871 2872 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2873 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2874 if (r) 2875 return r; 2876 } 2877 2878 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) { 2879 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2880 if (r) 2881 return r; 2882 } 2883 2884 /* HPD hotplug */ 2885 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); 2886 if (r) 2887 return r; 2888 2889 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2890 2891 adev->ddev->mode_config.async_page_flip = true; 2892 2893 adev->ddev->mode_config.max_width = 16384; 2894 adev->ddev->mode_config.max_height = 16384; 2895 2896 adev->ddev->mode_config.preferred_depth = 24; 2897 adev->ddev->mode_config.prefer_shadow = 1; 2898 2899 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2900 2901 r = amdgpu_display_modeset_create_props(adev); 2902 if (r) 2903 return r; 2904 2905 adev->ddev->mode_config.max_width = 16384; 2906 adev->ddev->mode_config.max_height = 16384; 2907 2908 2909 /* allocate crtcs */ 2910 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2911 r = dce_v11_0_crtc_init(adev, i); 2912 if (r) 2913 return r; 2914 } 2915 2916 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2917 amdgpu_display_print_display_setup(adev->ddev); 2918 else 2919 return -EINVAL; 2920 2921 /* setup afmt */ 2922 r = dce_v11_0_afmt_init(adev); 2923 if (r) 2924 return r; 2925 2926 r = dce_v11_0_audio_init(adev); 2927 if (r) 2928 return r; 2929 2930 drm_kms_helper_poll_init(adev->ddev); 2931 2932 adev->mode_info.mode_config_initialized = true; 2933 return 0; 2934 } 2935 2936 static int dce_v11_0_sw_fini(void *handle) 2937 { 2938 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2939 2940 kfree(adev->mode_info.bios_hardcoded_edid); 2941 2942 drm_kms_helper_poll_fini(adev->ddev); 2943 2944 dce_v11_0_audio_fini(adev); 2945 2946 dce_v11_0_afmt_fini(adev); 2947 2948 drm_mode_config_cleanup(adev->ddev); 2949 adev->mode_info.mode_config_initialized = false; 2950 2951 return 0; 2952 } 2953 2954 static int dce_v11_0_hw_init(void *handle) 2955 { 2956 int i; 2957 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2958 2959 dce_v11_0_init_golden_registers(adev); 2960 2961 /* disable vga render */ 2962 dce_v11_0_set_vga_render_state(adev, false); 2963 /* init dig PHYs, disp eng pll */ 2964 amdgpu_atombios_crtc_powergate_init(adev); 2965 amdgpu_atombios_encoder_init_dig(adev); 2966 if ((adev->asic_type == CHIP_POLARIS10) || 2967 (adev->asic_type == CHIP_POLARIS11) || 2968 (adev->asic_type == CHIP_POLARIS12) || 2969 (adev->asic_type == CHIP_VEGAM)) { 2970 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 2971 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 2972 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 2973 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 2974 } else { 2975 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2976 } 2977 2978 /* initialize hpd */ 2979 dce_v11_0_hpd_init(adev); 2980 2981 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2982 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2983 } 2984 2985 dce_v11_0_pageflip_interrupt_init(adev); 2986 2987 return 0; 2988 } 2989 2990 static int dce_v11_0_hw_fini(void *handle) 2991 { 2992 int i; 2993 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2994 2995 dce_v11_0_hpd_fini(adev); 2996 2997 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2998 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2999 } 3000 3001 dce_v11_0_pageflip_interrupt_fini(adev); 3002 3003 return 0; 3004 } 3005 3006 static int dce_v11_0_suspend(void *handle) 3007 { 3008 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3009 3010 adev->mode_info.bl_level = 3011 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 3012 3013 return dce_v11_0_hw_fini(handle); 3014 } 3015 3016 static int dce_v11_0_resume(void *handle) 3017 { 3018 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3019 int ret; 3020 3021 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 3022 adev->mode_info.bl_level); 3023 3024 ret = dce_v11_0_hw_init(handle); 3025 3026 /* turn on the BL */ 3027 if (adev->mode_info.bl_encoder) { 3028 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3029 adev->mode_info.bl_encoder); 3030 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3031 bl_level); 3032 } 3033 3034 return ret; 3035 } 3036 3037 static bool dce_v11_0_is_idle(void *handle) 3038 { 3039 return true; 3040 } 3041 3042 static int dce_v11_0_wait_for_idle(void *handle) 3043 { 3044 return 0; 3045 } 3046 3047 static int dce_v11_0_soft_reset(void *handle) 3048 { 3049 u32 srbm_soft_reset = 0, tmp; 3050 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3051 3052 if (dce_v11_0_is_display_hung(adev)) 3053 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3054 3055 if (srbm_soft_reset) { 3056 tmp = RREG32(mmSRBM_SOFT_RESET); 3057 tmp |= srbm_soft_reset; 3058 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3059 WREG32(mmSRBM_SOFT_RESET, tmp); 3060 tmp = RREG32(mmSRBM_SOFT_RESET); 3061 3062 udelay(50); 3063 3064 tmp &= ~srbm_soft_reset; 3065 WREG32(mmSRBM_SOFT_RESET, tmp); 3066 tmp = RREG32(mmSRBM_SOFT_RESET); 3067 3068 /* Wait a little for things to settle down */ 3069 udelay(50); 3070 } 3071 return 0; 3072 } 3073 3074 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3075 int crtc, 3076 enum amdgpu_interrupt_state state) 3077 { 3078 u32 lb_interrupt_mask; 3079 3080 if (crtc >= adev->mode_info.num_crtc) { 3081 DRM_DEBUG("invalid crtc %d\n", crtc); 3082 return; 3083 } 3084 3085 switch (state) { 3086 case AMDGPU_IRQ_STATE_DISABLE: 3087 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3088 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3089 VBLANK_INTERRUPT_MASK, 0); 3090 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3091 break; 3092 case AMDGPU_IRQ_STATE_ENABLE: 3093 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3094 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3095 VBLANK_INTERRUPT_MASK, 1); 3096 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3097 break; 3098 default: 3099 break; 3100 } 3101 } 3102 3103 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3104 int crtc, 3105 enum amdgpu_interrupt_state state) 3106 { 3107 u32 lb_interrupt_mask; 3108 3109 if (crtc >= adev->mode_info.num_crtc) { 3110 DRM_DEBUG("invalid crtc %d\n", crtc); 3111 return; 3112 } 3113 3114 switch (state) { 3115 case AMDGPU_IRQ_STATE_DISABLE: 3116 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3117 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3118 VLINE_INTERRUPT_MASK, 0); 3119 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3120 break; 3121 case AMDGPU_IRQ_STATE_ENABLE: 3122 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3123 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3124 VLINE_INTERRUPT_MASK, 1); 3125 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3126 break; 3127 default: 3128 break; 3129 } 3130 } 3131 3132 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3133 struct amdgpu_irq_src *source, 3134 unsigned hpd, 3135 enum amdgpu_interrupt_state state) 3136 { 3137 u32 tmp; 3138 3139 if (hpd >= adev->mode_info.num_hpd) { 3140 DRM_DEBUG("invalid hdp %d\n", hpd); 3141 return 0; 3142 } 3143 3144 switch (state) { 3145 case AMDGPU_IRQ_STATE_DISABLE: 3146 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3147 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3148 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3149 break; 3150 case AMDGPU_IRQ_STATE_ENABLE: 3151 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3152 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3153 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3154 break; 3155 default: 3156 break; 3157 } 3158 3159 return 0; 3160 } 3161 3162 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3163 struct amdgpu_irq_src *source, 3164 unsigned type, 3165 enum amdgpu_interrupt_state state) 3166 { 3167 switch (type) { 3168 case AMDGPU_CRTC_IRQ_VBLANK1: 3169 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3170 break; 3171 case AMDGPU_CRTC_IRQ_VBLANK2: 3172 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3173 break; 3174 case AMDGPU_CRTC_IRQ_VBLANK3: 3175 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3176 break; 3177 case AMDGPU_CRTC_IRQ_VBLANK4: 3178 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3179 break; 3180 case AMDGPU_CRTC_IRQ_VBLANK5: 3181 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3182 break; 3183 case AMDGPU_CRTC_IRQ_VBLANK6: 3184 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3185 break; 3186 case AMDGPU_CRTC_IRQ_VLINE1: 3187 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3188 break; 3189 case AMDGPU_CRTC_IRQ_VLINE2: 3190 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3191 break; 3192 case AMDGPU_CRTC_IRQ_VLINE3: 3193 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3194 break; 3195 case AMDGPU_CRTC_IRQ_VLINE4: 3196 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3197 break; 3198 case AMDGPU_CRTC_IRQ_VLINE5: 3199 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3200 break; 3201 case AMDGPU_CRTC_IRQ_VLINE6: 3202 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3203 break; 3204 default: 3205 break; 3206 } 3207 return 0; 3208 } 3209 3210 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3211 struct amdgpu_irq_src *src, 3212 unsigned type, 3213 enum amdgpu_interrupt_state state) 3214 { 3215 u32 reg; 3216 3217 if (type >= adev->mode_info.num_crtc) { 3218 DRM_ERROR("invalid pageflip crtc %d\n", type); 3219 return -EINVAL; 3220 } 3221 3222 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3223 if (state == AMDGPU_IRQ_STATE_DISABLE) 3224 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3225 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3226 else 3227 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3228 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3229 3230 return 0; 3231 } 3232 3233 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3234 struct amdgpu_irq_src *source, 3235 struct amdgpu_iv_entry *entry) 3236 { 3237 unsigned long flags; 3238 unsigned crtc_id; 3239 struct amdgpu_crtc *amdgpu_crtc; 3240 struct amdgpu_flip_work *works; 3241 3242 crtc_id = (entry->src_id - 8) >> 1; 3243 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3244 3245 if (crtc_id >= adev->mode_info.num_crtc) { 3246 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3247 return -EINVAL; 3248 } 3249 3250 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3251 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3252 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3253 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3254 3255 /* IRQ could occur when in initial stage */ 3256 if(amdgpu_crtc == NULL) 3257 return 0; 3258 3259 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3260 works = amdgpu_crtc->pflip_works; 3261 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3262 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3263 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3264 amdgpu_crtc->pflip_status, 3265 AMDGPU_FLIP_SUBMITTED); 3266 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3267 return 0; 3268 } 3269 3270 /* page flip completed. clean up */ 3271 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3272 amdgpu_crtc->pflip_works = NULL; 3273 3274 /* wakeup usersapce */ 3275 if(works->event) 3276 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3277 3278 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3279 3280 drm_crtc_vblank_put(&amdgpu_crtc->base); 3281 schedule_work(&works->unpin_work); 3282 3283 return 0; 3284 } 3285 3286 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3287 int hpd) 3288 { 3289 u32 tmp; 3290 3291 if (hpd >= adev->mode_info.num_hpd) { 3292 DRM_DEBUG("invalid hdp %d\n", hpd); 3293 return; 3294 } 3295 3296 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3297 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3298 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3299 } 3300 3301 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3302 int crtc) 3303 { 3304 u32 tmp; 3305 3306 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3307 DRM_DEBUG("invalid crtc %d\n", crtc); 3308 return; 3309 } 3310 3311 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3312 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3313 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3314 } 3315 3316 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3317 int crtc) 3318 { 3319 u32 tmp; 3320 3321 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3322 DRM_DEBUG("invalid crtc %d\n", crtc); 3323 return; 3324 } 3325 3326 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3327 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3328 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3329 } 3330 3331 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3332 struct amdgpu_irq_src *source, 3333 struct amdgpu_iv_entry *entry) 3334 { 3335 unsigned crtc = entry->src_id - 1; 3336 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3337 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, 3338 crtc); 3339 3340 switch (entry->src_data[0]) { 3341 case 0: /* vblank */ 3342 if (disp_int & interrupt_status_offsets[crtc].vblank) 3343 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3344 else 3345 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3346 3347 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3348 drm_handle_vblank(adev->ddev, crtc); 3349 } 3350 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3351 3352 break; 3353 case 1: /* vline */ 3354 if (disp_int & interrupt_status_offsets[crtc].vline) 3355 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3356 else 3357 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3358 3359 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3360 3361 break; 3362 default: 3363 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3364 break; 3365 } 3366 3367 return 0; 3368 } 3369 3370 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3371 struct amdgpu_irq_src *source, 3372 struct amdgpu_iv_entry *entry) 3373 { 3374 uint32_t disp_int, mask; 3375 unsigned hpd; 3376 3377 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3378 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3379 return 0; 3380 } 3381 3382 hpd = entry->src_data[0]; 3383 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3384 mask = interrupt_status_offsets[hpd].hpd; 3385 3386 if (disp_int & mask) { 3387 dce_v11_0_hpd_int_ack(adev, hpd); 3388 schedule_work(&adev->hotplug_work); 3389 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3390 } 3391 3392 return 0; 3393 } 3394 3395 static int dce_v11_0_set_clockgating_state(void *handle, 3396 enum amd_clockgating_state state) 3397 { 3398 return 0; 3399 } 3400 3401 static int dce_v11_0_set_powergating_state(void *handle, 3402 enum amd_powergating_state state) 3403 { 3404 return 0; 3405 } 3406 3407 static const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3408 .name = "dce_v11_0", 3409 .early_init = dce_v11_0_early_init, 3410 .late_init = NULL, 3411 .sw_init = dce_v11_0_sw_init, 3412 .sw_fini = dce_v11_0_sw_fini, 3413 .hw_init = dce_v11_0_hw_init, 3414 .hw_fini = dce_v11_0_hw_fini, 3415 .suspend = dce_v11_0_suspend, 3416 .resume = dce_v11_0_resume, 3417 .is_idle = dce_v11_0_is_idle, 3418 .wait_for_idle = dce_v11_0_wait_for_idle, 3419 .soft_reset = dce_v11_0_soft_reset, 3420 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3421 .set_powergating_state = dce_v11_0_set_powergating_state, 3422 }; 3423 3424 static void 3425 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3426 struct drm_display_mode *mode, 3427 struct drm_display_mode *adjusted_mode) 3428 { 3429 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3430 3431 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3432 3433 /* need to call this here rather than in prepare() since we need some crtc info */ 3434 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3435 3436 /* set scaler clears this on some chips */ 3437 dce_v11_0_set_interleave(encoder->crtc, mode); 3438 3439 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3440 dce_v11_0_afmt_enable(encoder, true); 3441 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3442 } 3443 } 3444 3445 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3446 { 3447 struct amdgpu_device *adev = encoder->dev->dev_private; 3448 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3449 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3450 3451 if ((amdgpu_encoder->active_device & 3452 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3453 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3454 ENCODER_OBJECT_ID_NONE)) { 3455 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3456 if (dig) { 3457 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3458 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3459 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3460 } 3461 } 3462 3463 amdgpu_atombios_scratch_regs_lock(adev, true); 3464 3465 if (connector) { 3466 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3467 3468 /* select the clock/data port if it uses a router */ 3469 if (amdgpu_connector->router.cd_valid) 3470 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3471 3472 /* turn eDP panel on for mode set */ 3473 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3474 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3475 ATOM_TRANSMITTER_ACTION_POWER_ON); 3476 } 3477 3478 /* this is needed for the pll/ss setup to work correctly in some cases */ 3479 amdgpu_atombios_encoder_set_crtc_source(encoder); 3480 /* set up the FMT blocks */ 3481 dce_v11_0_program_fmt(encoder); 3482 } 3483 3484 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3485 { 3486 struct drm_device *dev = encoder->dev; 3487 struct amdgpu_device *adev = dev->dev_private; 3488 3489 /* need to call this here as we need the crtc set up */ 3490 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3491 amdgpu_atombios_scratch_regs_lock(adev, false); 3492 } 3493 3494 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3495 { 3496 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3497 struct amdgpu_encoder_atom_dig *dig; 3498 3499 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3500 3501 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3502 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3503 dce_v11_0_afmt_enable(encoder, false); 3504 dig = amdgpu_encoder->enc_priv; 3505 dig->dig_encoder = -1; 3506 } 3507 amdgpu_encoder->active_device = 0; 3508 } 3509 3510 /* these are handled by the primary encoders */ 3511 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3512 { 3513 3514 } 3515 3516 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3517 { 3518 3519 } 3520 3521 static void 3522 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3523 struct drm_display_mode *mode, 3524 struct drm_display_mode *adjusted_mode) 3525 { 3526 3527 } 3528 3529 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3530 { 3531 3532 } 3533 3534 static void 3535 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3536 { 3537 3538 } 3539 3540 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3541 .dpms = dce_v11_0_ext_dpms, 3542 .prepare = dce_v11_0_ext_prepare, 3543 .mode_set = dce_v11_0_ext_mode_set, 3544 .commit = dce_v11_0_ext_commit, 3545 .disable = dce_v11_0_ext_disable, 3546 /* no detect for TMDS/LVDS yet */ 3547 }; 3548 3549 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3550 .dpms = amdgpu_atombios_encoder_dpms, 3551 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3552 .prepare = dce_v11_0_encoder_prepare, 3553 .mode_set = dce_v11_0_encoder_mode_set, 3554 .commit = dce_v11_0_encoder_commit, 3555 .disable = dce_v11_0_encoder_disable, 3556 .detect = amdgpu_atombios_encoder_dig_detect, 3557 }; 3558 3559 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3560 .dpms = amdgpu_atombios_encoder_dpms, 3561 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3562 .prepare = dce_v11_0_encoder_prepare, 3563 .mode_set = dce_v11_0_encoder_mode_set, 3564 .commit = dce_v11_0_encoder_commit, 3565 .detect = amdgpu_atombios_encoder_dac_detect, 3566 }; 3567 3568 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3569 { 3570 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3571 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3572 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3573 kfree(amdgpu_encoder->enc_priv); 3574 drm_encoder_cleanup(encoder); 3575 kfree(amdgpu_encoder); 3576 } 3577 3578 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3579 .destroy = dce_v11_0_encoder_destroy, 3580 }; 3581 3582 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3583 uint32_t encoder_enum, 3584 uint32_t supported_device, 3585 u16 caps) 3586 { 3587 struct drm_device *dev = adev->ddev; 3588 struct drm_encoder *encoder; 3589 struct amdgpu_encoder *amdgpu_encoder; 3590 3591 /* see if we already added it */ 3592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3593 amdgpu_encoder = to_amdgpu_encoder(encoder); 3594 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3595 amdgpu_encoder->devices |= supported_device; 3596 return; 3597 } 3598 3599 } 3600 3601 /* add a new one */ 3602 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3603 if (!amdgpu_encoder) 3604 return; 3605 3606 encoder = &amdgpu_encoder->base; 3607 switch (adev->mode_info.num_crtc) { 3608 case 1: 3609 encoder->possible_crtcs = 0x1; 3610 break; 3611 case 2: 3612 default: 3613 encoder->possible_crtcs = 0x3; 3614 break; 3615 case 3: 3616 encoder->possible_crtcs = 0x7; 3617 break; 3618 case 4: 3619 encoder->possible_crtcs = 0xf; 3620 break; 3621 case 5: 3622 encoder->possible_crtcs = 0x1f; 3623 break; 3624 case 6: 3625 encoder->possible_crtcs = 0x3f; 3626 break; 3627 } 3628 3629 amdgpu_encoder->enc_priv = NULL; 3630 3631 amdgpu_encoder->encoder_enum = encoder_enum; 3632 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3633 amdgpu_encoder->devices = supported_device; 3634 amdgpu_encoder->rmx_type = RMX_OFF; 3635 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3636 amdgpu_encoder->is_ext_encoder = false; 3637 amdgpu_encoder->caps = caps; 3638 3639 switch (amdgpu_encoder->encoder_id) { 3640 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3641 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3642 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3643 DRM_MODE_ENCODER_DAC, NULL); 3644 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3645 break; 3646 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3647 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3648 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3649 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3650 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3651 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3652 amdgpu_encoder->rmx_type = RMX_FULL; 3653 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3654 DRM_MODE_ENCODER_LVDS, NULL); 3655 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3656 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3657 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3658 DRM_MODE_ENCODER_DAC, NULL); 3659 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3660 } else { 3661 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3662 DRM_MODE_ENCODER_TMDS, NULL); 3663 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3664 } 3665 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3666 break; 3667 case ENCODER_OBJECT_ID_SI170B: 3668 case ENCODER_OBJECT_ID_CH7303: 3669 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3670 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3671 case ENCODER_OBJECT_ID_TITFP513: 3672 case ENCODER_OBJECT_ID_VT1623: 3673 case ENCODER_OBJECT_ID_HDMI_SI1930: 3674 case ENCODER_OBJECT_ID_TRAVIS: 3675 case ENCODER_OBJECT_ID_NUTMEG: 3676 /* these are handled by the primary encoders */ 3677 amdgpu_encoder->is_ext_encoder = true; 3678 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3679 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3680 DRM_MODE_ENCODER_LVDS, NULL); 3681 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3682 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3683 DRM_MODE_ENCODER_DAC, NULL); 3684 else 3685 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3686 DRM_MODE_ENCODER_TMDS, NULL); 3687 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3688 break; 3689 } 3690 } 3691 3692 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3693 .bandwidth_update = &dce_v11_0_bandwidth_update, 3694 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3695 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3696 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3697 .hpd_sense = &dce_v11_0_hpd_sense, 3698 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3699 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3700 .page_flip = &dce_v11_0_page_flip, 3701 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3702 .add_encoder = &dce_v11_0_encoder_add, 3703 .add_connector = &amdgpu_connector_add, 3704 }; 3705 3706 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3707 { 3708 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3709 } 3710 3711 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3712 .set = dce_v11_0_set_crtc_irq_state, 3713 .process = dce_v11_0_crtc_irq, 3714 }; 3715 3716 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3717 .set = dce_v11_0_set_pageflip_irq_state, 3718 .process = dce_v11_0_pageflip_irq, 3719 }; 3720 3721 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3722 .set = dce_v11_0_set_hpd_irq_state, 3723 .process = dce_v11_0_hpd_irq, 3724 }; 3725 3726 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3727 { 3728 if (adev->mode_info.num_crtc > 0) 3729 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3730 else 3731 adev->crtc_irq.num_types = 0; 3732 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3733 3734 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3735 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3736 3737 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3738 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3739 } 3740 3741 const struct amdgpu_ip_block_version dce_v11_0_ip_block = 3742 { 3743 .type = AMD_IP_BLOCK_TYPE_DCE, 3744 .major = 11, 3745 .minor = 0, 3746 .rev = 0, 3747 .funcs = &dce_v11_0_ip_funcs, 3748 }; 3749 3750 const struct amdgpu_ip_block_version dce_v11_2_ip_block = 3751 { 3752 .type = AMD_IP_BLOCK_TYPE_DCE, 3753 .major = 11, 3754 .minor = 2, 3755 .rev = 0, 3756 .funcs = &dce_v11_0_ip_funcs, 3757 }; 3758