1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 #include "dce_v11_0.h" 35 36 #include "dce/dce_11_0_d.h" 37 #include "dce/dce_11_0_sh_mask.h" 38 #include "dce/dce_11_0_enum.h" 39 #include "oss/oss_3_0_d.h" 40 #include "oss/oss_3_0_sh_mask.h" 41 #include "gmc/gmc_8_1_d.h" 42 #include "gmc/gmc_8_1_sh_mask.h" 43 44 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 45 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 46 47 static const u32 crtc_offsets[] = 48 { 49 CRTC0_REGISTER_OFFSET, 50 CRTC1_REGISTER_OFFSET, 51 CRTC2_REGISTER_OFFSET, 52 CRTC3_REGISTER_OFFSET, 53 CRTC4_REGISTER_OFFSET, 54 CRTC5_REGISTER_OFFSET, 55 CRTC6_REGISTER_OFFSET 56 }; 57 58 static const u32 hpd_offsets[] = 59 { 60 HPD0_REGISTER_OFFSET, 61 HPD1_REGISTER_OFFSET, 62 HPD2_REGISTER_OFFSET, 63 HPD3_REGISTER_OFFSET, 64 HPD4_REGISTER_OFFSET, 65 HPD5_REGISTER_OFFSET 66 }; 67 68 static const uint32_t dig_offsets[] = { 69 DIG0_REGISTER_OFFSET, 70 DIG1_REGISTER_OFFSET, 71 DIG2_REGISTER_OFFSET, 72 DIG3_REGISTER_OFFSET, 73 DIG4_REGISTER_OFFSET, 74 DIG5_REGISTER_OFFSET, 75 DIG6_REGISTER_OFFSET, 76 DIG7_REGISTER_OFFSET, 77 DIG8_REGISTER_OFFSET 78 }; 79 80 static const struct { 81 uint32_t reg; 82 uint32_t vblank; 83 uint32_t vline; 84 uint32_t hpd; 85 86 } interrupt_status_offsets[] = { { 87 .reg = mmDISP_INTERRUPT_STATUS, 88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 91 }, { 92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 96 }, { 97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 101 }, { 102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 106 }, { 107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 111 }, { 112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 116 } }; 117 118 static const u32 cz_golden_settings_a11[] = 119 { 120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 121 mmFBC_MISC, 0x1f311fff, 0x14300000, 122 }; 123 124 static const u32 cz_mgcg_cgcg_init[] = 125 { 126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 128 }; 129 130 static const u32 stoney_golden_settings_a11[] = 131 { 132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 133 mmFBC_MISC, 0x1f311fff, 0x14302000, 134 }; 135 136 static const u32 polaris11_golden_settings_a11[] = 137 { 138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 140 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 141 mmFBC_MISC, 0x9f313fff, 0x14302008, 142 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 143 }; 144 145 static const u32 polaris10_golden_settings_a11[] = 146 { 147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 149 mmFBC_MISC, 0x9f313fff, 0x14302008, 150 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 151 }; 152 153 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 154 { 155 switch (adev->asic_type) { 156 case CHIP_CARRIZO: 157 amdgpu_program_register_sequence(adev, 158 cz_mgcg_cgcg_init, 159 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 160 amdgpu_program_register_sequence(adev, 161 cz_golden_settings_a11, 162 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 163 break; 164 case CHIP_STONEY: 165 amdgpu_program_register_sequence(adev, 166 stoney_golden_settings_a11, 167 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 168 break; 169 case CHIP_POLARIS11: 170 case CHIP_POLARIS12: 171 amdgpu_program_register_sequence(adev, 172 polaris11_golden_settings_a11, 173 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); 174 break; 175 case CHIP_POLARIS10: 176 amdgpu_program_register_sequence(adev, 177 polaris10_golden_settings_a11, 178 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); 179 break; 180 default: 181 break; 182 } 183 } 184 185 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 186 u32 block_offset, u32 reg) 187 { 188 unsigned long flags; 189 u32 r; 190 191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 195 196 return r; 197 } 198 199 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 200 u32 block_offset, u32 reg, u32 v) 201 { 202 unsigned long flags; 203 204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 208 } 209 210 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 211 { 212 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 213 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 214 return true; 215 else 216 return false; 217 } 218 219 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 220 { 221 u32 pos1, pos2; 222 223 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 224 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 225 226 if (pos1 != pos2) 227 return true; 228 else 229 return false; 230 } 231 232 /** 233 * dce_v11_0_vblank_wait - vblank wait asic callback. 234 * 235 * @adev: amdgpu_device pointer 236 * @crtc: crtc to wait for vblank on 237 * 238 * Wait for vblank on the requested crtc (evergreen+). 239 */ 240 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 241 { 242 unsigned i = 100; 243 244 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 245 return; 246 247 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 248 return; 249 250 /* depending on when we hit vblank, we may be close to active; if so, 251 * wait for another frame. 252 */ 253 while (dce_v11_0_is_in_vblank(adev, crtc)) { 254 if (i++ == 100) { 255 i = 0; 256 if (!dce_v11_0_is_counter_moving(adev, crtc)) 257 break; 258 } 259 } 260 261 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 262 if (i++ == 100) { 263 i = 0; 264 if (!dce_v11_0_is_counter_moving(adev, crtc)) 265 break; 266 } 267 } 268 } 269 270 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 271 { 272 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 273 return 0; 274 else 275 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 276 } 277 278 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 279 { 280 unsigned i; 281 282 /* Enable pflip interrupts */ 283 for (i = 0; i < adev->mode_info.num_crtc; i++) 284 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 285 } 286 287 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 288 { 289 unsigned i; 290 291 /* Disable pflip interrupts */ 292 for (i = 0; i < adev->mode_info.num_crtc; i++) 293 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 294 } 295 296 /** 297 * dce_v11_0_page_flip - pageflip callback. 298 * 299 * @adev: amdgpu_device pointer 300 * @crtc_id: crtc to cleanup pageflip on 301 * @crtc_base: new address of the crtc (GPU MC address) 302 * 303 * Triggers the actual pageflip by updating the primary 304 * surface base address. 305 */ 306 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 307 int crtc_id, u64 crtc_base, bool async) 308 { 309 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 310 u32 tmp; 311 312 /* flip immediate for async, default is vsync */ 313 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 314 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 315 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 316 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 317 /* update the scanout addresses */ 318 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 319 upper_32_bits(crtc_base)); 320 /* writing to the low address triggers the update */ 321 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 322 lower_32_bits(crtc_base)); 323 /* post the write */ 324 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 325 } 326 327 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 328 u32 *vbl, u32 *position) 329 { 330 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 331 return -EINVAL; 332 333 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 334 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 335 336 return 0; 337 } 338 339 /** 340 * dce_v11_0_hpd_sense - hpd sense callback. 341 * 342 * @adev: amdgpu_device pointer 343 * @hpd: hpd (hotplug detect) pin 344 * 345 * Checks if a digital monitor is connected (evergreen+). 346 * Returns true if connected, false if not connected. 347 */ 348 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 349 enum amdgpu_hpd_id hpd) 350 { 351 bool connected = false; 352 353 if (hpd >= adev->mode_info.num_hpd) 354 return connected; 355 356 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 357 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 358 connected = true; 359 360 return connected; 361 } 362 363 /** 364 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 365 * 366 * @adev: amdgpu_device pointer 367 * @hpd: hpd (hotplug detect) pin 368 * 369 * Set the polarity of the hpd pin (evergreen+). 370 */ 371 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 372 enum amdgpu_hpd_id hpd) 373 { 374 u32 tmp; 375 bool connected = dce_v11_0_hpd_sense(adev, hpd); 376 377 if (hpd >= adev->mode_info.num_hpd) 378 return; 379 380 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 381 if (connected) 382 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 383 else 384 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 385 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 386 } 387 388 /** 389 * dce_v11_0_hpd_init - hpd setup callback. 390 * 391 * @adev: amdgpu_device pointer 392 * 393 * Setup the hpd pins used by the card (evergreen+). 394 * Enable the pin, set the polarity, and enable the hpd interrupts. 395 */ 396 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 397 { 398 struct drm_device *dev = adev->ddev; 399 struct drm_connector *connector; 400 u32 tmp; 401 402 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 403 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 404 405 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 406 continue; 407 408 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 409 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 410 /* don't try to enable hpd on eDP or LVDS avoid breaking the 411 * aux dp channel on imac and help (but not completely fix) 412 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 413 * also avoid interrupt storms during dpms. 414 */ 415 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 416 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 417 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 418 continue; 419 } 420 421 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 422 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 423 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 424 425 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 426 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 427 DC_HPD_CONNECT_INT_DELAY, 428 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 429 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 430 DC_HPD_DISCONNECT_INT_DELAY, 431 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 432 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 433 434 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 435 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 436 } 437 } 438 439 /** 440 * dce_v11_0_hpd_fini - hpd tear down callback. 441 * 442 * @adev: amdgpu_device pointer 443 * 444 * Tear down the hpd pins used by the card (evergreen+). 445 * Disable the hpd interrupts. 446 */ 447 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 448 { 449 struct drm_device *dev = adev->ddev; 450 struct drm_connector *connector; 451 u32 tmp; 452 453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 454 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 455 456 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 457 continue; 458 459 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 460 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 461 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 462 463 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 464 } 465 } 466 467 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 468 { 469 return mmDC_GPIO_HPD_A; 470 } 471 472 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 473 { 474 u32 crtc_hung = 0; 475 u32 crtc_status[6]; 476 u32 i, j, tmp; 477 478 for (i = 0; i < adev->mode_info.num_crtc; i++) { 479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 480 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 481 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 482 crtc_hung |= (1 << i); 483 } 484 } 485 486 for (j = 0; j < 10; j++) { 487 for (i = 0; i < adev->mode_info.num_crtc; i++) { 488 if (crtc_hung & (1 << i)) { 489 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 490 if (tmp != crtc_status[i]) 491 crtc_hung &= ~(1 << i); 492 } 493 } 494 if (crtc_hung == 0) 495 return false; 496 udelay(100); 497 } 498 499 return true; 500 } 501 502 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 503 struct amdgpu_mode_mc_save *save) 504 { 505 u32 crtc_enabled, tmp; 506 int i; 507 508 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 509 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 510 511 /* disable VGA render */ 512 tmp = RREG32(mmVGA_RENDER_CONTROL); 513 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 514 WREG32(mmVGA_RENDER_CONTROL, tmp); 515 516 /* blank the display controllers */ 517 for (i = 0; i < adev->mode_info.num_crtc; i++) { 518 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 519 CRTC_CONTROL, CRTC_MASTER_EN); 520 if (crtc_enabled) { 521 #if 1 522 save->crtc_enabled[i] = true; 523 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 524 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 525 /*it is correct only for RGB ; black is 0*/ 526 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 527 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 528 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 529 } 530 #else 531 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 532 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 533 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 534 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 535 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 536 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 537 save->crtc_enabled[i] = false; 538 /* ***** */ 539 #endif 540 } else { 541 save->crtc_enabled[i] = false; 542 } 543 } 544 } 545 546 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 547 struct amdgpu_mode_mc_save *save) 548 { 549 u32 tmp; 550 int i; 551 552 /* update crtc base addresses */ 553 for (i = 0; i < adev->mode_info.num_crtc; i++) { 554 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 555 upper_32_bits(adev->mc.vram_start)); 556 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 557 (u32)adev->mc.vram_start); 558 559 if (save->crtc_enabled[i]) { 560 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 561 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 562 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 563 } 564 } 565 566 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 567 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 568 569 /* Unlock vga access */ 570 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 571 mdelay(1); 572 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 573 } 574 575 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 576 bool render) 577 { 578 u32 tmp; 579 580 /* Lockout access through VGA aperture*/ 581 tmp = RREG32(mmVGA_HDP_CONTROL); 582 if (render) 583 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 584 else 585 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 586 WREG32(mmVGA_HDP_CONTROL, tmp); 587 588 /* disable VGA render */ 589 tmp = RREG32(mmVGA_RENDER_CONTROL); 590 if (render) 591 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 592 else 593 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 594 WREG32(mmVGA_RENDER_CONTROL, tmp); 595 } 596 597 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) 598 { 599 int num_crtc = 0; 600 601 switch (adev->asic_type) { 602 case CHIP_CARRIZO: 603 num_crtc = 3; 604 break; 605 case CHIP_STONEY: 606 num_crtc = 2; 607 break; 608 case CHIP_POLARIS10: 609 num_crtc = 6; 610 break; 611 case CHIP_POLARIS11: 612 case CHIP_POLARIS12: 613 num_crtc = 5; 614 break; 615 default: 616 num_crtc = 0; 617 } 618 return num_crtc; 619 } 620 621 void dce_v11_0_disable_dce(struct amdgpu_device *adev) 622 { 623 /*Disable VGA render and enabled crtc, if has DCE engine*/ 624 if (amdgpu_atombios_has_dce_engine_info(adev)) { 625 u32 tmp; 626 int crtc_enabled, i; 627 628 dce_v11_0_set_vga_render_state(adev, false); 629 630 /*Disable crtc*/ 631 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { 632 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 633 CRTC_CONTROL, CRTC_MASTER_EN); 634 if (crtc_enabled) { 635 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 636 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 637 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 638 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 639 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 640 } 641 } 642 } 643 } 644 645 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 646 { 647 struct drm_device *dev = encoder->dev; 648 struct amdgpu_device *adev = dev->dev_private; 649 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 650 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 651 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 652 int bpc = 0; 653 u32 tmp = 0; 654 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 655 656 if (connector) { 657 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 658 bpc = amdgpu_connector_get_monitor_bpc(connector); 659 dither = amdgpu_connector->dither; 660 } 661 662 /* LVDS/eDP FMT is set up by atom */ 663 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 664 return; 665 666 /* not needed for analog */ 667 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 668 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 669 return; 670 671 if (bpc == 0) 672 return; 673 674 switch (bpc) { 675 case 6: 676 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 677 /* XXX sort out optimal dither settings */ 678 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 679 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 680 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 681 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 682 } else { 683 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 684 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 685 } 686 break; 687 case 8: 688 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 689 /* XXX sort out optimal dither settings */ 690 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 691 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 692 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 693 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 694 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 695 } else { 696 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 697 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 698 } 699 break; 700 case 10: 701 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 702 /* XXX sort out optimal dither settings */ 703 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 704 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 705 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 706 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 707 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 708 } else { 709 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 710 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 711 } 712 break; 713 default: 714 /* not needed */ 715 break; 716 } 717 718 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 719 } 720 721 722 /* display watermark setup */ 723 /** 724 * dce_v11_0_line_buffer_adjust - Set up the line buffer 725 * 726 * @adev: amdgpu_device pointer 727 * @amdgpu_crtc: the selected display controller 728 * @mode: the current display mode on the selected display 729 * controller 730 * 731 * Setup up the line buffer allocation for 732 * the selected display controller (CIK). 733 * Returns the line buffer size in pixels. 734 */ 735 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 736 struct amdgpu_crtc *amdgpu_crtc, 737 struct drm_display_mode *mode) 738 { 739 u32 tmp, buffer_alloc, i, mem_cfg; 740 u32 pipe_offset = amdgpu_crtc->crtc_id; 741 /* 742 * Line Buffer Setup 743 * There are 6 line buffers, one for each display controllers. 744 * There are 3 partitions per LB. Select the number of partitions 745 * to enable based on the display width. For display widths larger 746 * than 4096, you need use to use 2 display controllers and combine 747 * them using the stereo blender. 748 */ 749 if (amdgpu_crtc->base.enabled && mode) { 750 if (mode->crtc_hdisplay < 1920) { 751 mem_cfg = 1; 752 buffer_alloc = 2; 753 } else if (mode->crtc_hdisplay < 2560) { 754 mem_cfg = 2; 755 buffer_alloc = 2; 756 } else if (mode->crtc_hdisplay < 4096) { 757 mem_cfg = 0; 758 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 759 } else { 760 DRM_DEBUG_KMS("Mode too big for LB!\n"); 761 mem_cfg = 0; 762 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 763 } 764 } else { 765 mem_cfg = 1; 766 buffer_alloc = 0; 767 } 768 769 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 770 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 771 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 772 773 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 774 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 775 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 776 777 for (i = 0; i < adev->usec_timeout; i++) { 778 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 779 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 780 break; 781 udelay(1); 782 } 783 784 if (amdgpu_crtc->base.enabled && mode) { 785 switch (mem_cfg) { 786 case 0: 787 default: 788 return 4096 * 2; 789 case 1: 790 return 1920 * 2; 791 case 2: 792 return 2560 * 2; 793 } 794 } 795 796 /* controller not enabled, so no lb used */ 797 return 0; 798 } 799 800 /** 801 * cik_get_number_of_dram_channels - get the number of dram channels 802 * 803 * @adev: amdgpu_device pointer 804 * 805 * Look up the number of video ram channels (CIK). 806 * Used for display watermark bandwidth calculations 807 * Returns the number of dram channels 808 */ 809 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 810 { 811 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 812 813 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 814 case 0: 815 default: 816 return 1; 817 case 1: 818 return 2; 819 case 2: 820 return 4; 821 case 3: 822 return 8; 823 case 4: 824 return 3; 825 case 5: 826 return 6; 827 case 6: 828 return 10; 829 case 7: 830 return 12; 831 case 8: 832 return 16; 833 } 834 } 835 836 struct dce10_wm_params { 837 u32 dram_channels; /* number of dram channels */ 838 u32 yclk; /* bandwidth per dram data pin in kHz */ 839 u32 sclk; /* engine clock in kHz */ 840 u32 disp_clk; /* display clock in kHz */ 841 u32 src_width; /* viewport width */ 842 u32 active_time; /* active display time in ns */ 843 u32 blank_time; /* blank time in ns */ 844 bool interlaced; /* mode is interlaced */ 845 fixed20_12 vsc; /* vertical scale ratio */ 846 u32 num_heads; /* number of active crtcs */ 847 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 848 u32 lb_size; /* line buffer allocated to pipe */ 849 u32 vtaps; /* vertical scaler taps */ 850 }; 851 852 /** 853 * dce_v11_0_dram_bandwidth - get the dram bandwidth 854 * 855 * @wm: watermark calculation data 856 * 857 * Calculate the raw dram bandwidth (CIK). 858 * Used for display watermark bandwidth calculations 859 * Returns the dram bandwidth in MBytes/s 860 */ 861 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 862 { 863 /* Calculate raw DRAM Bandwidth */ 864 fixed20_12 dram_efficiency; /* 0.7 */ 865 fixed20_12 yclk, dram_channels, bandwidth; 866 fixed20_12 a; 867 868 a.full = dfixed_const(1000); 869 yclk.full = dfixed_const(wm->yclk); 870 yclk.full = dfixed_div(yclk, a); 871 dram_channels.full = dfixed_const(wm->dram_channels * 4); 872 a.full = dfixed_const(10); 873 dram_efficiency.full = dfixed_const(7); 874 dram_efficiency.full = dfixed_div(dram_efficiency, a); 875 bandwidth.full = dfixed_mul(dram_channels, yclk); 876 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 877 878 return dfixed_trunc(bandwidth); 879 } 880 881 /** 882 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 883 * 884 * @wm: watermark calculation data 885 * 886 * Calculate the dram bandwidth used for display (CIK). 887 * Used for display watermark bandwidth calculations 888 * Returns the dram bandwidth for display in MBytes/s 889 */ 890 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 891 { 892 /* Calculate DRAM Bandwidth and the part allocated to display. */ 893 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 894 fixed20_12 yclk, dram_channels, bandwidth; 895 fixed20_12 a; 896 897 a.full = dfixed_const(1000); 898 yclk.full = dfixed_const(wm->yclk); 899 yclk.full = dfixed_div(yclk, a); 900 dram_channels.full = dfixed_const(wm->dram_channels * 4); 901 a.full = dfixed_const(10); 902 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 903 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 904 bandwidth.full = dfixed_mul(dram_channels, yclk); 905 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 906 907 return dfixed_trunc(bandwidth); 908 } 909 910 /** 911 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 912 * 913 * @wm: watermark calculation data 914 * 915 * Calculate the data return bandwidth used for display (CIK). 916 * Used for display watermark bandwidth calculations 917 * Returns the data return bandwidth in MBytes/s 918 */ 919 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 920 { 921 /* Calculate the display Data return Bandwidth */ 922 fixed20_12 return_efficiency; /* 0.8 */ 923 fixed20_12 sclk, bandwidth; 924 fixed20_12 a; 925 926 a.full = dfixed_const(1000); 927 sclk.full = dfixed_const(wm->sclk); 928 sclk.full = dfixed_div(sclk, a); 929 a.full = dfixed_const(10); 930 return_efficiency.full = dfixed_const(8); 931 return_efficiency.full = dfixed_div(return_efficiency, a); 932 a.full = dfixed_const(32); 933 bandwidth.full = dfixed_mul(a, sclk); 934 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 935 936 return dfixed_trunc(bandwidth); 937 } 938 939 /** 940 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 941 * 942 * @wm: watermark calculation data 943 * 944 * Calculate the dmif bandwidth used for display (CIK). 945 * Used for display watermark bandwidth calculations 946 * Returns the dmif bandwidth in MBytes/s 947 */ 948 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 949 { 950 /* Calculate the DMIF Request Bandwidth */ 951 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 952 fixed20_12 disp_clk, bandwidth; 953 fixed20_12 a, b; 954 955 a.full = dfixed_const(1000); 956 disp_clk.full = dfixed_const(wm->disp_clk); 957 disp_clk.full = dfixed_div(disp_clk, a); 958 a.full = dfixed_const(32); 959 b.full = dfixed_mul(a, disp_clk); 960 961 a.full = dfixed_const(10); 962 disp_clk_request_efficiency.full = dfixed_const(8); 963 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 964 965 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 966 967 return dfixed_trunc(bandwidth); 968 } 969 970 /** 971 * dce_v11_0_available_bandwidth - get the min available bandwidth 972 * 973 * @wm: watermark calculation data 974 * 975 * Calculate the min available bandwidth used for display (CIK). 976 * Used for display watermark bandwidth calculations 977 * Returns the min available bandwidth in MBytes/s 978 */ 979 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 980 { 981 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 982 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 983 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 984 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 985 986 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 987 } 988 989 /** 990 * dce_v11_0_average_bandwidth - get the average available bandwidth 991 * 992 * @wm: watermark calculation data 993 * 994 * Calculate the average available bandwidth used for display (CIK). 995 * Used for display watermark bandwidth calculations 996 * Returns the average available bandwidth in MBytes/s 997 */ 998 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 999 { 1000 /* Calculate the display mode Average Bandwidth 1001 * DisplayMode should contain the source and destination dimensions, 1002 * timing, etc. 1003 */ 1004 fixed20_12 bpp; 1005 fixed20_12 line_time; 1006 fixed20_12 src_width; 1007 fixed20_12 bandwidth; 1008 fixed20_12 a; 1009 1010 a.full = dfixed_const(1000); 1011 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1012 line_time.full = dfixed_div(line_time, a); 1013 bpp.full = dfixed_const(wm->bytes_per_pixel); 1014 src_width.full = dfixed_const(wm->src_width); 1015 bandwidth.full = dfixed_mul(src_width, bpp); 1016 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1017 bandwidth.full = dfixed_div(bandwidth, line_time); 1018 1019 return dfixed_trunc(bandwidth); 1020 } 1021 1022 /** 1023 * dce_v11_0_latency_watermark - get the latency watermark 1024 * 1025 * @wm: watermark calculation data 1026 * 1027 * Calculate the latency watermark (CIK). 1028 * Used for display watermark bandwidth calculations 1029 * Returns the latency watermark in ns 1030 */ 1031 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1032 { 1033 /* First calculate the latency in ns */ 1034 u32 mc_latency = 2000; /* 2000 ns. */ 1035 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1036 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1037 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1038 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1039 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1040 (wm->num_heads * cursor_line_pair_return_time); 1041 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1042 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1043 u32 tmp, dmif_size = 12288; 1044 fixed20_12 a, b, c; 1045 1046 if (wm->num_heads == 0) 1047 return 0; 1048 1049 a.full = dfixed_const(2); 1050 b.full = dfixed_const(1); 1051 if ((wm->vsc.full > a.full) || 1052 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1053 (wm->vtaps >= 5) || 1054 ((wm->vsc.full >= a.full) && wm->interlaced)) 1055 max_src_lines_per_dst_line = 4; 1056 else 1057 max_src_lines_per_dst_line = 2; 1058 1059 a.full = dfixed_const(available_bandwidth); 1060 b.full = dfixed_const(wm->num_heads); 1061 a.full = dfixed_div(a, b); 1062 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 1063 tmp = min(dfixed_trunc(a), tmp); 1064 1065 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 1066 1067 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1068 b.full = dfixed_const(1000); 1069 c.full = dfixed_const(lb_fill_bw); 1070 b.full = dfixed_div(c, b); 1071 a.full = dfixed_div(a, b); 1072 line_fill_time = dfixed_trunc(a); 1073 1074 if (line_fill_time < wm->active_time) 1075 return latency; 1076 else 1077 return latency + (line_fill_time - wm->active_time); 1078 1079 } 1080 1081 /** 1082 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1083 * average and available dram bandwidth 1084 * 1085 * @wm: watermark calculation data 1086 * 1087 * Check if the display average bandwidth fits in the display 1088 * dram bandwidth (CIK). 1089 * Used for display watermark bandwidth calculations 1090 * Returns true if the display fits, false if not. 1091 */ 1092 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1093 { 1094 if (dce_v11_0_average_bandwidth(wm) <= 1095 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1096 return true; 1097 else 1098 return false; 1099 } 1100 1101 /** 1102 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1103 * average and available bandwidth 1104 * 1105 * @wm: watermark calculation data 1106 * 1107 * Check if the display average bandwidth fits in the display 1108 * available bandwidth (CIK). 1109 * Used for display watermark bandwidth calculations 1110 * Returns true if the display fits, false if not. 1111 */ 1112 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1113 { 1114 if (dce_v11_0_average_bandwidth(wm) <= 1115 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1116 return true; 1117 else 1118 return false; 1119 } 1120 1121 /** 1122 * dce_v11_0_check_latency_hiding - check latency hiding 1123 * 1124 * @wm: watermark calculation data 1125 * 1126 * Check latency hiding (CIK). 1127 * Used for display watermark bandwidth calculations 1128 * Returns true if the display fits, false if not. 1129 */ 1130 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1131 { 1132 u32 lb_partitions = wm->lb_size / wm->src_width; 1133 u32 line_time = wm->active_time + wm->blank_time; 1134 u32 latency_tolerant_lines; 1135 u32 latency_hiding; 1136 fixed20_12 a; 1137 1138 a.full = dfixed_const(1); 1139 if (wm->vsc.full > a.full) 1140 latency_tolerant_lines = 1; 1141 else { 1142 if (lb_partitions <= (wm->vtaps + 1)) 1143 latency_tolerant_lines = 1; 1144 else 1145 latency_tolerant_lines = 2; 1146 } 1147 1148 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1149 1150 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1151 return true; 1152 else 1153 return false; 1154 } 1155 1156 /** 1157 * dce_v11_0_program_watermarks - program display watermarks 1158 * 1159 * @adev: amdgpu_device pointer 1160 * @amdgpu_crtc: the selected display controller 1161 * @lb_size: line buffer size 1162 * @num_heads: number of display controllers in use 1163 * 1164 * Calculate and program the display watermarks for the 1165 * selected display controller (CIK). 1166 */ 1167 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1168 struct amdgpu_crtc *amdgpu_crtc, 1169 u32 lb_size, u32 num_heads) 1170 { 1171 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1172 struct dce10_wm_params wm_low, wm_high; 1173 u32 active_time; 1174 u32 line_time = 0; 1175 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1176 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1177 1178 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1179 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1180 (u32)mode->clock); 1181 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1182 (u32)mode->clock); 1183 line_time = min(line_time, (u32)65535); 1184 1185 /* watermark for high clocks */ 1186 if (adev->pm.dpm_enabled) { 1187 wm_high.yclk = 1188 amdgpu_dpm_get_mclk(adev, false) * 10; 1189 wm_high.sclk = 1190 amdgpu_dpm_get_sclk(adev, false) * 10; 1191 } else { 1192 wm_high.yclk = adev->pm.current_mclk * 10; 1193 wm_high.sclk = adev->pm.current_sclk * 10; 1194 } 1195 1196 wm_high.disp_clk = mode->clock; 1197 wm_high.src_width = mode->crtc_hdisplay; 1198 wm_high.active_time = active_time; 1199 wm_high.blank_time = line_time - wm_high.active_time; 1200 wm_high.interlaced = false; 1201 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1202 wm_high.interlaced = true; 1203 wm_high.vsc = amdgpu_crtc->vsc; 1204 wm_high.vtaps = 1; 1205 if (amdgpu_crtc->rmx_type != RMX_OFF) 1206 wm_high.vtaps = 2; 1207 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1208 wm_high.lb_size = lb_size; 1209 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1210 wm_high.num_heads = num_heads; 1211 1212 /* set for high clocks */ 1213 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1214 1215 /* possibly force display priority to high */ 1216 /* should really do this at mode validation time... */ 1217 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1218 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1219 !dce_v11_0_check_latency_hiding(&wm_high) || 1220 (adev->mode_info.disp_priority == 2)) { 1221 DRM_DEBUG_KMS("force priority to high\n"); 1222 } 1223 1224 /* watermark for low clocks */ 1225 if (adev->pm.dpm_enabled) { 1226 wm_low.yclk = 1227 amdgpu_dpm_get_mclk(adev, true) * 10; 1228 wm_low.sclk = 1229 amdgpu_dpm_get_sclk(adev, true) * 10; 1230 } else { 1231 wm_low.yclk = adev->pm.current_mclk * 10; 1232 wm_low.sclk = adev->pm.current_sclk * 10; 1233 } 1234 1235 wm_low.disp_clk = mode->clock; 1236 wm_low.src_width = mode->crtc_hdisplay; 1237 wm_low.active_time = active_time; 1238 wm_low.blank_time = line_time - wm_low.active_time; 1239 wm_low.interlaced = false; 1240 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1241 wm_low.interlaced = true; 1242 wm_low.vsc = amdgpu_crtc->vsc; 1243 wm_low.vtaps = 1; 1244 if (amdgpu_crtc->rmx_type != RMX_OFF) 1245 wm_low.vtaps = 2; 1246 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1247 wm_low.lb_size = lb_size; 1248 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1249 wm_low.num_heads = num_heads; 1250 1251 /* set for low clocks */ 1252 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1253 1254 /* possibly force display priority to high */ 1255 /* should really do this at mode validation time... */ 1256 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1257 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1258 !dce_v11_0_check_latency_hiding(&wm_low) || 1259 (adev->mode_info.disp_priority == 2)) { 1260 DRM_DEBUG_KMS("force priority to high\n"); 1261 } 1262 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1263 } 1264 1265 /* select wm A */ 1266 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1267 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1268 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1269 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1270 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1271 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1272 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1273 /* select wm B */ 1274 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1275 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1276 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1277 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1278 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1279 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1280 /* restore original selection */ 1281 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1282 1283 /* save values for DPM */ 1284 amdgpu_crtc->line_time = line_time; 1285 amdgpu_crtc->wm_high = latency_watermark_a; 1286 amdgpu_crtc->wm_low = latency_watermark_b; 1287 /* Save number of lines the linebuffer leads before the scanout */ 1288 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1289 } 1290 1291 /** 1292 * dce_v11_0_bandwidth_update - program display watermarks 1293 * 1294 * @adev: amdgpu_device pointer 1295 * 1296 * Calculate and program the display watermarks and line 1297 * buffer allocation (CIK). 1298 */ 1299 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1300 { 1301 struct drm_display_mode *mode = NULL; 1302 u32 num_heads = 0, lb_size; 1303 int i; 1304 1305 amdgpu_update_display_priority(adev); 1306 1307 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1308 if (adev->mode_info.crtcs[i]->base.enabled) 1309 num_heads++; 1310 } 1311 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1312 mode = &adev->mode_info.crtcs[i]->base.mode; 1313 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1314 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1315 lb_size, num_heads); 1316 } 1317 } 1318 1319 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1320 { 1321 int i; 1322 u32 offset, tmp; 1323 1324 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1325 offset = adev->mode_info.audio.pin[i].offset; 1326 tmp = RREG32_AUDIO_ENDPT(offset, 1327 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1328 if (((tmp & 1329 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1330 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1331 adev->mode_info.audio.pin[i].connected = false; 1332 else 1333 adev->mode_info.audio.pin[i].connected = true; 1334 } 1335 } 1336 1337 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1338 { 1339 int i; 1340 1341 dce_v11_0_audio_get_connected_pins(adev); 1342 1343 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1344 if (adev->mode_info.audio.pin[i].connected) 1345 return &adev->mode_info.audio.pin[i]; 1346 } 1347 DRM_ERROR("No connected audio pins found!\n"); 1348 return NULL; 1349 } 1350 1351 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1352 { 1353 struct amdgpu_device *adev = encoder->dev->dev_private; 1354 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1355 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1356 u32 tmp; 1357 1358 if (!dig || !dig->afmt || !dig->afmt->pin) 1359 return; 1360 1361 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1362 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1363 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1364 } 1365 1366 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1367 struct drm_display_mode *mode) 1368 { 1369 struct amdgpu_device *adev = encoder->dev->dev_private; 1370 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1371 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1372 struct drm_connector *connector; 1373 struct amdgpu_connector *amdgpu_connector = NULL; 1374 u32 tmp; 1375 int interlace = 0; 1376 1377 if (!dig || !dig->afmt || !dig->afmt->pin) 1378 return; 1379 1380 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1381 if (connector->encoder == encoder) { 1382 amdgpu_connector = to_amdgpu_connector(connector); 1383 break; 1384 } 1385 } 1386 1387 if (!amdgpu_connector) { 1388 DRM_ERROR("Couldn't find encoder's connector\n"); 1389 return; 1390 } 1391 1392 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1393 interlace = 1; 1394 if (connector->latency_present[interlace]) { 1395 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1396 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1397 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1398 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1399 } else { 1400 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1401 VIDEO_LIPSYNC, 0); 1402 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1403 AUDIO_LIPSYNC, 0); 1404 } 1405 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1406 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1407 } 1408 1409 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1410 { 1411 struct amdgpu_device *adev = encoder->dev->dev_private; 1412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1413 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1414 struct drm_connector *connector; 1415 struct amdgpu_connector *amdgpu_connector = NULL; 1416 u32 tmp; 1417 u8 *sadb = NULL; 1418 int sad_count; 1419 1420 if (!dig || !dig->afmt || !dig->afmt->pin) 1421 return; 1422 1423 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1424 if (connector->encoder == encoder) { 1425 amdgpu_connector = to_amdgpu_connector(connector); 1426 break; 1427 } 1428 } 1429 1430 if (!amdgpu_connector) { 1431 DRM_ERROR("Couldn't find encoder's connector\n"); 1432 return; 1433 } 1434 1435 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1436 if (sad_count < 0) { 1437 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1438 sad_count = 0; 1439 } 1440 1441 /* program the speaker allocation */ 1442 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1443 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1444 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1445 DP_CONNECTION, 0); 1446 /* set HDMI mode */ 1447 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1448 HDMI_CONNECTION, 1); 1449 if (sad_count) 1450 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1451 SPEAKER_ALLOCATION, sadb[0]); 1452 else 1453 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1454 SPEAKER_ALLOCATION, 5); /* stereo */ 1455 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1456 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1457 1458 kfree(sadb); 1459 } 1460 1461 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1462 { 1463 struct amdgpu_device *adev = encoder->dev->dev_private; 1464 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1465 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1466 struct drm_connector *connector; 1467 struct amdgpu_connector *amdgpu_connector = NULL; 1468 struct cea_sad *sads; 1469 int i, sad_count; 1470 1471 static const u16 eld_reg_to_type[][2] = { 1472 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1473 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1474 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1475 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1476 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1477 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1478 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1479 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1480 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1481 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1482 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1483 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1484 }; 1485 1486 if (!dig || !dig->afmt || !dig->afmt->pin) 1487 return; 1488 1489 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1490 if (connector->encoder == encoder) { 1491 amdgpu_connector = to_amdgpu_connector(connector); 1492 break; 1493 } 1494 } 1495 1496 if (!amdgpu_connector) { 1497 DRM_ERROR("Couldn't find encoder's connector\n"); 1498 return; 1499 } 1500 1501 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1502 if (sad_count <= 0) { 1503 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1504 return; 1505 } 1506 BUG_ON(!sads); 1507 1508 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1509 u32 tmp = 0; 1510 u8 stereo_freqs = 0; 1511 int max_channels = -1; 1512 int j; 1513 1514 for (j = 0; j < sad_count; j++) { 1515 struct cea_sad *sad = &sads[j]; 1516 1517 if (sad->format == eld_reg_to_type[i][1]) { 1518 if (sad->channels > max_channels) { 1519 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1520 MAX_CHANNELS, sad->channels); 1521 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1522 DESCRIPTOR_BYTE_2, sad->byte2); 1523 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1524 SUPPORTED_FREQUENCIES, sad->freq); 1525 max_channels = sad->channels; 1526 } 1527 1528 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1529 stereo_freqs |= sad->freq; 1530 else 1531 break; 1532 } 1533 } 1534 1535 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1536 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1537 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1538 } 1539 1540 kfree(sads); 1541 } 1542 1543 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1544 struct amdgpu_audio_pin *pin, 1545 bool enable) 1546 { 1547 if (!pin) 1548 return; 1549 1550 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1551 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1552 } 1553 1554 static const u32 pin_offsets[] = 1555 { 1556 AUD0_REGISTER_OFFSET, 1557 AUD1_REGISTER_OFFSET, 1558 AUD2_REGISTER_OFFSET, 1559 AUD3_REGISTER_OFFSET, 1560 AUD4_REGISTER_OFFSET, 1561 AUD5_REGISTER_OFFSET, 1562 AUD6_REGISTER_OFFSET, 1563 AUD7_REGISTER_OFFSET, 1564 }; 1565 1566 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1567 { 1568 int i; 1569 1570 if (!amdgpu_audio) 1571 return 0; 1572 1573 adev->mode_info.audio.enabled = true; 1574 1575 switch (adev->asic_type) { 1576 case CHIP_CARRIZO: 1577 case CHIP_STONEY: 1578 adev->mode_info.audio.num_pins = 7; 1579 break; 1580 case CHIP_POLARIS10: 1581 adev->mode_info.audio.num_pins = 8; 1582 break; 1583 case CHIP_POLARIS11: 1584 case CHIP_POLARIS12: 1585 adev->mode_info.audio.num_pins = 6; 1586 break; 1587 default: 1588 return -EINVAL; 1589 } 1590 1591 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1592 adev->mode_info.audio.pin[i].channels = -1; 1593 adev->mode_info.audio.pin[i].rate = -1; 1594 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1595 adev->mode_info.audio.pin[i].status_bits = 0; 1596 adev->mode_info.audio.pin[i].category_code = 0; 1597 adev->mode_info.audio.pin[i].connected = false; 1598 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1599 adev->mode_info.audio.pin[i].id = i; 1600 /* disable audio. it will be set up later */ 1601 /* XXX remove once we switch to ip funcs */ 1602 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1603 } 1604 1605 return 0; 1606 } 1607 1608 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1609 { 1610 int i; 1611 1612 if (!amdgpu_audio) 1613 return; 1614 1615 if (!adev->mode_info.audio.enabled) 1616 return; 1617 1618 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1619 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1620 1621 adev->mode_info.audio.enabled = false; 1622 } 1623 1624 /* 1625 * update the N and CTS parameters for a given pixel clock rate 1626 */ 1627 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1628 { 1629 struct drm_device *dev = encoder->dev; 1630 struct amdgpu_device *adev = dev->dev_private; 1631 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1632 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1633 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1634 u32 tmp; 1635 1636 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1637 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1638 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1639 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1640 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1641 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1642 1643 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1644 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1645 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1646 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1647 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1648 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1649 1650 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1651 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1652 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1653 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1654 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1655 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1656 1657 } 1658 1659 /* 1660 * build a HDMI Video Info Frame 1661 */ 1662 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1663 void *buffer, size_t size) 1664 { 1665 struct drm_device *dev = encoder->dev; 1666 struct amdgpu_device *adev = dev->dev_private; 1667 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1668 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1669 uint8_t *frame = buffer + 3; 1670 uint8_t *header = buffer; 1671 1672 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1673 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1674 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1675 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1676 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1677 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1678 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1679 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1680 } 1681 1682 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1683 { 1684 struct drm_device *dev = encoder->dev; 1685 struct amdgpu_device *adev = dev->dev_private; 1686 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1687 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1688 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1689 u32 dto_phase = 24 * 1000; 1690 u32 dto_modulo = clock; 1691 u32 tmp; 1692 1693 if (!dig || !dig->afmt) 1694 return; 1695 1696 /* XXX two dtos; generally use dto0 for hdmi */ 1697 /* Express [24MHz / target pixel clock] as an exact rational 1698 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1699 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1700 */ 1701 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1702 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1703 amdgpu_crtc->crtc_id); 1704 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1705 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1706 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1707 } 1708 1709 /* 1710 * update the info frames with the data from the current display mode 1711 */ 1712 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1713 struct drm_display_mode *mode) 1714 { 1715 struct drm_device *dev = encoder->dev; 1716 struct amdgpu_device *adev = dev->dev_private; 1717 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1718 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1719 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1720 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1721 struct hdmi_avi_infoframe frame; 1722 ssize_t err; 1723 u32 tmp; 1724 int bpc = 8; 1725 1726 if (!dig || !dig->afmt) 1727 return; 1728 1729 /* Silent, r600_hdmi_enable will raise WARN for us */ 1730 if (!dig->afmt->enabled) 1731 return; 1732 1733 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1734 if (encoder->crtc) { 1735 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1736 bpc = amdgpu_crtc->bpc; 1737 } 1738 1739 /* disable audio prior to setting up hw */ 1740 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1741 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1742 1743 dce_v11_0_audio_set_dto(encoder, mode->clock); 1744 1745 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1746 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1747 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1748 1749 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1750 1751 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1752 switch (bpc) { 1753 case 0: 1754 case 6: 1755 case 8: 1756 case 16: 1757 default: 1758 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1759 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1760 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1761 connector->name, bpc); 1762 break; 1763 case 10: 1764 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1765 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1766 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1767 connector->name); 1768 break; 1769 case 12: 1770 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1771 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1772 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1773 connector->name); 1774 break; 1775 } 1776 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1777 1778 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1779 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1780 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1781 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1782 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1783 1784 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1785 /* enable audio info frames (frames won't be set until audio is enabled) */ 1786 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1787 /* required for audio info values to be updated */ 1788 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1789 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1790 1791 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1792 /* required for audio info values to be updated */ 1793 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1794 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1795 1796 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1797 /* anything other than 0 */ 1798 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1799 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1800 1801 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1802 1803 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1804 /* set the default audio delay */ 1805 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1806 /* should be suffient for all audio modes and small enough for all hblanks */ 1807 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1808 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1809 1810 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1811 /* allow 60958 channel status fields to be updated */ 1812 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1813 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1814 1815 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1816 if (bpc > 8) 1817 /* clear SW CTS value */ 1818 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1819 else 1820 /* select SW CTS value */ 1821 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1822 /* allow hw to sent ACR packets when required */ 1823 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1824 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1825 1826 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1827 1828 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1829 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1830 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1831 1832 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1833 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1834 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1835 1836 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1837 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1838 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1839 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1840 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1841 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1842 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1843 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1844 1845 dce_v11_0_audio_write_speaker_allocation(encoder); 1846 1847 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1848 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1849 1850 dce_v11_0_afmt_audio_select_pin(encoder); 1851 dce_v11_0_audio_write_sad_regs(encoder); 1852 dce_v11_0_audio_write_latency_fields(encoder, mode); 1853 1854 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1855 if (err < 0) { 1856 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1857 return; 1858 } 1859 1860 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1861 if (err < 0) { 1862 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1863 return; 1864 } 1865 1866 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1867 1868 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1869 /* enable AVI info frames */ 1870 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1871 /* required for audio info values to be updated */ 1872 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1873 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1874 1875 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1876 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1877 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1878 1879 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1880 /* send audio packets */ 1881 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1882 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1883 1884 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1885 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1886 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1887 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1888 1889 /* enable audio after to setting up hw */ 1890 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1891 } 1892 1893 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1894 { 1895 struct drm_device *dev = encoder->dev; 1896 struct amdgpu_device *adev = dev->dev_private; 1897 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1898 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1899 1900 if (!dig || !dig->afmt) 1901 return; 1902 1903 /* Silent, r600_hdmi_enable will raise WARN for us */ 1904 if (enable && dig->afmt->enabled) 1905 return; 1906 if (!enable && !dig->afmt->enabled) 1907 return; 1908 1909 if (!enable && dig->afmt->pin) { 1910 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1911 dig->afmt->pin = NULL; 1912 } 1913 1914 dig->afmt->enabled = enable; 1915 1916 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1917 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1918 } 1919 1920 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 1921 { 1922 int i; 1923 1924 for (i = 0; i < adev->mode_info.num_dig; i++) 1925 adev->mode_info.afmt[i] = NULL; 1926 1927 /* DCE11 has audio blocks tied to DIG encoders */ 1928 for (i = 0; i < adev->mode_info.num_dig; i++) { 1929 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1930 if (adev->mode_info.afmt[i]) { 1931 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1932 adev->mode_info.afmt[i]->id = i; 1933 } else { 1934 int j; 1935 for (j = 0; j < i; j++) { 1936 kfree(adev->mode_info.afmt[j]); 1937 adev->mode_info.afmt[j] = NULL; 1938 } 1939 return -ENOMEM; 1940 } 1941 } 1942 return 0; 1943 } 1944 1945 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 1946 { 1947 int i; 1948 1949 for (i = 0; i < adev->mode_info.num_dig; i++) { 1950 kfree(adev->mode_info.afmt[i]); 1951 adev->mode_info.afmt[i] = NULL; 1952 } 1953 } 1954 1955 static const u32 vga_control_regs[6] = 1956 { 1957 mmD1VGA_CONTROL, 1958 mmD2VGA_CONTROL, 1959 mmD3VGA_CONTROL, 1960 mmD4VGA_CONTROL, 1961 mmD5VGA_CONTROL, 1962 mmD6VGA_CONTROL, 1963 }; 1964 1965 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 1966 { 1967 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1968 struct drm_device *dev = crtc->dev; 1969 struct amdgpu_device *adev = dev->dev_private; 1970 u32 vga_control; 1971 1972 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1973 if (enable) 1974 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1975 else 1976 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1977 } 1978 1979 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 1980 { 1981 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1982 struct drm_device *dev = crtc->dev; 1983 struct amdgpu_device *adev = dev->dev_private; 1984 1985 if (enable) 1986 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1987 else 1988 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1989 } 1990 1991 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 1992 struct drm_framebuffer *fb, 1993 int x, int y, int atomic) 1994 { 1995 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1996 struct drm_device *dev = crtc->dev; 1997 struct amdgpu_device *adev = dev->dev_private; 1998 struct amdgpu_framebuffer *amdgpu_fb; 1999 struct drm_framebuffer *target_fb; 2000 struct drm_gem_object *obj; 2001 struct amdgpu_bo *abo; 2002 uint64_t fb_location, tiling_flags; 2003 uint32_t fb_format, fb_pitch_pixels; 2004 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2005 u32 pipe_config; 2006 u32 tmp, viewport_w, viewport_h; 2007 int r; 2008 bool bypass_lut = false; 2009 struct drm_format_name_buf format_name; 2010 2011 /* no fb bound */ 2012 if (!atomic && !crtc->primary->fb) { 2013 DRM_DEBUG_KMS("No FB bound\n"); 2014 return 0; 2015 } 2016 2017 if (atomic) { 2018 amdgpu_fb = to_amdgpu_framebuffer(fb); 2019 target_fb = fb; 2020 } else { 2021 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2022 target_fb = crtc->primary->fb; 2023 } 2024 2025 /* If atomic, assume fb object is pinned & idle & fenced and 2026 * just update base pointers 2027 */ 2028 obj = amdgpu_fb->obj; 2029 abo = gem_to_amdgpu_bo(obj); 2030 r = amdgpu_bo_reserve(abo, false); 2031 if (unlikely(r != 0)) 2032 return r; 2033 2034 if (atomic) { 2035 fb_location = amdgpu_bo_gpu_offset(abo); 2036 } else { 2037 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2038 if (unlikely(r != 0)) { 2039 amdgpu_bo_unreserve(abo); 2040 return -EINVAL; 2041 } 2042 } 2043 2044 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 2045 amdgpu_bo_unreserve(abo); 2046 2047 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2048 2049 switch (target_fb->format->format) { 2050 case DRM_FORMAT_C8: 2051 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2052 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2053 break; 2054 case DRM_FORMAT_XRGB4444: 2055 case DRM_FORMAT_ARGB4444: 2056 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2057 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2058 #ifdef __BIG_ENDIAN 2059 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2060 ENDIAN_8IN16); 2061 #endif 2062 break; 2063 case DRM_FORMAT_XRGB1555: 2064 case DRM_FORMAT_ARGB1555: 2065 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2066 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2067 #ifdef __BIG_ENDIAN 2068 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2069 ENDIAN_8IN16); 2070 #endif 2071 break; 2072 case DRM_FORMAT_BGRX5551: 2073 case DRM_FORMAT_BGRA5551: 2074 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2075 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2076 #ifdef __BIG_ENDIAN 2077 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2078 ENDIAN_8IN16); 2079 #endif 2080 break; 2081 case DRM_FORMAT_RGB565: 2082 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2083 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2084 #ifdef __BIG_ENDIAN 2085 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2086 ENDIAN_8IN16); 2087 #endif 2088 break; 2089 case DRM_FORMAT_XRGB8888: 2090 case DRM_FORMAT_ARGB8888: 2091 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2092 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2093 #ifdef __BIG_ENDIAN 2094 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2095 ENDIAN_8IN32); 2096 #endif 2097 break; 2098 case DRM_FORMAT_XRGB2101010: 2099 case DRM_FORMAT_ARGB2101010: 2100 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2101 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2102 #ifdef __BIG_ENDIAN 2103 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2104 ENDIAN_8IN32); 2105 #endif 2106 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2107 bypass_lut = true; 2108 break; 2109 case DRM_FORMAT_BGRX1010102: 2110 case DRM_FORMAT_BGRA1010102: 2111 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2112 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2113 #ifdef __BIG_ENDIAN 2114 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2115 ENDIAN_8IN32); 2116 #endif 2117 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2118 bypass_lut = true; 2119 break; 2120 default: 2121 DRM_ERROR("Unsupported screen format %s\n", 2122 drm_get_format_name(target_fb->format->format, &format_name)); 2123 return -EINVAL; 2124 } 2125 2126 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2127 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2128 2129 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2130 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2131 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2132 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2133 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2134 2135 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2136 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2137 ARRAY_2D_TILED_THIN1); 2138 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2139 tile_split); 2140 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2141 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2142 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2143 mtaspect); 2144 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2145 ADDR_SURF_MICRO_TILING_DISPLAY); 2146 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2147 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2148 ARRAY_1D_TILED_THIN1); 2149 } 2150 2151 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2152 pipe_config); 2153 2154 dce_v11_0_vga_enable(crtc, false); 2155 2156 /* Make sure surface address is updated at vertical blank rather than 2157 * horizontal blank 2158 */ 2159 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2160 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2161 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2162 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2163 2164 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2165 upper_32_bits(fb_location)); 2166 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2167 upper_32_bits(fb_location)); 2168 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2169 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2170 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2171 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2172 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2173 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2174 2175 /* 2176 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2177 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2178 * retain the full precision throughout the pipeline. 2179 */ 2180 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2181 if (bypass_lut) 2182 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2183 else 2184 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2185 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2186 2187 if (bypass_lut) 2188 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2189 2190 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2191 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2192 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2193 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2194 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2195 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2196 2197 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2198 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2199 2200 dce_v11_0_grph_enable(crtc, true); 2201 2202 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2203 target_fb->height); 2204 2205 x &= ~3; 2206 y &= ~1; 2207 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2208 (x << 16) | y); 2209 viewport_w = crtc->mode.hdisplay; 2210 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2211 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2212 (viewport_w << 16) | viewport_h); 2213 2214 /* set pageflip to happen anywhere in vblank interval */ 2215 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2216 2217 if (!atomic && fb && fb != crtc->primary->fb) { 2218 amdgpu_fb = to_amdgpu_framebuffer(fb); 2219 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2220 r = amdgpu_bo_reserve(abo, true); 2221 if (unlikely(r != 0)) 2222 return r; 2223 amdgpu_bo_unpin(abo); 2224 amdgpu_bo_unreserve(abo); 2225 } 2226 2227 /* Bytes per pixel may have changed */ 2228 dce_v11_0_bandwidth_update(adev); 2229 2230 return 0; 2231 } 2232 2233 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2234 struct drm_display_mode *mode) 2235 { 2236 struct drm_device *dev = crtc->dev; 2237 struct amdgpu_device *adev = dev->dev_private; 2238 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2239 u32 tmp; 2240 2241 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2242 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2243 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2244 else 2245 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2246 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2247 } 2248 2249 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2250 { 2251 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2252 struct drm_device *dev = crtc->dev; 2253 struct amdgpu_device *adev = dev->dev_private; 2254 int i; 2255 u32 tmp; 2256 2257 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2258 2259 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2260 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2261 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2262 2263 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2264 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2265 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2266 2267 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2268 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2269 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2270 2271 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2272 2273 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2274 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2275 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2276 2277 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2278 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2279 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2280 2281 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2282 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2283 2284 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2285 for (i = 0; i < 256; i++) { 2286 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2287 (amdgpu_crtc->lut_r[i] << 20) | 2288 (amdgpu_crtc->lut_g[i] << 10) | 2289 (amdgpu_crtc->lut_b[i] << 0)); 2290 } 2291 2292 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2293 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2294 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2295 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2296 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2297 2298 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2299 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2300 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2301 2302 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2303 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2304 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2305 2306 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2307 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2308 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2309 2310 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2311 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2312 /* XXX this only needs to be programmed once per crtc at startup, 2313 * not sure where the best place for it is 2314 */ 2315 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2316 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2317 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2318 } 2319 2320 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2321 { 2322 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2323 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2324 2325 switch (amdgpu_encoder->encoder_id) { 2326 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2327 if (dig->linkb) 2328 return 1; 2329 else 2330 return 0; 2331 break; 2332 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2333 if (dig->linkb) 2334 return 3; 2335 else 2336 return 2; 2337 break; 2338 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2339 if (dig->linkb) 2340 return 5; 2341 else 2342 return 4; 2343 break; 2344 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2345 return 6; 2346 break; 2347 default: 2348 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2349 return 0; 2350 } 2351 } 2352 2353 /** 2354 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2355 * 2356 * @crtc: drm crtc 2357 * 2358 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2359 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2360 * monitors a dedicated PPLL must be used. If a particular board has 2361 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2362 * as there is no need to program the PLL itself. If we are not able to 2363 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2364 * avoid messing up an existing monitor. 2365 * 2366 * Asic specific PLL information 2367 * 2368 * DCE 10.x 2369 * Tonga 2370 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2371 * CI 2372 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2373 * 2374 */ 2375 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2376 { 2377 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2378 struct drm_device *dev = crtc->dev; 2379 struct amdgpu_device *adev = dev->dev_private; 2380 u32 pll_in_use; 2381 int pll; 2382 2383 if ((adev->asic_type == CHIP_POLARIS10) || 2384 (adev->asic_type == CHIP_POLARIS11) || 2385 (adev->asic_type == CHIP_POLARIS12)) { 2386 struct amdgpu_encoder *amdgpu_encoder = 2387 to_amdgpu_encoder(amdgpu_crtc->encoder); 2388 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2389 2390 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2391 return ATOM_DP_DTO; 2392 2393 switch (amdgpu_encoder->encoder_id) { 2394 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2395 if (dig->linkb) 2396 return ATOM_COMBOPHY_PLL1; 2397 else 2398 return ATOM_COMBOPHY_PLL0; 2399 break; 2400 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2401 if (dig->linkb) 2402 return ATOM_COMBOPHY_PLL3; 2403 else 2404 return ATOM_COMBOPHY_PLL2; 2405 break; 2406 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2407 if (dig->linkb) 2408 return ATOM_COMBOPHY_PLL5; 2409 else 2410 return ATOM_COMBOPHY_PLL4; 2411 break; 2412 default: 2413 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2414 return ATOM_PPLL_INVALID; 2415 } 2416 } 2417 2418 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2419 if (adev->clock.dp_extclk) 2420 /* skip PPLL programming if using ext clock */ 2421 return ATOM_PPLL_INVALID; 2422 else { 2423 /* use the same PPLL for all DP monitors */ 2424 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2425 if (pll != ATOM_PPLL_INVALID) 2426 return pll; 2427 } 2428 } else { 2429 /* use the same PPLL for all monitors with the same clock */ 2430 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2431 if (pll != ATOM_PPLL_INVALID) 2432 return pll; 2433 } 2434 2435 /* XXX need to determine what plls are available on each DCE11 part */ 2436 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2437 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2438 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2439 return ATOM_PPLL1; 2440 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2441 return ATOM_PPLL0; 2442 DRM_ERROR("unable to allocate a PPLL\n"); 2443 return ATOM_PPLL_INVALID; 2444 } else { 2445 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2446 return ATOM_PPLL2; 2447 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2448 return ATOM_PPLL1; 2449 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2450 return ATOM_PPLL0; 2451 DRM_ERROR("unable to allocate a PPLL\n"); 2452 return ATOM_PPLL_INVALID; 2453 } 2454 return ATOM_PPLL_INVALID; 2455 } 2456 2457 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2458 { 2459 struct amdgpu_device *adev = crtc->dev->dev_private; 2460 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2461 uint32_t cur_lock; 2462 2463 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2464 if (lock) 2465 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2466 else 2467 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2468 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2469 } 2470 2471 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2472 { 2473 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2474 struct amdgpu_device *adev = crtc->dev->dev_private; 2475 u32 tmp; 2476 2477 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2478 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2479 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2480 } 2481 2482 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2483 { 2484 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2485 struct amdgpu_device *adev = crtc->dev->dev_private; 2486 u32 tmp; 2487 2488 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2489 upper_32_bits(amdgpu_crtc->cursor_addr)); 2490 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2491 lower_32_bits(amdgpu_crtc->cursor_addr)); 2492 2493 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2494 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2495 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2496 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2497 } 2498 2499 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2500 int x, int y) 2501 { 2502 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2503 struct amdgpu_device *adev = crtc->dev->dev_private; 2504 int xorigin = 0, yorigin = 0; 2505 2506 amdgpu_crtc->cursor_x = x; 2507 amdgpu_crtc->cursor_y = y; 2508 2509 /* avivo cursor are offset into the total surface */ 2510 x += crtc->x; 2511 y += crtc->y; 2512 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2513 2514 if (x < 0) { 2515 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2516 x = 0; 2517 } 2518 if (y < 0) { 2519 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2520 y = 0; 2521 } 2522 2523 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2524 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2525 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2526 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2527 2528 return 0; 2529 } 2530 2531 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2532 int x, int y) 2533 { 2534 int ret; 2535 2536 dce_v11_0_lock_cursor(crtc, true); 2537 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2538 dce_v11_0_lock_cursor(crtc, false); 2539 2540 return ret; 2541 } 2542 2543 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2544 struct drm_file *file_priv, 2545 uint32_t handle, 2546 uint32_t width, 2547 uint32_t height, 2548 int32_t hot_x, 2549 int32_t hot_y) 2550 { 2551 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2552 struct drm_gem_object *obj; 2553 struct amdgpu_bo *aobj; 2554 int ret; 2555 2556 if (!handle) { 2557 /* turn off cursor */ 2558 dce_v11_0_hide_cursor(crtc); 2559 obj = NULL; 2560 goto unpin; 2561 } 2562 2563 if ((width > amdgpu_crtc->max_cursor_width) || 2564 (height > amdgpu_crtc->max_cursor_height)) { 2565 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2566 return -EINVAL; 2567 } 2568 2569 obj = drm_gem_object_lookup(file_priv, handle); 2570 if (!obj) { 2571 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2572 return -ENOENT; 2573 } 2574 2575 aobj = gem_to_amdgpu_bo(obj); 2576 ret = amdgpu_bo_reserve(aobj, false); 2577 if (ret != 0) { 2578 drm_gem_object_unreference_unlocked(obj); 2579 return ret; 2580 } 2581 2582 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2583 amdgpu_bo_unreserve(aobj); 2584 if (ret) { 2585 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2586 drm_gem_object_unreference_unlocked(obj); 2587 return ret; 2588 } 2589 2590 dce_v11_0_lock_cursor(crtc, true); 2591 2592 if (width != amdgpu_crtc->cursor_width || 2593 height != amdgpu_crtc->cursor_height || 2594 hot_x != amdgpu_crtc->cursor_hot_x || 2595 hot_y != amdgpu_crtc->cursor_hot_y) { 2596 int x, y; 2597 2598 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2599 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2600 2601 dce_v11_0_cursor_move_locked(crtc, x, y); 2602 2603 amdgpu_crtc->cursor_width = width; 2604 amdgpu_crtc->cursor_height = height; 2605 amdgpu_crtc->cursor_hot_x = hot_x; 2606 amdgpu_crtc->cursor_hot_y = hot_y; 2607 } 2608 2609 dce_v11_0_show_cursor(crtc); 2610 dce_v11_0_lock_cursor(crtc, false); 2611 2612 unpin: 2613 if (amdgpu_crtc->cursor_bo) { 2614 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2615 ret = amdgpu_bo_reserve(aobj, true); 2616 if (likely(ret == 0)) { 2617 amdgpu_bo_unpin(aobj); 2618 amdgpu_bo_unreserve(aobj); 2619 } 2620 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2621 } 2622 2623 amdgpu_crtc->cursor_bo = obj; 2624 return 0; 2625 } 2626 2627 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2628 { 2629 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2630 2631 if (amdgpu_crtc->cursor_bo) { 2632 dce_v11_0_lock_cursor(crtc, true); 2633 2634 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2635 amdgpu_crtc->cursor_y); 2636 2637 dce_v11_0_show_cursor(crtc); 2638 2639 dce_v11_0_lock_cursor(crtc, false); 2640 } 2641 } 2642 2643 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2644 u16 *blue, uint32_t size, 2645 struct drm_modeset_acquire_ctx *ctx) 2646 { 2647 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2648 int i; 2649 2650 /* userspace palettes are always correct as is */ 2651 for (i = 0; i < size; i++) { 2652 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2653 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2654 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2655 } 2656 dce_v11_0_crtc_load_lut(crtc); 2657 2658 return 0; 2659 } 2660 2661 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2662 { 2663 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2664 2665 drm_crtc_cleanup(crtc); 2666 kfree(amdgpu_crtc); 2667 } 2668 2669 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2670 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2671 .cursor_move = dce_v11_0_crtc_cursor_move, 2672 .gamma_set = dce_v11_0_crtc_gamma_set, 2673 .set_config = amdgpu_crtc_set_config, 2674 .destroy = dce_v11_0_crtc_destroy, 2675 .page_flip_target = amdgpu_crtc_page_flip_target, 2676 }; 2677 2678 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2679 { 2680 struct drm_device *dev = crtc->dev; 2681 struct amdgpu_device *adev = dev->dev_private; 2682 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2683 unsigned type; 2684 2685 switch (mode) { 2686 case DRM_MODE_DPMS_ON: 2687 amdgpu_crtc->enabled = true; 2688 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2689 dce_v11_0_vga_enable(crtc, true); 2690 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2691 dce_v11_0_vga_enable(crtc, false); 2692 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2693 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2694 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2695 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2696 drm_crtc_vblank_on(crtc); 2697 dce_v11_0_crtc_load_lut(crtc); 2698 break; 2699 case DRM_MODE_DPMS_STANDBY: 2700 case DRM_MODE_DPMS_SUSPEND: 2701 case DRM_MODE_DPMS_OFF: 2702 drm_crtc_vblank_off(crtc); 2703 if (amdgpu_crtc->enabled) { 2704 dce_v11_0_vga_enable(crtc, true); 2705 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2706 dce_v11_0_vga_enable(crtc, false); 2707 } 2708 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2709 amdgpu_crtc->enabled = false; 2710 break; 2711 } 2712 /* adjust pm to dpms */ 2713 amdgpu_pm_compute_clocks(adev); 2714 } 2715 2716 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2717 { 2718 /* disable crtc pair power gating before programming */ 2719 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2720 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2721 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2722 } 2723 2724 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2725 { 2726 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2727 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2728 } 2729 2730 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2731 { 2732 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2733 struct drm_device *dev = crtc->dev; 2734 struct amdgpu_device *adev = dev->dev_private; 2735 struct amdgpu_atom_ss ss; 2736 int i; 2737 2738 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2739 if (crtc->primary->fb) { 2740 int r; 2741 struct amdgpu_framebuffer *amdgpu_fb; 2742 struct amdgpu_bo *abo; 2743 2744 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2745 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2746 r = amdgpu_bo_reserve(abo, true); 2747 if (unlikely(r)) 2748 DRM_ERROR("failed to reserve abo before unpin\n"); 2749 else { 2750 amdgpu_bo_unpin(abo); 2751 amdgpu_bo_unreserve(abo); 2752 } 2753 } 2754 /* disable the GRPH */ 2755 dce_v11_0_grph_enable(crtc, false); 2756 2757 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2758 2759 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2760 if (adev->mode_info.crtcs[i] && 2761 adev->mode_info.crtcs[i]->enabled && 2762 i != amdgpu_crtc->crtc_id && 2763 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2764 /* one other crtc is using this pll don't turn 2765 * off the pll 2766 */ 2767 goto done; 2768 } 2769 } 2770 2771 switch (amdgpu_crtc->pll_id) { 2772 case ATOM_PPLL0: 2773 case ATOM_PPLL1: 2774 case ATOM_PPLL2: 2775 /* disable the ppll */ 2776 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2777 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2778 break; 2779 case ATOM_COMBOPHY_PLL0: 2780 case ATOM_COMBOPHY_PLL1: 2781 case ATOM_COMBOPHY_PLL2: 2782 case ATOM_COMBOPHY_PLL3: 2783 case ATOM_COMBOPHY_PLL4: 2784 case ATOM_COMBOPHY_PLL5: 2785 /* disable the ppll */ 2786 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2787 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2788 break; 2789 default: 2790 break; 2791 } 2792 done: 2793 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2794 amdgpu_crtc->adjusted_clock = 0; 2795 amdgpu_crtc->encoder = NULL; 2796 amdgpu_crtc->connector = NULL; 2797 } 2798 2799 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2800 struct drm_display_mode *mode, 2801 struct drm_display_mode *adjusted_mode, 2802 int x, int y, struct drm_framebuffer *old_fb) 2803 { 2804 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2805 struct drm_device *dev = crtc->dev; 2806 struct amdgpu_device *adev = dev->dev_private; 2807 2808 if (!amdgpu_crtc->adjusted_clock) 2809 return -EINVAL; 2810 2811 if ((adev->asic_type == CHIP_POLARIS10) || 2812 (adev->asic_type == CHIP_POLARIS11) || 2813 (adev->asic_type == CHIP_POLARIS12)) { 2814 struct amdgpu_encoder *amdgpu_encoder = 2815 to_amdgpu_encoder(amdgpu_crtc->encoder); 2816 int encoder_mode = 2817 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2818 2819 /* SetPixelClock calculates the plls and ss values now */ 2820 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2821 amdgpu_crtc->pll_id, 2822 encoder_mode, amdgpu_encoder->encoder_id, 2823 adjusted_mode->clock, 0, 0, 0, 0, 2824 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2825 } else { 2826 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2827 } 2828 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2829 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2830 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2831 amdgpu_atombios_crtc_scaler_setup(crtc); 2832 dce_v11_0_cursor_reset(crtc); 2833 /* update the hw version fpr dpm */ 2834 amdgpu_crtc->hw_mode = *adjusted_mode; 2835 2836 return 0; 2837 } 2838 2839 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2840 const struct drm_display_mode *mode, 2841 struct drm_display_mode *adjusted_mode) 2842 { 2843 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2844 struct drm_device *dev = crtc->dev; 2845 struct drm_encoder *encoder; 2846 2847 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2848 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2849 if (encoder->crtc == crtc) { 2850 amdgpu_crtc->encoder = encoder; 2851 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2852 break; 2853 } 2854 } 2855 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2856 amdgpu_crtc->encoder = NULL; 2857 amdgpu_crtc->connector = NULL; 2858 return false; 2859 } 2860 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2861 return false; 2862 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2863 return false; 2864 /* pick pll */ 2865 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2866 /* if we can't get a PPLL for a non-DP encoder, fail */ 2867 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2868 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2869 return false; 2870 2871 return true; 2872 } 2873 2874 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2875 struct drm_framebuffer *old_fb) 2876 { 2877 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2878 } 2879 2880 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2881 struct drm_framebuffer *fb, 2882 int x, int y, enum mode_set_atomic state) 2883 { 2884 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2885 } 2886 2887 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2888 .dpms = dce_v11_0_crtc_dpms, 2889 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2890 .mode_set = dce_v11_0_crtc_mode_set, 2891 .mode_set_base = dce_v11_0_crtc_set_base, 2892 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2893 .prepare = dce_v11_0_crtc_prepare, 2894 .commit = dce_v11_0_crtc_commit, 2895 .load_lut = dce_v11_0_crtc_load_lut, 2896 .disable = dce_v11_0_crtc_disable, 2897 }; 2898 2899 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2900 { 2901 struct amdgpu_crtc *amdgpu_crtc; 2902 int i; 2903 2904 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2905 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2906 if (amdgpu_crtc == NULL) 2907 return -ENOMEM; 2908 2909 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2910 2911 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2912 amdgpu_crtc->crtc_id = index; 2913 adev->mode_info.crtcs[index] = amdgpu_crtc; 2914 2915 amdgpu_crtc->max_cursor_width = 128; 2916 amdgpu_crtc->max_cursor_height = 128; 2917 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2918 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2919 2920 for (i = 0; i < 256; i++) { 2921 amdgpu_crtc->lut_r[i] = i << 2; 2922 amdgpu_crtc->lut_g[i] = i << 2; 2923 amdgpu_crtc->lut_b[i] = i << 2; 2924 } 2925 2926 switch (amdgpu_crtc->crtc_id) { 2927 case 0: 2928 default: 2929 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2930 break; 2931 case 1: 2932 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2933 break; 2934 case 2: 2935 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2936 break; 2937 case 3: 2938 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2939 break; 2940 case 4: 2941 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2942 break; 2943 case 5: 2944 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2945 break; 2946 } 2947 2948 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2949 amdgpu_crtc->adjusted_clock = 0; 2950 amdgpu_crtc->encoder = NULL; 2951 amdgpu_crtc->connector = NULL; 2952 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 2953 2954 return 0; 2955 } 2956 2957 static int dce_v11_0_early_init(void *handle) 2958 { 2959 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2960 2961 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 2962 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 2963 2964 dce_v11_0_set_display_funcs(adev); 2965 dce_v11_0_set_irq_funcs(adev); 2966 2967 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); 2968 2969 switch (adev->asic_type) { 2970 case CHIP_CARRIZO: 2971 adev->mode_info.num_hpd = 6; 2972 adev->mode_info.num_dig = 9; 2973 break; 2974 case CHIP_STONEY: 2975 adev->mode_info.num_hpd = 6; 2976 adev->mode_info.num_dig = 9; 2977 break; 2978 case CHIP_POLARIS10: 2979 adev->mode_info.num_hpd = 6; 2980 adev->mode_info.num_dig = 6; 2981 break; 2982 case CHIP_POLARIS11: 2983 case CHIP_POLARIS12: 2984 adev->mode_info.num_hpd = 5; 2985 adev->mode_info.num_dig = 5; 2986 break; 2987 default: 2988 /* FIXME: not supported yet */ 2989 return -EINVAL; 2990 } 2991 2992 return 0; 2993 } 2994 2995 static int dce_v11_0_sw_init(void *handle) 2996 { 2997 int r, i; 2998 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2999 3000 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3001 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 3002 if (r) 3003 return r; 3004 } 3005 3006 for (i = 8; i < 20; i += 2) { 3007 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); 3008 if (r) 3009 return r; 3010 } 3011 3012 /* HPD hotplug */ 3013 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); 3014 if (r) 3015 return r; 3016 3017 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 3018 3019 adev->ddev->mode_config.async_page_flip = true; 3020 3021 adev->ddev->mode_config.max_width = 16384; 3022 adev->ddev->mode_config.max_height = 16384; 3023 3024 adev->ddev->mode_config.preferred_depth = 24; 3025 adev->ddev->mode_config.prefer_shadow = 1; 3026 3027 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 3028 3029 r = amdgpu_modeset_create_props(adev); 3030 if (r) 3031 return r; 3032 3033 adev->ddev->mode_config.max_width = 16384; 3034 adev->ddev->mode_config.max_height = 16384; 3035 3036 3037 /* allocate crtcs */ 3038 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3039 r = dce_v11_0_crtc_init(adev, i); 3040 if (r) 3041 return r; 3042 } 3043 3044 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3045 amdgpu_print_display_setup(adev->ddev); 3046 else 3047 return -EINVAL; 3048 3049 /* setup afmt */ 3050 r = dce_v11_0_afmt_init(adev); 3051 if (r) 3052 return r; 3053 3054 r = dce_v11_0_audio_init(adev); 3055 if (r) 3056 return r; 3057 3058 drm_kms_helper_poll_init(adev->ddev); 3059 3060 adev->mode_info.mode_config_initialized = true; 3061 return 0; 3062 } 3063 3064 static int dce_v11_0_sw_fini(void *handle) 3065 { 3066 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3067 3068 kfree(adev->mode_info.bios_hardcoded_edid); 3069 3070 drm_kms_helper_poll_fini(adev->ddev); 3071 3072 dce_v11_0_audio_fini(adev); 3073 3074 dce_v11_0_afmt_fini(adev); 3075 3076 drm_mode_config_cleanup(adev->ddev); 3077 adev->mode_info.mode_config_initialized = false; 3078 3079 return 0; 3080 } 3081 3082 static int dce_v11_0_hw_init(void *handle) 3083 { 3084 int i; 3085 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3086 3087 dce_v11_0_init_golden_registers(adev); 3088 3089 /* init dig PHYs, disp eng pll */ 3090 amdgpu_atombios_crtc_powergate_init(adev); 3091 amdgpu_atombios_encoder_init_dig(adev); 3092 if ((adev->asic_type == CHIP_POLARIS10) || 3093 (adev->asic_type == CHIP_POLARIS11) || 3094 (adev->asic_type == CHIP_POLARIS12)) { 3095 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 3096 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 3097 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 3098 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 3099 } else { 3100 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3101 } 3102 3103 /* initialize hpd */ 3104 dce_v11_0_hpd_init(adev); 3105 3106 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3107 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3108 } 3109 3110 dce_v11_0_pageflip_interrupt_init(adev); 3111 3112 return 0; 3113 } 3114 3115 static int dce_v11_0_hw_fini(void *handle) 3116 { 3117 int i; 3118 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3119 3120 dce_v11_0_hpd_fini(adev); 3121 3122 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3123 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3124 } 3125 3126 dce_v11_0_pageflip_interrupt_fini(adev); 3127 3128 return 0; 3129 } 3130 3131 static int dce_v11_0_suspend(void *handle) 3132 { 3133 return dce_v11_0_hw_fini(handle); 3134 } 3135 3136 static int dce_v11_0_resume(void *handle) 3137 { 3138 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3139 int ret; 3140 3141 ret = dce_v11_0_hw_init(handle); 3142 3143 /* turn on the BL */ 3144 if (adev->mode_info.bl_encoder) { 3145 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3146 adev->mode_info.bl_encoder); 3147 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3148 bl_level); 3149 } 3150 3151 return ret; 3152 } 3153 3154 static bool dce_v11_0_is_idle(void *handle) 3155 { 3156 return true; 3157 } 3158 3159 static int dce_v11_0_wait_for_idle(void *handle) 3160 { 3161 return 0; 3162 } 3163 3164 static int dce_v11_0_soft_reset(void *handle) 3165 { 3166 u32 srbm_soft_reset = 0, tmp; 3167 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3168 3169 if (dce_v11_0_is_display_hung(adev)) 3170 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3171 3172 if (srbm_soft_reset) { 3173 tmp = RREG32(mmSRBM_SOFT_RESET); 3174 tmp |= srbm_soft_reset; 3175 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3176 WREG32(mmSRBM_SOFT_RESET, tmp); 3177 tmp = RREG32(mmSRBM_SOFT_RESET); 3178 3179 udelay(50); 3180 3181 tmp &= ~srbm_soft_reset; 3182 WREG32(mmSRBM_SOFT_RESET, tmp); 3183 tmp = RREG32(mmSRBM_SOFT_RESET); 3184 3185 /* Wait a little for things to settle down */ 3186 udelay(50); 3187 } 3188 return 0; 3189 } 3190 3191 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3192 int crtc, 3193 enum amdgpu_interrupt_state state) 3194 { 3195 u32 lb_interrupt_mask; 3196 3197 if (crtc >= adev->mode_info.num_crtc) { 3198 DRM_DEBUG("invalid crtc %d\n", crtc); 3199 return; 3200 } 3201 3202 switch (state) { 3203 case AMDGPU_IRQ_STATE_DISABLE: 3204 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3205 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3206 VBLANK_INTERRUPT_MASK, 0); 3207 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3208 break; 3209 case AMDGPU_IRQ_STATE_ENABLE: 3210 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3211 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3212 VBLANK_INTERRUPT_MASK, 1); 3213 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3214 break; 3215 default: 3216 break; 3217 } 3218 } 3219 3220 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3221 int crtc, 3222 enum amdgpu_interrupt_state state) 3223 { 3224 u32 lb_interrupt_mask; 3225 3226 if (crtc >= adev->mode_info.num_crtc) { 3227 DRM_DEBUG("invalid crtc %d\n", crtc); 3228 return; 3229 } 3230 3231 switch (state) { 3232 case AMDGPU_IRQ_STATE_DISABLE: 3233 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3234 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3235 VLINE_INTERRUPT_MASK, 0); 3236 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3237 break; 3238 case AMDGPU_IRQ_STATE_ENABLE: 3239 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3240 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3241 VLINE_INTERRUPT_MASK, 1); 3242 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3243 break; 3244 default: 3245 break; 3246 } 3247 } 3248 3249 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3250 struct amdgpu_irq_src *source, 3251 unsigned hpd, 3252 enum amdgpu_interrupt_state state) 3253 { 3254 u32 tmp; 3255 3256 if (hpd >= adev->mode_info.num_hpd) { 3257 DRM_DEBUG("invalid hdp %d\n", hpd); 3258 return 0; 3259 } 3260 3261 switch (state) { 3262 case AMDGPU_IRQ_STATE_DISABLE: 3263 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3264 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3265 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3266 break; 3267 case AMDGPU_IRQ_STATE_ENABLE: 3268 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3269 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3270 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3271 break; 3272 default: 3273 break; 3274 } 3275 3276 return 0; 3277 } 3278 3279 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3280 struct amdgpu_irq_src *source, 3281 unsigned type, 3282 enum amdgpu_interrupt_state state) 3283 { 3284 switch (type) { 3285 case AMDGPU_CRTC_IRQ_VBLANK1: 3286 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3287 break; 3288 case AMDGPU_CRTC_IRQ_VBLANK2: 3289 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3290 break; 3291 case AMDGPU_CRTC_IRQ_VBLANK3: 3292 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3293 break; 3294 case AMDGPU_CRTC_IRQ_VBLANK4: 3295 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3296 break; 3297 case AMDGPU_CRTC_IRQ_VBLANK5: 3298 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3299 break; 3300 case AMDGPU_CRTC_IRQ_VBLANK6: 3301 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3302 break; 3303 case AMDGPU_CRTC_IRQ_VLINE1: 3304 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3305 break; 3306 case AMDGPU_CRTC_IRQ_VLINE2: 3307 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3308 break; 3309 case AMDGPU_CRTC_IRQ_VLINE3: 3310 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3311 break; 3312 case AMDGPU_CRTC_IRQ_VLINE4: 3313 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3314 break; 3315 case AMDGPU_CRTC_IRQ_VLINE5: 3316 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3317 break; 3318 case AMDGPU_CRTC_IRQ_VLINE6: 3319 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3320 break; 3321 default: 3322 break; 3323 } 3324 return 0; 3325 } 3326 3327 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3328 struct amdgpu_irq_src *src, 3329 unsigned type, 3330 enum amdgpu_interrupt_state state) 3331 { 3332 u32 reg; 3333 3334 if (type >= adev->mode_info.num_crtc) { 3335 DRM_ERROR("invalid pageflip crtc %d\n", type); 3336 return -EINVAL; 3337 } 3338 3339 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3340 if (state == AMDGPU_IRQ_STATE_DISABLE) 3341 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3342 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3343 else 3344 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3345 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3346 3347 return 0; 3348 } 3349 3350 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3351 struct amdgpu_irq_src *source, 3352 struct amdgpu_iv_entry *entry) 3353 { 3354 unsigned long flags; 3355 unsigned crtc_id; 3356 struct amdgpu_crtc *amdgpu_crtc; 3357 struct amdgpu_flip_work *works; 3358 3359 crtc_id = (entry->src_id - 8) >> 1; 3360 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3361 3362 if (crtc_id >= adev->mode_info.num_crtc) { 3363 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3364 return -EINVAL; 3365 } 3366 3367 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3368 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3369 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3370 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3371 3372 /* IRQ could occur when in initial stage */ 3373 if(amdgpu_crtc == NULL) 3374 return 0; 3375 3376 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3377 works = amdgpu_crtc->pflip_works; 3378 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3379 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3380 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3381 amdgpu_crtc->pflip_status, 3382 AMDGPU_FLIP_SUBMITTED); 3383 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3384 return 0; 3385 } 3386 3387 /* page flip completed. clean up */ 3388 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3389 amdgpu_crtc->pflip_works = NULL; 3390 3391 /* wakeup usersapce */ 3392 if(works->event) 3393 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3394 3395 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3396 3397 drm_crtc_vblank_put(&amdgpu_crtc->base); 3398 schedule_work(&works->unpin_work); 3399 3400 return 0; 3401 } 3402 3403 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3404 int hpd) 3405 { 3406 u32 tmp; 3407 3408 if (hpd >= adev->mode_info.num_hpd) { 3409 DRM_DEBUG("invalid hdp %d\n", hpd); 3410 return; 3411 } 3412 3413 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3414 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3415 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3416 } 3417 3418 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3419 int crtc) 3420 { 3421 u32 tmp; 3422 3423 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3424 DRM_DEBUG("invalid crtc %d\n", crtc); 3425 return; 3426 } 3427 3428 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3429 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3430 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3431 } 3432 3433 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3434 int crtc) 3435 { 3436 u32 tmp; 3437 3438 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3439 DRM_DEBUG("invalid crtc %d\n", crtc); 3440 return; 3441 } 3442 3443 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3444 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3445 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3446 } 3447 3448 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3449 struct amdgpu_irq_src *source, 3450 struct amdgpu_iv_entry *entry) 3451 { 3452 unsigned crtc = entry->src_id - 1; 3453 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3454 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3455 3456 switch (entry->src_data[0]) { 3457 case 0: /* vblank */ 3458 if (disp_int & interrupt_status_offsets[crtc].vblank) 3459 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3460 else 3461 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3462 3463 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3464 drm_handle_vblank(adev->ddev, crtc); 3465 } 3466 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3467 3468 break; 3469 case 1: /* vline */ 3470 if (disp_int & interrupt_status_offsets[crtc].vline) 3471 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3472 else 3473 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3474 3475 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3476 3477 break; 3478 default: 3479 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3480 break; 3481 } 3482 3483 return 0; 3484 } 3485 3486 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3487 struct amdgpu_irq_src *source, 3488 struct amdgpu_iv_entry *entry) 3489 { 3490 uint32_t disp_int, mask; 3491 unsigned hpd; 3492 3493 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3494 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3495 return 0; 3496 } 3497 3498 hpd = entry->src_data[0]; 3499 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3500 mask = interrupt_status_offsets[hpd].hpd; 3501 3502 if (disp_int & mask) { 3503 dce_v11_0_hpd_int_ack(adev, hpd); 3504 schedule_work(&adev->hotplug_work); 3505 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3506 } 3507 3508 return 0; 3509 } 3510 3511 static int dce_v11_0_set_clockgating_state(void *handle, 3512 enum amd_clockgating_state state) 3513 { 3514 return 0; 3515 } 3516 3517 static int dce_v11_0_set_powergating_state(void *handle, 3518 enum amd_powergating_state state) 3519 { 3520 return 0; 3521 } 3522 3523 static const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3524 .name = "dce_v11_0", 3525 .early_init = dce_v11_0_early_init, 3526 .late_init = NULL, 3527 .sw_init = dce_v11_0_sw_init, 3528 .sw_fini = dce_v11_0_sw_fini, 3529 .hw_init = dce_v11_0_hw_init, 3530 .hw_fini = dce_v11_0_hw_fini, 3531 .suspend = dce_v11_0_suspend, 3532 .resume = dce_v11_0_resume, 3533 .is_idle = dce_v11_0_is_idle, 3534 .wait_for_idle = dce_v11_0_wait_for_idle, 3535 .soft_reset = dce_v11_0_soft_reset, 3536 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3537 .set_powergating_state = dce_v11_0_set_powergating_state, 3538 }; 3539 3540 static void 3541 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3542 struct drm_display_mode *mode, 3543 struct drm_display_mode *adjusted_mode) 3544 { 3545 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3546 3547 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3548 3549 /* need to call this here rather than in prepare() since we need some crtc info */ 3550 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3551 3552 /* set scaler clears this on some chips */ 3553 dce_v11_0_set_interleave(encoder->crtc, mode); 3554 3555 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3556 dce_v11_0_afmt_enable(encoder, true); 3557 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3558 } 3559 } 3560 3561 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3562 { 3563 struct amdgpu_device *adev = encoder->dev->dev_private; 3564 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3565 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3566 3567 if ((amdgpu_encoder->active_device & 3568 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3569 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3570 ENCODER_OBJECT_ID_NONE)) { 3571 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3572 if (dig) { 3573 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3574 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3575 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3576 } 3577 } 3578 3579 amdgpu_atombios_scratch_regs_lock(adev, true); 3580 3581 if (connector) { 3582 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3583 3584 /* select the clock/data port if it uses a router */ 3585 if (amdgpu_connector->router.cd_valid) 3586 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3587 3588 /* turn eDP panel on for mode set */ 3589 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3590 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3591 ATOM_TRANSMITTER_ACTION_POWER_ON); 3592 } 3593 3594 /* this is needed for the pll/ss setup to work correctly in some cases */ 3595 amdgpu_atombios_encoder_set_crtc_source(encoder); 3596 /* set up the FMT blocks */ 3597 dce_v11_0_program_fmt(encoder); 3598 } 3599 3600 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3601 { 3602 struct drm_device *dev = encoder->dev; 3603 struct amdgpu_device *adev = dev->dev_private; 3604 3605 /* need to call this here as we need the crtc set up */ 3606 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3607 amdgpu_atombios_scratch_regs_lock(adev, false); 3608 } 3609 3610 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3611 { 3612 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3613 struct amdgpu_encoder_atom_dig *dig; 3614 3615 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3616 3617 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3618 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3619 dce_v11_0_afmt_enable(encoder, false); 3620 dig = amdgpu_encoder->enc_priv; 3621 dig->dig_encoder = -1; 3622 } 3623 amdgpu_encoder->active_device = 0; 3624 } 3625 3626 /* these are handled by the primary encoders */ 3627 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3628 { 3629 3630 } 3631 3632 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3633 { 3634 3635 } 3636 3637 static void 3638 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3639 struct drm_display_mode *mode, 3640 struct drm_display_mode *adjusted_mode) 3641 { 3642 3643 } 3644 3645 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3646 { 3647 3648 } 3649 3650 static void 3651 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3652 { 3653 3654 } 3655 3656 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3657 .dpms = dce_v11_0_ext_dpms, 3658 .prepare = dce_v11_0_ext_prepare, 3659 .mode_set = dce_v11_0_ext_mode_set, 3660 .commit = dce_v11_0_ext_commit, 3661 .disable = dce_v11_0_ext_disable, 3662 /* no detect for TMDS/LVDS yet */ 3663 }; 3664 3665 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3666 .dpms = amdgpu_atombios_encoder_dpms, 3667 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3668 .prepare = dce_v11_0_encoder_prepare, 3669 .mode_set = dce_v11_0_encoder_mode_set, 3670 .commit = dce_v11_0_encoder_commit, 3671 .disable = dce_v11_0_encoder_disable, 3672 .detect = amdgpu_atombios_encoder_dig_detect, 3673 }; 3674 3675 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3676 .dpms = amdgpu_atombios_encoder_dpms, 3677 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3678 .prepare = dce_v11_0_encoder_prepare, 3679 .mode_set = dce_v11_0_encoder_mode_set, 3680 .commit = dce_v11_0_encoder_commit, 3681 .detect = amdgpu_atombios_encoder_dac_detect, 3682 }; 3683 3684 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3685 { 3686 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3687 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3688 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3689 kfree(amdgpu_encoder->enc_priv); 3690 drm_encoder_cleanup(encoder); 3691 kfree(amdgpu_encoder); 3692 } 3693 3694 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3695 .destroy = dce_v11_0_encoder_destroy, 3696 }; 3697 3698 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3699 uint32_t encoder_enum, 3700 uint32_t supported_device, 3701 u16 caps) 3702 { 3703 struct drm_device *dev = adev->ddev; 3704 struct drm_encoder *encoder; 3705 struct amdgpu_encoder *amdgpu_encoder; 3706 3707 /* see if we already added it */ 3708 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3709 amdgpu_encoder = to_amdgpu_encoder(encoder); 3710 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3711 amdgpu_encoder->devices |= supported_device; 3712 return; 3713 } 3714 3715 } 3716 3717 /* add a new one */ 3718 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3719 if (!amdgpu_encoder) 3720 return; 3721 3722 encoder = &amdgpu_encoder->base; 3723 switch (adev->mode_info.num_crtc) { 3724 case 1: 3725 encoder->possible_crtcs = 0x1; 3726 break; 3727 case 2: 3728 default: 3729 encoder->possible_crtcs = 0x3; 3730 break; 3731 case 3: 3732 encoder->possible_crtcs = 0x7; 3733 break; 3734 case 4: 3735 encoder->possible_crtcs = 0xf; 3736 break; 3737 case 5: 3738 encoder->possible_crtcs = 0x1f; 3739 break; 3740 case 6: 3741 encoder->possible_crtcs = 0x3f; 3742 break; 3743 } 3744 3745 amdgpu_encoder->enc_priv = NULL; 3746 3747 amdgpu_encoder->encoder_enum = encoder_enum; 3748 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3749 amdgpu_encoder->devices = supported_device; 3750 amdgpu_encoder->rmx_type = RMX_OFF; 3751 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3752 amdgpu_encoder->is_ext_encoder = false; 3753 amdgpu_encoder->caps = caps; 3754 3755 switch (amdgpu_encoder->encoder_id) { 3756 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3757 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3758 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3759 DRM_MODE_ENCODER_DAC, NULL); 3760 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3761 break; 3762 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3763 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3764 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3765 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3767 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3768 amdgpu_encoder->rmx_type = RMX_FULL; 3769 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3770 DRM_MODE_ENCODER_LVDS, NULL); 3771 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3772 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3773 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3774 DRM_MODE_ENCODER_DAC, NULL); 3775 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3776 } else { 3777 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3778 DRM_MODE_ENCODER_TMDS, NULL); 3779 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3780 } 3781 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3782 break; 3783 case ENCODER_OBJECT_ID_SI170B: 3784 case ENCODER_OBJECT_ID_CH7303: 3785 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3786 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3787 case ENCODER_OBJECT_ID_TITFP513: 3788 case ENCODER_OBJECT_ID_VT1623: 3789 case ENCODER_OBJECT_ID_HDMI_SI1930: 3790 case ENCODER_OBJECT_ID_TRAVIS: 3791 case ENCODER_OBJECT_ID_NUTMEG: 3792 /* these are handled by the primary encoders */ 3793 amdgpu_encoder->is_ext_encoder = true; 3794 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3795 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3796 DRM_MODE_ENCODER_LVDS, NULL); 3797 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3798 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3799 DRM_MODE_ENCODER_DAC, NULL); 3800 else 3801 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3802 DRM_MODE_ENCODER_TMDS, NULL); 3803 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3804 break; 3805 } 3806 } 3807 3808 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3809 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3810 .bandwidth_update = &dce_v11_0_bandwidth_update, 3811 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3812 .vblank_wait = &dce_v11_0_vblank_wait, 3813 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3814 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3815 .hpd_sense = &dce_v11_0_hpd_sense, 3816 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3817 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3818 .page_flip = &dce_v11_0_page_flip, 3819 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3820 .add_encoder = &dce_v11_0_encoder_add, 3821 .add_connector = &amdgpu_connector_add, 3822 .stop_mc_access = &dce_v11_0_stop_mc_access, 3823 .resume_mc_access = &dce_v11_0_resume_mc_access, 3824 }; 3825 3826 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3827 { 3828 if (adev->mode_info.funcs == NULL) 3829 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3830 } 3831 3832 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3833 .set = dce_v11_0_set_crtc_irq_state, 3834 .process = dce_v11_0_crtc_irq, 3835 }; 3836 3837 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3838 .set = dce_v11_0_set_pageflip_irq_state, 3839 .process = dce_v11_0_pageflip_irq, 3840 }; 3841 3842 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3843 .set = dce_v11_0_set_hpd_irq_state, 3844 .process = dce_v11_0_hpd_irq, 3845 }; 3846 3847 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3848 { 3849 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3850 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3851 3852 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3853 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3854 3855 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3856 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3857 } 3858 3859 const struct amdgpu_ip_block_version dce_v11_0_ip_block = 3860 { 3861 .type = AMD_IP_BLOCK_TYPE_DCE, 3862 .major = 11, 3863 .minor = 0, 3864 .rev = 0, 3865 .funcs = &dce_v11_0_ip_funcs, 3866 }; 3867 3868 const struct amdgpu_ip_block_version dce_v11_2_ip_block = 3869 { 3870 .type = AMD_IP_BLOCK_TYPE_DCE, 3871 .major = 11, 3872 .minor = 2, 3873 .rev = 0, 3874 .funcs = &dce_v11_0_ip_funcs, 3875 }; 3876