1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 #include "dce/dce_11_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET, 75 DIG7_REGISTER_OFFSET, 76 DIG8_REGISTER_OFFSET 77 }; 78 79 static const struct { 80 uint32_t reg; 81 uint32_t vblank; 82 uint32_t vline; 83 uint32_t hpd; 84 85 } interrupt_status_offsets[] = { { 86 .reg = mmDISP_INTERRUPT_STATUS, 87 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 88 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 89 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 90 }, { 91 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 92 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 93 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 94 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 95 }, { 96 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 97 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 98 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 99 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 100 }, { 101 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 102 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 103 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 104 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 105 }, { 106 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 107 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 108 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 109 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 110 }, { 111 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 112 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 113 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 114 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 115 } }; 116 117 static const u32 cz_golden_settings_a11[] = 118 { 119 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 120 mmFBC_MISC, 0x1f311fff, 0x14300000, 121 }; 122 123 static const u32 cz_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 stoney_golden_settings_a11[] = 130 { 131 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, 132 mmFBC_MISC, 0x1f311fff, 0x14302000, 133 }; 134 135 static const u32 polaris11_golden_settings_a11[] = 136 { 137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 139 mmFBC_DEBUG1, 0xffffffff, 0x00000008, 140 mmFBC_MISC, 0x9f313fff, 0x14302008, 141 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 142 }; 143 144 static const u32 polaris10_golden_settings_a11[] = 145 { 146 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 147 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 148 mmFBC_MISC, 0x9f313fff, 0x14302008, 149 mmHDMI_CONTROL, 0x313f031f, 0x00000011, 150 }; 151 152 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) 153 { 154 switch (adev->asic_type) { 155 case CHIP_CARRIZO: 156 amdgpu_program_register_sequence(adev, 157 cz_mgcg_cgcg_init, 158 (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); 159 amdgpu_program_register_sequence(adev, 160 cz_golden_settings_a11, 161 (const u32)ARRAY_SIZE(cz_golden_settings_a11)); 162 break; 163 case CHIP_STONEY: 164 amdgpu_program_register_sequence(adev, 165 stoney_golden_settings_a11, 166 (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); 167 break; 168 case CHIP_POLARIS11: 169 amdgpu_program_register_sequence(adev, 170 polaris11_golden_settings_a11, 171 (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); 172 break; 173 case CHIP_POLARIS10: 174 amdgpu_program_register_sequence(adev, 175 polaris10_golden_settings_a11, 176 (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); 177 break; 178 default: 179 break; 180 } 181 } 182 183 static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, 184 u32 block_offset, u32 reg) 185 { 186 unsigned long flags; 187 u32 r; 188 189 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 190 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 191 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 192 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 193 194 return r; 195 } 196 197 static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, 198 u32 block_offset, u32 reg, u32 v) 199 { 200 unsigned long flags; 201 202 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 203 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 204 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 205 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 206 } 207 208 static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 209 { 210 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 211 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 212 return true; 213 else 214 return false; 215 } 216 217 static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 218 { 219 u32 pos1, pos2; 220 221 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 222 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 223 224 if (pos1 != pos2) 225 return true; 226 else 227 return false; 228 } 229 230 /** 231 * dce_v11_0_vblank_wait - vblank wait asic callback. 232 * 233 * @adev: amdgpu_device pointer 234 * @crtc: crtc to wait for vblank on 235 * 236 * Wait for vblank on the requested crtc (evergreen+). 237 */ 238 static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) 239 { 240 unsigned i = 100; 241 242 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 243 return; 244 245 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 246 return; 247 248 /* depending on when we hit vblank, we may be close to active; if so, 249 * wait for another frame. 250 */ 251 while (dce_v11_0_is_in_vblank(adev, crtc)) { 252 if (i++ == 100) { 253 i = 0; 254 if (!dce_v11_0_is_counter_moving(adev, crtc)) 255 break; 256 } 257 } 258 259 while (!dce_v11_0_is_in_vblank(adev, crtc)) { 260 if (i++ == 100) { 261 i = 0; 262 if (!dce_v11_0_is_counter_moving(adev, crtc)) 263 break; 264 } 265 } 266 } 267 268 static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 269 { 270 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 271 return 0; 272 else 273 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 274 } 275 276 static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev) 277 { 278 unsigned i; 279 280 /* Enable pflip interrupts */ 281 for (i = 0; i < adev->mode_info.num_crtc; i++) 282 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 283 } 284 285 static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 286 { 287 unsigned i; 288 289 /* Disable pflip interrupts */ 290 for (i = 0; i < adev->mode_info.num_crtc; i++) 291 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 292 } 293 294 /** 295 * dce_v11_0_page_flip - pageflip callback. 296 * 297 * @adev: amdgpu_device pointer 298 * @crtc_id: crtc to cleanup pageflip on 299 * @crtc_base: new address of the crtc (GPU MC address) 300 * 301 * Triggers the actual pageflip by updating the primary 302 * surface base address. 303 */ 304 static void dce_v11_0_page_flip(struct amdgpu_device *adev, 305 int crtc_id, u64 crtc_base, bool async) 306 { 307 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 308 u32 tmp; 309 310 /* flip immediate for async, default is vsync */ 311 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 312 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 313 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); 314 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 315 /* update the scanout addresses */ 316 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 317 upper_32_bits(crtc_base)); 318 /* writing to the low address triggers the update */ 319 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 320 lower_32_bits(crtc_base)); 321 /* post the write */ 322 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 323 } 324 325 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 326 u32 *vbl, u32 *position) 327 { 328 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 329 return -EINVAL; 330 331 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 332 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 333 334 return 0; 335 } 336 337 /** 338 * dce_v11_0_hpd_sense - hpd sense callback. 339 * 340 * @adev: amdgpu_device pointer 341 * @hpd: hpd (hotplug detect) pin 342 * 343 * Checks if a digital monitor is connected (evergreen+). 344 * Returns true if connected, false if not connected. 345 */ 346 static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, 347 enum amdgpu_hpd_id hpd) 348 { 349 int idx; 350 bool connected = false; 351 352 switch (hpd) { 353 case AMDGPU_HPD_1: 354 idx = 0; 355 break; 356 case AMDGPU_HPD_2: 357 idx = 1; 358 break; 359 case AMDGPU_HPD_3: 360 idx = 2; 361 break; 362 case AMDGPU_HPD_4: 363 idx = 3; 364 break; 365 case AMDGPU_HPD_5: 366 idx = 4; 367 break; 368 case AMDGPU_HPD_6: 369 idx = 5; 370 break; 371 default: 372 return connected; 373 } 374 375 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 376 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 377 connected = true; 378 379 return connected; 380 } 381 382 /** 383 * dce_v11_0_hpd_set_polarity - hpd set polarity callback. 384 * 385 * @adev: amdgpu_device pointer 386 * @hpd: hpd (hotplug detect) pin 387 * 388 * Set the polarity of the hpd pin (evergreen+). 389 */ 390 static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, 391 enum amdgpu_hpd_id hpd) 392 { 393 u32 tmp; 394 bool connected = dce_v11_0_hpd_sense(adev, hpd); 395 int idx; 396 397 switch (hpd) { 398 case AMDGPU_HPD_1: 399 idx = 0; 400 break; 401 case AMDGPU_HPD_2: 402 idx = 1; 403 break; 404 case AMDGPU_HPD_3: 405 idx = 2; 406 break; 407 case AMDGPU_HPD_4: 408 idx = 3; 409 break; 410 case AMDGPU_HPD_5: 411 idx = 4; 412 break; 413 case AMDGPU_HPD_6: 414 idx = 5; 415 break; 416 default: 417 return; 418 } 419 420 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 421 if (connected) 422 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 423 else 424 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 425 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 426 } 427 428 /** 429 * dce_v11_0_hpd_init - hpd setup callback. 430 * 431 * @adev: amdgpu_device pointer 432 * 433 * Setup the hpd pins used by the card (evergreen+). 434 * Enable the pin, set the polarity, and enable the hpd interrupts. 435 */ 436 static void dce_v11_0_hpd_init(struct amdgpu_device *adev) 437 { 438 struct drm_device *dev = adev->ddev; 439 struct drm_connector *connector; 440 u32 tmp; 441 int idx; 442 443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 444 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 445 446 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 447 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 448 /* don't try to enable hpd on eDP or LVDS avoid breaking the 449 * aux dp channel on imac and help (but not completely fix) 450 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 451 * also avoid interrupt storms during dpms. 452 */ 453 continue; 454 } 455 456 switch (amdgpu_connector->hpd.hpd) { 457 case AMDGPU_HPD_1: 458 idx = 0; 459 break; 460 case AMDGPU_HPD_2: 461 idx = 1; 462 break; 463 case AMDGPU_HPD_3: 464 idx = 2; 465 break; 466 case AMDGPU_HPD_4: 467 idx = 3; 468 break; 469 case AMDGPU_HPD_5: 470 idx = 4; 471 break; 472 case AMDGPU_HPD_6: 473 idx = 5; 474 break; 475 default: 476 continue; 477 } 478 479 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 480 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 481 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 482 483 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 484 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 485 DC_HPD_CONNECT_INT_DELAY, 486 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 487 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 488 DC_HPD_DISCONNECT_INT_DELAY, 489 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 490 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 491 492 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 493 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 494 } 495 } 496 497 /** 498 * dce_v11_0_hpd_fini - hpd tear down callback. 499 * 500 * @adev: amdgpu_device pointer 501 * 502 * Tear down the hpd pins used by the card (evergreen+). 503 * Disable the hpd interrupts. 504 */ 505 static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) 506 { 507 struct drm_device *dev = adev->ddev; 508 struct drm_connector *connector; 509 u32 tmp; 510 int idx; 511 512 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 513 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 514 515 switch (amdgpu_connector->hpd.hpd) { 516 case AMDGPU_HPD_1: 517 idx = 0; 518 break; 519 case AMDGPU_HPD_2: 520 idx = 1; 521 break; 522 case AMDGPU_HPD_3: 523 idx = 2; 524 break; 525 case AMDGPU_HPD_4: 526 idx = 3; 527 break; 528 case AMDGPU_HPD_5: 529 idx = 4; 530 break; 531 case AMDGPU_HPD_6: 532 idx = 5; 533 break; 534 default: 535 continue; 536 } 537 538 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 539 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 540 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 541 542 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); 543 } 544 } 545 546 static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 547 { 548 return mmDC_GPIO_HPD_A; 549 } 550 551 static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) 552 { 553 u32 crtc_hung = 0; 554 u32 crtc_status[6]; 555 u32 i, j, tmp; 556 557 for (i = 0; i < adev->mode_info.num_crtc; i++) { 558 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 559 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 560 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 561 crtc_hung |= (1 << i); 562 } 563 } 564 565 for (j = 0; j < 10; j++) { 566 for (i = 0; i < adev->mode_info.num_crtc; i++) { 567 if (crtc_hung & (1 << i)) { 568 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 569 if (tmp != crtc_status[i]) 570 crtc_hung &= ~(1 << i); 571 } 572 } 573 if (crtc_hung == 0) 574 return false; 575 udelay(100); 576 } 577 578 return true; 579 } 580 581 static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, 582 struct amdgpu_mode_mc_save *save) 583 { 584 u32 crtc_enabled, tmp; 585 int i; 586 587 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 588 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 589 590 /* disable VGA render */ 591 tmp = RREG32(mmVGA_RENDER_CONTROL); 592 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 593 WREG32(mmVGA_RENDER_CONTROL, tmp); 594 595 /* blank the display controllers */ 596 for (i = 0; i < adev->mode_info.num_crtc; i++) { 597 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 598 CRTC_CONTROL, CRTC_MASTER_EN); 599 if (crtc_enabled) { 600 #if 1 601 save->crtc_enabled[i] = true; 602 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 603 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 604 /*it is correct only for RGB ; black is 0*/ 605 WREG32(mmCRTC_BLANK_DATA_COLOR + crtc_offsets[i], 0); 606 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 607 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 608 } 609 #else 610 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 611 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 612 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 613 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 614 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 615 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 616 save->crtc_enabled[i] = false; 617 /* ***** */ 618 #endif 619 } else { 620 save->crtc_enabled[i] = false; 621 } 622 } 623 } 624 625 static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, 626 struct amdgpu_mode_mc_save *save) 627 { 628 u32 tmp; 629 int i; 630 631 /* update crtc base addresses */ 632 for (i = 0; i < adev->mode_info.num_crtc; i++) { 633 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 634 upper_32_bits(adev->mc.vram_start)); 635 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 636 (u32)adev->mc.vram_start); 637 638 if (save->crtc_enabled[i]) { 639 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 640 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 641 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 642 } 643 } 644 645 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 646 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 647 648 /* Unlock vga access */ 649 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 650 mdelay(1); 651 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 652 } 653 654 static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, 655 bool render) 656 { 657 u32 tmp; 658 659 /* Lockout access through VGA aperture*/ 660 tmp = RREG32(mmVGA_HDP_CONTROL); 661 if (render) 662 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 663 else 664 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 665 WREG32(mmVGA_HDP_CONTROL, tmp); 666 667 /* disable VGA render */ 668 tmp = RREG32(mmVGA_RENDER_CONTROL); 669 if (render) 670 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 671 else 672 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 673 WREG32(mmVGA_RENDER_CONTROL, tmp); 674 } 675 676 static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev) 677 { 678 int num_crtc = 0; 679 680 switch (adev->asic_type) { 681 case CHIP_CARRIZO: 682 num_crtc = 3; 683 break; 684 case CHIP_STONEY: 685 num_crtc = 2; 686 break; 687 case CHIP_POLARIS10: 688 num_crtc = 6; 689 break; 690 case CHIP_POLARIS11: 691 num_crtc = 5; 692 break; 693 default: 694 num_crtc = 0; 695 } 696 return num_crtc; 697 } 698 699 void dce_v11_0_disable_dce(struct amdgpu_device *adev) 700 { 701 /*Disable VGA render and enabled crtc, if has DCE engine*/ 702 if (amdgpu_atombios_has_dce_engine_info(adev)) { 703 u32 tmp; 704 int crtc_enabled, i; 705 706 dce_v11_0_set_vga_render_state(adev, false); 707 708 /*Disable crtc*/ 709 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) { 710 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 711 CRTC_CONTROL, CRTC_MASTER_EN); 712 if (crtc_enabled) { 713 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 714 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 715 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 716 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 717 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 718 } 719 } 720 } 721 } 722 723 static void dce_v11_0_program_fmt(struct drm_encoder *encoder) 724 { 725 struct drm_device *dev = encoder->dev; 726 struct amdgpu_device *adev = dev->dev_private; 727 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 728 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 729 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 730 int bpc = 0; 731 u32 tmp = 0; 732 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 733 734 if (connector) { 735 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 736 bpc = amdgpu_connector_get_monitor_bpc(connector); 737 dither = amdgpu_connector->dither; 738 } 739 740 /* LVDS/eDP FMT is set up by atom */ 741 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 742 return; 743 744 /* not needed for analog */ 745 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 746 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 747 return; 748 749 if (bpc == 0) 750 return; 751 752 switch (bpc) { 753 case 6: 754 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 755 /* XXX sort out optimal dither settings */ 756 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 757 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 758 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 759 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 760 } else { 761 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 762 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 763 } 764 break; 765 case 8: 766 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 767 /* XXX sort out optimal dither settings */ 768 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 769 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 770 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 771 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 772 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 773 } else { 774 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 775 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 776 } 777 break; 778 case 10: 779 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 780 /* XXX sort out optimal dither settings */ 781 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 782 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 783 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 784 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 785 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 786 } else { 787 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 788 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 789 } 790 break; 791 default: 792 /* not needed */ 793 break; 794 } 795 796 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 797 } 798 799 800 /* display watermark setup */ 801 /** 802 * dce_v11_0_line_buffer_adjust - Set up the line buffer 803 * 804 * @adev: amdgpu_device pointer 805 * @amdgpu_crtc: the selected display controller 806 * @mode: the current display mode on the selected display 807 * controller 808 * 809 * Setup up the line buffer allocation for 810 * the selected display controller (CIK). 811 * Returns the line buffer size in pixels. 812 */ 813 static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, 814 struct amdgpu_crtc *amdgpu_crtc, 815 struct drm_display_mode *mode) 816 { 817 u32 tmp, buffer_alloc, i, mem_cfg; 818 u32 pipe_offset = amdgpu_crtc->crtc_id; 819 /* 820 * Line Buffer Setup 821 * There are 6 line buffers, one for each display controllers. 822 * There are 3 partitions per LB. Select the number of partitions 823 * to enable based on the display width. For display widths larger 824 * than 4096, you need use to use 2 display controllers and combine 825 * them using the stereo blender. 826 */ 827 if (amdgpu_crtc->base.enabled && mode) { 828 if (mode->crtc_hdisplay < 1920) { 829 mem_cfg = 1; 830 buffer_alloc = 2; 831 } else if (mode->crtc_hdisplay < 2560) { 832 mem_cfg = 2; 833 buffer_alloc = 2; 834 } else if (mode->crtc_hdisplay < 4096) { 835 mem_cfg = 0; 836 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 837 } else { 838 DRM_DEBUG_KMS("Mode too big for LB!\n"); 839 mem_cfg = 0; 840 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 841 } 842 } else { 843 mem_cfg = 1; 844 buffer_alloc = 0; 845 } 846 847 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 848 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 849 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 850 851 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 852 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 853 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 854 855 for (i = 0; i < adev->usec_timeout; i++) { 856 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 857 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 858 break; 859 udelay(1); 860 } 861 862 if (amdgpu_crtc->base.enabled && mode) { 863 switch (mem_cfg) { 864 case 0: 865 default: 866 return 4096 * 2; 867 case 1: 868 return 1920 * 2; 869 case 2: 870 return 2560 * 2; 871 } 872 } 873 874 /* controller not enabled, so no lb used */ 875 return 0; 876 } 877 878 /** 879 * cik_get_number_of_dram_channels - get the number of dram channels 880 * 881 * @adev: amdgpu_device pointer 882 * 883 * Look up the number of video ram channels (CIK). 884 * Used for display watermark bandwidth calculations 885 * Returns the number of dram channels 886 */ 887 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 888 { 889 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 890 891 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 892 case 0: 893 default: 894 return 1; 895 case 1: 896 return 2; 897 case 2: 898 return 4; 899 case 3: 900 return 8; 901 case 4: 902 return 3; 903 case 5: 904 return 6; 905 case 6: 906 return 10; 907 case 7: 908 return 12; 909 case 8: 910 return 16; 911 } 912 } 913 914 struct dce10_wm_params { 915 u32 dram_channels; /* number of dram channels */ 916 u32 yclk; /* bandwidth per dram data pin in kHz */ 917 u32 sclk; /* engine clock in kHz */ 918 u32 disp_clk; /* display clock in kHz */ 919 u32 src_width; /* viewport width */ 920 u32 active_time; /* active display time in ns */ 921 u32 blank_time; /* blank time in ns */ 922 bool interlaced; /* mode is interlaced */ 923 fixed20_12 vsc; /* vertical scale ratio */ 924 u32 num_heads; /* number of active crtcs */ 925 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 926 u32 lb_size; /* line buffer allocated to pipe */ 927 u32 vtaps; /* vertical scaler taps */ 928 }; 929 930 /** 931 * dce_v11_0_dram_bandwidth - get the dram bandwidth 932 * 933 * @wm: watermark calculation data 934 * 935 * Calculate the raw dram bandwidth (CIK). 936 * Used for display watermark bandwidth calculations 937 * Returns the dram bandwidth in MBytes/s 938 */ 939 static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) 940 { 941 /* Calculate raw DRAM Bandwidth */ 942 fixed20_12 dram_efficiency; /* 0.7 */ 943 fixed20_12 yclk, dram_channels, bandwidth; 944 fixed20_12 a; 945 946 a.full = dfixed_const(1000); 947 yclk.full = dfixed_const(wm->yclk); 948 yclk.full = dfixed_div(yclk, a); 949 dram_channels.full = dfixed_const(wm->dram_channels * 4); 950 a.full = dfixed_const(10); 951 dram_efficiency.full = dfixed_const(7); 952 dram_efficiency.full = dfixed_div(dram_efficiency, a); 953 bandwidth.full = dfixed_mul(dram_channels, yclk); 954 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 955 956 return dfixed_trunc(bandwidth); 957 } 958 959 /** 960 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display 961 * 962 * @wm: watermark calculation data 963 * 964 * Calculate the dram bandwidth used for display (CIK). 965 * Used for display watermark bandwidth calculations 966 * Returns the dram bandwidth for display in MBytes/s 967 */ 968 static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 969 { 970 /* Calculate DRAM Bandwidth and the part allocated to display. */ 971 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 972 fixed20_12 yclk, dram_channels, bandwidth; 973 fixed20_12 a; 974 975 a.full = dfixed_const(1000); 976 yclk.full = dfixed_const(wm->yclk); 977 yclk.full = dfixed_div(yclk, a); 978 dram_channels.full = dfixed_const(wm->dram_channels * 4); 979 a.full = dfixed_const(10); 980 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 981 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 982 bandwidth.full = dfixed_mul(dram_channels, yclk); 983 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 984 985 return dfixed_trunc(bandwidth); 986 } 987 988 /** 989 * dce_v11_0_data_return_bandwidth - get the data return bandwidth 990 * 991 * @wm: watermark calculation data 992 * 993 * Calculate the data return bandwidth used for display (CIK). 994 * Used for display watermark bandwidth calculations 995 * Returns the data return bandwidth in MBytes/s 996 */ 997 static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) 998 { 999 /* Calculate the display Data return Bandwidth */ 1000 fixed20_12 return_efficiency; /* 0.8 */ 1001 fixed20_12 sclk, bandwidth; 1002 fixed20_12 a; 1003 1004 a.full = dfixed_const(1000); 1005 sclk.full = dfixed_const(wm->sclk); 1006 sclk.full = dfixed_div(sclk, a); 1007 a.full = dfixed_const(10); 1008 return_efficiency.full = dfixed_const(8); 1009 return_efficiency.full = dfixed_div(return_efficiency, a); 1010 a.full = dfixed_const(32); 1011 bandwidth.full = dfixed_mul(a, sclk); 1012 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 1013 1014 return dfixed_trunc(bandwidth); 1015 } 1016 1017 /** 1018 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth 1019 * 1020 * @wm: watermark calculation data 1021 * 1022 * Calculate the dmif bandwidth used for display (CIK). 1023 * Used for display watermark bandwidth calculations 1024 * Returns the dmif bandwidth in MBytes/s 1025 */ 1026 static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 1027 { 1028 /* Calculate the DMIF Request Bandwidth */ 1029 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 1030 fixed20_12 disp_clk, bandwidth; 1031 fixed20_12 a, b; 1032 1033 a.full = dfixed_const(1000); 1034 disp_clk.full = dfixed_const(wm->disp_clk); 1035 disp_clk.full = dfixed_div(disp_clk, a); 1036 a.full = dfixed_const(32); 1037 b.full = dfixed_mul(a, disp_clk); 1038 1039 a.full = dfixed_const(10); 1040 disp_clk_request_efficiency.full = dfixed_const(8); 1041 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1042 1043 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1044 1045 return dfixed_trunc(bandwidth); 1046 } 1047 1048 /** 1049 * dce_v11_0_available_bandwidth - get the min available bandwidth 1050 * 1051 * @wm: watermark calculation data 1052 * 1053 * Calculate the min available bandwidth used for display (CIK). 1054 * Used for display watermark bandwidth calculations 1055 * Returns the min available bandwidth in MBytes/s 1056 */ 1057 static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) 1058 { 1059 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1060 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); 1061 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); 1062 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); 1063 1064 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1065 } 1066 1067 /** 1068 * dce_v11_0_average_bandwidth - get the average available bandwidth 1069 * 1070 * @wm: watermark calculation data 1071 * 1072 * Calculate the average available bandwidth used for display (CIK). 1073 * Used for display watermark bandwidth calculations 1074 * Returns the average available bandwidth in MBytes/s 1075 */ 1076 static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) 1077 { 1078 /* Calculate the display mode Average Bandwidth 1079 * DisplayMode should contain the source and destination dimensions, 1080 * timing, etc. 1081 */ 1082 fixed20_12 bpp; 1083 fixed20_12 line_time; 1084 fixed20_12 src_width; 1085 fixed20_12 bandwidth; 1086 fixed20_12 a; 1087 1088 a.full = dfixed_const(1000); 1089 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1090 line_time.full = dfixed_div(line_time, a); 1091 bpp.full = dfixed_const(wm->bytes_per_pixel); 1092 src_width.full = dfixed_const(wm->src_width); 1093 bandwidth.full = dfixed_mul(src_width, bpp); 1094 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1095 bandwidth.full = dfixed_div(bandwidth, line_time); 1096 1097 return dfixed_trunc(bandwidth); 1098 } 1099 1100 /** 1101 * dce_v11_0_latency_watermark - get the latency watermark 1102 * 1103 * @wm: watermark calculation data 1104 * 1105 * Calculate the latency watermark (CIK). 1106 * Used for display watermark bandwidth calculations 1107 * Returns the latency watermark in ns 1108 */ 1109 static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) 1110 { 1111 /* First calculate the latency in ns */ 1112 u32 mc_latency = 2000; /* 2000 ns. */ 1113 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); 1114 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1115 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1116 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1117 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1118 (wm->num_heads * cursor_line_pair_return_time); 1119 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1120 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1121 u32 tmp, dmif_size = 12288; 1122 fixed20_12 a, b, c; 1123 1124 if (wm->num_heads == 0) 1125 return 0; 1126 1127 a.full = dfixed_const(2); 1128 b.full = dfixed_const(1); 1129 if ((wm->vsc.full > a.full) || 1130 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1131 (wm->vtaps >= 5) || 1132 ((wm->vsc.full >= a.full) && wm->interlaced)) 1133 max_src_lines_per_dst_line = 4; 1134 else 1135 max_src_lines_per_dst_line = 2; 1136 1137 a.full = dfixed_const(available_bandwidth); 1138 b.full = dfixed_const(wm->num_heads); 1139 a.full = dfixed_div(a, b); 1140 1141 b.full = dfixed_const(mc_latency + 512); 1142 c.full = dfixed_const(wm->disp_clk); 1143 b.full = dfixed_div(b, c); 1144 1145 c.full = dfixed_const(dmif_size); 1146 b.full = dfixed_div(c, b); 1147 1148 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1149 1150 b.full = dfixed_const(1000); 1151 c.full = dfixed_const(wm->disp_clk); 1152 b.full = dfixed_div(c, b); 1153 c.full = dfixed_const(wm->bytes_per_pixel); 1154 b.full = dfixed_mul(b, c); 1155 1156 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1157 1158 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1159 b.full = dfixed_const(1000); 1160 c.full = dfixed_const(lb_fill_bw); 1161 b.full = dfixed_div(c, b); 1162 a.full = dfixed_div(a, b); 1163 line_fill_time = dfixed_trunc(a); 1164 1165 if (line_fill_time < wm->active_time) 1166 return latency; 1167 else 1168 return latency + (line_fill_time - wm->active_time); 1169 1170 } 1171 1172 /** 1173 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1174 * average and available dram bandwidth 1175 * 1176 * @wm: watermark calculation data 1177 * 1178 * Check if the display average bandwidth fits in the display 1179 * dram bandwidth (CIK). 1180 * Used for display watermark bandwidth calculations 1181 * Returns true if the display fits, false if not. 1182 */ 1183 static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1184 { 1185 if (dce_v11_0_average_bandwidth(wm) <= 1186 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1187 return true; 1188 else 1189 return false; 1190 } 1191 1192 /** 1193 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check 1194 * average and available bandwidth 1195 * 1196 * @wm: watermark calculation data 1197 * 1198 * Check if the display average bandwidth fits in the display 1199 * available bandwidth (CIK). 1200 * Used for display watermark bandwidth calculations 1201 * Returns true if the display fits, false if not. 1202 */ 1203 static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1204 { 1205 if (dce_v11_0_average_bandwidth(wm) <= 1206 (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) 1207 return true; 1208 else 1209 return false; 1210 } 1211 1212 /** 1213 * dce_v11_0_check_latency_hiding - check latency hiding 1214 * 1215 * @wm: watermark calculation data 1216 * 1217 * Check latency hiding (CIK). 1218 * Used for display watermark bandwidth calculations 1219 * Returns true if the display fits, false if not. 1220 */ 1221 static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) 1222 { 1223 u32 lb_partitions = wm->lb_size / wm->src_width; 1224 u32 line_time = wm->active_time + wm->blank_time; 1225 u32 latency_tolerant_lines; 1226 u32 latency_hiding; 1227 fixed20_12 a; 1228 1229 a.full = dfixed_const(1); 1230 if (wm->vsc.full > a.full) 1231 latency_tolerant_lines = 1; 1232 else { 1233 if (lb_partitions <= (wm->vtaps + 1)) 1234 latency_tolerant_lines = 1; 1235 else 1236 latency_tolerant_lines = 2; 1237 } 1238 1239 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1240 1241 if (dce_v11_0_latency_watermark(wm) <= latency_hiding) 1242 return true; 1243 else 1244 return false; 1245 } 1246 1247 /** 1248 * dce_v11_0_program_watermarks - program display watermarks 1249 * 1250 * @adev: amdgpu_device pointer 1251 * @amdgpu_crtc: the selected display controller 1252 * @lb_size: line buffer size 1253 * @num_heads: number of display controllers in use 1254 * 1255 * Calculate and program the display watermarks for the 1256 * selected display controller (CIK). 1257 */ 1258 static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, 1259 struct amdgpu_crtc *amdgpu_crtc, 1260 u32 lb_size, u32 num_heads) 1261 { 1262 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1263 struct dce10_wm_params wm_low, wm_high; 1264 u32 pixel_period; 1265 u32 line_time = 0; 1266 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1267 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1268 1269 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1270 pixel_period = 1000000 / (u32)mode->clock; 1271 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1272 1273 /* watermark for high clocks */ 1274 if (adev->pm.dpm_enabled) { 1275 wm_high.yclk = 1276 amdgpu_dpm_get_mclk(adev, false) * 10; 1277 wm_high.sclk = 1278 amdgpu_dpm_get_sclk(adev, false) * 10; 1279 } else { 1280 wm_high.yclk = adev->pm.current_mclk * 10; 1281 wm_high.sclk = adev->pm.current_sclk * 10; 1282 } 1283 1284 wm_high.disp_clk = mode->clock; 1285 wm_high.src_width = mode->crtc_hdisplay; 1286 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1287 wm_high.blank_time = line_time - wm_high.active_time; 1288 wm_high.interlaced = false; 1289 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1290 wm_high.interlaced = true; 1291 wm_high.vsc = amdgpu_crtc->vsc; 1292 wm_high.vtaps = 1; 1293 if (amdgpu_crtc->rmx_type != RMX_OFF) 1294 wm_high.vtaps = 2; 1295 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1296 wm_high.lb_size = lb_size; 1297 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1298 wm_high.num_heads = num_heads; 1299 1300 /* set for high clocks */ 1301 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); 1302 1303 /* possibly force display priority to high */ 1304 /* should really do this at mode validation time... */ 1305 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1306 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1307 !dce_v11_0_check_latency_hiding(&wm_high) || 1308 (adev->mode_info.disp_priority == 2)) { 1309 DRM_DEBUG_KMS("force priority to high\n"); 1310 } 1311 1312 /* watermark for low clocks */ 1313 if (adev->pm.dpm_enabled) { 1314 wm_low.yclk = 1315 amdgpu_dpm_get_mclk(adev, true) * 10; 1316 wm_low.sclk = 1317 amdgpu_dpm_get_sclk(adev, true) * 10; 1318 } else { 1319 wm_low.yclk = adev->pm.current_mclk * 10; 1320 wm_low.sclk = adev->pm.current_sclk * 10; 1321 } 1322 1323 wm_low.disp_clk = mode->clock; 1324 wm_low.src_width = mode->crtc_hdisplay; 1325 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1326 wm_low.blank_time = line_time - wm_low.active_time; 1327 wm_low.interlaced = false; 1328 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1329 wm_low.interlaced = true; 1330 wm_low.vsc = amdgpu_crtc->vsc; 1331 wm_low.vtaps = 1; 1332 if (amdgpu_crtc->rmx_type != RMX_OFF) 1333 wm_low.vtaps = 2; 1334 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1335 wm_low.lb_size = lb_size; 1336 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1337 wm_low.num_heads = num_heads; 1338 1339 /* set for low clocks */ 1340 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); 1341 1342 /* possibly force display priority to high */ 1343 /* should really do this at mode validation time... */ 1344 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1345 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1346 !dce_v11_0_check_latency_hiding(&wm_low) || 1347 (adev->mode_info.disp_priority == 2)) { 1348 DRM_DEBUG_KMS("force priority to high\n"); 1349 } 1350 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1351 } 1352 1353 /* select wm A */ 1354 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1355 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1356 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1357 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1358 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1359 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1360 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1361 /* select wm B */ 1362 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1363 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1364 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1365 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1366 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1367 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1368 /* restore original selection */ 1369 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1370 1371 /* save values for DPM */ 1372 amdgpu_crtc->line_time = line_time; 1373 amdgpu_crtc->wm_high = latency_watermark_a; 1374 amdgpu_crtc->wm_low = latency_watermark_b; 1375 /* Save number of lines the linebuffer leads before the scanout */ 1376 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1377 } 1378 1379 /** 1380 * dce_v11_0_bandwidth_update - program display watermarks 1381 * 1382 * @adev: amdgpu_device pointer 1383 * 1384 * Calculate and program the display watermarks and line 1385 * buffer allocation (CIK). 1386 */ 1387 static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) 1388 { 1389 struct drm_display_mode *mode = NULL; 1390 u32 num_heads = 0, lb_size; 1391 int i; 1392 1393 amdgpu_update_display_priority(adev); 1394 1395 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1396 if (adev->mode_info.crtcs[i]->base.enabled) 1397 num_heads++; 1398 } 1399 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1400 mode = &adev->mode_info.crtcs[i]->base.mode; 1401 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1402 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1403 lb_size, num_heads); 1404 } 1405 } 1406 1407 static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) 1408 { 1409 int i; 1410 u32 offset, tmp; 1411 1412 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1413 offset = adev->mode_info.audio.pin[i].offset; 1414 tmp = RREG32_AUDIO_ENDPT(offset, 1415 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1416 if (((tmp & 1417 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1418 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1419 adev->mode_info.audio.pin[i].connected = false; 1420 else 1421 adev->mode_info.audio.pin[i].connected = true; 1422 } 1423 } 1424 1425 static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) 1426 { 1427 int i; 1428 1429 dce_v11_0_audio_get_connected_pins(adev); 1430 1431 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1432 if (adev->mode_info.audio.pin[i].connected) 1433 return &adev->mode_info.audio.pin[i]; 1434 } 1435 DRM_ERROR("No connected audio pins found!\n"); 1436 return NULL; 1437 } 1438 1439 static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1440 { 1441 struct amdgpu_device *adev = encoder->dev->dev_private; 1442 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1443 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1444 u32 tmp; 1445 1446 if (!dig || !dig->afmt || !dig->afmt->pin) 1447 return; 1448 1449 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1450 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1451 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1452 } 1453 1454 static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, 1455 struct drm_display_mode *mode) 1456 { 1457 struct amdgpu_device *adev = encoder->dev->dev_private; 1458 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1459 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1460 struct drm_connector *connector; 1461 struct amdgpu_connector *amdgpu_connector = NULL; 1462 u32 tmp; 1463 int interlace = 0; 1464 1465 if (!dig || !dig->afmt || !dig->afmt->pin) 1466 return; 1467 1468 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1469 if (connector->encoder == encoder) { 1470 amdgpu_connector = to_amdgpu_connector(connector); 1471 break; 1472 } 1473 } 1474 1475 if (!amdgpu_connector) { 1476 DRM_ERROR("Couldn't find encoder's connector\n"); 1477 return; 1478 } 1479 1480 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1481 interlace = 1; 1482 if (connector->latency_present[interlace]) { 1483 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1484 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1485 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1486 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1487 } else { 1488 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1489 VIDEO_LIPSYNC, 0); 1490 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1491 AUDIO_LIPSYNC, 0); 1492 } 1493 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1494 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1495 } 1496 1497 static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1498 { 1499 struct amdgpu_device *adev = encoder->dev->dev_private; 1500 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1501 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1502 struct drm_connector *connector; 1503 struct amdgpu_connector *amdgpu_connector = NULL; 1504 u32 tmp; 1505 u8 *sadb = NULL; 1506 int sad_count; 1507 1508 if (!dig || !dig->afmt || !dig->afmt->pin) 1509 return; 1510 1511 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1512 if (connector->encoder == encoder) { 1513 amdgpu_connector = to_amdgpu_connector(connector); 1514 break; 1515 } 1516 } 1517 1518 if (!amdgpu_connector) { 1519 DRM_ERROR("Couldn't find encoder's connector\n"); 1520 return; 1521 } 1522 1523 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1524 if (sad_count < 0) { 1525 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1526 sad_count = 0; 1527 } 1528 1529 /* program the speaker allocation */ 1530 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1531 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1532 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1533 DP_CONNECTION, 0); 1534 /* set HDMI mode */ 1535 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1536 HDMI_CONNECTION, 1); 1537 if (sad_count) 1538 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1539 SPEAKER_ALLOCATION, sadb[0]); 1540 else 1541 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1542 SPEAKER_ALLOCATION, 5); /* stereo */ 1543 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1544 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1545 1546 kfree(sadb); 1547 } 1548 1549 static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) 1550 { 1551 struct amdgpu_device *adev = encoder->dev->dev_private; 1552 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1553 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1554 struct drm_connector *connector; 1555 struct amdgpu_connector *amdgpu_connector = NULL; 1556 struct cea_sad *sads; 1557 int i, sad_count; 1558 1559 static const u16 eld_reg_to_type[][2] = { 1560 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1561 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1562 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1563 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1564 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1565 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1566 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1567 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1568 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1569 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1570 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1571 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1572 }; 1573 1574 if (!dig || !dig->afmt || !dig->afmt->pin) 1575 return; 1576 1577 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1578 if (connector->encoder == encoder) { 1579 amdgpu_connector = to_amdgpu_connector(connector); 1580 break; 1581 } 1582 } 1583 1584 if (!amdgpu_connector) { 1585 DRM_ERROR("Couldn't find encoder's connector\n"); 1586 return; 1587 } 1588 1589 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1590 if (sad_count <= 0) { 1591 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1592 return; 1593 } 1594 BUG_ON(!sads); 1595 1596 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1597 u32 tmp = 0; 1598 u8 stereo_freqs = 0; 1599 int max_channels = -1; 1600 int j; 1601 1602 for (j = 0; j < sad_count; j++) { 1603 struct cea_sad *sad = &sads[j]; 1604 1605 if (sad->format == eld_reg_to_type[i][1]) { 1606 if (sad->channels > max_channels) { 1607 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1608 MAX_CHANNELS, sad->channels); 1609 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1610 DESCRIPTOR_BYTE_2, sad->byte2); 1611 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1612 SUPPORTED_FREQUENCIES, sad->freq); 1613 max_channels = sad->channels; 1614 } 1615 1616 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1617 stereo_freqs |= sad->freq; 1618 else 1619 break; 1620 } 1621 } 1622 1623 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1624 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1625 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1626 } 1627 1628 kfree(sads); 1629 } 1630 1631 static void dce_v11_0_audio_enable(struct amdgpu_device *adev, 1632 struct amdgpu_audio_pin *pin, 1633 bool enable) 1634 { 1635 if (!pin) 1636 return; 1637 1638 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1639 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1640 } 1641 1642 static const u32 pin_offsets[] = 1643 { 1644 AUD0_REGISTER_OFFSET, 1645 AUD1_REGISTER_OFFSET, 1646 AUD2_REGISTER_OFFSET, 1647 AUD3_REGISTER_OFFSET, 1648 AUD4_REGISTER_OFFSET, 1649 AUD5_REGISTER_OFFSET, 1650 AUD6_REGISTER_OFFSET, 1651 AUD7_REGISTER_OFFSET, 1652 }; 1653 1654 static int dce_v11_0_audio_init(struct amdgpu_device *adev) 1655 { 1656 int i; 1657 1658 if (!amdgpu_audio) 1659 return 0; 1660 1661 adev->mode_info.audio.enabled = true; 1662 1663 switch (adev->asic_type) { 1664 case CHIP_CARRIZO: 1665 case CHIP_STONEY: 1666 adev->mode_info.audio.num_pins = 7; 1667 break; 1668 case CHIP_POLARIS10: 1669 adev->mode_info.audio.num_pins = 8; 1670 break; 1671 case CHIP_POLARIS11: 1672 adev->mode_info.audio.num_pins = 6; 1673 break; 1674 default: 1675 return -EINVAL; 1676 } 1677 1678 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1679 adev->mode_info.audio.pin[i].channels = -1; 1680 adev->mode_info.audio.pin[i].rate = -1; 1681 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1682 adev->mode_info.audio.pin[i].status_bits = 0; 1683 adev->mode_info.audio.pin[i].category_code = 0; 1684 adev->mode_info.audio.pin[i].connected = false; 1685 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1686 adev->mode_info.audio.pin[i].id = i; 1687 /* disable audio. it will be set up later */ 1688 /* XXX remove once we switch to ip funcs */ 1689 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1690 } 1691 1692 return 0; 1693 } 1694 1695 static void dce_v11_0_audio_fini(struct amdgpu_device *adev) 1696 { 1697 int i; 1698 1699 if (!amdgpu_audio) 1700 return; 1701 1702 if (!adev->mode_info.audio.enabled) 1703 return; 1704 1705 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1706 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1707 1708 adev->mode_info.audio.enabled = false; 1709 } 1710 1711 /* 1712 * update the N and CTS parameters for a given pixel clock rate 1713 */ 1714 static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1715 { 1716 struct drm_device *dev = encoder->dev; 1717 struct amdgpu_device *adev = dev->dev_private; 1718 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1719 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1720 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1721 u32 tmp; 1722 1723 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1724 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1725 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1726 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1727 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1728 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1729 1730 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1731 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1732 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1733 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1734 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1735 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1736 1737 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1738 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1739 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1740 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1741 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1742 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1743 1744 } 1745 1746 /* 1747 * build a HDMI Video Info Frame 1748 */ 1749 static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1750 void *buffer, size_t size) 1751 { 1752 struct drm_device *dev = encoder->dev; 1753 struct amdgpu_device *adev = dev->dev_private; 1754 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1755 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1756 uint8_t *frame = buffer + 3; 1757 uint8_t *header = buffer; 1758 1759 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1760 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1761 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1762 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1763 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1764 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1765 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1766 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1767 } 1768 1769 static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1770 { 1771 struct drm_device *dev = encoder->dev; 1772 struct amdgpu_device *adev = dev->dev_private; 1773 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1774 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1775 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1776 u32 dto_phase = 24 * 1000; 1777 u32 dto_modulo = clock; 1778 u32 tmp; 1779 1780 if (!dig || !dig->afmt) 1781 return; 1782 1783 /* XXX two dtos; generally use dto0 for hdmi */ 1784 /* Express [24MHz / target pixel clock] as an exact rational 1785 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1786 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1787 */ 1788 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1789 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1790 amdgpu_crtc->crtc_id); 1791 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1792 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1793 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1794 } 1795 1796 /* 1797 * update the info frames with the data from the current display mode 1798 */ 1799 static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, 1800 struct drm_display_mode *mode) 1801 { 1802 struct drm_device *dev = encoder->dev; 1803 struct amdgpu_device *adev = dev->dev_private; 1804 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1805 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1806 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1807 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1808 struct hdmi_avi_infoframe frame; 1809 ssize_t err; 1810 u32 tmp; 1811 int bpc = 8; 1812 1813 if (!dig || !dig->afmt) 1814 return; 1815 1816 /* Silent, r600_hdmi_enable will raise WARN for us */ 1817 if (!dig->afmt->enabled) 1818 return; 1819 1820 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1821 if (encoder->crtc) { 1822 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1823 bpc = amdgpu_crtc->bpc; 1824 } 1825 1826 /* disable audio prior to setting up hw */ 1827 dig->afmt->pin = dce_v11_0_audio_get_pin(adev); 1828 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1829 1830 dce_v11_0_audio_set_dto(encoder, mode->clock); 1831 1832 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1833 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1834 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1835 1836 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1837 1838 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1839 switch (bpc) { 1840 case 0: 1841 case 6: 1842 case 8: 1843 case 16: 1844 default: 1845 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1846 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1847 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1848 connector->name, bpc); 1849 break; 1850 case 10: 1851 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1852 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1853 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1854 connector->name); 1855 break; 1856 case 12: 1857 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1858 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1859 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1860 connector->name); 1861 break; 1862 } 1863 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1864 1865 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1866 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1867 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1868 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1869 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1870 1871 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1872 /* enable audio info frames (frames won't be set until audio is enabled) */ 1873 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1874 /* required for audio info values to be updated */ 1875 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1876 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1877 1878 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1879 /* required for audio info values to be updated */ 1880 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1881 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1882 1883 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1884 /* anything other than 0 */ 1885 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1886 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1887 1888 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1889 1890 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1891 /* set the default audio delay */ 1892 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1893 /* should be suffient for all audio modes and small enough for all hblanks */ 1894 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1895 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1896 1897 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1898 /* allow 60958 channel status fields to be updated */ 1899 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1900 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1901 1902 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1903 if (bpc > 8) 1904 /* clear SW CTS value */ 1905 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1906 else 1907 /* select SW CTS value */ 1908 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1909 /* allow hw to sent ACR packets when required */ 1910 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1911 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1912 1913 dce_v11_0_afmt_update_ACR(encoder, mode->clock); 1914 1915 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1916 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1917 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1918 1919 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1920 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1921 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1922 1923 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1924 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1925 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1926 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1927 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1928 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1929 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1930 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1931 1932 dce_v11_0_audio_write_speaker_allocation(encoder); 1933 1934 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1935 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1936 1937 dce_v11_0_afmt_audio_select_pin(encoder); 1938 dce_v11_0_audio_write_sad_regs(encoder); 1939 dce_v11_0_audio_write_latency_fields(encoder, mode); 1940 1941 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1942 if (err < 0) { 1943 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1944 return; 1945 } 1946 1947 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1948 if (err < 0) { 1949 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1950 return; 1951 } 1952 1953 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1954 1955 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1956 /* enable AVI info frames */ 1957 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1958 /* required for audio info values to be updated */ 1959 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1960 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1961 1962 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1963 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1964 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1965 1966 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1967 /* send audio packets */ 1968 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1969 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1970 1971 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1972 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1973 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1974 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1975 1976 /* enable audio after to setting up hw */ 1977 dce_v11_0_audio_enable(adev, dig->afmt->pin, true); 1978 } 1979 1980 static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1981 { 1982 struct drm_device *dev = encoder->dev; 1983 struct amdgpu_device *adev = dev->dev_private; 1984 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1985 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1986 1987 if (!dig || !dig->afmt) 1988 return; 1989 1990 /* Silent, r600_hdmi_enable will raise WARN for us */ 1991 if (enable && dig->afmt->enabled) 1992 return; 1993 if (!enable && !dig->afmt->enabled) 1994 return; 1995 1996 if (!enable && dig->afmt->pin) { 1997 dce_v11_0_audio_enable(adev, dig->afmt->pin, false); 1998 dig->afmt->pin = NULL; 1999 } 2000 2001 dig->afmt->enabled = enable; 2002 2003 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 2004 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 2005 } 2006 2007 static int dce_v11_0_afmt_init(struct amdgpu_device *adev) 2008 { 2009 int i; 2010 2011 for (i = 0; i < adev->mode_info.num_dig; i++) 2012 adev->mode_info.afmt[i] = NULL; 2013 2014 /* DCE11 has audio blocks tied to DIG encoders */ 2015 for (i = 0; i < adev->mode_info.num_dig; i++) { 2016 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 2017 if (adev->mode_info.afmt[i]) { 2018 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 2019 adev->mode_info.afmt[i]->id = i; 2020 } else { 2021 int j; 2022 for (j = 0; j < i; j++) { 2023 kfree(adev->mode_info.afmt[j]); 2024 adev->mode_info.afmt[j] = NULL; 2025 } 2026 return -ENOMEM; 2027 } 2028 } 2029 return 0; 2030 } 2031 2032 static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) 2033 { 2034 int i; 2035 2036 for (i = 0; i < adev->mode_info.num_dig; i++) { 2037 kfree(adev->mode_info.afmt[i]); 2038 adev->mode_info.afmt[i] = NULL; 2039 } 2040 } 2041 2042 static const u32 vga_control_regs[6] = 2043 { 2044 mmD1VGA_CONTROL, 2045 mmD2VGA_CONTROL, 2046 mmD3VGA_CONTROL, 2047 mmD4VGA_CONTROL, 2048 mmD5VGA_CONTROL, 2049 mmD6VGA_CONTROL, 2050 }; 2051 2052 static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) 2053 { 2054 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2055 struct drm_device *dev = crtc->dev; 2056 struct amdgpu_device *adev = dev->dev_private; 2057 u32 vga_control; 2058 2059 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2060 if (enable) 2061 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2062 else 2063 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2064 } 2065 2066 static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) 2067 { 2068 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2069 struct drm_device *dev = crtc->dev; 2070 struct amdgpu_device *adev = dev->dev_private; 2071 2072 if (enable) 2073 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2074 else 2075 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2076 } 2077 2078 static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, 2079 struct drm_framebuffer *fb, 2080 int x, int y, int atomic) 2081 { 2082 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2083 struct drm_device *dev = crtc->dev; 2084 struct amdgpu_device *adev = dev->dev_private; 2085 struct amdgpu_framebuffer *amdgpu_fb; 2086 struct drm_framebuffer *target_fb; 2087 struct drm_gem_object *obj; 2088 struct amdgpu_bo *rbo; 2089 uint64_t fb_location, tiling_flags; 2090 uint32_t fb_format, fb_pitch_pixels; 2091 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2092 u32 pipe_config; 2093 u32 tmp, viewport_w, viewport_h; 2094 int r; 2095 bool bypass_lut = false; 2096 2097 /* no fb bound */ 2098 if (!atomic && !crtc->primary->fb) { 2099 DRM_DEBUG_KMS("No FB bound\n"); 2100 return 0; 2101 } 2102 2103 if (atomic) { 2104 amdgpu_fb = to_amdgpu_framebuffer(fb); 2105 target_fb = fb; 2106 } else { 2107 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2108 target_fb = crtc->primary->fb; 2109 } 2110 2111 /* If atomic, assume fb object is pinned & idle & fenced and 2112 * just update base pointers 2113 */ 2114 obj = amdgpu_fb->obj; 2115 rbo = gem_to_amdgpu_bo(obj); 2116 r = amdgpu_bo_reserve(rbo, false); 2117 if (unlikely(r != 0)) 2118 return r; 2119 2120 if (atomic) { 2121 fb_location = amdgpu_bo_gpu_offset(rbo); 2122 } else { 2123 r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2124 if (unlikely(r != 0)) { 2125 amdgpu_bo_unreserve(rbo); 2126 return -EINVAL; 2127 } 2128 } 2129 2130 amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); 2131 amdgpu_bo_unreserve(rbo); 2132 2133 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2134 2135 switch (target_fb->pixel_format) { 2136 case DRM_FORMAT_C8: 2137 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2138 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2139 break; 2140 case DRM_FORMAT_XRGB4444: 2141 case DRM_FORMAT_ARGB4444: 2142 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2143 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2144 #ifdef __BIG_ENDIAN 2145 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2146 ENDIAN_8IN16); 2147 #endif 2148 break; 2149 case DRM_FORMAT_XRGB1555: 2150 case DRM_FORMAT_ARGB1555: 2151 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2152 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2153 #ifdef __BIG_ENDIAN 2154 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2155 ENDIAN_8IN16); 2156 #endif 2157 break; 2158 case DRM_FORMAT_BGRX5551: 2159 case DRM_FORMAT_BGRA5551: 2160 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2162 #ifdef __BIG_ENDIAN 2163 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2164 ENDIAN_8IN16); 2165 #endif 2166 break; 2167 case DRM_FORMAT_RGB565: 2168 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2169 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2170 #ifdef __BIG_ENDIAN 2171 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2172 ENDIAN_8IN16); 2173 #endif 2174 break; 2175 case DRM_FORMAT_XRGB8888: 2176 case DRM_FORMAT_ARGB8888: 2177 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2178 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2179 #ifdef __BIG_ENDIAN 2180 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2181 ENDIAN_8IN32); 2182 #endif 2183 break; 2184 case DRM_FORMAT_XRGB2101010: 2185 case DRM_FORMAT_ARGB2101010: 2186 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2187 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2188 #ifdef __BIG_ENDIAN 2189 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2190 ENDIAN_8IN32); 2191 #endif 2192 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2193 bypass_lut = true; 2194 break; 2195 case DRM_FORMAT_BGRX1010102: 2196 case DRM_FORMAT_BGRA1010102: 2197 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2198 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2199 #ifdef __BIG_ENDIAN 2200 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2201 ENDIAN_8IN32); 2202 #endif 2203 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2204 bypass_lut = true; 2205 break; 2206 default: 2207 DRM_ERROR("Unsupported screen format %s\n", 2208 drm_get_format_name(target_fb->pixel_format)); 2209 return -EINVAL; 2210 } 2211 2212 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2213 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2214 2215 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2216 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2217 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2218 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2219 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2220 2221 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2222 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2223 ARRAY_2D_TILED_THIN1); 2224 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2225 tile_split); 2226 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2227 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2228 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2229 mtaspect); 2230 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2231 ADDR_SURF_MICRO_TILING_DISPLAY); 2232 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2233 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2234 ARRAY_1D_TILED_THIN1); 2235 } 2236 2237 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2238 pipe_config); 2239 2240 dce_v11_0_vga_enable(crtc, false); 2241 2242 /* Make sure surface address is updated at vertical blank rather than 2243 * horizontal blank 2244 */ 2245 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2246 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2247 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2248 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2249 2250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2251 upper_32_bits(fb_location)); 2252 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2253 upper_32_bits(fb_location)); 2254 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2255 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2256 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2257 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2258 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2259 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2260 2261 /* 2262 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2263 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2264 * retain the full precision throughout the pipeline. 2265 */ 2266 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2267 if (bypass_lut) 2268 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2269 else 2270 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2271 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2272 2273 if (bypass_lut) 2274 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2275 2276 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2277 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2278 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2279 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2280 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2281 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2282 2283 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2284 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2285 2286 dce_v11_0_grph_enable(crtc, true); 2287 2288 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2289 target_fb->height); 2290 2291 x &= ~3; 2292 y &= ~1; 2293 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2294 (x << 16) | y); 2295 viewport_w = crtc->mode.hdisplay; 2296 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2297 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2298 (viewport_w << 16) | viewport_h); 2299 2300 /* set pageflip to happen only at start of vblank interval (front porch) */ 2301 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); 2302 2303 if (!atomic && fb && fb != crtc->primary->fb) { 2304 amdgpu_fb = to_amdgpu_framebuffer(fb); 2305 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2306 r = amdgpu_bo_reserve(rbo, false); 2307 if (unlikely(r != 0)) 2308 return r; 2309 amdgpu_bo_unpin(rbo); 2310 amdgpu_bo_unreserve(rbo); 2311 } 2312 2313 /* Bytes per pixel may have changed */ 2314 dce_v11_0_bandwidth_update(adev); 2315 2316 return 0; 2317 } 2318 2319 static void dce_v11_0_set_interleave(struct drm_crtc *crtc, 2320 struct drm_display_mode *mode) 2321 { 2322 struct drm_device *dev = crtc->dev; 2323 struct amdgpu_device *adev = dev->dev_private; 2324 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2325 u32 tmp; 2326 2327 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2328 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2329 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2330 else 2331 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2332 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2333 } 2334 2335 static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) 2336 { 2337 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2338 struct drm_device *dev = crtc->dev; 2339 struct amdgpu_device *adev = dev->dev_private; 2340 int i; 2341 u32 tmp; 2342 2343 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2344 2345 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2346 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2347 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2348 2349 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2350 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2351 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2352 2353 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2354 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2355 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2356 2357 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2358 2359 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2360 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2361 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2362 2363 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2364 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2365 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2366 2367 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2368 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2369 2370 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2371 for (i = 0; i < 256; i++) { 2372 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2373 (amdgpu_crtc->lut_r[i] << 20) | 2374 (amdgpu_crtc->lut_g[i] << 10) | 2375 (amdgpu_crtc->lut_b[i] << 0)); 2376 } 2377 2378 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2379 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2380 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2381 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); 2382 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2383 2384 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2385 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2386 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2387 2388 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2389 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2390 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2391 2392 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2393 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2394 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2395 2396 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2397 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2398 /* XXX this only needs to be programmed once per crtc at startup, 2399 * not sure where the best place for it is 2400 */ 2401 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2402 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2403 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2404 } 2405 2406 static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) 2407 { 2408 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2409 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2410 2411 switch (amdgpu_encoder->encoder_id) { 2412 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2413 if (dig->linkb) 2414 return 1; 2415 else 2416 return 0; 2417 break; 2418 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2419 if (dig->linkb) 2420 return 3; 2421 else 2422 return 2; 2423 break; 2424 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2425 if (dig->linkb) 2426 return 5; 2427 else 2428 return 4; 2429 break; 2430 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2431 return 6; 2432 break; 2433 default: 2434 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2435 return 0; 2436 } 2437 } 2438 2439 /** 2440 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. 2441 * 2442 * @crtc: drm crtc 2443 * 2444 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2445 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2446 * monitors a dedicated PPLL must be used. If a particular board has 2447 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2448 * as there is no need to program the PLL itself. If we are not able to 2449 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2450 * avoid messing up an existing monitor. 2451 * 2452 * Asic specific PLL information 2453 * 2454 * DCE 10.x 2455 * Tonga 2456 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2457 * CI 2458 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2459 * 2460 */ 2461 static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) 2462 { 2463 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2464 struct drm_device *dev = crtc->dev; 2465 struct amdgpu_device *adev = dev->dev_private; 2466 u32 pll_in_use; 2467 int pll; 2468 2469 if ((adev->asic_type == CHIP_POLARIS10) || 2470 (adev->asic_type == CHIP_POLARIS11)) { 2471 struct amdgpu_encoder *amdgpu_encoder = 2472 to_amdgpu_encoder(amdgpu_crtc->encoder); 2473 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2474 2475 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2476 return ATOM_DP_DTO; 2477 2478 switch (amdgpu_encoder->encoder_id) { 2479 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2480 if (dig->linkb) 2481 return ATOM_COMBOPHY_PLL1; 2482 else 2483 return ATOM_COMBOPHY_PLL0; 2484 break; 2485 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2486 if (dig->linkb) 2487 return ATOM_COMBOPHY_PLL3; 2488 else 2489 return ATOM_COMBOPHY_PLL2; 2490 break; 2491 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2492 if (dig->linkb) 2493 return ATOM_COMBOPHY_PLL5; 2494 else 2495 return ATOM_COMBOPHY_PLL4; 2496 break; 2497 default: 2498 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2499 return ATOM_PPLL_INVALID; 2500 } 2501 } 2502 2503 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2504 if (adev->clock.dp_extclk) 2505 /* skip PPLL programming if using ext clock */ 2506 return ATOM_PPLL_INVALID; 2507 else { 2508 /* use the same PPLL for all DP monitors */ 2509 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2510 if (pll != ATOM_PPLL_INVALID) 2511 return pll; 2512 } 2513 } else { 2514 /* use the same PPLL for all monitors with the same clock */ 2515 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2516 if (pll != ATOM_PPLL_INVALID) 2517 return pll; 2518 } 2519 2520 /* XXX need to determine what plls are available on each DCE11 part */ 2521 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2522 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { 2523 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2524 return ATOM_PPLL1; 2525 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2526 return ATOM_PPLL0; 2527 DRM_ERROR("unable to allocate a PPLL\n"); 2528 return ATOM_PPLL_INVALID; 2529 } else { 2530 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2531 return ATOM_PPLL2; 2532 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2533 return ATOM_PPLL1; 2534 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2535 return ATOM_PPLL0; 2536 DRM_ERROR("unable to allocate a PPLL\n"); 2537 return ATOM_PPLL_INVALID; 2538 } 2539 return ATOM_PPLL_INVALID; 2540 } 2541 2542 static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2543 { 2544 struct amdgpu_device *adev = crtc->dev->dev_private; 2545 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2546 uint32_t cur_lock; 2547 2548 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2549 if (lock) 2550 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2551 else 2552 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2553 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2554 } 2555 2556 static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) 2557 { 2558 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2559 struct amdgpu_device *adev = crtc->dev->dev_private; 2560 u32 tmp; 2561 2562 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2563 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2564 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2565 } 2566 2567 static void dce_v11_0_show_cursor(struct drm_crtc *crtc) 2568 { 2569 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2570 struct amdgpu_device *adev = crtc->dev->dev_private; 2571 u32 tmp; 2572 2573 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2574 upper_32_bits(amdgpu_crtc->cursor_addr)); 2575 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2576 lower_32_bits(amdgpu_crtc->cursor_addr)); 2577 2578 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2579 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2580 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2581 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2582 } 2583 2584 static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc, 2585 int x, int y) 2586 { 2587 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2588 struct amdgpu_device *adev = crtc->dev->dev_private; 2589 int xorigin = 0, yorigin = 0; 2590 2591 /* avivo cursor are offset into the total surface */ 2592 x += crtc->x; 2593 y += crtc->y; 2594 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2595 2596 if (x < 0) { 2597 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2598 x = 0; 2599 } 2600 if (y < 0) { 2601 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2602 y = 0; 2603 } 2604 2605 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2606 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2607 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2608 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2609 2610 amdgpu_crtc->cursor_x = x; 2611 amdgpu_crtc->cursor_y = y; 2612 2613 return 0; 2614 } 2615 2616 static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, 2617 int x, int y) 2618 { 2619 int ret; 2620 2621 dce_v11_0_lock_cursor(crtc, true); 2622 ret = dce_v11_0_cursor_move_locked(crtc, x, y); 2623 dce_v11_0_lock_cursor(crtc, false); 2624 2625 return ret; 2626 } 2627 2628 static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, 2629 struct drm_file *file_priv, 2630 uint32_t handle, 2631 uint32_t width, 2632 uint32_t height, 2633 int32_t hot_x, 2634 int32_t hot_y) 2635 { 2636 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2637 struct drm_gem_object *obj; 2638 struct amdgpu_bo *aobj; 2639 int ret; 2640 2641 if (!handle) { 2642 /* turn off cursor */ 2643 dce_v11_0_hide_cursor(crtc); 2644 obj = NULL; 2645 goto unpin; 2646 } 2647 2648 if ((width > amdgpu_crtc->max_cursor_width) || 2649 (height > amdgpu_crtc->max_cursor_height)) { 2650 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2651 return -EINVAL; 2652 } 2653 2654 obj = drm_gem_object_lookup(file_priv, handle); 2655 if (!obj) { 2656 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2657 return -ENOENT; 2658 } 2659 2660 aobj = gem_to_amdgpu_bo(obj); 2661 ret = amdgpu_bo_reserve(aobj, false); 2662 if (ret != 0) { 2663 drm_gem_object_unreference_unlocked(obj); 2664 return ret; 2665 } 2666 2667 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2668 amdgpu_bo_unreserve(aobj); 2669 if (ret) { 2670 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2671 drm_gem_object_unreference_unlocked(obj); 2672 return ret; 2673 } 2674 2675 amdgpu_crtc->cursor_width = width; 2676 amdgpu_crtc->cursor_height = height; 2677 2678 dce_v11_0_lock_cursor(crtc, true); 2679 2680 if (hot_x != amdgpu_crtc->cursor_hot_x || 2681 hot_y != amdgpu_crtc->cursor_hot_y) { 2682 int x, y; 2683 2684 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2685 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2686 2687 dce_v11_0_cursor_move_locked(crtc, x, y); 2688 2689 amdgpu_crtc->cursor_hot_x = hot_x; 2690 amdgpu_crtc->cursor_hot_y = hot_y; 2691 } 2692 2693 dce_v11_0_show_cursor(crtc); 2694 dce_v11_0_lock_cursor(crtc, false); 2695 2696 unpin: 2697 if (amdgpu_crtc->cursor_bo) { 2698 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2699 ret = amdgpu_bo_reserve(aobj, false); 2700 if (likely(ret == 0)) { 2701 amdgpu_bo_unpin(aobj); 2702 amdgpu_bo_unreserve(aobj); 2703 } 2704 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2705 } 2706 2707 amdgpu_crtc->cursor_bo = obj; 2708 return 0; 2709 } 2710 2711 static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) 2712 { 2713 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2714 2715 if (amdgpu_crtc->cursor_bo) { 2716 dce_v11_0_lock_cursor(crtc, true); 2717 2718 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2719 amdgpu_crtc->cursor_y); 2720 2721 dce_v11_0_show_cursor(crtc); 2722 2723 dce_v11_0_lock_cursor(crtc, false); 2724 } 2725 } 2726 2727 static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2728 u16 *blue, uint32_t size) 2729 { 2730 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2731 int i; 2732 2733 /* userspace palettes are always correct as is */ 2734 for (i = 0; i < size; i++) { 2735 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2736 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2737 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2738 } 2739 dce_v11_0_crtc_load_lut(crtc); 2740 2741 return 0; 2742 } 2743 2744 static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) 2745 { 2746 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2747 2748 drm_crtc_cleanup(crtc); 2749 kfree(amdgpu_crtc); 2750 } 2751 2752 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { 2753 .cursor_set2 = dce_v11_0_crtc_cursor_set2, 2754 .cursor_move = dce_v11_0_crtc_cursor_move, 2755 .gamma_set = dce_v11_0_crtc_gamma_set, 2756 .set_config = amdgpu_crtc_set_config, 2757 .destroy = dce_v11_0_crtc_destroy, 2758 .page_flip = amdgpu_crtc_page_flip, 2759 }; 2760 2761 static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2762 { 2763 struct drm_device *dev = crtc->dev; 2764 struct amdgpu_device *adev = dev->dev_private; 2765 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2766 unsigned type; 2767 2768 switch (mode) { 2769 case DRM_MODE_DPMS_ON: 2770 amdgpu_crtc->enabled = true; 2771 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2772 dce_v11_0_vga_enable(crtc, true); 2773 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2774 dce_v11_0_vga_enable(crtc, false); 2775 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2776 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2777 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2778 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2779 drm_crtc_vblank_on(crtc); 2780 dce_v11_0_crtc_load_lut(crtc); 2781 break; 2782 case DRM_MODE_DPMS_STANDBY: 2783 case DRM_MODE_DPMS_SUSPEND: 2784 case DRM_MODE_DPMS_OFF: 2785 drm_crtc_vblank_off(crtc); 2786 if (amdgpu_crtc->enabled) { 2787 dce_v11_0_vga_enable(crtc, true); 2788 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2789 dce_v11_0_vga_enable(crtc, false); 2790 } 2791 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2792 amdgpu_crtc->enabled = false; 2793 break; 2794 } 2795 /* adjust pm to dpms */ 2796 amdgpu_pm_compute_clocks(adev); 2797 } 2798 2799 static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) 2800 { 2801 /* disable crtc pair power gating before programming */ 2802 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2803 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2804 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2805 } 2806 2807 static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) 2808 { 2809 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2810 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2811 } 2812 2813 static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) 2814 { 2815 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2816 struct drm_device *dev = crtc->dev; 2817 struct amdgpu_device *adev = dev->dev_private; 2818 struct amdgpu_atom_ss ss; 2819 int i; 2820 2821 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2822 if (crtc->primary->fb) { 2823 int r; 2824 struct amdgpu_framebuffer *amdgpu_fb; 2825 struct amdgpu_bo *rbo; 2826 2827 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2828 rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2829 r = amdgpu_bo_reserve(rbo, false); 2830 if (unlikely(r)) 2831 DRM_ERROR("failed to reserve rbo before unpin\n"); 2832 else { 2833 amdgpu_bo_unpin(rbo); 2834 amdgpu_bo_unreserve(rbo); 2835 } 2836 } 2837 /* disable the GRPH */ 2838 dce_v11_0_grph_enable(crtc, false); 2839 2840 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2841 2842 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2843 if (adev->mode_info.crtcs[i] && 2844 adev->mode_info.crtcs[i]->enabled && 2845 i != amdgpu_crtc->crtc_id && 2846 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2847 /* one other crtc is using this pll don't turn 2848 * off the pll 2849 */ 2850 goto done; 2851 } 2852 } 2853 2854 switch (amdgpu_crtc->pll_id) { 2855 case ATOM_PPLL0: 2856 case ATOM_PPLL1: 2857 case ATOM_PPLL2: 2858 /* disable the ppll */ 2859 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2860 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2861 break; 2862 case ATOM_COMBOPHY_PLL0: 2863 case ATOM_COMBOPHY_PLL1: 2864 case ATOM_COMBOPHY_PLL2: 2865 case ATOM_COMBOPHY_PLL3: 2866 case ATOM_COMBOPHY_PLL4: 2867 case ATOM_COMBOPHY_PLL5: 2868 /* disable the ppll */ 2869 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id, 2870 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2871 break; 2872 default: 2873 break; 2874 } 2875 done: 2876 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2877 amdgpu_crtc->adjusted_clock = 0; 2878 amdgpu_crtc->encoder = NULL; 2879 amdgpu_crtc->connector = NULL; 2880 } 2881 2882 static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, 2883 struct drm_display_mode *mode, 2884 struct drm_display_mode *adjusted_mode, 2885 int x, int y, struct drm_framebuffer *old_fb) 2886 { 2887 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2888 struct drm_device *dev = crtc->dev; 2889 struct amdgpu_device *adev = dev->dev_private; 2890 2891 if (!amdgpu_crtc->adjusted_clock) 2892 return -EINVAL; 2893 2894 if ((adev->asic_type == CHIP_POLARIS10) || 2895 (adev->asic_type == CHIP_POLARIS11)) { 2896 struct amdgpu_encoder *amdgpu_encoder = 2897 to_amdgpu_encoder(amdgpu_crtc->encoder); 2898 int encoder_mode = 2899 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder); 2900 2901 /* SetPixelClock calculates the plls and ss values now */ 2902 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, 2903 amdgpu_crtc->pll_id, 2904 encoder_mode, amdgpu_encoder->encoder_id, 2905 adjusted_mode->clock, 0, 0, 0, 0, 2906 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss); 2907 } else { 2908 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2909 } 2910 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2911 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2912 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2913 amdgpu_atombios_crtc_scaler_setup(crtc); 2914 dce_v11_0_cursor_reset(crtc); 2915 /* update the hw version fpr dpm */ 2916 amdgpu_crtc->hw_mode = *adjusted_mode; 2917 2918 return 0; 2919 } 2920 2921 static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, 2922 const struct drm_display_mode *mode, 2923 struct drm_display_mode *adjusted_mode) 2924 { 2925 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2926 struct drm_device *dev = crtc->dev; 2927 struct drm_encoder *encoder; 2928 2929 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2930 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2931 if (encoder->crtc == crtc) { 2932 amdgpu_crtc->encoder = encoder; 2933 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2934 break; 2935 } 2936 } 2937 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2938 amdgpu_crtc->encoder = NULL; 2939 amdgpu_crtc->connector = NULL; 2940 return false; 2941 } 2942 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2943 return false; 2944 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2945 return false; 2946 /* pick pll */ 2947 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); 2948 /* if we can't get a PPLL for a non-DP encoder, fail */ 2949 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2950 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2951 return false; 2952 2953 return true; 2954 } 2955 2956 static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2957 struct drm_framebuffer *old_fb) 2958 { 2959 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2960 } 2961 2962 static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2963 struct drm_framebuffer *fb, 2964 int x, int y, enum mode_set_atomic state) 2965 { 2966 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); 2967 } 2968 2969 static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { 2970 .dpms = dce_v11_0_crtc_dpms, 2971 .mode_fixup = dce_v11_0_crtc_mode_fixup, 2972 .mode_set = dce_v11_0_crtc_mode_set, 2973 .mode_set_base = dce_v11_0_crtc_set_base, 2974 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, 2975 .prepare = dce_v11_0_crtc_prepare, 2976 .commit = dce_v11_0_crtc_commit, 2977 .load_lut = dce_v11_0_crtc_load_lut, 2978 .disable = dce_v11_0_crtc_disable, 2979 }; 2980 2981 static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) 2982 { 2983 struct amdgpu_crtc *amdgpu_crtc; 2984 int i; 2985 2986 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2987 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2988 if (amdgpu_crtc == NULL) 2989 return -ENOMEM; 2990 2991 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); 2992 2993 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2994 amdgpu_crtc->crtc_id = index; 2995 adev->mode_info.crtcs[index] = amdgpu_crtc; 2996 2997 amdgpu_crtc->max_cursor_width = 128; 2998 amdgpu_crtc->max_cursor_height = 128; 2999 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 3000 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 3001 3002 for (i = 0; i < 256; i++) { 3003 amdgpu_crtc->lut_r[i] = i << 2; 3004 amdgpu_crtc->lut_g[i] = i << 2; 3005 amdgpu_crtc->lut_b[i] = i << 2; 3006 } 3007 3008 switch (amdgpu_crtc->crtc_id) { 3009 case 0: 3010 default: 3011 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 3012 break; 3013 case 1: 3014 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 3015 break; 3016 case 2: 3017 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 3018 break; 3019 case 3: 3020 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 3021 break; 3022 case 4: 3023 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 3024 break; 3025 case 5: 3026 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 3027 break; 3028 } 3029 3030 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 3031 amdgpu_crtc->adjusted_clock = 0; 3032 amdgpu_crtc->encoder = NULL; 3033 amdgpu_crtc->connector = NULL; 3034 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); 3035 3036 return 0; 3037 } 3038 3039 static int dce_v11_0_early_init(void *handle) 3040 { 3041 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3042 3043 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; 3044 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; 3045 3046 dce_v11_0_set_display_funcs(adev); 3047 dce_v11_0_set_irq_funcs(adev); 3048 3049 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev); 3050 3051 switch (adev->asic_type) { 3052 case CHIP_CARRIZO: 3053 adev->mode_info.num_hpd = 6; 3054 adev->mode_info.num_dig = 9; 3055 break; 3056 case CHIP_STONEY: 3057 adev->mode_info.num_hpd = 6; 3058 adev->mode_info.num_dig = 9; 3059 break; 3060 case CHIP_POLARIS10: 3061 adev->mode_info.num_hpd = 6; 3062 adev->mode_info.num_dig = 6; 3063 break; 3064 case CHIP_POLARIS11: 3065 adev->mode_info.num_hpd = 5; 3066 adev->mode_info.num_dig = 5; 3067 break; 3068 default: 3069 /* FIXME: not supported yet */ 3070 return -EINVAL; 3071 } 3072 3073 return 0; 3074 } 3075 3076 static int dce_v11_0_sw_init(void *handle) 3077 { 3078 int r, i; 3079 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3080 3081 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3082 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 3083 if (r) 3084 return r; 3085 } 3086 3087 for (i = 8; i < 20; i += 2) { 3088 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 3089 if (r) 3090 return r; 3091 } 3092 3093 /* HPD hotplug */ 3094 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 3095 if (r) 3096 return r; 3097 3098 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 3099 3100 adev->ddev->mode_config.async_page_flip = true; 3101 3102 adev->ddev->mode_config.max_width = 16384; 3103 adev->ddev->mode_config.max_height = 16384; 3104 3105 adev->ddev->mode_config.preferred_depth = 24; 3106 adev->ddev->mode_config.prefer_shadow = 1; 3107 3108 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 3109 3110 r = amdgpu_modeset_create_props(adev); 3111 if (r) 3112 return r; 3113 3114 adev->ddev->mode_config.max_width = 16384; 3115 adev->ddev->mode_config.max_height = 16384; 3116 3117 3118 /* allocate crtcs */ 3119 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3120 r = dce_v11_0_crtc_init(adev, i); 3121 if (r) 3122 return r; 3123 } 3124 3125 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3126 amdgpu_print_display_setup(adev->ddev); 3127 else 3128 return -EINVAL; 3129 3130 /* setup afmt */ 3131 r = dce_v11_0_afmt_init(adev); 3132 if (r) 3133 return r; 3134 3135 r = dce_v11_0_audio_init(adev); 3136 if (r) 3137 return r; 3138 3139 drm_kms_helper_poll_init(adev->ddev); 3140 3141 adev->mode_info.mode_config_initialized = true; 3142 return 0; 3143 } 3144 3145 static int dce_v11_0_sw_fini(void *handle) 3146 { 3147 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3148 3149 kfree(adev->mode_info.bios_hardcoded_edid); 3150 3151 drm_kms_helper_poll_fini(adev->ddev); 3152 3153 dce_v11_0_audio_fini(adev); 3154 3155 dce_v11_0_afmt_fini(adev); 3156 3157 adev->mode_info.mode_config_initialized = false; 3158 3159 return 0; 3160 } 3161 3162 static int dce_v11_0_hw_init(void *handle) 3163 { 3164 int i; 3165 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3166 3167 dce_v11_0_init_golden_registers(adev); 3168 3169 /* init dig PHYs, disp eng pll */ 3170 amdgpu_atombios_crtc_powergate_init(adev); 3171 amdgpu_atombios_encoder_init_dig(adev); 3172 if ((adev->asic_type == CHIP_POLARIS10) || 3173 (adev->asic_type == CHIP_POLARIS11)) { 3174 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, 3175 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); 3176 amdgpu_atombios_crtc_set_dce_clock(adev, 0, 3177 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS); 3178 } else { 3179 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3180 } 3181 3182 /* initialize hpd */ 3183 dce_v11_0_hpd_init(adev); 3184 3185 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3186 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3187 } 3188 3189 dce_v11_0_pageflip_interrupt_init(adev); 3190 3191 return 0; 3192 } 3193 3194 static int dce_v11_0_hw_fini(void *handle) 3195 { 3196 int i; 3197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3198 3199 dce_v11_0_hpd_fini(adev); 3200 3201 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3202 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3203 } 3204 3205 dce_v11_0_pageflip_interrupt_fini(adev); 3206 3207 return 0; 3208 } 3209 3210 static int dce_v11_0_suspend(void *handle) 3211 { 3212 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3213 3214 amdgpu_atombios_scratch_regs_save(adev); 3215 3216 return dce_v11_0_hw_fini(handle); 3217 } 3218 3219 static int dce_v11_0_resume(void *handle) 3220 { 3221 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3222 int ret; 3223 3224 ret = dce_v11_0_hw_init(handle); 3225 3226 amdgpu_atombios_scratch_regs_restore(adev); 3227 3228 /* turn on the BL */ 3229 if (adev->mode_info.bl_encoder) { 3230 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3231 adev->mode_info.bl_encoder); 3232 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3233 bl_level); 3234 } 3235 3236 return ret; 3237 } 3238 3239 static bool dce_v11_0_is_idle(void *handle) 3240 { 3241 return true; 3242 } 3243 3244 static int dce_v11_0_wait_for_idle(void *handle) 3245 { 3246 return 0; 3247 } 3248 3249 static int dce_v11_0_soft_reset(void *handle) 3250 { 3251 u32 srbm_soft_reset = 0, tmp; 3252 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3253 3254 if (dce_v11_0_is_display_hung(adev)) 3255 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3256 3257 if (srbm_soft_reset) { 3258 tmp = RREG32(mmSRBM_SOFT_RESET); 3259 tmp |= srbm_soft_reset; 3260 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3261 WREG32(mmSRBM_SOFT_RESET, tmp); 3262 tmp = RREG32(mmSRBM_SOFT_RESET); 3263 3264 udelay(50); 3265 3266 tmp &= ~srbm_soft_reset; 3267 WREG32(mmSRBM_SOFT_RESET, tmp); 3268 tmp = RREG32(mmSRBM_SOFT_RESET); 3269 3270 /* Wait a little for things to settle down */ 3271 udelay(50); 3272 } 3273 return 0; 3274 } 3275 3276 static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3277 int crtc, 3278 enum amdgpu_interrupt_state state) 3279 { 3280 u32 lb_interrupt_mask; 3281 3282 if (crtc >= adev->mode_info.num_crtc) { 3283 DRM_DEBUG("invalid crtc %d\n", crtc); 3284 return; 3285 } 3286 3287 switch (state) { 3288 case AMDGPU_IRQ_STATE_DISABLE: 3289 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3290 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3291 VBLANK_INTERRUPT_MASK, 0); 3292 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3293 break; 3294 case AMDGPU_IRQ_STATE_ENABLE: 3295 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3296 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3297 VBLANK_INTERRUPT_MASK, 1); 3298 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3299 break; 3300 default: 3301 break; 3302 } 3303 } 3304 3305 static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3306 int crtc, 3307 enum amdgpu_interrupt_state state) 3308 { 3309 u32 lb_interrupt_mask; 3310 3311 if (crtc >= adev->mode_info.num_crtc) { 3312 DRM_DEBUG("invalid crtc %d\n", crtc); 3313 return; 3314 } 3315 3316 switch (state) { 3317 case AMDGPU_IRQ_STATE_DISABLE: 3318 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3319 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3320 VLINE_INTERRUPT_MASK, 0); 3321 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3322 break; 3323 case AMDGPU_IRQ_STATE_ENABLE: 3324 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3325 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3326 VLINE_INTERRUPT_MASK, 1); 3327 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3328 break; 3329 default: 3330 break; 3331 } 3332 } 3333 3334 static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, 3335 struct amdgpu_irq_src *source, 3336 unsigned hpd, 3337 enum amdgpu_interrupt_state state) 3338 { 3339 u32 tmp; 3340 3341 if (hpd >= adev->mode_info.num_hpd) { 3342 DRM_DEBUG("invalid hdp %d\n", hpd); 3343 return 0; 3344 } 3345 3346 switch (state) { 3347 case AMDGPU_IRQ_STATE_DISABLE: 3348 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3349 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3350 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3351 break; 3352 case AMDGPU_IRQ_STATE_ENABLE: 3353 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3354 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3355 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3356 break; 3357 default: 3358 break; 3359 } 3360 3361 return 0; 3362 } 3363 3364 static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, 3365 struct amdgpu_irq_src *source, 3366 unsigned type, 3367 enum amdgpu_interrupt_state state) 3368 { 3369 switch (type) { 3370 case AMDGPU_CRTC_IRQ_VBLANK1: 3371 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3372 break; 3373 case AMDGPU_CRTC_IRQ_VBLANK2: 3374 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3375 break; 3376 case AMDGPU_CRTC_IRQ_VBLANK3: 3377 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3378 break; 3379 case AMDGPU_CRTC_IRQ_VBLANK4: 3380 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3381 break; 3382 case AMDGPU_CRTC_IRQ_VBLANK5: 3383 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3384 break; 3385 case AMDGPU_CRTC_IRQ_VBLANK6: 3386 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3387 break; 3388 case AMDGPU_CRTC_IRQ_VLINE1: 3389 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); 3390 break; 3391 case AMDGPU_CRTC_IRQ_VLINE2: 3392 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); 3393 break; 3394 case AMDGPU_CRTC_IRQ_VLINE3: 3395 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); 3396 break; 3397 case AMDGPU_CRTC_IRQ_VLINE4: 3398 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); 3399 break; 3400 case AMDGPU_CRTC_IRQ_VLINE5: 3401 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); 3402 break; 3403 case AMDGPU_CRTC_IRQ_VLINE6: 3404 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); 3405 break; 3406 default: 3407 break; 3408 } 3409 return 0; 3410 } 3411 3412 static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3413 struct amdgpu_irq_src *src, 3414 unsigned type, 3415 enum amdgpu_interrupt_state state) 3416 { 3417 u32 reg; 3418 3419 if (type >= adev->mode_info.num_crtc) { 3420 DRM_ERROR("invalid pageflip crtc %d\n", type); 3421 return -EINVAL; 3422 } 3423 3424 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3425 if (state == AMDGPU_IRQ_STATE_DISABLE) 3426 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3427 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3428 else 3429 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3430 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3431 3432 return 0; 3433 } 3434 3435 static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, 3436 struct amdgpu_irq_src *source, 3437 struct amdgpu_iv_entry *entry) 3438 { 3439 unsigned long flags; 3440 unsigned crtc_id; 3441 struct amdgpu_crtc *amdgpu_crtc; 3442 struct amdgpu_flip_work *works; 3443 3444 crtc_id = (entry->src_id - 8) >> 1; 3445 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3446 3447 if (crtc_id >= adev->mode_info.num_crtc) { 3448 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3449 return -EINVAL; 3450 } 3451 3452 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3453 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3454 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3455 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3456 3457 /* IRQ could occur when in initial stage */ 3458 if(amdgpu_crtc == NULL) 3459 return 0; 3460 3461 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3462 works = amdgpu_crtc->pflip_works; 3463 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ 3464 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3465 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3466 amdgpu_crtc->pflip_status, 3467 AMDGPU_FLIP_SUBMITTED); 3468 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3469 return 0; 3470 } 3471 3472 /* page flip completed. clean up */ 3473 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3474 amdgpu_crtc->pflip_works = NULL; 3475 3476 /* wakeup usersapce */ 3477 if(works->event) 3478 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3479 3480 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3481 3482 drm_crtc_vblank_put(&amdgpu_crtc->base); 3483 schedule_work(&works->unpin_work); 3484 3485 return 0; 3486 } 3487 3488 static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, 3489 int hpd) 3490 { 3491 u32 tmp; 3492 3493 if (hpd >= adev->mode_info.num_hpd) { 3494 DRM_DEBUG("invalid hdp %d\n", hpd); 3495 return; 3496 } 3497 3498 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3499 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3500 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3501 } 3502 3503 static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3504 int crtc) 3505 { 3506 u32 tmp; 3507 3508 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3509 DRM_DEBUG("invalid crtc %d\n", crtc); 3510 return; 3511 } 3512 3513 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3514 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3515 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3516 } 3517 3518 static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3519 int crtc) 3520 { 3521 u32 tmp; 3522 3523 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) { 3524 DRM_DEBUG("invalid crtc %d\n", crtc); 3525 return; 3526 } 3527 3528 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3529 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3530 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3531 } 3532 3533 static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, 3534 struct amdgpu_irq_src *source, 3535 struct amdgpu_iv_entry *entry) 3536 { 3537 unsigned crtc = entry->src_id - 1; 3538 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3539 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3540 3541 switch (entry->src_data) { 3542 case 0: /* vblank */ 3543 if (disp_int & interrupt_status_offsets[crtc].vblank) 3544 dce_v11_0_crtc_vblank_int_ack(adev, crtc); 3545 else 3546 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3547 3548 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3549 drm_handle_vblank(adev->ddev, crtc); 3550 } 3551 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3552 3553 break; 3554 case 1: /* vline */ 3555 if (disp_int & interrupt_status_offsets[crtc].vline) 3556 dce_v11_0_crtc_vline_int_ack(adev, crtc); 3557 else 3558 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3559 3560 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3561 3562 break; 3563 default: 3564 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3565 break; 3566 } 3567 3568 return 0; 3569 } 3570 3571 static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, 3572 struct amdgpu_irq_src *source, 3573 struct amdgpu_iv_entry *entry) 3574 { 3575 uint32_t disp_int, mask; 3576 unsigned hpd; 3577 3578 if (entry->src_data >= adev->mode_info.num_hpd) { 3579 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3580 return 0; 3581 } 3582 3583 hpd = entry->src_data; 3584 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3585 mask = interrupt_status_offsets[hpd].hpd; 3586 3587 if (disp_int & mask) { 3588 dce_v11_0_hpd_int_ack(adev, hpd); 3589 schedule_work(&adev->hotplug_work); 3590 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3591 } 3592 3593 return 0; 3594 } 3595 3596 static int dce_v11_0_set_clockgating_state(void *handle, 3597 enum amd_clockgating_state state) 3598 { 3599 return 0; 3600 } 3601 3602 static int dce_v11_0_set_powergating_state(void *handle, 3603 enum amd_powergating_state state) 3604 { 3605 return 0; 3606 } 3607 3608 const struct amd_ip_funcs dce_v11_0_ip_funcs = { 3609 .name = "dce_v11_0", 3610 .early_init = dce_v11_0_early_init, 3611 .late_init = NULL, 3612 .sw_init = dce_v11_0_sw_init, 3613 .sw_fini = dce_v11_0_sw_fini, 3614 .hw_init = dce_v11_0_hw_init, 3615 .hw_fini = dce_v11_0_hw_fini, 3616 .suspend = dce_v11_0_suspend, 3617 .resume = dce_v11_0_resume, 3618 .is_idle = dce_v11_0_is_idle, 3619 .wait_for_idle = dce_v11_0_wait_for_idle, 3620 .soft_reset = dce_v11_0_soft_reset, 3621 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3622 .set_powergating_state = dce_v11_0_set_powergating_state, 3623 }; 3624 3625 static void 3626 dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, 3627 struct drm_display_mode *mode, 3628 struct drm_display_mode *adjusted_mode) 3629 { 3630 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3631 3632 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3633 3634 /* need to call this here rather than in prepare() since we need some crtc info */ 3635 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3636 3637 /* set scaler clears this on some chips */ 3638 dce_v11_0_set_interleave(encoder->crtc, mode); 3639 3640 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3641 dce_v11_0_afmt_enable(encoder, true); 3642 dce_v11_0_afmt_setmode(encoder, adjusted_mode); 3643 } 3644 } 3645 3646 static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) 3647 { 3648 struct amdgpu_device *adev = encoder->dev->dev_private; 3649 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3650 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3651 3652 if ((amdgpu_encoder->active_device & 3653 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3654 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3655 ENCODER_OBJECT_ID_NONE)) { 3656 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3657 if (dig) { 3658 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); 3659 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3660 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3661 } 3662 } 3663 3664 amdgpu_atombios_scratch_regs_lock(adev, true); 3665 3666 if (connector) { 3667 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3668 3669 /* select the clock/data port if it uses a router */ 3670 if (amdgpu_connector->router.cd_valid) 3671 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3672 3673 /* turn eDP panel on for mode set */ 3674 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3675 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3676 ATOM_TRANSMITTER_ACTION_POWER_ON); 3677 } 3678 3679 /* this is needed for the pll/ss setup to work correctly in some cases */ 3680 amdgpu_atombios_encoder_set_crtc_source(encoder); 3681 /* set up the FMT blocks */ 3682 dce_v11_0_program_fmt(encoder); 3683 } 3684 3685 static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) 3686 { 3687 struct drm_device *dev = encoder->dev; 3688 struct amdgpu_device *adev = dev->dev_private; 3689 3690 /* need to call this here as we need the crtc set up */ 3691 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3692 amdgpu_atombios_scratch_regs_lock(adev, false); 3693 } 3694 3695 static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) 3696 { 3697 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3698 struct amdgpu_encoder_atom_dig *dig; 3699 3700 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3701 3702 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3703 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3704 dce_v11_0_afmt_enable(encoder, false); 3705 dig = amdgpu_encoder->enc_priv; 3706 dig->dig_encoder = -1; 3707 } 3708 amdgpu_encoder->active_device = 0; 3709 } 3710 3711 /* these are handled by the primary encoders */ 3712 static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) 3713 { 3714 3715 } 3716 3717 static void dce_v11_0_ext_commit(struct drm_encoder *encoder) 3718 { 3719 3720 } 3721 3722 static void 3723 dce_v11_0_ext_mode_set(struct drm_encoder *encoder, 3724 struct drm_display_mode *mode, 3725 struct drm_display_mode *adjusted_mode) 3726 { 3727 3728 } 3729 3730 static void dce_v11_0_ext_disable(struct drm_encoder *encoder) 3731 { 3732 3733 } 3734 3735 static void 3736 dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) 3737 { 3738 3739 } 3740 3741 static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { 3742 .dpms = dce_v11_0_ext_dpms, 3743 .prepare = dce_v11_0_ext_prepare, 3744 .mode_set = dce_v11_0_ext_mode_set, 3745 .commit = dce_v11_0_ext_commit, 3746 .disable = dce_v11_0_ext_disable, 3747 /* no detect for TMDS/LVDS yet */ 3748 }; 3749 3750 static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { 3751 .dpms = amdgpu_atombios_encoder_dpms, 3752 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3753 .prepare = dce_v11_0_encoder_prepare, 3754 .mode_set = dce_v11_0_encoder_mode_set, 3755 .commit = dce_v11_0_encoder_commit, 3756 .disable = dce_v11_0_encoder_disable, 3757 .detect = amdgpu_atombios_encoder_dig_detect, 3758 }; 3759 3760 static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { 3761 .dpms = amdgpu_atombios_encoder_dpms, 3762 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3763 .prepare = dce_v11_0_encoder_prepare, 3764 .mode_set = dce_v11_0_encoder_mode_set, 3765 .commit = dce_v11_0_encoder_commit, 3766 .detect = amdgpu_atombios_encoder_dac_detect, 3767 }; 3768 3769 static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) 3770 { 3771 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3772 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3773 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3774 kfree(amdgpu_encoder->enc_priv); 3775 drm_encoder_cleanup(encoder); 3776 kfree(amdgpu_encoder); 3777 } 3778 3779 static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { 3780 .destroy = dce_v11_0_encoder_destroy, 3781 }; 3782 3783 static void dce_v11_0_encoder_add(struct amdgpu_device *adev, 3784 uint32_t encoder_enum, 3785 uint32_t supported_device, 3786 u16 caps) 3787 { 3788 struct drm_device *dev = adev->ddev; 3789 struct drm_encoder *encoder; 3790 struct amdgpu_encoder *amdgpu_encoder; 3791 3792 /* see if we already added it */ 3793 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3794 amdgpu_encoder = to_amdgpu_encoder(encoder); 3795 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3796 amdgpu_encoder->devices |= supported_device; 3797 return; 3798 } 3799 3800 } 3801 3802 /* add a new one */ 3803 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3804 if (!amdgpu_encoder) 3805 return; 3806 3807 encoder = &amdgpu_encoder->base; 3808 switch (adev->mode_info.num_crtc) { 3809 case 1: 3810 encoder->possible_crtcs = 0x1; 3811 break; 3812 case 2: 3813 default: 3814 encoder->possible_crtcs = 0x3; 3815 break; 3816 case 4: 3817 encoder->possible_crtcs = 0xf; 3818 break; 3819 case 6: 3820 encoder->possible_crtcs = 0x3f; 3821 break; 3822 } 3823 3824 amdgpu_encoder->enc_priv = NULL; 3825 3826 amdgpu_encoder->encoder_enum = encoder_enum; 3827 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3828 amdgpu_encoder->devices = supported_device; 3829 amdgpu_encoder->rmx_type = RMX_OFF; 3830 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3831 amdgpu_encoder->is_ext_encoder = false; 3832 amdgpu_encoder->caps = caps; 3833 3834 switch (amdgpu_encoder->encoder_id) { 3835 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3836 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3837 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3838 DRM_MODE_ENCODER_DAC, NULL); 3839 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); 3840 break; 3841 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3842 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3843 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3844 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3845 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3846 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3847 amdgpu_encoder->rmx_type = RMX_FULL; 3848 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3849 DRM_MODE_ENCODER_LVDS, NULL); 3850 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3851 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3852 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3853 DRM_MODE_ENCODER_DAC, NULL); 3854 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3855 } else { 3856 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3857 DRM_MODE_ENCODER_TMDS, NULL); 3858 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3859 } 3860 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); 3861 break; 3862 case ENCODER_OBJECT_ID_SI170B: 3863 case ENCODER_OBJECT_ID_CH7303: 3864 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3865 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3866 case ENCODER_OBJECT_ID_TITFP513: 3867 case ENCODER_OBJECT_ID_VT1623: 3868 case ENCODER_OBJECT_ID_HDMI_SI1930: 3869 case ENCODER_OBJECT_ID_TRAVIS: 3870 case ENCODER_OBJECT_ID_NUTMEG: 3871 /* these are handled by the primary encoders */ 3872 amdgpu_encoder->is_ext_encoder = true; 3873 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3874 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3875 DRM_MODE_ENCODER_LVDS, NULL); 3876 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3877 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3878 DRM_MODE_ENCODER_DAC, NULL); 3879 else 3880 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, 3881 DRM_MODE_ENCODER_TMDS, NULL); 3882 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); 3883 break; 3884 } 3885 } 3886 3887 static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { 3888 .set_vga_render_state = &dce_v11_0_set_vga_render_state, 3889 .bandwidth_update = &dce_v11_0_bandwidth_update, 3890 .vblank_get_counter = &dce_v11_0_vblank_get_counter, 3891 .vblank_wait = &dce_v11_0_vblank_wait, 3892 .is_display_hung = &dce_v11_0_is_display_hung, 3893 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3894 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3895 .hpd_sense = &dce_v11_0_hpd_sense, 3896 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, 3897 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, 3898 .page_flip = &dce_v11_0_page_flip, 3899 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, 3900 .add_encoder = &dce_v11_0_encoder_add, 3901 .add_connector = &amdgpu_connector_add, 3902 .stop_mc_access = &dce_v11_0_stop_mc_access, 3903 .resume_mc_access = &dce_v11_0_resume_mc_access, 3904 }; 3905 3906 static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) 3907 { 3908 if (adev->mode_info.funcs == NULL) 3909 adev->mode_info.funcs = &dce_v11_0_display_funcs; 3910 } 3911 3912 static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { 3913 .set = dce_v11_0_set_crtc_irq_state, 3914 .process = dce_v11_0_crtc_irq, 3915 }; 3916 3917 static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { 3918 .set = dce_v11_0_set_pageflip_irq_state, 3919 .process = dce_v11_0_pageflip_irq, 3920 }; 3921 3922 static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { 3923 .set = dce_v11_0_set_hpd_irq_state, 3924 .process = dce_v11_0_hpd_irq, 3925 }; 3926 3927 static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) 3928 { 3929 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3930 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; 3931 3932 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3933 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; 3934 3935 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3936 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; 3937 } 3938