1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_vblank.h>
26 
27 #include "amdgpu.h"
28 #include "amdgpu_pm.h"
29 #include "amdgpu_i2c.h"
30 #include "vid.h"
31 #include "atom.h"
32 #include "amdgpu_atombios.h"
33 #include "atombios_crtc.h"
34 #include "atombios_encoders.h"
35 #include "amdgpu_pll.h"
36 #include "amdgpu_connectors.h"
37 #include "amdgpu_display.h"
38 #include "dce_v10_0.h"
39 
40 #include "dce/dce_10_0_d.h"
41 #include "dce/dce_10_0_sh_mask.h"
42 #include "dce/dce_10_0_enum.h"
43 #include "oss/oss_3_0_d.h"
44 #include "oss/oss_3_0_sh_mask.h"
45 #include "gmc/gmc_8_1_d.h"
46 #include "gmc/gmc_8_1_sh_mask.h"
47 
48 #include "ivsrcid/ivsrcid_vislands30.h"
49 
50 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
51 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
52 
53 static const u32 crtc_offsets[] =
54 {
55 	CRTC0_REGISTER_OFFSET,
56 	CRTC1_REGISTER_OFFSET,
57 	CRTC2_REGISTER_OFFSET,
58 	CRTC3_REGISTER_OFFSET,
59 	CRTC4_REGISTER_OFFSET,
60 	CRTC5_REGISTER_OFFSET,
61 	CRTC6_REGISTER_OFFSET
62 };
63 
64 static const u32 hpd_offsets[] =
65 {
66 	HPD0_REGISTER_OFFSET,
67 	HPD1_REGISTER_OFFSET,
68 	HPD2_REGISTER_OFFSET,
69 	HPD3_REGISTER_OFFSET,
70 	HPD4_REGISTER_OFFSET,
71 	HPD5_REGISTER_OFFSET
72 };
73 
74 static const uint32_t dig_offsets[] = {
75 	DIG0_REGISTER_OFFSET,
76 	DIG1_REGISTER_OFFSET,
77 	DIG2_REGISTER_OFFSET,
78 	DIG3_REGISTER_OFFSET,
79 	DIG4_REGISTER_OFFSET,
80 	DIG5_REGISTER_OFFSET,
81 	DIG6_REGISTER_OFFSET
82 };
83 
84 static const struct {
85 	uint32_t        reg;
86 	uint32_t        vblank;
87 	uint32_t        vline;
88 	uint32_t        hpd;
89 
90 } interrupt_status_offsets[] = { {
91 	.reg = mmDISP_INTERRUPT_STATUS,
92 	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 }, {
96 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 }, {
101 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 }, {
106 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 }, {
111 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 }, {
116 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120 } };
121 
122 static const u32 golden_settings_tonga_a11[] =
123 {
124 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
125 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
126 	mmFBC_MISC, 0x1f311fff, 0x12300000,
127 	mmHDMI_CONTROL, 0x31000111, 0x00000011,
128 };
129 
130 static const u32 tonga_mgcg_cgcg_init[] =
131 {
132 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134 };
135 
136 static const u32 golden_settings_fiji_a10[] =
137 {
138 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 	mmFBC_MISC, 0x1f311fff, 0x12300000,
141 	mmHDMI_CONTROL, 0x31000111, 0x00000011,
142 };
143 
144 static const u32 fiji_mgcg_cgcg_init[] =
145 {
146 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
147 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
148 };
149 
150 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
151 {
152 	switch (adev->asic_type) {
153 	case CHIP_FIJI:
154 		amdgpu_device_program_register_sequence(adev,
155 							fiji_mgcg_cgcg_init,
156 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
157 		amdgpu_device_program_register_sequence(adev,
158 							golden_settings_fiji_a10,
159 							ARRAY_SIZE(golden_settings_fiji_a10));
160 		break;
161 	case CHIP_TONGA:
162 		amdgpu_device_program_register_sequence(adev,
163 							tonga_mgcg_cgcg_init,
164 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
165 		amdgpu_device_program_register_sequence(adev,
166 							golden_settings_tonga_a11,
167 							ARRAY_SIZE(golden_settings_tonga_a11));
168 		break;
169 	default:
170 		break;
171 	}
172 }
173 
174 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
175 				     u32 block_offset, u32 reg)
176 {
177 	unsigned long flags;
178 	u32 r;
179 
180 	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
181 	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
182 	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
183 	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
184 
185 	return r;
186 }
187 
188 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
189 				      u32 block_offset, u32 reg, u32 v)
190 {
191 	unsigned long flags;
192 
193 	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
194 	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
195 	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
196 	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
197 }
198 
199 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
200 {
201 	if (crtc >= adev->mode_info.num_crtc)
202 		return 0;
203 	else
204 		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
205 }
206 
207 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
208 {
209 	unsigned i;
210 
211 	/* Enable pflip interrupts */
212 	for (i = 0; i < adev->mode_info.num_crtc; i++)
213 		amdgpu_irq_get(adev, &adev->pageflip_irq, i);
214 }
215 
216 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
217 {
218 	unsigned i;
219 
220 	/* Disable pflip interrupts */
221 	for (i = 0; i < adev->mode_info.num_crtc; i++)
222 		amdgpu_irq_put(adev, &adev->pageflip_irq, i);
223 }
224 
225 /**
226  * dce_v10_0_page_flip - pageflip callback.
227  *
228  * @adev: amdgpu_device pointer
229  * @crtc_id: crtc to cleanup pageflip on
230  * @crtc_base: new address of the crtc (GPU MC address)
231  *
232  * Triggers the actual pageflip by updating the primary
233  * surface base address.
234  */
235 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
236 				int crtc_id, u64 crtc_base, bool async)
237 {
238 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
239 	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
240 	u32 tmp;
241 
242 	/* flip at hsync for async, default is vsync */
243 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
244 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
245 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
246 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
247 	/* update pitch */
248 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
249 	       fb->pitches[0] / fb->format->cpp[0]);
250 	/* update the primary scanout address */
251 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
252 	       upper_32_bits(crtc_base));
253 	/* writing to the low address triggers the update */
254 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
255 	       lower_32_bits(crtc_base));
256 	/* post the write */
257 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
258 }
259 
260 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
261 					u32 *vbl, u32 *position)
262 {
263 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
264 		return -EINVAL;
265 
266 	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
267 	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
268 
269 	return 0;
270 }
271 
272 /**
273  * dce_v10_0_hpd_sense - hpd sense callback.
274  *
275  * @adev: amdgpu_device pointer
276  * @hpd: hpd (hotplug detect) pin
277  *
278  * Checks if a digital monitor is connected (evergreen+).
279  * Returns true if connected, false if not connected.
280  */
281 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
282 			       enum amdgpu_hpd_id hpd)
283 {
284 	bool connected = false;
285 
286 	if (hpd >= adev->mode_info.num_hpd)
287 		return connected;
288 
289 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
290 	    DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
291 		connected = true;
292 
293 	return connected;
294 }
295 
296 /**
297  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
298  *
299  * @adev: amdgpu_device pointer
300  * @hpd: hpd (hotplug detect) pin
301  *
302  * Set the polarity of the hpd pin (evergreen+).
303  */
304 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
305 				      enum amdgpu_hpd_id hpd)
306 {
307 	u32 tmp;
308 	bool connected = dce_v10_0_hpd_sense(adev, hpd);
309 
310 	if (hpd >= adev->mode_info.num_hpd)
311 		return;
312 
313 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
314 	if (connected)
315 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
316 	else
317 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
318 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
319 }
320 
321 /**
322  * dce_v10_0_hpd_init - hpd setup callback.
323  *
324  * @adev: amdgpu_device pointer
325  *
326  * Setup the hpd pins used by the card (evergreen+).
327  * Enable the pin, set the polarity, and enable the hpd interrupts.
328  */
329 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
330 {
331 	struct drm_device *dev = adev->ddev;
332 	struct drm_connector *connector;
333 	struct drm_connector_list_iter iter;
334 	u32 tmp;
335 
336 	drm_connector_list_iter_begin(dev, &iter);
337 	drm_for_each_connector_iter(connector, &iter) {
338 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
339 
340 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
341 			continue;
342 
343 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
344 		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
345 			/* don't try to enable hpd on eDP or LVDS avoid breaking the
346 			 * aux dp channel on imac and help (but not completely fix)
347 			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
348 			 * also avoid interrupt storms during dpms.
349 			 */
350 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
351 			tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
352 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
353 			continue;
354 		}
355 
356 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
357 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
358 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
359 
360 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
361 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
362 				    DC_HPD_CONNECT_INT_DELAY,
363 				    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
364 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
365 				    DC_HPD_DISCONNECT_INT_DELAY,
366 				    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
367 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
368 
369 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
370 		amdgpu_irq_get(adev, &adev->hpd_irq,
371 			       amdgpu_connector->hpd.hpd);
372 	}
373 	drm_connector_list_iter_end(&iter);
374 }
375 
376 /**
377  * dce_v10_0_hpd_fini - hpd tear down callback.
378  *
379  * @adev: amdgpu_device pointer
380  *
381  * Tear down the hpd pins used by the card (evergreen+).
382  * Disable the hpd interrupts.
383  */
384 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
385 {
386 	struct drm_device *dev = adev->ddev;
387 	struct drm_connector *connector;
388 	struct drm_connector_list_iter iter;
389 	u32 tmp;
390 
391 	drm_connector_list_iter_begin(dev, &iter);
392 	drm_for_each_connector_iter(connector, &iter) {
393 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
394 
395 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
396 			continue;
397 
398 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
400 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401 
402 		amdgpu_irq_put(adev, &adev->hpd_irq,
403 			       amdgpu_connector->hpd.hpd);
404 	}
405 	drm_connector_list_iter_end(&iter);
406 }
407 
408 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
409 {
410 	return mmDC_GPIO_HPD_A;
411 }
412 
413 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
414 {
415 	u32 crtc_hung = 0;
416 	u32 crtc_status[6];
417 	u32 i, j, tmp;
418 
419 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
420 		tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
421 		if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
422 			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
423 			crtc_hung |= (1 << i);
424 		}
425 	}
426 
427 	for (j = 0; j < 10; j++) {
428 		for (i = 0; i < adev->mode_info.num_crtc; i++) {
429 			if (crtc_hung & (1 << i)) {
430 				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
431 				if (tmp != crtc_status[i])
432 					crtc_hung &= ~(1 << i);
433 			}
434 		}
435 		if (crtc_hung == 0)
436 			return false;
437 		udelay(100);
438 	}
439 
440 	return true;
441 }
442 
443 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
444 					   bool render)
445 {
446 	u32 tmp;
447 
448 	/* Lockout access through VGA aperture*/
449 	tmp = RREG32(mmVGA_HDP_CONTROL);
450 	if (render)
451 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
452 	else
453 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
454 	WREG32(mmVGA_HDP_CONTROL, tmp);
455 
456 	/* disable VGA render */
457 	tmp = RREG32(mmVGA_RENDER_CONTROL);
458 	if (render)
459 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
460 	else
461 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
462 	WREG32(mmVGA_RENDER_CONTROL, tmp);
463 }
464 
465 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
466 {
467 	int num_crtc = 0;
468 
469 	switch (adev->asic_type) {
470 	case CHIP_FIJI:
471 	case CHIP_TONGA:
472 		num_crtc = 6;
473 		break;
474 	default:
475 		num_crtc = 0;
476 	}
477 	return num_crtc;
478 }
479 
480 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
481 {
482 	/*Disable VGA render and enabled crtc, if has DCE engine*/
483 	if (amdgpu_atombios_has_dce_engine_info(adev)) {
484 		u32 tmp;
485 		int crtc_enabled, i;
486 
487 		dce_v10_0_set_vga_render_state(adev, false);
488 
489 		/*Disable crtc*/
490 		for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
491 			crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
492 									 CRTC_CONTROL, CRTC_MASTER_EN);
493 			if (crtc_enabled) {
494 				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
495 				tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
496 				tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
497 				WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
498 				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
499 			}
500 		}
501 	}
502 }
503 
504 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
505 {
506 	struct drm_device *dev = encoder->dev;
507 	struct amdgpu_device *adev = dev->dev_private;
508 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
509 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
510 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
511 	int bpc = 0;
512 	u32 tmp = 0;
513 	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
514 
515 	if (connector) {
516 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517 		bpc = amdgpu_connector_get_monitor_bpc(connector);
518 		dither = amdgpu_connector->dither;
519 	}
520 
521 	/* LVDS/eDP FMT is set up by atom */
522 	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
523 		return;
524 
525 	/* not needed for analog */
526 	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
527 	    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
528 		return;
529 
530 	if (bpc == 0)
531 		return;
532 
533 	switch (bpc) {
534 	case 6:
535 		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
536 			/* XXX sort out optimal dither settings */
537 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
538 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
539 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
540 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
541 		} else {
542 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
543 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
544 		}
545 		break;
546 	case 8:
547 		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
548 			/* XXX sort out optimal dither settings */
549 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
550 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
551 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
552 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
553 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
554 		} else {
555 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
556 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
557 		}
558 		break;
559 	case 10:
560 		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
561 			/* XXX sort out optimal dither settings */
562 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
563 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
564 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
565 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
567 		} else {
568 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
570 		}
571 		break;
572 	default:
573 		/* not needed */
574 		break;
575 	}
576 
577 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
578 }
579 
580 
581 /* display watermark setup */
582 /**
583  * dce_v10_0_line_buffer_adjust - Set up the line buffer
584  *
585  * @adev: amdgpu_device pointer
586  * @amdgpu_crtc: the selected display controller
587  * @mode: the current display mode on the selected display
588  * controller
589  *
590  * Setup up the line buffer allocation for
591  * the selected display controller (CIK).
592  * Returns the line buffer size in pixels.
593  */
594 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
595 				       struct amdgpu_crtc *amdgpu_crtc,
596 				       struct drm_display_mode *mode)
597 {
598 	u32 tmp, buffer_alloc, i, mem_cfg;
599 	u32 pipe_offset = amdgpu_crtc->crtc_id;
600 	/*
601 	 * Line Buffer Setup
602 	 * There are 6 line buffers, one for each display controllers.
603 	 * There are 3 partitions per LB. Select the number of partitions
604 	 * to enable based on the display width.  For display widths larger
605 	 * than 4096, you need use to use 2 display controllers and combine
606 	 * them using the stereo blender.
607 	 */
608 	if (amdgpu_crtc->base.enabled && mode) {
609 		if (mode->crtc_hdisplay < 1920) {
610 			mem_cfg = 1;
611 			buffer_alloc = 2;
612 		} else if (mode->crtc_hdisplay < 2560) {
613 			mem_cfg = 2;
614 			buffer_alloc = 2;
615 		} else if (mode->crtc_hdisplay < 4096) {
616 			mem_cfg = 0;
617 			buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
618 		} else {
619 			DRM_DEBUG_KMS("Mode too big for LB!\n");
620 			mem_cfg = 0;
621 			buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
622 		}
623 	} else {
624 		mem_cfg = 1;
625 		buffer_alloc = 0;
626 	}
627 
628 	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
629 	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
630 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
631 
632 	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
633 	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
634 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
635 
636 	for (i = 0; i < adev->usec_timeout; i++) {
637 		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
638 		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
639 			break;
640 		udelay(1);
641 	}
642 
643 	if (amdgpu_crtc->base.enabled && mode) {
644 		switch (mem_cfg) {
645 		case 0:
646 		default:
647 			return 4096 * 2;
648 		case 1:
649 			return 1920 * 2;
650 		case 2:
651 			return 2560 * 2;
652 		}
653 	}
654 
655 	/* controller not enabled, so no lb used */
656 	return 0;
657 }
658 
659 /**
660  * cik_get_number_of_dram_channels - get the number of dram channels
661  *
662  * @adev: amdgpu_device pointer
663  *
664  * Look up the number of video ram channels (CIK).
665  * Used for display watermark bandwidth calculations
666  * Returns the number of dram channels
667  */
668 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
669 {
670 	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
671 
672 	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
673 	case 0:
674 	default:
675 		return 1;
676 	case 1:
677 		return 2;
678 	case 2:
679 		return 4;
680 	case 3:
681 		return 8;
682 	case 4:
683 		return 3;
684 	case 5:
685 		return 6;
686 	case 6:
687 		return 10;
688 	case 7:
689 		return 12;
690 	case 8:
691 		return 16;
692 	}
693 }
694 
695 struct dce10_wm_params {
696 	u32 dram_channels; /* number of dram channels */
697 	u32 yclk;          /* bandwidth per dram data pin in kHz */
698 	u32 sclk;          /* engine clock in kHz */
699 	u32 disp_clk;      /* display clock in kHz */
700 	u32 src_width;     /* viewport width */
701 	u32 active_time;   /* active display time in ns */
702 	u32 blank_time;    /* blank time in ns */
703 	bool interlaced;    /* mode is interlaced */
704 	fixed20_12 vsc;    /* vertical scale ratio */
705 	u32 num_heads;     /* number of active crtcs */
706 	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
707 	u32 lb_size;       /* line buffer allocated to pipe */
708 	u32 vtaps;         /* vertical scaler taps */
709 };
710 
711 /**
712  * dce_v10_0_dram_bandwidth - get the dram bandwidth
713  *
714  * @wm: watermark calculation data
715  *
716  * Calculate the raw dram bandwidth (CIK).
717  * Used for display watermark bandwidth calculations
718  * Returns the dram bandwidth in MBytes/s
719  */
720 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
721 {
722 	/* Calculate raw DRAM Bandwidth */
723 	fixed20_12 dram_efficiency; /* 0.7 */
724 	fixed20_12 yclk, dram_channels, bandwidth;
725 	fixed20_12 a;
726 
727 	a.full = dfixed_const(1000);
728 	yclk.full = dfixed_const(wm->yclk);
729 	yclk.full = dfixed_div(yclk, a);
730 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
731 	a.full = dfixed_const(10);
732 	dram_efficiency.full = dfixed_const(7);
733 	dram_efficiency.full = dfixed_div(dram_efficiency, a);
734 	bandwidth.full = dfixed_mul(dram_channels, yclk);
735 	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
736 
737 	return dfixed_trunc(bandwidth);
738 }
739 
740 /**
741  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
742  *
743  * @wm: watermark calculation data
744  *
745  * Calculate the dram bandwidth used for display (CIK).
746  * Used for display watermark bandwidth calculations
747  * Returns the dram bandwidth for display in MBytes/s
748  */
749 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
750 {
751 	/* Calculate DRAM Bandwidth and the part allocated to display. */
752 	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
753 	fixed20_12 yclk, dram_channels, bandwidth;
754 	fixed20_12 a;
755 
756 	a.full = dfixed_const(1000);
757 	yclk.full = dfixed_const(wm->yclk);
758 	yclk.full = dfixed_div(yclk, a);
759 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
760 	a.full = dfixed_const(10);
761 	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
762 	disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
763 	bandwidth.full = dfixed_mul(dram_channels, yclk);
764 	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
765 
766 	return dfixed_trunc(bandwidth);
767 }
768 
769 /**
770  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
771  *
772  * @wm: watermark calculation data
773  *
774  * Calculate the data return bandwidth used for display (CIK).
775  * Used for display watermark bandwidth calculations
776  * Returns the data return bandwidth in MBytes/s
777  */
778 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
779 {
780 	/* Calculate the display Data return Bandwidth */
781 	fixed20_12 return_efficiency; /* 0.8 */
782 	fixed20_12 sclk, bandwidth;
783 	fixed20_12 a;
784 
785 	a.full = dfixed_const(1000);
786 	sclk.full = dfixed_const(wm->sclk);
787 	sclk.full = dfixed_div(sclk, a);
788 	a.full = dfixed_const(10);
789 	return_efficiency.full = dfixed_const(8);
790 	return_efficiency.full = dfixed_div(return_efficiency, a);
791 	a.full = dfixed_const(32);
792 	bandwidth.full = dfixed_mul(a, sclk);
793 	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
794 
795 	return dfixed_trunc(bandwidth);
796 }
797 
798 /**
799  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
800  *
801  * @wm: watermark calculation data
802  *
803  * Calculate the dmif bandwidth used for display (CIK).
804  * Used for display watermark bandwidth calculations
805  * Returns the dmif bandwidth in MBytes/s
806  */
807 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
808 {
809 	/* Calculate the DMIF Request Bandwidth */
810 	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
811 	fixed20_12 disp_clk, bandwidth;
812 	fixed20_12 a, b;
813 
814 	a.full = dfixed_const(1000);
815 	disp_clk.full = dfixed_const(wm->disp_clk);
816 	disp_clk.full = dfixed_div(disp_clk, a);
817 	a.full = dfixed_const(32);
818 	b.full = dfixed_mul(a, disp_clk);
819 
820 	a.full = dfixed_const(10);
821 	disp_clk_request_efficiency.full = dfixed_const(8);
822 	disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
823 
824 	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
825 
826 	return dfixed_trunc(bandwidth);
827 }
828 
829 /**
830  * dce_v10_0_available_bandwidth - get the min available bandwidth
831  *
832  * @wm: watermark calculation data
833  *
834  * Calculate the min available bandwidth used for display (CIK).
835  * Used for display watermark bandwidth calculations
836  * Returns the min available bandwidth in MBytes/s
837  */
838 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
839 {
840 	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
841 	u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
842 	u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
843 	u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
844 
845 	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
846 }
847 
848 /**
849  * dce_v10_0_average_bandwidth - get the average available bandwidth
850  *
851  * @wm: watermark calculation data
852  *
853  * Calculate the average available bandwidth used for display (CIK).
854  * Used for display watermark bandwidth calculations
855  * Returns the average available bandwidth in MBytes/s
856  */
857 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
858 {
859 	/* Calculate the display mode Average Bandwidth
860 	 * DisplayMode should contain the source and destination dimensions,
861 	 * timing, etc.
862 	 */
863 	fixed20_12 bpp;
864 	fixed20_12 line_time;
865 	fixed20_12 src_width;
866 	fixed20_12 bandwidth;
867 	fixed20_12 a;
868 
869 	a.full = dfixed_const(1000);
870 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
871 	line_time.full = dfixed_div(line_time, a);
872 	bpp.full = dfixed_const(wm->bytes_per_pixel);
873 	src_width.full = dfixed_const(wm->src_width);
874 	bandwidth.full = dfixed_mul(src_width, bpp);
875 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
876 	bandwidth.full = dfixed_div(bandwidth, line_time);
877 
878 	return dfixed_trunc(bandwidth);
879 }
880 
881 /**
882  * dce_v10_0_latency_watermark - get the latency watermark
883  *
884  * @wm: watermark calculation data
885  *
886  * Calculate the latency watermark (CIK).
887  * Used for display watermark bandwidth calculations
888  * Returns the latency watermark in ns
889  */
890 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
891 {
892 	/* First calculate the latency in ns */
893 	u32 mc_latency = 2000; /* 2000 ns. */
894 	u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
895 	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
896 	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
897 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
898 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
899 		(wm->num_heads * cursor_line_pair_return_time);
900 	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
901 	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
902 	u32 tmp, dmif_size = 12288;
903 	fixed20_12 a, b, c;
904 
905 	if (wm->num_heads == 0)
906 		return 0;
907 
908 	a.full = dfixed_const(2);
909 	b.full = dfixed_const(1);
910 	if ((wm->vsc.full > a.full) ||
911 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
912 	    (wm->vtaps >= 5) ||
913 	    ((wm->vsc.full >= a.full) && wm->interlaced))
914 		max_src_lines_per_dst_line = 4;
915 	else
916 		max_src_lines_per_dst_line = 2;
917 
918 	a.full = dfixed_const(available_bandwidth);
919 	b.full = dfixed_const(wm->num_heads);
920 	a.full = dfixed_div(a, b);
921 	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
922 	tmp = min(dfixed_trunc(a), tmp);
923 
924 	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
925 
926 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
927 	b.full = dfixed_const(1000);
928 	c.full = dfixed_const(lb_fill_bw);
929 	b.full = dfixed_div(c, b);
930 	a.full = dfixed_div(a, b);
931 	line_fill_time = dfixed_trunc(a);
932 
933 	if (line_fill_time < wm->active_time)
934 		return latency;
935 	else
936 		return latency + (line_fill_time - wm->active_time);
937 
938 }
939 
940 /**
941  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
942  * average and available dram bandwidth
943  *
944  * @wm: watermark calculation data
945  *
946  * Check if the display average bandwidth fits in the display
947  * dram bandwidth (CIK).
948  * Used for display watermark bandwidth calculations
949  * Returns true if the display fits, false if not.
950  */
951 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
952 {
953 	if (dce_v10_0_average_bandwidth(wm) <=
954 	    (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
955 		return true;
956 	else
957 		return false;
958 }
959 
960 /**
961  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
962  * average and available bandwidth
963  *
964  * @wm: watermark calculation data
965  *
966  * Check if the display average bandwidth fits in the display
967  * available bandwidth (CIK).
968  * Used for display watermark bandwidth calculations
969  * Returns true if the display fits, false if not.
970  */
971 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
972 {
973 	if (dce_v10_0_average_bandwidth(wm) <=
974 	    (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
975 		return true;
976 	else
977 		return false;
978 }
979 
980 /**
981  * dce_v10_0_check_latency_hiding - check latency hiding
982  *
983  * @wm: watermark calculation data
984  *
985  * Check latency hiding (CIK).
986  * Used for display watermark bandwidth calculations
987  * Returns true if the display fits, false if not.
988  */
989 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
990 {
991 	u32 lb_partitions = wm->lb_size / wm->src_width;
992 	u32 line_time = wm->active_time + wm->blank_time;
993 	u32 latency_tolerant_lines;
994 	u32 latency_hiding;
995 	fixed20_12 a;
996 
997 	a.full = dfixed_const(1);
998 	if (wm->vsc.full > a.full)
999 		latency_tolerant_lines = 1;
1000 	else {
1001 		if (lb_partitions <= (wm->vtaps + 1))
1002 			latency_tolerant_lines = 1;
1003 		else
1004 			latency_tolerant_lines = 2;
1005 	}
1006 
1007 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1008 
1009 	if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1010 		return true;
1011 	else
1012 		return false;
1013 }
1014 
1015 /**
1016  * dce_v10_0_program_watermarks - program display watermarks
1017  *
1018  * @adev: amdgpu_device pointer
1019  * @amdgpu_crtc: the selected display controller
1020  * @lb_size: line buffer size
1021  * @num_heads: number of display controllers in use
1022  *
1023  * Calculate and program the display watermarks for the
1024  * selected display controller (CIK).
1025  */
1026 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1027 					struct amdgpu_crtc *amdgpu_crtc,
1028 					u32 lb_size, u32 num_heads)
1029 {
1030 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1031 	struct dce10_wm_params wm_low, wm_high;
1032 	u32 active_time;
1033 	u32 line_time = 0;
1034 	u32 latency_watermark_a = 0, latency_watermark_b = 0;
1035 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1036 
1037 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
1038 		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1039 					    (u32)mode->clock);
1040 		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1041 					  (u32)mode->clock);
1042 		line_time = min(line_time, (u32)65535);
1043 
1044 		/* watermark for high clocks */
1045 		if (adev->pm.dpm_enabled) {
1046 			wm_high.yclk =
1047 				amdgpu_dpm_get_mclk(adev, false) * 10;
1048 			wm_high.sclk =
1049 				amdgpu_dpm_get_sclk(adev, false) * 10;
1050 		} else {
1051 			wm_high.yclk = adev->pm.current_mclk * 10;
1052 			wm_high.sclk = adev->pm.current_sclk * 10;
1053 		}
1054 
1055 		wm_high.disp_clk = mode->clock;
1056 		wm_high.src_width = mode->crtc_hdisplay;
1057 		wm_high.active_time = active_time;
1058 		wm_high.blank_time = line_time - wm_high.active_time;
1059 		wm_high.interlaced = false;
1060 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1061 			wm_high.interlaced = true;
1062 		wm_high.vsc = amdgpu_crtc->vsc;
1063 		wm_high.vtaps = 1;
1064 		if (amdgpu_crtc->rmx_type != RMX_OFF)
1065 			wm_high.vtaps = 2;
1066 		wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1067 		wm_high.lb_size = lb_size;
1068 		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1069 		wm_high.num_heads = num_heads;
1070 
1071 		/* set for high clocks */
1072 		latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1073 
1074 		/* possibly force display priority to high */
1075 		/* should really do this at mode validation time... */
1076 		if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1077 		    !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1078 		    !dce_v10_0_check_latency_hiding(&wm_high) ||
1079 		    (adev->mode_info.disp_priority == 2)) {
1080 			DRM_DEBUG_KMS("force priority to high\n");
1081 		}
1082 
1083 		/* watermark for low clocks */
1084 		if (adev->pm.dpm_enabled) {
1085 			wm_low.yclk =
1086 				amdgpu_dpm_get_mclk(adev, true) * 10;
1087 			wm_low.sclk =
1088 				amdgpu_dpm_get_sclk(adev, true) * 10;
1089 		} else {
1090 			wm_low.yclk = adev->pm.current_mclk * 10;
1091 			wm_low.sclk = adev->pm.current_sclk * 10;
1092 		}
1093 
1094 		wm_low.disp_clk = mode->clock;
1095 		wm_low.src_width = mode->crtc_hdisplay;
1096 		wm_low.active_time = active_time;
1097 		wm_low.blank_time = line_time - wm_low.active_time;
1098 		wm_low.interlaced = false;
1099 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1100 			wm_low.interlaced = true;
1101 		wm_low.vsc = amdgpu_crtc->vsc;
1102 		wm_low.vtaps = 1;
1103 		if (amdgpu_crtc->rmx_type != RMX_OFF)
1104 			wm_low.vtaps = 2;
1105 		wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1106 		wm_low.lb_size = lb_size;
1107 		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1108 		wm_low.num_heads = num_heads;
1109 
1110 		/* set for low clocks */
1111 		latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1112 
1113 		/* possibly force display priority to high */
1114 		/* should really do this at mode validation time... */
1115 		if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1116 		    !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1117 		    !dce_v10_0_check_latency_hiding(&wm_low) ||
1118 		    (adev->mode_info.disp_priority == 2)) {
1119 			DRM_DEBUG_KMS("force priority to high\n");
1120 		}
1121 		lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1122 	}
1123 
1124 	/* select wm A */
1125 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1126 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1127 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1128 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1129 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1130 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1131 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1132 	/* select wm B */
1133 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1134 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1135 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1136 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1137 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1138 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1139 	/* restore original selection */
1140 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1141 
1142 	/* save values for DPM */
1143 	amdgpu_crtc->line_time = line_time;
1144 	amdgpu_crtc->wm_high = latency_watermark_a;
1145 	amdgpu_crtc->wm_low = latency_watermark_b;
1146 	/* Save number of lines the linebuffer leads before the scanout */
1147 	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1148 }
1149 
1150 /**
1151  * dce_v10_0_bandwidth_update - program display watermarks
1152  *
1153  * @adev: amdgpu_device pointer
1154  *
1155  * Calculate and program the display watermarks and line
1156  * buffer allocation (CIK).
1157  */
1158 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1159 {
1160 	struct drm_display_mode *mode = NULL;
1161 	u32 num_heads = 0, lb_size;
1162 	int i;
1163 
1164 	amdgpu_display_update_priority(adev);
1165 
1166 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1167 		if (adev->mode_info.crtcs[i]->base.enabled)
1168 			num_heads++;
1169 	}
1170 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1171 		mode = &adev->mode_info.crtcs[i]->base.mode;
1172 		lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1173 		dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1174 					    lb_size, num_heads);
1175 	}
1176 }
1177 
1178 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1179 {
1180 	int i;
1181 	u32 offset, tmp;
1182 
1183 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1184 		offset = adev->mode_info.audio.pin[i].offset;
1185 		tmp = RREG32_AUDIO_ENDPT(offset,
1186 					 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1187 		if (((tmp &
1188 		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1189 		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1190 			adev->mode_info.audio.pin[i].connected = false;
1191 		else
1192 			adev->mode_info.audio.pin[i].connected = true;
1193 	}
1194 }
1195 
1196 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1197 {
1198 	int i;
1199 
1200 	dce_v10_0_audio_get_connected_pins(adev);
1201 
1202 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1203 		if (adev->mode_info.audio.pin[i].connected)
1204 			return &adev->mode_info.audio.pin[i];
1205 	}
1206 	DRM_ERROR("No connected audio pins found!\n");
1207 	return NULL;
1208 }
1209 
1210 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1211 {
1212 	struct amdgpu_device *adev = encoder->dev->dev_private;
1213 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1214 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1215 	u32 tmp;
1216 
1217 	if (!dig || !dig->afmt || !dig->afmt->pin)
1218 		return;
1219 
1220 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1221 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1222 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1223 }
1224 
1225 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1226 						struct drm_display_mode *mode)
1227 {
1228 	struct drm_device *dev = encoder->dev;
1229 	struct amdgpu_device *adev = dev->dev_private;
1230 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1231 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1232 	struct drm_connector *connector;
1233 	struct drm_connector_list_iter iter;
1234 	struct amdgpu_connector *amdgpu_connector = NULL;
1235 	u32 tmp;
1236 	int interlace = 0;
1237 
1238 	if (!dig || !dig->afmt || !dig->afmt->pin)
1239 		return;
1240 
1241 	drm_connector_list_iter_begin(dev, &iter);
1242 	drm_for_each_connector_iter(connector, &iter) {
1243 		if (connector->encoder == encoder) {
1244 			amdgpu_connector = to_amdgpu_connector(connector);
1245 			break;
1246 		}
1247 	}
1248 	drm_connector_list_iter_end(&iter);
1249 
1250 	if (!amdgpu_connector) {
1251 		DRM_ERROR("Couldn't find encoder's connector\n");
1252 		return;
1253 	}
1254 
1255 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1256 		interlace = 1;
1257 	if (connector->latency_present[interlace]) {
1258 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1259 				    VIDEO_LIPSYNC, connector->video_latency[interlace]);
1260 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1261 				    AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1262 	} else {
1263 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1264 				    VIDEO_LIPSYNC, 0);
1265 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1266 				    AUDIO_LIPSYNC, 0);
1267 	}
1268 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1269 			   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1270 }
1271 
1272 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1273 {
1274 	struct drm_device *dev = encoder->dev;
1275 	struct amdgpu_device *adev = dev->dev_private;
1276 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1277 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1278 	struct drm_connector *connector;
1279 	struct drm_connector_list_iter iter;
1280 	struct amdgpu_connector *amdgpu_connector = NULL;
1281 	u32 tmp;
1282 	u8 *sadb = NULL;
1283 	int sad_count;
1284 
1285 	if (!dig || !dig->afmt || !dig->afmt->pin)
1286 		return;
1287 
1288 	drm_connector_list_iter_begin(dev, &iter);
1289 	drm_for_each_connector_iter(connector, &iter) {
1290 		if (connector->encoder == encoder) {
1291 			amdgpu_connector = to_amdgpu_connector(connector);
1292 			break;
1293 		}
1294 	}
1295 	drm_connector_list_iter_end(&iter);
1296 
1297 	if (!amdgpu_connector) {
1298 		DRM_ERROR("Couldn't find encoder's connector\n");
1299 		return;
1300 	}
1301 
1302 	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1303 	if (sad_count < 0) {
1304 		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1305 		sad_count = 0;
1306 	}
1307 
1308 	/* program the speaker allocation */
1309 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1310 				 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1311 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1312 			    DP_CONNECTION, 0);
1313 	/* set HDMI mode */
1314 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1315 			    HDMI_CONNECTION, 1);
1316 	if (sad_count)
1317 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1318 				    SPEAKER_ALLOCATION, sadb[0]);
1319 	else
1320 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1321 				    SPEAKER_ALLOCATION, 5); /* stereo */
1322 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1323 			   ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1324 
1325 	kfree(sadb);
1326 }
1327 
1328 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1329 {
1330 	struct drm_device *dev = encoder->dev;
1331 	struct amdgpu_device *adev = dev->dev_private;
1332 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1333 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1334 	struct drm_connector *connector;
1335 	struct drm_connector_list_iter iter;
1336 	struct amdgpu_connector *amdgpu_connector = NULL;
1337 	struct cea_sad *sads;
1338 	int i, sad_count;
1339 
1340 	static const u16 eld_reg_to_type[][2] = {
1341 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1342 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1343 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1344 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1345 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1346 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1347 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1348 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1349 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1350 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1351 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1352 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1353 	};
1354 
1355 	if (!dig || !dig->afmt || !dig->afmt->pin)
1356 		return;
1357 
1358 	drm_connector_list_iter_begin(dev, &iter);
1359 	drm_for_each_connector_iter(connector, &iter) {
1360 		if (connector->encoder == encoder) {
1361 			amdgpu_connector = to_amdgpu_connector(connector);
1362 			break;
1363 		}
1364 	}
1365 	drm_connector_list_iter_end(&iter);
1366 
1367 	if (!amdgpu_connector) {
1368 		DRM_ERROR("Couldn't find encoder's connector\n");
1369 		return;
1370 	}
1371 
1372 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1373 	if (sad_count < 0)
1374 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1375 	if (sad_count <= 0)
1376 		return;
1377 	BUG_ON(!sads);
1378 
1379 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1380 		u32 tmp = 0;
1381 		u8 stereo_freqs = 0;
1382 		int max_channels = -1;
1383 		int j;
1384 
1385 		for (j = 0; j < sad_count; j++) {
1386 			struct cea_sad *sad = &sads[j];
1387 
1388 			if (sad->format == eld_reg_to_type[i][1]) {
1389 				if (sad->channels > max_channels) {
1390 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391 							    MAX_CHANNELS, sad->channels);
1392 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1393 							    DESCRIPTOR_BYTE_2, sad->byte2);
1394 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1395 							    SUPPORTED_FREQUENCIES, sad->freq);
1396 					max_channels = sad->channels;
1397 				}
1398 
1399 				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1400 					stereo_freqs |= sad->freq;
1401 				else
1402 					break;
1403 			}
1404 		}
1405 
1406 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1407 				    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1408 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1409 	}
1410 
1411 	kfree(sads);
1412 }
1413 
1414 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1415 				  struct amdgpu_audio_pin *pin,
1416 				  bool enable)
1417 {
1418 	if (!pin)
1419 		return;
1420 
1421 	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1422 			   enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1423 }
1424 
1425 static const u32 pin_offsets[] =
1426 {
1427 	AUD0_REGISTER_OFFSET,
1428 	AUD1_REGISTER_OFFSET,
1429 	AUD2_REGISTER_OFFSET,
1430 	AUD3_REGISTER_OFFSET,
1431 	AUD4_REGISTER_OFFSET,
1432 	AUD5_REGISTER_OFFSET,
1433 	AUD6_REGISTER_OFFSET,
1434 };
1435 
1436 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1437 {
1438 	int i;
1439 
1440 	if (!amdgpu_audio)
1441 		return 0;
1442 
1443 	adev->mode_info.audio.enabled = true;
1444 
1445 	adev->mode_info.audio.num_pins = 7;
1446 
1447 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1448 		adev->mode_info.audio.pin[i].channels = -1;
1449 		adev->mode_info.audio.pin[i].rate = -1;
1450 		adev->mode_info.audio.pin[i].bits_per_sample = -1;
1451 		adev->mode_info.audio.pin[i].status_bits = 0;
1452 		adev->mode_info.audio.pin[i].category_code = 0;
1453 		adev->mode_info.audio.pin[i].connected = false;
1454 		adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1455 		adev->mode_info.audio.pin[i].id = i;
1456 		/* disable audio.  it will be set up later */
1457 		/* XXX remove once we switch to ip funcs */
1458 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1459 	}
1460 
1461 	return 0;
1462 }
1463 
1464 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1465 {
1466 	int i;
1467 
1468 	if (!amdgpu_audio)
1469 		return;
1470 
1471 	if (!adev->mode_info.audio.enabled)
1472 		return;
1473 
1474 	for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1475 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1476 
1477 	adev->mode_info.audio.enabled = false;
1478 }
1479 
1480 /*
1481  * update the N and CTS parameters for a given pixel clock rate
1482  */
1483 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1484 {
1485 	struct drm_device *dev = encoder->dev;
1486 	struct amdgpu_device *adev = dev->dev_private;
1487 	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1488 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1489 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1490 	u32 tmp;
1491 
1492 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1493 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1494 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1495 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1496 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1497 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1498 
1499 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1500 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1501 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1502 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1503 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1504 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1505 
1506 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1507 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1508 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1509 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1510 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1511 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1512 
1513 }
1514 
1515 /*
1516  * build a HDMI Video Info Frame
1517  */
1518 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1519 					       void *buffer, size_t size)
1520 {
1521 	struct drm_device *dev = encoder->dev;
1522 	struct amdgpu_device *adev = dev->dev_private;
1523 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1524 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1525 	uint8_t *frame = buffer + 3;
1526 	uint8_t *header = buffer;
1527 
1528 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1529 		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1530 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1531 		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1532 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1533 		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1534 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1535 		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1536 }
1537 
1538 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1539 {
1540 	struct drm_device *dev = encoder->dev;
1541 	struct amdgpu_device *adev = dev->dev_private;
1542 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1543 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1544 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1545 	u32 dto_phase = 24 * 1000;
1546 	u32 dto_modulo = clock;
1547 	u32 tmp;
1548 
1549 	if (!dig || !dig->afmt)
1550 		return;
1551 
1552 	/* XXX two dtos; generally use dto0 for hdmi */
1553 	/* Express [24MHz / target pixel clock] as an exact rational
1554 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1555 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1556 	 */
1557 	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1558 	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1559 			    amdgpu_crtc->crtc_id);
1560 	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1561 	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1562 	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1563 }
1564 
1565 /*
1566  * update the info frames with the data from the current display mode
1567  */
1568 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1569 				  struct drm_display_mode *mode)
1570 {
1571 	struct drm_device *dev = encoder->dev;
1572 	struct amdgpu_device *adev = dev->dev_private;
1573 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1574 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1575 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1576 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1577 	struct hdmi_avi_infoframe frame;
1578 	ssize_t err;
1579 	u32 tmp;
1580 	int bpc = 8;
1581 
1582 	if (!dig || !dig->afmt)
1583 		return;
1584 
1585 	/* Silent, r600_hdmi_enable will raise WARN for us */
1586 	if (!dig->afmt->enabled)
1587 		return;
1588 
1589 	/* hdmi deep color mode general control packets setup, if bpc > 8 */
1590 	if (encoder->crtc) {
1591 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1592 		bpc = amdgpu_crtc->bpc;
1593 	}
1594 
1595 	/* disable audio prior to setting up hw */
1596 	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1597 	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1598 
1599 	dce_v10_0_audio_set_dto(encoder, mode->clock);
1600 
1601 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1602 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1603 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1604 
1605 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1606 
1607 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1608 	switch (bpc) {
1609 	case 0:
1610 	case 6:
1611 	case 8:
1612 	case 16:
1613 	default:
1614 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1615 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1616 		DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1617 			  connector->name, bpc);
1618 		break;
1619 	case 10:
1620 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1621 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1622 		DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1623 			  connector->name);
1624 		break;
1625 	case 12:
1626 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1627 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1628 		DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1629 			  connector->name);
1630 		break;
1631 	}
1632 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1633 
1634 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1635 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1636 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1637 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1638 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1639 
1640 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1641 	/* enable audio info frames (frames won't be set until audio is enabled) */
1642 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1643 	/* required for audio info values to be updated */
1644 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1645 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1646 
1647 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1648 	/* required for audio info values to be updated */
1649 	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1650 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1651 
1652 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1653 	/* anything other than 0 */
1654 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1655 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1656 
1657 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1658 
1659 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1660 	/* set the default audio delay */
1661 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1662 	/* should be suffient for all audio modes and small enough for all hblanks */
1663 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1664 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1665 
1666 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1667 	/* allow 60958 channel status fields to be updated */
1668 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1669 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1670 
1671 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1672 	if (bpc > 8)
1673 		/* clear SW CTS value */
1674 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1675 	else
1676 		/* select SW CTS value */
1677 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1678 	/* allow hw to sent ACR packets when required */
1679 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1680 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1681 
1682 	dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1683 
1684 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1685 	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1686 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1687 
1688 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1689 	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1690 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1691 
1692 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1693 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1694 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1695 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1696 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1697 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1698 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1699 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1700 
1701 	dce_v10_0_audio_write_speaker_allocation(encoder);
1702 
1703 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1704 	       (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1705 
1706 	dce_v10_0_afmt_audio_select_pin(encoder);
1707 	dce_v10_0_audio_write_sad_regs(encoder);
1708 	dce_v10_0_audio_write_latency_fields(encoder, mode);
1709 
1710 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1711 	if (err < 0) {
1712 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1713 		return;
1714 	}
1715 
1716 	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1717 	if (err < 0) {
1718 		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1719 		return;
1720 	}
1721 
1722 	dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1723 
1724 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1725 	/* enable AVI info frames */
1726 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1727 	/* required for audio info values to be updated */
1728 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1729 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1730 
1731 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1732 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1733 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1734 
1735 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1736 	/* send audio packets */
1737 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1738 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1739 
1740 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1741 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1742 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1743 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1744 
1745 	/* enable audio after to setting up hw */
1746 	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1747 }
1748 
1749 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1750 {
1751 	struct drm_device *dev = encoder->dev;
1752 	struct amdgpu_device *adev = dev->dev_private;
1753 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1754 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1755 
1756 	if (!dig || !dig->afmt)
1757 		return;
1758 
1759 	/* Silent, r600_hdmi_enable will raise WARN for us */
1760 	if (enable && dig->afmt->enabled)
1761 		return;
1762 	if (!enable && !dig->afmt->enabled)
1763 		return;
1764 
1765 	if (!enable && dig->afmt->pin) {
1766 		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1767 		dig->afmt->pin = NULL;
1768 	}
1769 
1770 	dig->afmt->enabled = enable;
1771 
1772 	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1773 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1774 }
1775 
1776 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1777 {
1778 	int i;
1779 
1780 	for (i = 0; i < adev->mode_info.num_dig; i++)
1781 		adev->mode_info.afmt[i] = NULL;
1782 
1783 	/* DCE10 has audio blocks tied to DIG encoders */
1784 	for (i = 0; i < adev->mode_info.num_dig; i++) {
1785 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1786 		if (adev->mode_info.afmt[i]) {
1787 			adev->mode_info.afmt[i]->offset = dig_offsets[i];
1788 			adev->mode_info.afmt[i]->id = i;
1789 		} else {
1790 			int j;
1791 			for (j = 0; j < i; j++) {
1792 				kfree(adev->mode_info.afmt[j]);
1793 				adev->mode_info.afmt[j] = NULL;
1794 			}
1795 			return -ENOMEM;
1796 		}
1797 	}
1798 	return 0;
1799 }
1800 
1801 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1802 {
1803 	int i;
1804 
1805 	for (i = 0; i < adev->mode_info.num_dig; i++) {
1806 		kfree(adev->mode_info.afmt[i]);
1807 		adev->mode_info.afmt[i] = NULL;
1808 	}
1809 }
1810 
1811 static const u32 vga_control_regs[6] =
1812 {
1813 	mmD1VGA_CONTROL,
1814 	mmD2VGA_CONTROL,
1815 	mmD3VGA_CONTROL,
1816 	mmD4VGA_CONTROL,
1817 	mmD5VGA_CONTROL,
1818 	mmD6VGA_CONTROL,
1819 };
1820 
1821 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1822 {
1823 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1824 	struct drm_device *dev = crtc->dev;
1825 	struct amdgpu_device *adev = dev->dev_private;
1826 	u32 vga_control;
1827 
1828 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1829 	if (enable)
1830 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1831 	else
1832 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1833 }
1834 
1835 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1836 {
1837 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1838 	struct drm_device *dev = crtc->dev;
1839 	struct amdgpu_device *adev = dev->dev_private;
1840 
1841 	if (enable)
1842 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1843 	else
1844 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1845 }
1846 
1847 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1848 				     struct drm_framebuffer *fb,
1849 				     int x, int y, int atomic)
1850 {
1851 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1852 	struct drm_device *dev = crtc->dev;
1853 	struct amdgpu_device *adev = dev->dev_private;
1854 	struct drm_framebuffer *target_fb;
1855 	struct drm_gem_object *obj;
1856 	struct amdgpu_bo *abo;
1857 	uint64_t fb_location, tiling_flags;
1858 	uint32_t fb_format, fb_pitch_pixels;
1859 	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1860 	u32 pipe_config;
1861 	u32 tmp, viewport_w, viewport_h;
1862 	int r;
1863 	bool bypass_lut = false;
1864 	struct drm_format_name_buf format_name;
1865 
1866 	/* no fb bound */
1867 	if (!atomic && !crtc->primary->fb) {
1868 		DRM_DEBUG_KMS("No FB bound\n");
1869 		return 0;
1870 	}
1871 
1872 	if (atomic)
1873 		target_fb = fb;
1874 	else
1875 		target_fb = crtc->primary->fb;
1876 
1877 	/* If atomic, assume fb object is pinned & idle & fenced and
1878 	 * just update base pointers
1879 	 */
1880 	obj = target_fb->obj[0];
1881 	abo = gem_to_amdgpu_bo(obj);
1882 	r = amdgpu_bo_reserve(abo, false);
1883 	if (unlikely(r != 0))
1884 		return r;
1885 
1886 	if (!atomic) {
1887 		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1888 		if (unlikely(r != 0)) {
1889 			amdgpu_bo_unreserve(abo);
1890 			return -EINVAL;
1891 		}
1892 	}
1893 	fb_location = amdgpu_bo_gpu_offset(abo);
1894 
1895 	amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1896 	amdgpu_bo_unreserve(abo);
1897 
1898 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1899 
1900 	switch (target_fb->format->format) {
1901 	case DRM_FORMAT_C8:
1902 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1903 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1904 		break;
1905 	case DRM_FORMAT_XRGB4444:
1906 	case DRM_FORMAT_ARGB4444:
1907 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1908 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1909 #ifdef __BIG_ENDIAN
1910 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1911 					ENDIAN_8IN16);
1912 #endif
1913 		break;
1914 	case DRM_FORMAT_XRGB1555:
1915 	case DRM_FORMAT_ARGB1555:
1916 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1917 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1918 #ifdef __BIG_ENDIAN
1919 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1920 					ENDIAN_8IN16);
1921 #endif
1922 		break;
1923 	case DRM_FORMAT_BGRX5551:
1924 	case DRM_FORMAT_BGRA5551:
1925 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1926 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1927 #ifdef __BIG_ENDIAN
1928 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1929 					ENDIAN_8IN16);
1930 #endif
1931 		break;
1932 	case DRM_FORMAT_RGB565:
1933 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1934 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1935 #ifdef __BIG_ENDIAN
1936 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1937 					ENDIAN_8IN16);
1938 #endif
1939 		break;
1940 	case DRM_FORMAT_XRGB8888:
1941 	case DRM_FORMAT_ARGB8888:
1942 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1943 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1944 #ifdef __BIG_ENDIAN
1945 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1946 					ENDIAN_8IN32);
1947 #endif
1948 		break;
1949 	case DRM_FORMAT_XRGB2101010:
1950 	case DRM_FORMAT_ARGB2101010:
1951 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1952 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1953 #ifdef __BIG_ENDIAN
1954 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1955 					ENDIAN_8IN32);
1956 #endif
1957 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1958 		bypass_lut = true;
1959 		break;
1960 	case DRM_FORMAT_BGRX1010102:
1961 	case DRM_FORMAT_BGRA1010102:
1962 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1963 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1964 #ifdef __BIG_ENDIAN
1965 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1966 					ENDIAN_8IN32);
1967 #endif
1968 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1969 		bypass_lut = true;
1970 		break;
1971 	case DRM_FORMAT_XBGR8888:
1972 	case DRM_FORMAT_ABGR8888:
1973 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1974 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1975 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1976 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1977 #ifdef __BIG_ENDIAN
1978 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1979 					ENDIAN_8IN32);
1980 #endif
1981 		break;
1982 	default:
1983 		DRM_ERROR("Unsupported screen format %s\n",
1984 		          drm_get_format_name(target_fb->format->format, &format_name));
1985 		return -EINVAL;
1986 	}
1987 
1988 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1989 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1990 
1991 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1992 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1993 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1994 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1995 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1996 
1997 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1998 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1999 					  ARRAY_2D_TILED_THIN1);
2000 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2001 					  tile_split);
2002 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2003 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2004 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2005 					  mtaspect);
2006 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2007 					  ADDR_SURF_MICRO_TILING_DISPLAY);
2008 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2009 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2010 					  ARRAY_1D_TILED_THIN1);
2011 	}
2012 
2013 	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2014 				  pipe_config);
2015 
2016 	dce_v10_0_vga_enable(crtc, false);
2017 
2018 	/* Make sure surface address is updated at vertical blank rather than
2019 	 * horizontal blank
2020 	 */
2021 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2022 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2023 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2024 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2025 
2026 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2027 	       upper_32_bits(fb_location));
2028 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2029 	       upper_32_bits(fb_location));
2030 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2031 	       (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2032 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2033 	       (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2034 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2035 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2036 
2037 	/*
2038 	 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2039 	 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2040 	 * retain the full precision throughout the pipeline.
2041 	 */
2042 	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2043 	if (bypass_lut)
2044 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2045 	else
2046 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2047 	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2048 
2049 	if (bypass_lut)
2050 		DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2051 
2052 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2053 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2054 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2055 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2056 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2057 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2058 
2059 	fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2060 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2061 
2062 	dce_v10_0_grph_enable(crtc, true);
2063 
2064 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2065 	       target_fb->height);
2066 
2067 	x &= ~3;
2068 	y &= ~1;
2069 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2070 	       (x << 16) | y);
2071 	viewport_w = crtc->mode.hdisplay;
2072 	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2073 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2074 	       (viewport_w << 16) | viewport_h);
2075 
2076 	/* set pageflip to happen anywhere in vblank interval */
2077 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2078 
2079 	if (!atomic && fb && fb != crtc->primary->fb) {
2080 		abo = gem_to_amdgpu_bo(fb->obj[0]);
2081 		r = amdgpu_bo_reserve(abo, true);
2082 		if (unlikely(r != 0))
2083 			return r;
2084 		amdgpu_bo_unpin(abo);
2085 		amdgpu_bo_unreserve(abo);
2086 	}
2087 
2088 	/* Bytes per pixel may have changed */
2089 	dce_v10_0_bandwidth_update(adev);
2090 
2091 	return 0;
2092 }
2093 
2094 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2095 				     struct drm_display_mode *mode)
2096 {
2097 	struct drm_device *dev = crtc->dev;
2098 	struct amdgpu_device *adev = dev->dev_private;
2099 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2100 	u32 tmp;
2101 
2102 	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2103 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2104 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2105 	else
2106 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2107 	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2108 }
2109 
2110 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2111 {
2112 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2113 	struct drm_device *dev = crtc->dev;
2114 	struct amdgpu_device *adev = dev->dev_private;
2115 	u16 *r, *g, *b;
2116 	int i;
2117 	u32 tmp;
2118 
2119 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2120 
2121 	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2122 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2123 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2124 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2125 
2126 	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2127 	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2128 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2129 
2130 	tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2131 	tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2132 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2133 
2134 	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2135 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2136 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2137 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2138 
2139 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2140 
2141 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2142 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2143 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2144 
2145 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2146 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2147 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2148 
2149 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2150 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2151 
2152 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2153 	r = crtc->gamma_store;
2154 	g = r + crtc->gamma_size;
2155 	b = g + crtc->gamma_size;
2156 	for (i = 0; i < 256; i++) {
2157 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2158 		       ((*r++ & 0xffc0) << 14) |
2159 		       ((*g++ & 0xffc0) << 4) |
2160 		       (*b++ >> 6));
2161 	}
2162 
2163 	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2164 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2165 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2166 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2167 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2168 
2169 	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2170 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2171 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2172 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2173 
2174 	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2175 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2176 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2177 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2178 
2179 	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2180 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2181 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2182 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2183 
2184 	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
2185 	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2186 	/* XXX this only needs to be programmed once per crtc at startup,
2187 	 * not sure where the best place for it is
2188 	 */
2189 	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2190 	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2191 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2192 }
2193 
2194 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2195 {
2196 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2197 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2198 
2199 	switch (amdgpu_encoder->encoder_id) {
2200 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2201 		if (dig->linkb)
2202 			return 1;
2203 		else
2204 			return 0;
2205 		break;
2206 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2207 		if (dig->linkb)
2208 			return 3;
2209 		else
2210 			return 2;
2211 		break;
2212 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2213 		if (dig->linkb)
2214 			return 5;
2215 		else
2216 			return 4;
2217 		break;
2218 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2219 		return 6;
2220 		break;
2221 	default:
2222 		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2223 		return 0;
2224 	}
2225 }
2226 
2227 /**
2228  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2229  *
2230  * @crtc: drm crtc
2231  *
2232  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2233  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2234  * monitors a dedicated PPLL must be used.  If a particular board has
2235  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2236  * as there is no need to program the PLL itself.  If we are not able to
2237  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2238  * avoid messing up an existing monitor.
2239  *
2240  * Asic specific PLL information
2241  *
2242  * DCE 10.x
2243  * Tonga
2244  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2245  * CI
2246  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2247  *
2248  */
2249 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2250 {
2251 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2252 	struct drm_device *dev = crtc->dev;
2253 	struct amdgpu_device *adev = dev->dev_private;
2254 	u32 pll_in_use;
2255 	int pll;
2256 
2257 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2258 		if (adev->clock.dp_extclk)
2259 			/* skip PPLL programming if using ext clock */
2260 			return ATOM_PPLL_INVALID;
2261 		else {
2262 			/* use the same PPLL for all DP monitors */
2263 			pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2264 			if (pll != ATOM_PPLL_INVALID)
2265 				return pll;
2266 		}
2267 	} else {
2268 		/* use the same PPLL for all monitors with the same clock */
2269 		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2270 		if (pll != ATOM_PPLL_INVALID)
2271 			return pll;
2272 	}
2273 
2274 	/* DCE10 has PPLL0, PPLL1, and PPLL2 */
2275 	pll_in_use = amdgpu_pll_get_use_mask(crtc);
2276 	if (!(pll_in_use & (1 << ATOM_PPLL2)))
2277 		return ATOM_PPLL2;
2278 	if (!(pll_in_use & (1 << ATOM_PPLL1)))
2279 		return ATOM_PPLL1;
2280 	if (!(pll_in_use & (1 << ATOM_PPLL0)))
2281 		return ATOM_PPLL0;
2282 	DRM_ERROR("unable to allocate a PPLL\n");
2283 	return ATOM_PPLL_INVALID;
2284 }
2285 
2286 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2287 {
2288 	struct amdgpu_device *adev = crtc->dev->dev_private;
2289 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2290 	uint32_t cur_lock;
2291 
2292 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2293 	if (lock)
2294 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2295 	else
2296 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2297 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2298 }
2299 
2300 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2301 {
2302 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2303 	struct amdgpu_device *adev = crtc->dev->dev_private;
2304 	u32 tmp;
2305 
2306 	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2307 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2308 	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2309 }
2310 
2311 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2312 {
2313 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2314 	struct amdgpu_device *adev = crtc->dev->dev_private;
2315 	u32 tmp;
2316 
2317 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2318 	       upper_32_bits(amdgpu_crtc->cursor_addr));
2319 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2320 	       lower_32_bits(amdgpu_crtc->cursor_addr));
2321 
2322 	tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2323 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2324 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2325 	WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2326 }
2327 
2328 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2329 					int x, int y)
2330 {
2331 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2332 	struct amdgpu_device *adev = crtc->dev->dev_private;
2333 	int xorigin = 0, yorigin = 0;
2334 
2335 	amdgpu_crtc->cursor_x = x;
2336 	amdgpu_crtc->cursor_y = y;
2337 
2338 	/* avivo cursor are offset into the total surface */
2339 	x += crtc->x;
2340 	y += crtc->y;
2341 	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2342 
2343 	if (x < 0) {
2344 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2345 		x = 0;
2346 	}
2347 	if (y < 0) {
2348 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2349 		y = 0;
2350 	}
2351 
2352 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2353 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2354 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2355 	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2356 
2357 	return 0;
2358 }
2359 
2360 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2361 				      int x, int y)
2362 {
2363 	int ret;
2364 
2365 	dce_v10_0_lock_cursor(crtc, true);
2366 	ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2367 	dce_v10_0_lock_cursor(crtc, false);
2368 
2369 	return ret;
2370 }
2371 
2372 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2373 				      struct drm_file *file_priv,
2374 				      uint32_t handle,
2375 				      uint32_t width,
2376 				      uint32_t height,
2377 				      int32_t hot_x,
2378 				      int32_t hot_y)
2379 {
2380 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2381 	struct drm_gem_object *obj;
2382 	struct amdgpu_bo *aobj;
2383 	int ret;
2384 
2385 	if (!handle) {
2386 		/* turn off cursor */
2387 		dce_v10_0_hide_cursor(crtc);
2388 		obj = NULL;
2389 		goto unpin;
2390 	}
2391 
2392 	if ((width > amdgpu_crtc->max_cursor_width) ||
2393 	    (height > amdgpu_crtc->max_cursor_height)) {
2394 		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2395 		return -EINVAL;
2396 	}
2397 
2398 	obj = drm_gem_object_lookup(file_priv, handle);
2399 	if (!obj) {
2400 		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2401 		return -ENOENT;
2402 	}
2403 
2404 	aobj = gem_to_amdgpu_bo(obj);
2405 	ret = amdgpu_bo_reserve(aobj, false);
2406 	if (ret != 0) {
2407 		drm_gem_object_put_unlocked(obj);
2408 		return ret;
2409 	}
2410 
2411 	ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2412 	amdgpu_bo_unreserve(aobj);
2413 	if (ret) {
2414 		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2415 		drm_gem_object_put_unlocked(obj);
2416 		return ret;
2417 	}
2418 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2419 
2420 	dce_v10_0_lock_cursor(crtc, true);
2421 
2422 	if (width != amdgpu_crtc->cursor_width ||
2423 	    height != amdgpu_crtc->cursor_height ||
2424 	    hot_x != amdgpu_crtc->cursor_hot_x ||
2425 	    hot_y != amdgpu_crtc->cursor_hot_y) {
2426 		int x, y;
2427 
2428 		x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2429 		y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2430 
2431 		dce_v10_0_cursor_move_locked(crtc, x, y);
2432 
2433 		amdgpu_crtc->cursor_width = width;
2434 		amdgpu_crtc->cursor_height = height;
2435 		amdgpu_crtc->cursor_hot_x = hot_x;
2436 		amdgpu_crtc->cursor_hot_y = hot_y;
2437 	}
2438 
2439 	dce_v10_0_show_cursor(crtc);
2440 	dce_v10_0_lock_cursor(crtc, false);
2441 
2442 unpin:
2443 	if (amdgpu_crtc->cursor_bo) {
2444 		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2445 		ret = amdgpu_bo_reserve(aobj, true);
2446 		if (likely(ret == 0)) {
2447 			amdgpu_bo_unpin(aobj);
2448 			amdgpu_bo_unreserve(aobj);
2449 		}
2450 		drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2451 	}
2452 
2453 	amdgpu_crtc->cursor_bo = obj;
2454 	return 0;
2455 }
2456 
2457 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2458 {
2459 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2460 
2461 	if (amdgpu_crtc->cursor_bo) {
2462 		dce_v10_0_lock_cursor(crtc, true);
2463 
2464 		dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2465 					     amdgpu_crtc->cursor_y);
2466 
2467 		dce_v10_0_show_cursor(crtc);
2468 
2469 		dce_v10_0_lock_cursor(crtc, false);
2470 	}
2471 }
2472 
2473 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2474 				    u16 *blue, uint32_t size,
2475 				    struct drm_modeset_acquire_ctx *ctx)
2476 {
2477 	dce_v10_0_crtc_load_lut(crtc);
2478 
2479 	return 0;
2480 }
2481 
2482 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2483 {
2484 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2485 
2486 	drm_crtc_cleanup(crtc);
2487 	kfree(amdgpu_crtc);
2488 }
2489 
2490 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2491 	.cursor_set2 = dce_v10_0_crtc_cursor_set2,
2492 	.cursor_move = dce_v10_0_crtc_cursor_move,
2493 	.gamma_set = dce_v10_0_crtc_gamma_set,
2494 	.set_config = amdgpu_display_crtc_set_config,
2495 	.destroy = dce_v10_0_crtc_destroy,
2496 	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2497 	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2498 	.enable_vblank = amdgpu_enable_vblank_kms,
2499 	.disable_vblank = amdgpu_disable_vblank_kms,
2500 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2501 };
2502 
2503 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2504 {
2505 	struct drm_device *dev = crtc->dev;
2506 	struct amdgpu_device *adev = dev->dev_private;
2507 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2508 	unsigned type;
2509 
2510 	switch (mode) {
2511 	case DRM_MODE_DPMS_ON:
2512 		amdgpu_crtc->enabled = true;
2513 		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2514 		dce_v10_0_vga_enable(crtc, true);
2515 		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2516 		dce_v10_0_vga_enable(crtc, false);
2517 		/* Make sure VBLANK and PFLIP interrupts are still enabled */
2518 		type = amdgpu_display_crtc_idx_to_irq_type(adev,
2519 						amdgpu_crtc->crtc_id);
2520 		amdgpu_irq_update(adev, &adev->crtc_irq, type);
2521 		amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2522 		drm_crtc_vblank_on(crtc);
2523 		dce_v10_0_crtc_load_lut(crtc);
2524 		break;
2525 	case DRM_MODE_DPMS_STANDBY:
2526 	case DRM_MODE_DPMS_SUSPEND:
2527 	case DRM_MODE_DPMS_OFF:
2528 		drm_crtc_vblank_off(crtc);
2529 		if (amdgpu_crtc->enabled) {
2530 			dce_v10_0_vga_enable(crtc, true);
2531 			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2532 			dce_v10_0_vga_enable(crtc, false);
2533 		}
2534 		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2535 		amdgpu_crtc->enabled = false;
2536 		break;
2537 	}
2538 	/* adjust pm to dpms */
2539 	amdgpu_pm_compute_clocks(adev);
2540 }
2541 
2542 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2543 {
2544 	/* disable crtc pair power gating before programming */
2545 	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2546 	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2547 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2548 }
2549 
2550 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2551 {
2552 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2553 	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2554 }
2555 
2556 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2557 {
2558 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2559 	struct drm_device *dev = crtc->dev;
2560 	struct amdgpu_device *adev = dev->dev_private;
2561 	struct amdgpu_atom_ss ss;
2562 	int i;
2563 
2564 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2565 	if (crtc->primary->fb) {
2566 		int r;
2567 		struct amdgpu_bo *abo;
2568 
2569 		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2570 		r = amdgpu_bo_reserve(abo, true);
2571 		if (unlikely(r))
2572 			DRM_ERROR("failed to reserve abo before unpin\n");
2573 		else {
2574 			amdgpu_bo_unpin(abo);
2575 			amdgpu_bo_unreserve(abo);
2576 		}
2577 	}
2578 	/* disable the GRPH */
2579 	dce_v10_0_grph_enable(crtc, false);
2580 
2581 	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2582 
2583 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2584 		if (adev->mode_info.crtcs[i] &&
2585 		    adev->mode_info.crtcs[i]->enabled &&
2586 		    i != amdgpu_crtc->crtc_id &&
2587 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2588 			/* one other crtc is using this pll don't turn
2589 			 * off the pll
2590 			 */
2591 			goto done;
2592 		}
2593 	}
2594 
2595 	switch (amdgpu_crtc->pll_id) {
2596 	case ATOM_PPLL0:
2597 	case ATOM_PPLL1:
2598 	case ATOM_PPLL2:
2599 		/* disable the ppll */
2600 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2601 					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2602 		break;
2603 	default:
2604 		break;
2605 	}
2606 done:
2607 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2608 	amdgpu_crtc->adjusted_clock = 0;
2609 	amdgpu_crtc->encoder = NULL;
2610 	amdgpu_crtc->connector = NULL;
2611 }
2612 
2613 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2614 				  struct drm_display_mode *mode,
2615 				  struct drm_display_mode *adjusted_mode,
2616 				  int x, int y, struct drm_framebuffer *old_fb)
2617 {
2618 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2619 
2620 	if (!amdgpu_crtc->adjusted_clock)
2621 		return -EINVAL;
2622 
2623 	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2624 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2625 	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2626 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2627 	amdgpu_atombios_crtc_scaler_setup(crtc);
2628 	dce_v10_0_cursor_reset(crtc);
2629 	/* update the hw version fpr dpm */
2630 	amdgpu_crtc->hw_mode = *adjusted_mode;
2631 
2632 	return 0;
2633 }
2634 
2635 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2636 				     const struct drm_display_mode *mode,
2637 				     struct drm_display_mode *adjusted_mode)
2638 {
2639 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2640 	struct drm_device *dev = crtc->dev;
2641 	struct drm_encoder *encoder;
2642 
2643 	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2644 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2645 		if (encoder->crtc == crtc) {
2646 			amdgpu_crtc->encoder = encoder;
2647 			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2648 			break;
2649 		}
2650 	}
2651 	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2652 		amdgpu_crtc->encoder = NULL;
2653 		amdgpu_crtc->connector = NULL;
2654 		return false;
2655 	}
2656 	if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2657 		return false;
2658 	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2659 		return false;
2660 	/* pick pll */
2661 	amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2662 	/* if we can't get a PPLL for a non-DP encoder, fail */
2663 	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2664 	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2665 		return false;
2666 
2667 	return true;
2668 }
2669 
2670 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2671 				  struct drm_framebuffer *old_fb)
2672 {
2673 	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2674 }
2675 
2676 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2677 					 struct drm_framebuffer *fb,
2678 					 int x, int y, enum mode_set_atomic state)
2679 {
2680        return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2681 }
2682 
2683 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2684 	.dpms = dce_v10_0_crtc_dpms,
2685 	.mode_fixup = dce_v10_0_crtc_mode_fixup,
2686 	.mode_set = dce_v10_0_crtc_mode_set,
2687 	.mode_set_base = dce_v10_0_crtc_set_base,
2688 	.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2689 	.prepare = dce_v10_0_crtc_prepare,
2690 	.commit = dce_v10_0_crtc_commit,
2691 	.disable = dce_v10_0_crtc_disable,
2692 	.get_scanout_position = amdgpu_crtc_get_scanout_position,
2693 };
2694 
2695 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2696 {
2697 	struct amdgpu_crtc *amdgpu_crtc;
2698 
2699 	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2700 			      (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2701 	if (amdgpu_crtc == NULL)
2702 		return -ENOMEM;
2703 
2704 	drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2705 
2706 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2707 	amdgpu_crtc->crtc_id = index;
2708 	adev->mode_info.crtcs[index] = amdgpu_crtc;
2709 
2710 	amdgpu_crtc->max_cursor_width = 128;
2711 	amdgpu_crtc->max_cursor_height = 128;
2712 	adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2713 	adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2714 
2715 	switch (amdgpu_crtc->crtc_id) {
2716 	case 0:
2717 	default:
2718 		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2719 		break;
2720 	case 1:
2721 		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2722 		break;
2723 	case 2:
2724 		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2725 		break;
2726 	case 3:
2727 		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2728 		break;
2729 	case 4:
2730 		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2731 		break;
2732 	case 5:
2733 		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2734 		break;
2735 	}
2736 
2737 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2738 	amdgpu_crtc->adjusted_clock = 0;
2739 	amdgpu_crtc->encoder = NULL;
2740 	amdgpu_crtc->connector = NULL;
2741 	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2742 
2743 	return 0;
2744 }
2745 
2746 static int dce_v10_0_early_init(void *handle)
2747 {
2748 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2749 
2750 	adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2751 	adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2752 
2753 	dce_v10_0_set_display_funcs(adev);
2754 
2755 	adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2756 
2757 	switch (adev->asic_type) {
2758 	case CHIP_FIJI:
2759 	case CHIP_TONGA:
2760 		adev->mode_info.num_hpd = 6;
2761 		adev->mode_info.num_dig = 7;
2762 		break;
2763 	default:
2764 		/* FIXME: not supported yet */
2765 		return -EINVAL;
2766 	}
2767 
2768 	dce_v10_0_set_irq_funcs(adev);
2769 
2770 	return 0;
2771 }
2772 
2773 static int dce_v10_0_sw_init(void *handle)
2774 {
2775 	int r, i;
2776 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2777 
2778 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2779 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2780 		if (r)
2781 			return r;
2782 	}
2783 
2784 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2785 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2786 		if (r)
2787 			return r;
2788 	}
2789 
2790 	/* HPD hotplug */
2791 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2792 	if (r)
2793 		return r;
2794 
2795 	adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2796 
2797 	adev->ddev->mode_config.async_page_flip = true;
2798 
2799 	adev->ddev->mode_config.max_width = 16384;
2800 	adev->ddev->mode_config.max_height = 16384;
2801 
2802 	adev->ddev->mode_config.preferred_depth = 24;
2803 	adev->ddev->mode_config.prefer_shadow = 1;
2804 
2805 	adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2806 
2807 	r = amdgpu_display_modeset_create_props(adev);
2808 	if (r)
2809 		return r;
2810 
2811 	adev->ddev->mode_config.max_width = 16384;
2812 	adev->ddev->mode_config.max_height = 16384;
2813 
2814 	/* allocate crtcs */
2815 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2816 		r = dce_v10_0_crtc_init(adev, i);
2817 		if (r)
2818 			return r;
2819 	}
2820 
2821 	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2822 		amdgpu_display_print_display_setup(adev->ddev);
2823 	else
2824 		return -EINVAL;
2825 
2826 	/* setup afmt */
2827 	r = dce_v10_0_afmt_init(adev);
2828 	if (r)
2829 		return r;
2830 
2831 	r = dce_v10_0_audio_init(adev);
2832 	if (r)
2833 		return r;
2834 
2835 	drm_kms_helper_poll_init(adev->ddev);
2836 
2837 	adev->mode_info.mode_config_initialized = true;
2838 	return 0;
2839 }
2840 
2841 static int dce_v10_0_sw_fini(void *handle)
2842 {
2843 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2844 
2845 	kfree(adev->mode_info.bios_hardcoded_edid);
2846 
2847 	drm_kms_helper_poll_fini(adev->ddev);
2848 
2849 	dce_v10_0_audio_fini(adev);
2850 
2851 	dce_v10_0_afmt_fini(adev);
2852 
2853 	drm_mode_config_cleanup(adev->ddev);
2854 	adev->mode_info.mode_config_initialized = false;
2855 
2856 	return 0;
2857 }
2858 
2859 static int dce_v10_0_hw_init(void *handle)
2860 {
2861 	int i;
2862 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2863 
2864 	dce_v10_0_init_golden_registers(adev);
2865 
2866 	/* disable vga render */
2867 	dce_v10_0_set_vga_render_state(adev, false);
2868 	/* init dig PHYs, disp eng pll */
2869 	amdgpu_atombios_encoder_init_dig(adev);
2870 	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2871 
2872 	/* initialize hpd */
2873 	dce_v10_0_hpd_init(adev);
2874 
2875 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2876 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2877 	}
2878 
2879 	dce_v10_0_pageflip_interrupt_init(adev);
2880 
2881 	return 0;
2882 }
2883 
2884 static int dce_v10_0_hw_fini(void *handle)
2885 {
2886 	int i;
2887 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2888 
2889 	dce_v10_0_hpd_fini(adev);
2890 
2891 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2892 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2893 	}
2894 
2895 	dce_v10_0_pageflip_interrupt_fini(adev);
2896 
2897 	return 0;
2898 }
2899 
2900 static int dce_v10_0_suspend(void *handle)
2901 {
2902 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2903 
2904 	adev->mode_info.bl_level =
2905 		amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2906 
2907 	return dce_v10_0_hw_fini(handle);
2908 }
2909 
2910 static int dce_v10_0_resume(void *handle)
2911 {
2912 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2913 	int ret;
2914 
2915 	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2916 							   adev->mode_info.bl_level);
2917 
2918 	ret = dce_v10_0_hw_init(handle);
2919 
2920 	/* turn on the BL */
2921 	if (adev->mode_info.bl_encoder) {
2922 		u8 bl_level = amdgpu_display_backlight_get_level(adev,
2923 								  adev->mode_info.bl_encoder);
2924 		amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2925 						    bl_level);
2926 	}
2927 
2928 	return ret;
2929 }
2930 
2931 static bool dce_v10_0_is_idle(void *handle)
2932 {
2933 	return true;
2934 }
2935 
2936 static int dce_v10_0_wait_for_idle(void *handle)
2937 {
2938 	return 0;
2939 }
2940 
2941 static bool dce_v10_0_check_soft_reset(void *handle)
2942 {
2943 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2944 
2945 	return dce_v10_0_is_display_hung(adev);
2946 }
2947 
2948 static int dce_v10_0_soft_reset(void *handle)
2949 {
2950 	u32 srbm_soft_reset = 0, tmp;
2951 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2952 
2953 	if (dce_v10_0_is_display_hung(adev))
2954 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2955 
2956 	if (srbm_soft_reset) {
2957 		tmp = RREG32(mmSRBM_SOFT_RESET);
2958 		tmp |= srbm_soft_reset;
2959 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2960 		WREG32(mmSRBM_SOFT_RESET, tmp);
2961 		tmp = RREG32(mmSRBM_SOFT_RESET);
2962 
2963 		udelay(50);
2964 
2965 		tmp &= ~srbm_soft_reset;
2966 		WREG32(mmSRBM_SOFT_RESET, tmp);
2967 		tmp = RREG32(mmSRBM_SOFT_RESET);
2968 
2969 		/* Wait a little for things to settle down */
2970 		udelay(50);
2971 	}
2972 	return 0;
2973 }
2974 
2975 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2976 						     int crtc,
2977 						     enum amdgpu_interrupt_state state)
2978 {
2979 	u32 lb_interrupt_mask;
2980 
2981 	if (crtc >= adev->mode_info.num_crtc) {
2982 		DRM_DEBUG("invalid crtc %d\n", crtc);
2983 		return;
2984 	}
2985 
2986 	switch (state) {
2987 	case AMDGPU_IRQ_STATE_DISABLE:
2988 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2989 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2990 						  VBLANK_INTERRUPT_MASK, 0);
2991 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2992 		break;
2993 	case AMDGPU_IRQ_STATE_ENABLE:
2994 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2995 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2996 						  VBLANK_INTERRUPT_MASK, 1);
2997 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2998 		break;
2999 	default:
3000 		break;
3001 	}
3002 }
3003 
3004 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3005 						    int crtc,
3006 						    enum amdgpu_interrupt_state state)
3007 {
3008 	u32 lb_interrupt_mask;
3009 
3010 	if (crtc >= adev->mode_info.num_crtc) {
3011 		DRM_DEBUG("invalid crtc %d\n", crtc);
3012 		return;
3013 	}
3014 
3015 	switch (state) {
3016 	case AMDGPU_IRQ_STATE_DISABLE:
3017 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3018 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3019 						  VLINE_INTERRUPT_MASK, 0);
3020 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3021 		break;
3022 	case AMDGPU_IRQ_STATE_ENABLE:
3023 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3024 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3025 						  VLINE_INTERRUPT_MASK, 1);
3026 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3027 		break;
3028 	default:
3029 		break;
3030 	}
3031 }
3032 
3033 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3034 				       struct amdgpu_irq_src *source,
3035 				       unsigned hpd,
3036 				       enum amdgpu_interrupt_state state)
3037 {
3038 	u32 tmp;
3039 
3040 	if (hpd >= adev->mode_info.num_hpd) {
3041 		DRM_DEBUG("invalid hdp %d\n", hpd);
3042 		return 0;
3043 	}
3044 
3045 	switch (state) {
3046 	case AMDGPU_IRQ_STATE_DISABLE:
3047 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3048 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3049 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3050 		break;
3051 	case AMDGPU_IRQ_STATE_ENABLE:
3052 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3053 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3054 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3055 		break;
3056 	default:
3057 		break;
3058 	}
3059 
3060 	return 0;
3061 }
3062 
3063 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3064 					struct amdgpu_irq_src *source,
3065 					unsigned type,
3066 					enum amdgpu_interrupt_state state)
3067 {
3068 	switch (type) {
3069 	case AMDGPU_CRTC_IRQ_VBLANK1:
3070 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3071 		break;
3072 	case AMDGPU_CRTC_IRQ_VBLANK2:
3073 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3074 		break;
3075 	case AMDGPU_CRTC_IRQ_VBLANK3:
3076 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3077 		break;
3078 	case AMDGPU_CRTC_IRQ_VBLANK4:
3079 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3080 		break;
3081 	case AMDGPU_CRTC_IRQ_VBLANK5:
3082 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3083 		break;
3084 	case AMDGPU_CRTC_IRQ_VBLANK6:
3085 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3086 		break;
3087 	case AMDGPU_CRTC_IRQ_VLINE1:
3088 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3089 		break;
3090 	case AMDGPU_CRTC_IRQ_VLINE2:
3091 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3092 		break;
3093 	case AMDGPU_CRTC_IRQ_VLINE3:
3094 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3095 		break;
3096 	case AMDGPU_CRTC_IRQ_VLINE4:
3097 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3098 		break;
3099 	case AMDGPU_CRTC_IRQ_VLINE5:
3100 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3101 		break;
3102 	case AMDGPU_CRTC_IRQ_VLINE6:
3103 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3104 		break;
3105 	default:
3106 		break;
3107 	}
3108 	return 0;
3109 }
3110 
3111 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3112 					    struct amdgpu_irq_src *src,
3113 					    unsigned type,
3114 					    enum amdgpu_interrupt_state state)
3115 {
3116 	u32 reg;
3117 
3118 	if (type >= adev->mode_info.num_crtc) {
3119 		DRM_ERROR("invalid pageflip crtc %d\n", type);
3120 		return -EINVAL;
3121 	}
3122 
3123 	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3124 	if (state == AMDGPU_IRQ_STATE_DISABLE)
3125 		WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3126 		       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3127 	else
3128 		WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3129 		       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3130 
3131 	return 0;
3132 }
3133 
3134 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3135 				  struct amdgpu_irq_src *source,
3136 				  struct amdgpu_iv_entry *entry)
3137 {
3138 	unsigned long flags;
3139 	unsigned crtc_id;
3140 	struct amdgpu_crtc *amdgpu_crtc;
3141 	struct amdgpu_flip_work *works;
3142 
3143 	crtc_id = (entry->src_id - 8) >> 1;
3144 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3145 
3146 	if (crtc_id >= adev->mode_info.num_crtc) {
3147 		DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3148 		return -EINVAL;
3149 	}
3150 
3151 	if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3152 	    GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3153 		WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3154 		       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3155 
3156 	/* IRQ could occur when in initial stage */
3157 	if (amdgpu_crtc == NULL)
3158 		return 0;
3159 
3160 	spin_lock_irqsave(&adev->ddev->event_lock, flags);
3161 	works = amdgpu_crtc->pflip_works;
3162 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3163 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3164 						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3165 						 amdgpu_crtc->pflip_status,
3166 						 AMDGPU_FLIP_SUBMITTED);
3167 		spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3168 		return 0;
3169 	}
3170 
3171 	/* page flip completed. clean up */
3172 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3173 	amdgpu_crtc->pflip_works = NULL;
3174 
3175 	/* wakeup usersapce */
3176 	if (works->event)
3177 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3178 
3179 	spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3180 
3181 	drm_crtc_vblank_put(&amdgpu_crtc->base);
3182 	schedule_work(&works->unpin_work);
3183 
3184 	return 0;
3185 }
3186 
3187 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3188 				  int hpd)
3189 {
3190 	u32 tmp;
3191 
3192 	if (hpd >= adev->mode_info.num_hpd) {
3193 		DRM_DEBUG("invalid hdp %d\n", hpd);
3194 		return;
3195 	}
3196 
3197 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3198 	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3199 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3200 }
3201 
3202 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3203 					  int crtc)
3204 {
3205 	u32 tmp;
3206 
3207 	if (crtc >= adev->mode_info.num_crtc) {
3208 		DRM_DEBUG("invalid crtc %d\n", crtc);
3209 		return;
3210 	}
3211 
3212 	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3213 	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3214 	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3215 }
3216 
3217 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3218 					 int crtc)
3219 {
3220 	u32 tmp;
3221 
3222 	if (crtc >= adev->mode_info.num_crtc) {
3223 		DRM_DEBUG("invalid crtc %d\n", crtc);
3224 		return;
3225 	}
3226 
3227 	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3228 	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3229 	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3230 }
3231 
3232 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3233 			      struct amdgpu_irq_src *source,
3234 			      struct amdgpu_iv_entry *entry)
3235 {
3236 	unsigned crtc = entry->src_id - 1;
3237 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3238 	unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3239 
3240 	switch (entry->src_data[0]) {
3241 	case 0: /* vblank */
3242 		if (disp_int & interrupt_status_offsets[crtc].vblank)
3243 			dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3244 		else
3245 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3246 
3247 		if (amdgpu_irq_enabled(adev, source, irq_type)) {
3248 			drm_handle_vblank(adev->ddev, crtc);
3249 		}
3250 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3251 
3252 		break;
3253 	case 1: /* vline */
3254 		if (disp_int & interrupt_status_offsets[crtc].vline)
3255 			dce_v10_0_crtc_vline_int_ack(adev, crtc);
3256 		else
3257 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3258 
3259 		DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3260 
3261 		break;
3262 	default:
3263 		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3264 		break;
3265 	}
3266 
3267 	return 0;
3268 }
3269 
3270 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3271 			     struct amdgpu_irq_src *source,
3272 			     struct amdgpu_iv_entry *entry)
3273 {
3274 	uint32_t disp_int, mask;
3275 	unsigned hpd;
3276 
3277 	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3278 		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3279 		return 0;
3280 	}
3281 
3282 	hpd = entry->src_data[0];
3283 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3284 	mask = interrupt_status_offsets[hpd].hpd;
3285 
3286 	if (disp_int & mask) {
3287 		dce_v10_0_hpd_int_ack(adev, hpd);
3288 		schedule_work(&adev->hotplug_work);
3289 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3290 	}
3291 
3292 	return 0;
3293 }
3294 
3295 static int dce_v10_0_set_clockgating_state(void *handle,
3296 					  enum amd_clockgating_state state)
3297 {
3298 	return 0;
3299 }
3300 
3301 static int dce_v10_0_set_powergating_state(void *handle,
3302 					  enum amd_powergating_state state)
3303 {
3304 	return 0;
3305 }
3306 
3307 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3308 	.name = "dce_v10_0",
3309 	.early_init = dce_v10_0_early_init,
3310 	.late_init = NULL,
3311 	.sw_init = dce_v10_0_sw_init,
3312 	.sw_fini = dce_v10_0_sw_fini,
3313 	.hw_init = dce_v10_0_hw_init,
3314 	.hw_fini = dce_v10_0_hw_fini,
3315 	.suspend = dce_v10_0_suspend,
3316 	.resume = dce_v10_0_resume,
3317 	.is_idle = dce_v10_0_is_idle,
3318 	.wait_for_idle = dce_v10_0_wait_for_idle,
3319 	.check_soft_reset = dce_v10_0_check_soft_reset,
3320 	.soft_reset = dce_v10_0_soft_reset,
3321 	.set_clockgating_state = dce_v10_0_set_clockgating_state,
3322 	.set_powergating_state = dce_v10_0_set_powergating_state,
3323 };
3324 
3325 static void
3326 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3327 			  struct drm_display_mode *mode,
3328 			  struct drm_display_mode *adjusted_mode)
3329 {
3330 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3331 
3332 	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3333 
3334 	/* need to call this here rather than in prepare() since we need some crtc info */
3335 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3336 
3337 	/* set scaler clears this on some chips */
3338 	dce_v10_0_set_interleave(encoder->crtc, mode);
3339 
3340 	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3341 		dce_v10_0_afmt_enable(encoder, true);
3342 		dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3343 	}
3344 }
3345 
3346 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3347 {
3348 	struct amdgpu_device *adev = encoder->dev->dev_private;
3349 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3350 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3351 
3352 	if ((amdgpu_encoder->active_device &
3353 	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3354 	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3355 	     ENCODER_OBJECT_ID_NONE)) {
3356 		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3357 		if (dig) {
3358 			dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3359 			if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3360 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3361 		}
3362 	}
3363 
3364 	amdgpu_atombios_scratch_regs_lock(adev, true);
3365 
3366 	if (connector) {
3367 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3368 
3369 		/* select the clock/data port if it uses a router */
3370 		if (amdgpu_connector->router.cd_valid)
3371 			amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3372 
3373 		/* turn eDP panel on for mode set */
3374 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3375 			amdgpu_atombios_encoder_set_edp_panel_power(connector,
3376 							     ATOM_TRANSMITTER_ACTION_POWER_ON);
3377 	}
3378 
3379 	/* this is needed for the pll/ss setup to work correctly in some cases */
3380 	amdgpu_atombios_encoder_set_crtc_source(encoder);
3381 	/* set up the FMT blocks */
3382 	dce_v10_0_program_fmt(encoder);
3383 }
3384 
3385 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3386 {
3387 	struct drm_device *dev = encoder->dev;
3388 	struct amdgpu_device *adev = dev->dev_private;
3389 
3390 	/* need to call this here as we need the crtc set up */
3391 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3392 	amdgpu_atombios_scratch_regs_lock(adev, false);
3393 }
3394 
3395 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3396 {
3397 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3398 	struct amdgpu_encoder_atom_dig *dig;
3399 
3400 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3401 
3402 	if (amdgpu_atombios_encoder_is_digital(encoder)) {
3403 		if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3404 			dce_v10_0_afmt_enable(encoder, false);
3405 		dig = amdgpu_encoder->enc_priv;
3406 		dig->dig_encoder = -1;
3407 	}
3408 	amdgpu_encoder->active_device = 0;
3409 }
3410 
3411 /* these are handled by the primary encoders */
3412 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3413 {
3414 
3415 }
3416 
3417 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3418 {
3419 
3420 }
3421 
3422 static void
3423 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3424 		      struct drm_display_mode *mode,
3425 		      struct drm_display_mode *adjusted_mode)
3426 {
3427 
3428 }
3429 
3430 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3431 {
3432 
3433 }
3434 
3435 static void
3436 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3437 {
3438 
3439 }
3440 
3441 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3442 	.dpms = dce_v10_0_ext_dpms,
3443 	.prepare = dce_v10_0_ext_prepare,
3444 	.mode_set = dce_v10_0_ext_mode_set,
3445 	.commit = dce_v10_0_ext_commit,
3446 	.disable = dce_v10_0_ext_disable,
3447 	/* no detect for TMDS/LVDS yet */
3448 };
3449 
3450 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3451 	.dpms = amdgpu_atombios_encoder_dpms,
3452 	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3453 	.prepare = dce_v10_0_encoder_prepare,
3454 	.mode_set = dce_v10_0_encoder_mode_set,
3455 	.commit = dce_v10_0_encoder_commit,
3456 	.disable = dce_v10_0_encoder_disable,
3457 	.detect = amdgpu_atombios_encoder_dig_detect,
3458 };
3459 
3460 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3461 	.dpms = amdgpu_atombios_encoder_dpms,
3462 	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3463 	.prepare = dce_v10_0_encoder_prepare,
3464 	.mode_set = dce_v10_0_encoder_mode_set,
3465 	.commit = dce_v10_0_encoder_commit,
3466 	.detect = amdgpu_atombios_encoder_dac_detect,
3467 };
3468 
3469 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3470 {
3471 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3472 	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3473 		amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3474 	kfree(amdgpu_encoder->enc_priv);
3475 	drm_encoder_cleanup(encoder);
3476 	kfree(amdgpu_encoder);
3477 }
3478 
3479 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3480 	.destroy = dce_v10_0_encoder_destroy,
3481 };
3482 
3483 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3484 				 uint32_t encoder_enum,
3485 				 uint32_t supported_device,
3486 				 u16 caps)
3487 {
3488 	struct drm_device *dev = adev->ddev;
3489 	struct drm_encoder *encoder;
3490 	struct amdgpu_encoder *amdgpu_encoder;
3491 
3492 	/* see if we already added it */
3493 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3494 		amdgpu_encoder = to_amdgpu_encoder(encoder);
3495 		if (amdgpu_encoder->encoder_enum == encoder_enum) {
3496 			amdgpu_encoder->devices |= supported_device;
3497 			return;
3498 		}
3499 
3500 	}
3501 
3502 	/* add a new one */
3503 	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3504 	if (!amdgpu_encoder)
3505 		return;
3506 
3507 	encoder = &amdgpu_encoder->base;
3508 	switch (adev->mode_info.num_crtc) {
3509 	case 1:
3510 		encoder->possible_crtcs = 0x1;
3511 		break;
3512 	case 2:
3513 	default:
3514 		encoder->possible_crtcs = 0x3;
3515 		break;
3516 	case 4:
3517 		encoder->possible_crtcs = 0xf;
3518 		break;
3519 	case 6:
3520 		encoder->possible_crtcs = 0x3f;
3521 		break;
3522 	}
3523 
3524 	amdgpu_encoder->enc_priv = NULL;
3525 
3526 	amdgpu_encoder->encoder_enum = encoder_enum;
3527 	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3528 	amdgpu_encoder->devices = supported_device;
3529 	amdgpu_encoder->rmx_type = RMX_OFF;
3530 	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3531 	amdgpu_encoder->is_ext_encoder = false;
3532 	amdgpu_encoder->caps = caps;
3533 
3534 	switch (amdgpu_encoder->encoder_id) {
3535 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3536 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3537 		drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3538 				 DRM_MODE_ENCODER_DAC, NULL);
3539 		drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3540 		break;
3541 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3542 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3543 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3544 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3545 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3546 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3547 			amdgpu_encoder->rmx_type = RMX_FULL;
3548 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3549 					 DRM_MODE_ENCODER_LVDS, NULL);
3550 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3551 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3552 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3553 					 DRM_MODE_ENCODER_DAC, NULL);
3554 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3555 		} else {
3556 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3557 					 DRM_MODE_ENCODER_TMDS, NULL);
3558 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3559 		}
3560 		drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3561 		break;
3562 	case ENCODER_OBJECT_ID_SI170B:
3563 	case ENCODER_OBJECT_ID_CH7303:
3564 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3565 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3566 	case ENCODER_OBJECT_ID_TITFP513:
3567 	case ENCODER_OBJECT_ID_VT1623:
3568 	case ENCODER_OBJECT_ID_HDMI_SI1930:
3569 	case ENCODER_OBJECT_ID_TRAVIS:
3570 	case ENCODER_OBJECT_ID_NUTMEG:
3571 		/* these are handled by the primary encoders */
3572 		amdgpu_encoder->is_ext_encoder = true;
3573 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3574 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3575 					 DRM_MODE_ENCODER_LVDS, NULL);
3576 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3577 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3578 					 DRM_MODE_ENCODER_DAC, NULL);
3579 		else
3580 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3581 					 DRM_MODE_ENCODER_TMDS, NULL);
3582 		drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3583 		break;
3584 	}
3585 }
3586 
3587 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3588 	.bandwidth_update = &dce_v10_0_bandwidth_update,
3589 	.vblank_get_counter = &dce_v10_0_vblank_get_counter,
3590 	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3591 	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3592 	.hpd_sense = &dce_v10_0_hpd_sense,
3593 	.hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3594 	.hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3595 	.page_flip = &dce_v10_0_page_flip,
3596 	.page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3597 	.add_encoder = &dce_v10_0_encoder_add,
3598 	.add_connector = &amdgpu_connector_add,
3599 };
3600 
3601 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3602 {
3603 	adev->mode_info.funcs = &dce_v10_0_display_funcs;
3604 }
3605 
3606 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3607 	.set = dce_v10_0_set_crtc_irq_state,
3608 	.process = dce_v10_0_crtc_irq,
3609 };
3610 
3611 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3612 	.set = dce_v10_0_set_pageflip_irq_state,
3613 	.process = dce_v10_0_pageflip_irq,
3614 };
3615 
3616 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3617 	.set = dce_v10_0_set_hpd_irq_state,
3618 	.process = dce_v10_0_hpd_irq,
3619 };
3620 
3621 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3622 {
3623 	if (adev->mode_info.num_crtc > 0)
3624 		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3625 	else
3626 		adev->crtc_irq.num_types = 0;
3627 	adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3628 
3629 	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3630 	adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3631 
3632 	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3633 	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3634 }
3635 
3636 const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3637 {
3638 	.type = AMD_IP_BLOCK_TYPE_DCE,
3639 	.major = 10,
3640 	.minor = 0,
3641 	.rev = 0,
3642 	.funcs = &dce_v10_0_ip_funcs,
3643 };
3644 
3645 const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3646 {
3647 	.type = AMD_IP_BLOCK_TYPE_DCE,
3648 	.major = 10,
3649 	.minor = 1,
3650 	.rev = 0,
3651 	.funcs = &dce_v10_0_ip_funcs,
3652 };
3653