1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 35 #include "dce/dce_10_0_d.h" 36 #include "dce/dce_10_0_sh_mask.h" 37 #include "dce/dce_10_0_enum.h" 38 #include "oss/oss_3_0_d.h" 39 #include "oss/oss_3_0_sh_mask.h" 40 #include "gmc/gmc_8_1_d.h" 41 #include "gmc/gmc_8_1_sh_mask.h" 42 43 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); 44 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); 45 46 static const u32 crtc_offsets[] = 47 { 48 CRTC0_REGISTER_OFFSET, 49 CRTC1_REGISTER_OFFSET, 50 CRTC2_REGISTER_OFFSET, 51 CRTC3_REGISTER_OFFSET, 52 CRTC4_REGISTER_OFFSET, 53 CRTC5_REGISTER_OFFSET, 54 CRTC6_REGISTER_OFFSET 55 }; 56 57 static const u32 hpd_offsets[] = 58 { 59 HPD0_REGISTER_OFFSET, 60 HPD1_REGISTER_OFFSET, 61 HPD2_REGISTER_OFFSET, 62 HPD3_REGISTER_OFFSET, 63 HPD4_REGISTER_OFFSET, 64 HPD5_REGISTER_OFFSET 65 }; 66 67 static const uint32_t dig_offsets[] = { 68 DIG0_REGISTER_OFFSET, 69 DIG1_REGISTER_OFFSET, 70 DIG2_REGISTER_OFFSET, 71 DIG3_REGISTER_OFFSET, 72 DIG4_REGISTER_OFFSET, 73 DIG5_REGISTER_OFFSET, 74 DIG6_REGISTER_OFFSET 75 }; 76 77 static const struct { 78 uint32_t reg; 79 uint32_t vblank; 80 uint32_t vline; 81 uint32_t hpd; 82 83 } interrupt_status_offsets[] = { { 84 .reg = mmDISP_INTERRUPT_STATUS, 85 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 86 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 87 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 88 }, { 89 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 90 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 91 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 92 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 93 }, { 94 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 95 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 96 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 97 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 98 }, { 99 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 100 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 101 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 102 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 103 }, { 104 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 105 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 106 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 107 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 108 }, { 109 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 110 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 111 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 112 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 113 } }; 114 115 static const u32 golden_settings_tonga_a11[] = 116 { 117 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 118 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 119 mmFBC_MISC, 0x1f311fff, 0x12300000, 120 mmHDMI_CONTROL, 0x31000111, 0x00000011, 121 }; 122 123 static const u32 tonga_mgcg_cgcg_init[] = 124 { 125 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 126 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 127 }; 128 129 static const u32 golden_settings_fiji_a10[] = 130 { 131 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 132 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 133 mmFBC_MISC, 0x1f311fff, 0x12300000, 134 mmHDMI_CONTROL, 0x31000111, 0x00000011, 135 }; 136 137 static const u32 fiji_mgcg_cgcg_init[] = 138 { 139 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 140 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 141 }; 142 143 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 144 { 145 switch (adev->asic_type) { 146 case CHIP_FIJI: 147 amdgpu_program_register_sequence(adev, 148 fiji_mgcg_cgcg_init, 149 (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); 150 amdgpu_program_register_sequence(adev, 151 golden_settings_fiji_a10, 152 (const u32)ARRAY_SIZE(golden_settings_fiji_a10)); 153 break; 154 case CHIP_TONGA: 155 amdgpu_program_register_sequence(adev, 156 tonga_mgcg_cgcg_init, 157 (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); 158 amdgpu_program_register_sequence(adev, 159 golden_settings_tonga_a11, 160 (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); 161 break; 162 default: 163 break; 164 } 165 } 166 167 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, 168 u32 block_offset, u32 reg) 169 { 170 unsigned long flags; 171 u32 r; 172 173 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 174 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 175 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 176 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 177 178 return r; 179 } 180 181 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, 182 u32 block_offset, u32 reg, u32 v) 183 { 184 unsigned long flags; 185 186 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 187 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 189 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 190 } 191 192 static bool dce_v10_0_is_in_vblank(struct amdgpu_device *adev, int crtc) 193 { 194 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & 195 CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) 196 return true; 197 else 198 return false; 199 } 200 201 static bool dce_v10_0_is_counter_moving(struct amdgpu_device *adev, int crtc) 202 { 203 u32 pos1, pos2; 204 205 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 206 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 207 208 if (pos1 != pos2) 209 return true; 210 else 211 return false; 212 } 213 214 /** 215 * dce_v10_0_vblank_wait - vblank wait asic callback. 216 * 217 * @adev: amdgpu_device pointer 218 * @crtc: crtc to wait for vblank on 219 * 220 * Wait for vblank on the requested crtc (evergreen+). 221 */ 222 static void dce_v10_0_vblank_wait(struct amdgpu_device *adev, int crtc) 223 { 224 unsigned i = 100; 225 226 if (crtc >= adev->mode_info.num_crtc) 227 return; 228 229 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) 230 return; 231 232 /* depending on when we hit vblank, we may be close to active; if so, 233 * wait for another frame. 234 */ 235 while (dce_v10_0_is_in_vblank(adev, crtc)) { 236 if (i++ == 100) { 237 i = 0; 238 if (!dce_v10_0_is_counter_moving(adev, crtc)) 239 break; 240 } 241 } 242 243 while (!dce_v10_0_is_in_vblank(adev, crtc)) { 244 if (i++ == 100) { 245 i = 0; 246 if (!dce_v10_0_is_counter_moving(adev, crtc)) 247 break; 248 } 249 } 250 } 251 252 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 253 { 254 if (crtc >= adev->mode_info.num_crtc) 255 return 0; 256 else 257 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 258 } 259 260 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) 261 { 262 unsigned i; 263 264 /* Enable pflip interrupts */ 265 for (i = 0; i < adev->mode_info.num_crtc; i++) 266 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 267 } 268 269 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 270 { 271 unsigned i; 272 273 /* Disable pflip interrupts */ 274 for (i = 0; i < adev->mode_info.num_crtc; i++) 275 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 276 } 277 278 /** 279 * dce_v10_0_page_flip - pageflip callback. 280 * 281 * @adev: amdgpu_device pointer 282 * @crtc_id: crtc to cleanup pageflip on 283 * @crtc_base: new address of the crtc (GPU MC address) 284 * 285 * Triggers the actual pageflip by updating the primary 286 * surface base address. 287 */ 288 static void dce_v10_0_page_flip(struct amdgpu_device *adev, 289 int crtc_id, u64 crtc_base, bool async) 290 { 291 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 292 u32 tmp; 293 294 /* flip at hsync for async, default is vsync */ 295 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 296 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 297 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); 298 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 299 /* update the primary scanout address */ 300 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 301 upper_32_bits(crtc_base)); 302 /* writing to the low address triggers the update */ 303 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 304 lower_32_bits(crtc_base)); 305 /* post the write */ 306 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 307 } 308 309 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 310 u32 *vbl, u32 *position) 311 { 312 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 313 return -EINVAL; 314 315 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 316 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 317 318 return 0; 319 } 320 321 /** 322 * dce_v10_0_hpd_sense - hpd sense callback. 323 * 324 * @adev: amdgpu_device pointer 325 * @hpd: hpd (hotplug detect) pin 326 * 327 * Checks if a digital monitor is connected (evergreen+). 328 * Returns true if connected, false if not connected. 329 */ 330 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, 331 enum amdgpu_hpd_id hpd) 332 { 333 int idx; 334 bool connected = false; 335 336 switch (hpd) { 337 case AMDGPU_HPD_1: 338 idx = 0; 339 break; 340 case AMDGPU_HPD_2: 341 idx = 1; 342 break; 343 case AMDGPU_HPD_3: 344 idx = 2; 345 break; 346 case AMDGPU_HPD_4: 347 idx = 3; 348 break; 349 case AMDGPU_HPD_5: 350 idx = 4; 351 break; 352 case AMDGPU_HPD_6: 353 idx = 5; 354 break; 355 default: 356 return connected; 357 } 358 359 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & 360 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 361 connected = true; 362 363 return connected; 364 } 365 366 /** 367 * dce_v10_0_hpd_set_polarity - hpd set polarity callback. 368 * 369 * @adev: amdgpu_device pointer 370 * @hpd: hpd (hotplug detect) pin 371 * 372 * Set the polarity of the hpd pin (evergreen+). 373 */ 374 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, 375 enum amdgpu_hpd_id hpd) 376 { 377 u32 tmp; 378 bool connected = dce_v10_0_hpd_sense(adev, hpd); 379 int idx; 380 381 switch (hpd) { 382 case AMDGPU_HPD_1: 383 idx = 0; 384 break; 385 case AMDGPU_HPD_2: 386 idx = 1; 387 break; 388 case AMDGPU_HPD_3: 389 idx = 2; 390 break; 391 case AMDGPU_HPD_4: 392 idx = 3; 393 break; 394 case AMDGPU_HPD_5: 395 idx = 4; 396 break; 397 case AMDGPU_HPD_6: 398 idx = 5; 399 break; 400 default: 401 return; 402 } 403 404 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 405 if (connected) 406 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 407 else 408 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 409 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 410 } 411 412 /** 413 * dce_v10_0_hpd_init - hpd setup callback. 414 * 415 * @adev: amdgpu_device pointer 416 * 417 * Setup the hpd pins used by the card (evergreen+). 418 * Enable the pin, set the polarity, and enable the hpd interrupts. 419 */ 420 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) 421 { 422 struct drm_device *dev = adev->ddev; 423 struct drm_connector *connector; 424 u32 tmp; 425 int idx; 426 427 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 428 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 429 430 switch (amdgpu_connector->hpd.hpd) { 431 case AMDGPU_HPD_1: 432 idx = 0; 433 break; 434 case AMDGPU_HPD_2: 435 idx = 1; 436 break; 437 case AMDGPU_HPD_3: 438 idx = 2; 439 break; 440 case AMDGPU_HPD_4: 441 idx = 3; 442 break; 443 case AMDGPU_HPD_5: 444 idx = 4; 445 break; 446 case AMDGPU_HPD_6: 447 idx = 5; 448 break; 449 default: 450 continue; 451 } 452 453 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 454 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 455 /* don't try to enable hpd on eDP or LVDS avoid breaking the 456 * aux dp channel on imac and help (but not completely fix) 457 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 458 * also avoid interrupt storms during dpms. 459 */ 460 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); 461 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 462 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); 463 continue; 464 } 465 466 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 467 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 468 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 469 470 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); 471 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 472 DC_HPD_CONNECT_INT_DELAY, 473 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 474 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 475 DC_HPD_DISCONNECT_INT_DELAY, 476 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 477 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); 478 479 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 480 amdgpu_irq_get(adev, &adev->hpd_irq, 481 amdgpu_connector->hpd.hpd); 482 } 483 } 484 485 /** 486 * dce_v10_0_hpd_fini - hpd tear down callback. 487 * 488 * @adev: amdgpu_device pointer 489 * 490 * Tear down the hpd pins used by the card (evergreen+). 491 * Disable the hpd interrupts. 492 */ 493 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) 494 { 495 struct drm_device *dev = adev->ddev; 496 struct drm_connector *connector; 497 u32 tmp; 498 int idx; 499 500 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 501 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 502 503 switch (amdgpu_connector->hpd.hpd) { 504 case AMDGPU_HPD_1: 505 idx = 0; 506 break; 507 case AMDGPU_HPD_2: 508 idx = 1; 509 break; 510 case AMDGPU_HPD_3: 511 idx = 2; 512 break; 513 case AMDGPU_HPD_4: 514 idx = 3; 515 break; 516 case AMDGPU_HPD_5: 517 idx = 4; 518 break; 519 case AMDGPU_HPD_6: 520 idx = 5; 521 break; 522 default: 523 continue; 524 } 525 526 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); 527 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 528 WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); 529 530 amdgpu_irq_put(adev, &adev->hpd_irq, 531 amdgpu_connector->hpd.hpd); 532 } 533 } 534 535 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 536 { 537 return mmDC_GPIO_HPD_A; 538 } 539 540 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) 541 { 542 u32 crtc_hung = 0; 543 u32 crtc_status[6]; 544 u32 i, j, tmp; 545 546 for (i = 0; i < adev->mode_info.num_crtc; i++) { 547 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 548 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 549 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 550 crtc_hung |= (1 << i); 551 } 552 } 553 554 for (j = 0; j < 10; j++) { 555 for (i = 0; i < adev->mode_info.num_crtc; i++) { 556 if (crtc_hung & (1 << i)) { 557 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 558 if (tmp != crtc_status[i]) 559 crtc_hung &= ~(1 << i); 560 } 561 } 562 if (crtc_hung == 0) 563 return false; 564 udelay(100); 565 } 566 567 return true; 568 } 569 570 static void dce_v10_0_stop_mc_access(struct amdgpu_device *adev, 571 struct amdgpu_mode_mc_save *save) 572 { 573 u32 crtc_enabled, tmp; 574 int i; 575 576 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 577 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); 578 579 /* disable VGA render */ 580 tmp = RREG32(mmVGA_RENDER_CONTROL); 581 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 582 WREG32(mmVGA_RENDER_CONTROL, tmp); 583 584 /* blank the display controllers */ 585 for (i = 0; i < adev->mode_info.num_crtc; i++) { 586 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 587 CRTC_CONTROL, CRTC_MASTER_EN); 588 if (crtc_enabled) { 589 #if 0 590 u32 frame_count; 591 int j; 592 593 save->crtc_enabled[i] = true; 594 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 595 if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { 596 amdgpu_display_vblank_wait(adev, i); 597 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 598 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); 599 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 600 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 601 } 602 /* wait for the next frame */ 603 frame_count = amdgpu_display_vblank_get_counter(adev, i); 604 for (j = 0; j < adev->usec_timeout; j++) { 605 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 606 break; 607 udelay(1); 608 } 609 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 610 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { 611 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); 612 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 613 } 614 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 615 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { 616 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); 617 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 618 } 619 #else 620 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ 621 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 622 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 623 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 624 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 625 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 626 save->crtc_enabled[i] = false; 627 /* ***** */ 628 #endif 629 } else { 630 save->crtc_enabled[i] = false; 631 } 632 } 633 } 634 635 static void dce_v10_0_resume_mc_access(struct amdgpu_device *adev, 636 struct amdgpu_mode_mc_save *save) 637 { 638 u32 tmp, frame_count; 639 int i, j; 640 641 /* update crtc base addresses */ 642 for (i = 0; i < adev->mode_info.num_crtc; i++) { 643 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 644 upper_32_bits(adev->mc.vram_start)); 645 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], 646 upper_32_bits(adev->mc.vram_start)); 647 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], 648 (u32)adev->mc.vram_start); 649 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 650 (u32)adev->mc.vram_start); 651 652 if (save->crtc_enabled[i]) { 653 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); 654 if (REG_GET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 0) { 655 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 0); 656 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); 657 } 658 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 659 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { 660 tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); 661 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); 662 } 663 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]); 664 if (REG_GET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { 665 tmp = REG_SET_FIELD(tmp, MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); 666 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp); 667 } 668 for (j = 0; j < adev->usec_timeout; j++) { 669 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); 670 if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) 671 break; 672 udelay(1); 673 } 674 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); 675 tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); 676 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 677 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 678 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 679 /* wait for the next frame */ 680 frame_count = amdgpu_display_vblank_get_counter(adev, i); 681 for (j = 0; j < adev->usec_timeout; j++) { 682 if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) 683 break; 684 udelay(1); 685 } 686 } 687 } 688 689 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); 690 WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); 691 692 /* Unlock vga access */ 693 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); 694 mdelay(1); 695 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); 696 } 697 698 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, 699 bool render) 700 { 701 u32 tmp; 702 703 /* Lockout access through VGA aperture*/ 704 tmp = RREG32(mmVGA_HDP_CONTROL); 705 if (render) 706 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 707 else 708 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 709 WREG32(mmVGA_HDP_CONTROL, tmp); 710 711 /* disable VGA render */ 712 tmp = RREG32(mmVGA_RENDER_CONTROL); 713 if (render) 714 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 715 else 716 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 717 WREG32(mmVGA_RENDER_CONTROL, tmp); 718 } 719 720 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev) 721 { 722 int num_crtc = 0; 723 724 switch (adev->asic_type) { 725 case CHIP_FIJI: 726 case CHIP_TONGA: 727 num_crtc = 6; 728 break; 729 default: 730 num_crtc = 0; 731 } 732 return num_crtc; 733 } 734 735 void dce_v10_0_disable_dce(struct amdgpu_device *adev) 736 { 737 /*Disable VGA render and enabled crtc, if has DCE engine*/ 738 if (amdgpu_atombios_has_dce_engine_info(adev)) { 739 u32 tmp; 740 int crtc_enabled, i; 741 742 dce_v10_0_set_vga_render_state(adev, false); 743 744 /*Disable crtc*/ 745 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) { 746 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 747 CRTC_CONTROL, CRTC_MASTER_EN); 748 if (crtc_enabled) { 749 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 750 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 751 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 752 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 753 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 754 } 755 } 756 } 757 } 758 759 static void dce_v10_0_program_fmt(struct drm_encoder *encoder) 760 { 761 struct drm_device *dev = encoder->dev; 762 struct amdgpu_device *adev = dev->dev_private; 763 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 764 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 765 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 766 int bpc = 0; 767 u32 tmp = 0; 768 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 769 770 if (connector) { 771 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 772 bpc = amdgpu_connector_get_monitor_bpc(connector); 773 dither = amdgpu_connector->dither; 774 } 775 776 /* LVDS/eDP FMT is set up by atom */ 777 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 778 return; 779 780 /* not needed for analog */ 781 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 782 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 783 return; 784 785 if (bpc == 0) 786 return; 787 788 switch (bpc) { 789 case 6: 790 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 791 /* XXX sort out optimal dither settings */ 792 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 793 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 794 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 795 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 796 } else { 797 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 798 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 799 } 800 break; 801 case 8: 802 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 803 /* XXX sort out optimal dither settings */ 804 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 805 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 806 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 807 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 808 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 809 } else { 810 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 811 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 812 } 813 break; 814 case 10: 815 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 816 /* XXX sort out optimal dither settings */ 817 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 818 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 819 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 820 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 821 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 822 } else { 823 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 824 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 825 } 826 break; 827 default: 828 /* not needed */ 829 break; 830 } 831 832 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 833 } 834 835 836 /* display watermark setup */ 837 /** 838 * dce_v10_0_line_buffer_adjust - Set up the line buffer 839 * 840 * @adev: amdgpu_device pointer 841 * @amdgpu_crtc: the selected display controller 842 * @mode: the current display mode on the selected display 843 * controller 844 * 845 * Setup up the line buffer allocation for 846 * the selected display controller (CIK). 847 * Returns the line buffer size in pixels. 848 */ 849 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, 850 struct amdgpu_crtc *amdgpu_crtc, 851 struct drm_display_mode *mode) 852 { 853 u32 tmp, buffer_alloc, i, mem_cfg; 854 u32 pipe_offset = amdgpu_crtc->crtc_id; 855 /* 856 * Line Buffer Setup 857 * There are 6 line buffers, one for each display controllers. 858 * There are 3 partitions per LB. Select the number of partitions 859 * to enable based on the display width. For display widths larger 860 * than 4096, you need use to use 2 display controllers and combine 861 * them using the stereo blender. 862 */ 863 if (amdgpu_crtc->base.enabled && mode) { 864 if (mode->crtc_hdisplay < 1920) { 865 mem_cfg = 1; 866 buffer_alloc = 2; 867 } else if (mode->crtc_hdisplay < 2560) { 868 mem_cfg = 2; 869 buffer_alloc = 2; 870 } else if (mode->crtc_hdisplay < 4096) { 871 mem_cfg = 0; 872 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 873 } else { 874 DRM_DEBUG_KMS("Mode too big for LB!\n"); 875 mem_cfg = 0; 876 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 877 } 878 } else { 879 mem_cfg = 1; 880 buffer_alloc = 0; 881 } 882 883 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 884 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 885 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 886 887 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 888 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 889 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 890 891 for (i = 0; i < adev->usec_timeout; i++) { 892 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 893 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 894 break; 895 udelay(1); 896 } 897 898 if (amdgpu_crtc->base.enabled && mode) { 899 switch (mem_cfg) { 900 case 0: 901 default: 902 return 4096 * 2; 903 case 1: 904 return 1920 * 2; 905 case 2: 906 return 2560 * 2; 907 } 908 } 909 910 /* controller not enabled, so no lb used */ 911 return 0; 912 } 913 914 /** 915 * cik_get_number_of_dram_channels - get the number of dram channels 916 * 917 * @adev: amdgpu_device pointer 918 * 919 * Look up the number of video ram channels (CIK). 920 * Used for display watermark bandwidth calculations 921 * Returns the number of dram channels 922 */ 923 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 924 { 925 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 926 927 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 928 case 0: 929 default: 930 return 1; 931 case 1: 932 return 2; 933 case 2: 934 return 4; 935 case 3: 936 return 8; 937 case 4: 938 return 3; 939 case 5: 940 return 6; 941 case 6: 942 return 10; 943 case 7: 944 return 12; 945 case 8: 946 return 16; 947 } 948 } 949 950 struct dce10_wm_params { 951 u32 dram_channels; /* number of dram channels */ 952 u32 yclk; /* bandwidth per dram data pin in kHz */ 953 u32 sclk; /* engine clock in kHz */ 954 u32 disp_clk; /* display clock in kHz */ 955 u32 src_width; /* viewport width */ 956 u32 active_time; /* active display time in ns */ 957 u32 blank_time; /* blank time in ns */ 958 bool interlaced; /* mode is interlaced */ 959 fixed20_12 vsc; /* vertical scale ratio */ 960 u32 num_heads; /* number of active crtcs */ 961 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 962 u32 lb_size; /* line buffer allocated to pipe */ 963 u32 vtaps; /* vertical scaler taps */ 964 }; 965 966 /** 967 * dce_v10_0_dram_bandwidth - get the dram bandwidth 968 * 969 * @wm: watermark calculation data 970 * 971 * Calculate the raw dram bandwidth (CIK). 972 * Used for display watermark bandwidth calculations 973 * Returns the dram bandwidth in MBytes/s 974 */ 975 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) 976 { 977 /* Calculate raw DRAM Bandwidth */ 978 fixed20_12 dram_efficiency; /* 0.7 */ 979 fixed20_12 yclk, dram_channels, bandwidth; 980 fixed20_12 a; 981 982 a.full = dfixed_const(1000); 983 yclk.full = dfixed_const(wm->yclk); 984 yclk.full = dfixed_div(yclk, a); 985 dram_channels.full = dfixed_const(wm->dram_channels * 4); 986 a.full = dfixed_const(10); 987 dram_efficiency.full = dfixed_const(7); 988 dram_efficiency.full = dfixed_div(dram_efficiency, a); 989 bandwidth.full = dfixed_mul(dram_channels, yclk); 990 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 991 992 return dfixed_trunc(bandwidth); 993 } 994 995 /** 996 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display 997 * 998 * @wm: watermark calculation data 999 * 1000 * Calculate the dram bandwidth used for display (CIK). 1001 * Used for display watermark bandwidth calculations 1002 * Returns the dram bandwidth for display in MBytes/s 1003 */ 1004 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1005 { 1006 /* Calculate DRAM Bandwidth and the part allocated to display. */ 1007 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 1008 fixed20_12 yclk, dram_channels, bandwidth; 1009 fixed20_12 a; 1010 1011 a.full = dfixed_const(1000); 1012 yclk.full = dfixed_const(wm->yclk); 1013 yclk.full = dfixed_div(yclk, a); 1014 dram_channels.full = dfixed_const(wm->dram_channels * 4); 1015 a.full = dfixed_const(10); 1016 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 1017 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 1018 bandwidth.full = dfixed_mul(dram_channels, yclk); 1019 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 1020 1021 return dfixed_trunc(bandwidth); 1022 } 1023 1024 /** 1025 * dce_v10_0_data_return_bandwidth - get the data return bandwidth 1026 * 1027 * @wm: watermark calculation data 1028 * 1029 * Calculate the data return bandwidth used for display (CIK). 1030 * Used for display watermark bandwidth calculations 1031 * Returns the data return bandwidth in MBytes/s 1032 */ 1033 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) 1034 { 1035 /* Calculate the display Data return Bandwidth */ 1036 fixed20_12 return_efficiency; /* 0.8 */ 1037 fixed20_12 sclk, bandwidth; 1038 fixed20_12 a; 1039 1040 a.full = dfixed_const(1000); 1041 sclk.full = dfixed_const(wm->sclk); 1042 sclk.full = dfixed_div(sclk, a); 1043 a.full = dfixed_const(10); 1044 return_efficiency.full = dfixed_const(8); 1045 return_efficiency.full = dfixed_div(return_efficiency, a); 1046 a.full = dfixed_const(32); 1047 bandwidth.full = dfixed_mul(a, sclk); 1048 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 1049 1050 return dfixed_trunc(bandwidth); 1051 } 1052 1053 /** 1054 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth 1055 * 1056 * @wm: watermark calculation data 1057 * 1058 * Calculate the dmif bandwidth used for display (CIK). 1059 * Used for display watermark bandwidth calculations 1060 * Returns the dmif bandwidth in MBytes/s 1061 */ 1062 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 1063 { 1064 /* Calculate the DMIF Request Bandwidth */ 1065 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 1066 fixed20_12 disp_clk, bandwidth; 1067 fixed20_12 a, b; 1068 1069 a.full = dfixed_const(1000); 1070 disp_clk.full = dfixed_const(wm->disp_clk); 1071 disp_clk.full = dfixed_div(disp_clk, a); 1072 a.full = dfixed_const(32); 1073 b.full = dfixed_mul(a, disp_clk); 1074 1075 a.full = dfixed_const(10); 1076 disp_clk_request_efficiency.full = dfixed_const(8); 1077 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 1078 1079 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 1080 1081 return dfixed_trunc(bandwidth); 1082 } 1083 1084 /** 1085 * dce_v10_0_available_bandwidth - get the min available bandwidth 1086 * 1087 * @wm: watermark calculation data 1088 * 1089 * Calculate the min available bandwidth used for display (CIK). 1090 * Used for display watermark bandwidth calculations 1091 * Returns the min available bandwidth in MBytes/s 1092 */ 1093 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) 1094 { 1095 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 1096 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); 1097 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); 1098 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); 1099 1100 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 1101 } 1102 1103 /** 1104 * dce_v10_0_average_bandwidth - get the average available bandwidth 1105 * 1106 * @wm: watermark calculation data 1107 * 1108 * Calculate the average available bandwidth used for display (CIK). 1109 * Used for display watermark bandwidth calculations 1110 * Returns the average available bandwidth in MBytes/s 1111 */ 1112 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) 1113 { 1114 /* Calculate the display mode Average Bandwidth 1115 * DisplayMode should contain the source and destination dimensions, 1116 * timing, etc. 1117 */ 1118 fixed20_12 bpp; 1119 fixed20_12 line_time; 1120 fixed20_12 src_width; 1121 fixed20_12 bandwidth; 1122 fixed20_12 a; 1123 1124 a.full = dfixed_const(1000); 1125 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 1126 line_time.full = dfixed_div(line_time, a); 1127 bpp.full = dfixed_const(wm->bytes_per_pixel); 1128 src_width.full = dfixed_const(wm->src_width); 1129 bandwidth.full = dfixed_mul(src_width, bpp); 1130 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 1131 bandwidth.full = dfixed_div(bandwidth, line_time); 1132 1133 return dfixed_trunc(bandwidth); 1134 } 1135 1136 /** 1137 * dce_v10_0_latency_watermark - get the latency watermark 1138 * 1139 * @wm: watermark calculation data 1140 * 1141 * Calculate the latency watermark (CIK). 1142 * Used for display watermark bandwidth calculations 1143 * Returns the latency watermark in ns 1144 */ 1145 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) 1146 { 1147 /* First calculate the latency in ns */ 1148 u32 mc_latency = 2000; /* 2000 ns. */ 1149 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); 1150 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 1151 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 1152 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 1153 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 1154 (wm->num_heads * cursor_line_pair_return_time); 1155 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 1156 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 1157 u32 tmp, dmif_size = 12288; 1158 fixed20_12 a, b, c; 1159 1160 if (wm->num_heads == 0) 1161 return 0; 1162 1163 a.full = dfixed_const(2); 1164 b.full = dfixed_const(1); 1165 if ((wm->vsc.full > a.full) || 1166 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 1167 (wm->vtaps >= 5) || 1168 ((wm->vsc.full >= a.full) && wm->interlaced)) 1169 max_src_lines_per_dst_line = 4; 1170 else 1171 max_src_lines_per_dst_line = 2; 1172 1173 a.full = dfixed_const(available_bandwidth); 1174 b.full = dfixed_const(wm->num_heads); 1175 a.full = dfixed_div(a, b); 1176 1177 b.full = dfixed_const(mc_latency + 512); 1178 c.full = dfixed_const(wm->disp_clk); 1179 b.full = dfixed_div(b, c); 1180 1181 c.full = dfixed_const(dmif_size); 1182 b.full = dfixed_div(c, b); 1183 1184 tmp = min(dfixed_trunc(a), dfixed_trunc(b)); 1185 1186 b.full = dfixed_const(1000); 1187 c.full = dfixed_const(wm->disp_clk); 1188 b.full = dfixed_div(c, b); 1189 c.full = dfixed_const(wm->bytes_per_pixel); 1190 b.full = dfixed_mul(b, c); 1191 1192 lb_fill_bw = min(tmp, dfixed_trunc(b)); 1193 1194 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 1195 b.full = dfixed_const(1000); 1196 c.full = dfixed_const(lb_fill_bw); 1197 b.full = dfixed_div(c, b); 1198 a.full = dfixed_div(a, b); 1199 line_fill_time = dfixed_trunc(a); 1200 1201 if (line_fill_time < wm->active_time) 1202 return latency; 1203 else 1204 return latency + (line_fill_time - wm->active_time); 1205 1206 } 1207 1208 /** 1209 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check 1210 * average and available dram bandwidth 1211 * 1212 * @wm: watermark calculation data 1213 * 1214 * Check if the display average bandwidth fits in the display 1215 * dram bandwidth (CIK). 1216 * Used for display watermark bandwidth calculations 1217 * Returns true if the display fits, false if not. 1218 */ 1219 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 1220 { 1221 if (dce_v10_0_average_bandwidth(wm) <= 1222 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 1223 return true; 1224 else 1225 return false; 1226 } 1227 1228 /** 1229 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check 1230 * average and available bandwidth 1231 * 1232 * @wm: watermark calculation data 1233 * 1234 * Check if the display average bandwidth fits in the display 1235 * available bandwidth (CIK). 1236 * Used for display watermark bandwidth calculations 1237 * Returns true if the display fits, false if not. 1238 */ 1239 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 1240 { 1241 if (dce_v10_0_average_bandwidth(wm) <= 1242 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) 1243 return true; 1244 else 1245 return false; 1246 } 1247 1248 /** 1249 * dce_v10_0_check_latency_hiding - check latency hiding 1250 * 1251 * @wm: watermark calculation data 1252 * 1253 * Check latency hiding (CIK). 1254 * Used for display watermark bandwidth calculations 1255 * Returns true if the display fits, false if not. 1256 */ 1257 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) 1258 { 1259 u32 lb_partitions = wm->lb_size / wm->src_width; 1260 u32 line_time = wm->active_time + wm->blank_time; 1261 u32 latency_tolerant_lines; 1262 u32 latency_hiding; 1263 fixed20_12 a; 1264 1265 a.full = dfixed_const(1); 1266 if (wm->vsc.full > a.full) 1267 latency_tolerant_lines = 1; 1268 else { 1269 if (lb_partitions <= (wm->vtaps + 1)) 1270 latency_tolerant_lines = 1; 1271 else 1272 latency_tolerant_lines = 2; 1273 } 1274 1275 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 1276 1277 if (dce_v10_0_latency_watermark(wm) <= latency_hiding) 1278 return true; 1279 else 1280 return false; 1281 } 1282 1283 /** 1284 * dce_v10_0_program_watermarks - program display watermarks 1285 * 1286 * @adev: amdgpu_device pointer 1287 * @amdgpu_crtc: the selected display controller 1288 * @lb_size: line buffer size 1289 * @num_heads: number of display controllers in use 1290 * 1291 * Calculate and program the display watermarks for the 1292 * selected display controller (CIK). 1293 */ 1294 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, 1295 struct amdgpu_crtc *amdgpu_crtc, 1296 u32 lb_size, u32 num_heads) 1297 { 1298 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1299 struct dce10_wm_params wm_low, wm_high; 1300 u32 pixel_period; 1301 u32 line_time = 0; 1302 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1303 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1304 1305 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1306 pixel_period = 1000000 / (u32)mode->clock; 1307 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); 1308 1309 /* watermark for high clocks */ 1310 if (adev->pm.dpm_enabled) { 1311 wm_high.yclk = 1312 amdgpu_dpm_get_mclk(adev, false) * 10; 1313 wm_high.sclk = 1314 amdgpu_dpm_get_sclk(adev, false) * 10; 1315 } else { 1316 wm_high.yclk = adev->pm.current_mclk * 10; 1317 wm_high.sclk = adev->pm.current_sclk * 10; 1318 } 1319 1320 wm_high.disp_clk = mode->clock; 1321 wm_high.src_width = mode->crtc_hdisplay; 1322 wm_high.active_time = mode->crtc_hdisplay * pixel_period; 1323 wm_high.blank_time = line_time - wm_high.active_time; 1324 wm_high.interlaced = false; 1325 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1326 wm_high.interlaced = true; 1327 wm_high.vsc = amdgpu_crtc->vsc; 1328 wm_high.vtaps = 1; 1329 if (amdgpu_crtc->rmx_type != RMX_OFF) 1330 wm_high.vtaps = 2; 1331 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1332 wm_high.lb_size = lb_size; 1333 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1334 wm_high.num_heads = num_heads; 1335 1336 /* set for high clocks */ 1337 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); 1338 1339 /* possibly force display priority to high */ 1340 /* should really do this at mode validation time... */ 1341 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1342 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1343 !dce_v10_0_check_latency_hiding(&wm_high) || 1344 (adev->mode_info.disp_priority == 2)) { 1345 DRM_DEBUG_KMS("force priority to high\n"); 1346 } 1347 1348 /* watermark for low clocks */ 1349 if (adev->pm.dpm_enabled) { 1350 wm_low.yclk = 1351 amdgpu_dpm_get_mclk(adev, true) * 10; 1352 wm_low.sclk = 1353 amdgpu_dpm_get_sclk(adev, true) * 10; 1354 } else { 1355 wm_low.yclk = adev->pm.current_mclk * 10; 1356 wm_low.sclk = adev->pm.current_sclk * 10; 1357 } 1358 1359 wm_low.disp_clk = mode->clock; 1360 wm_low.src_width = mode->crtc_hdisplay; 1361 wm_low.active_time = mode->crtc_hdisplay * pixel_period; 1362 wm_low.blank_time = line_time - wm_low.active_time; 1363 wm_low.interlaced = false; 1364 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1365 wm_low.interlaced = true; 1366 wm_low.vsc = amdgpu_crtc->vsc; 1367 wm_low.vtaps = 1; 1368 if (amdgpu_crtc->rmx_type != RMX_OFF) 1369 wm_low.vtaps = 2; 1370 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1371 wm_low.lb_size = lb_size; 1372 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1373 wm_low.num_heads = num_heads; 1374 1375 /* set for low clocks */ 1376 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); 1377 1378 /* possibly force display priority to high */ 1379 /* should really do this at mode validation time... */ 1380 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1381 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1382 !dce_v10_0_check_latency_hiding(&wm_low) || 1383 (adev->mode_info.disp_priority == 2)) { 1384 DRM_DEBUG_KMS("force priority to high\n"); 1385 } 1386 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1387 } 1388 1389 /* select wm A */ 1390 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1391 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1392 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1393 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1394 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1395 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1396 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1397 /* select wm B */ 1398 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1399 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1400 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1401 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1402 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1403 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1404 /* restore original selection */ 1405 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1406 1407 /* save values for DPM */ 1408 amdgpu_crtc->line_time = line_time; 1409 amdgpu_crtc->wm_high = latency_watermark_a; 1410 amdgpu_crtc->wm_low = latency_watermark_b; 1411 /* Save number of lines the linebuffer leads before the scanout */ 1412 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1413 } 1414 1415 /** 1416 * dce_v10_0_bandwidth_update - program display watermarks 1417 * 1418 * @adev: amdgpu_device pointer 1419 * 1420 * Calculate and program the display watermarks and line 1421 * buffer allocation (CIK). 1422 */ 1423 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) 1424 { 1425 struct drm_display_mode *mode = NULL; 1426 u32 num_heads = 0, lb_size; 1427 int i; 1428 1429 amdgpu_update_display_priority(adev); 1430 1431 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1432 if (adev->mode_info.crtcs[i]->base.enabled) 1433 num_heads++; 1434 } 1435 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1436 mode = &adev->mode_info.crtcs[i]->base.mode; 1437 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1438 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1439 lb_size, num_heads); 1440 } 1441 } 1442 1443 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) 1444 { 1445 int i; 1446 u32 offset, tmp; 1447 1448 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1449 offset = adev->mode_info.audio.pin[i].offset; 1450 tmp = RREG32_AUDIO_ENDPT(offset, 1451 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1452 if (((tmp & 1453 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1454 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1455 adev->mode_info.audio.pin[i].connected = false; 1456 else 1457 adev->mode_info.audio.pin[i].connected = true; 1458 } 1459 } 1460 1461 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) 1462 { 1463 int i; 1464 1465 dce_v10_0_audio_get_connected_pins(adev); 1466 1467 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1468 if (adev->mode_info.audio.pin[i].connected) 1469 return &adev->mode_info.audio.pin[i]; 1470 } 1471 DRM_ERROR("No connected audio pins found!\n"); 1472 return NULL; 1473 } 1474 1475 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1476 { 1477 struct amdgpu_device *adev = encoder->dev->dev_private; 1478 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1479 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1480 u32 tmp; 1481 1482 if (!dig || !dig->afmt || !dig->afmt->pin) 1483 return; 1484 1485 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1486 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1487 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1488 } 1489 1490 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, 1491 struct drm_display_mode *mode) 1492 { 1493 struct amdgpu_device *adev = encoder->dev->dev_private; 1494 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1495 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1496 struct drm_connector *connector; 1497 struct amdgpu_connector *amdgpu_connector = NULL; 1498 u32 tmp; 1499 int interlace = 0; 1500 1501 if (!dig || !dig->afmt || !dig->afmt->pin) 1502 return; 1503 1504 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1505 if (connector->encoder == encoder) { 1506 amdgpu_connector = to_amdgpu_connector(connector); 1507 break; 1508 } 1509 } 1510 1511 if (!amdgpu_connector) { 1512 DRM_ERROR("Couldn't find encoder's connector\n"); 1513 return; 1514 } 1515 1516 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1517 interlace = 1; 1518 if (connector->latency_present[interlace]) { 1519 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1520 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1521 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1522 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1523 } else { 1524 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1525 VIDEO_LIPSYNC, 0); 1526 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1527 AUDIO_LIPSYNC, 0); 1528 } 1529 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1530 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1531 } 1532 1533 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1534 { 1535 struct amdgpu_device *adev = encoder->dev->dev_private; 1536 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1537 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1538 struct drm_connector *connector; 1539 struct amdgpu_connector *amdgpu_connector = NULL; 1540 u32 tmp; 1541 u8 *sadb = NULL; 1542 int sad_count; 1543 1544 if (!dig || !dig->afmt || !dig->afmt->pin) 1545 return; 1546 1547 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1548 if (connector->encoder == encoder) { 1549 amdgpu_connector = to_amdgpu_connector(connector); 1550 break; 1551 } 1552 } 1553 1554 if (!amdgpu_connector) { 1555 DRM_ERROR("Couldn't find encoder's connector\n"); 1556 return; 1557 } 1558 1559 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1560 if (sad_count < 0) { 1561 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1562 sad_count = 0; 1563 } 1564 1565 /* program the speaker allocation */ 1566 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1567 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1568 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1569 DP_CONNECTION, 0); 1570 /* set HDMI mode */ 1571 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1572 HDMI_CONNECTION, 1); 1573 if (sad_count) 1574 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1575 SPEAKER_ALLOCATION, sadb[0]); 1576 else 1577 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1578 SPEAKER_ALLOCATION, 5); /* stereo */ 1579 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1580 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1581 1582 kfree(sadb); 1583 } 1584 1585 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) 1586 { 1587 struct amdgpu_device *adev = encoder->dev->dev_private; 1588 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1589 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1590 struct drm_connector *connector; 1591 struct amdgpu_connector *amdgpu_connector = NULL; 1592 struct cea_sad *sads; 1593 int i, sad_count; 1594 1595 static const u16 eld_reg_to_type[][2] = { 1596 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1597 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1598 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1599 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1600 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1601 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1602 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1603 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1604 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1605 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1606 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1607 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1608 }; 1609 1610 if (!dig || !dig->afmt || !dig->afmt->pin) 1611 return; 1612 1613 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1614 if (connector->encoder == encoder) { 1615 amdgpu_connector = to_amdgpu_connector(connector); 1616 break; 1617 } 1618 } 1619 1620 if (!amdgpu_connector) { 1621 DRM_ERROR("Couldn't find encoder's connector\n"); 1622 return; 1623 } 1624 1625 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1626 if (sad_count <= 0) { 1627 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1628 return; 1629 } 1630 BUG_ON(!sads); 1631 1632 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1633 u32 tmp = 0; 1634 u8 stereo_freqs = 0; 1635 int max_channels = -1; 1636 int j; 1637 1638 for (j = 0; j < sad_count; j++) { 1639 struct cea_sad *sad = &sads[j]; 1640 1641 if (sad->format == eld_reg_to_type[i][1]) { 1642 if (sad->channels > max_channels) { 1643 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1644 MAX_CHANNELS, sad->channels); 1645 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1646 DESCRIPTOR_BYTE_2, sad->byte2); 1647 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1648 SUPPORTED_FREQUENCIES, sad->freq); 1649 max_channels = sad->channels; 1650 } 1651 1652 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1653 stereo_freqs |= sad->freq; 1654 else 1655 break; 1656 } 1657 } 1658 1659 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1660 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1661 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1662 } 1663 1664 kfree(sads); 1665 } 1666 1667 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 1668 struct amdgpu_audio_pin *pin, 1669 bool enable) 1670 { 1671 if (!pin) 1672 return; 1673 1674 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1675 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1676 } 1677 1678 static const u32 pin_offsets[] = 1679 { 1680 AUD0_REGISTER_OFFSET, 1681 AUD1_REGISTER_OFFSET, 1682 AUD2_REGISTER_OFFSET, 1683 AUD3_REGISTER_OFFSET, 1684 AUD4_REGISTER_OFFSET, 1685 AUD5_REGISTER_OFFSET, 1686 AUD6_REGISTER_OFFSET, 1687 }; 1688 1689 static int dce_v10_0_audio_init(struct amdgpu_device *adev) 1690 { 1691 int i; 1692 1693 if (!amdgpu_audio) 1694 return 0; 1695 1696 adev->mode_info.audio.enabled = true; 1697 1698 adev->mode_info.audio.num_pins = 7; 1699 1700 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1701 adev->mode_info.audio.pin[i].channels = -1; 1702 adev->mode_info.audio.pin[i].rate = -1; 1703 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1704 adev->mode_info.audio.pin[i].status_bits = 0; 1705 adev->mode_info.audio.pin[i].category_code = 0; 1706 adev->mode_info.audio.pin[i].connected = false; 1707 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1708 adev->mode_info.audio.pin[i].id = i; 1709 /* disable audio. it will be set up later */ 1710 /* XXX remove once we switch to ip funcs */ 1711 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1712 } 1713 1714 return 0; 1715 } 1716 1717 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1718 { 1719 int i; 1720 1721 if (!amdgpu_audio) 1722 return; 1723 1724 if (!adev->mode_info.audio.enabled) 1725 return; 1726 1727 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1728 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1729 1730 adev->mode_info.audio.enabled = false; 1731 } 1732 1733 /* 1734 * update the N and CTS parameters for a given pixel clock rate 1735 */ 1736 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1737 { 1738 struct drm_device *dev = encoder->dev; 1739 struct amdgpu_device *adev = dev->dev_private; 1740 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1741 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1742 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1743 u32 tmp; 1744 1745 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1746 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1747 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1748 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1749 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1750 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1751 1752 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1753 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1754 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1755 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1756 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1757 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1758 1759 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1760 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1761 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1762 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1763 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1764 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1765 1766 } 1767 1768 /* 1769 * build a HDMI Video Info Frame 1770 */ 1771 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1772 void *buffer, size_t size) 1773 { 1774 struct drm_device *dev = encoder->dev; 1775 struct amdgpu_device *adev = dev->dev_private; 1776 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1777 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1778 uint8_t *frame = buffer + 3; 1779 uint8_t *header = buffer; 1780 1781 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1782 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1783 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1784 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1785 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1786 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1787 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1788 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1789 } 1790 1791 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1792 { 1793 struct drm_device *dev = encoder->dev; 1794 struct amdgpu_device *adev = dev->dev_private; 1795 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1796 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1797 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1798 u32 dto_phase = 24 * 1000; 1799 u32 dto_modulo = clock; 1800 u32 tmp; 1801 1802 if (!dig || !dig->afmt) 1803 return; 1804 1805 /* XXX two dtos; generally use dto0 for hdmi */ 1806 /* Express [24MHz / target pixel clock] as an exact rational 1807 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1808 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1809 */ 1810 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1811 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1812 amdgpu_crtc->crtc_id); 1813 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1814 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1815 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1816 } 1817 1818 /* 1819 * update the info frames with the data from the current display mode 1820 */ 1821 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, 1822 struct drm_display_mode *mode) 1823 { 1824 struct drm_device *dev = encoder->dev; 1825 struct amdgpu_device *adev = dev->dev_private; 1826 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1827 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1828 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1829 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1830 struct hdmi_avi_infoframe frame; 1831 ssize_t err; 1832 u32 tmp; 1833 int bpc = 8; 1834 1835 if (!dig || !dig->afmt) 1836 return; 1837 1838 /* Silent, r600_hdmi_enable will raise WARN for us */ 1839 if (!dig->afmt->enabled) 1840 return; 1841 1842 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1843 if (encoder->crtc) { 1844 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1845 bpc = amdgpu_crtc->bpc; 1846 } 1847 1848 /* disable audio prior to setting up hw */ 1849 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); 1850 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1851 1852 dce_v10_0_audio_set_dto(encoder, mode->clock); 1853 1854 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1855 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1856 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1857 1858 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1859 1860 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1861 switch (bpc) { 1862 case 0: 1863 case 6: 1864 case 8: 1865 case 16: 1866 default: 1867 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1868 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1869 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1870 connector->name, bpc); 1871 break; 1872 case 10: 1873 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1874 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1875 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1876 connector->name); 1877 break; 1878 case 12: 1879 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1880 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1881 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1882 connector->name); 1883 break; 1884 } 1885 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1886 1887 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1888 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1889 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1890 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1891 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1892 1893 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1894 /* enable audio info frames (frames won't be set until audio is enabled) */ 1895 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1896 /* required for audio info values to be updated */ 1897 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1898 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1899 1900 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1901 /* required for audio info values to be updated */ 1902 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1903 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1904 1905 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1906 /* anything other than 0 */ 1907 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1908 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1909 1910 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1911 1912 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1913 /* set the default audio delay */ 1914 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1915 /* should be suffient for all audio modes and small enough for all hblanks */ 1916 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1917 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1918 1919 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1920 /* allow 60958 channel status fields to be updated */ 1921 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1922 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1923 1924 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1925 if (bpc > 8) 1926 /* clear SW CTS value */ 1927 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1928 else 1929 /* select SW CTS value */ 1930 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1931 /* allow hw to sent ACR packets when required */ 1932 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1933 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1934 1935 dce_v10_0_afmt_update_ACR(encoder, mode->clock); 1936 1937 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1938 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1939 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1940 1941 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1942 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1943 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1944 1945 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1946 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1947 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1948 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1949 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1950 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1951 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1952 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1953 1954 dce_v10_0_audio_write_speaker_allocation(encoder); 1955 1956 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1957 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1958 1959 dce_v10_0_afmt_audio_select_pin(encoder); 1960 dce_v10_0_audio_write_sad_regs(encoder); 1961 dce_v10_0_audio_write_latency_fields(encoder, mode); 1962 1963 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1964 if (err < 0) { 1965 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1966 return; 1967 } 1968 1969 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1970 if (err < 0) { 1971 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1972 return; 1973 } 1974 1975 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1976 1977 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1978 /* enable AVI info frames */ 1979 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1980 /* required for audio info values to be updated */ 1981 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1982 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1983 1984 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1985 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1986 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1987 1988 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1989 /* send audio packets */ 1990 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1991 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1992 1993 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1994 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1995 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1996 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1997 1998 /* enable audio after to setting up hw */ 1999 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); 2000 } 2001 2002 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) 2003 { 2004 struct drm_device *dev = encoder->dev; 2005 struct amdgpu_device *adev = dev->dev_private; 2006 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2007 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2008 2009 if (!dig || !dig->afmt) 2010 return; 2011 2012 /* Silent, r600_hdmi_enable will raise WARN for us */ 2013 if (enable && dig->afmt->enabled) 2014 return; 2015 if (!enable && !dig->afmt->enabled) 2016 return; 2017 2018 if (!enable && dig->afmt->pin) { 2019 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 2020 dig->afmt->pin = NULL; 2021 } 2022 2023 dig->afmt->enabled = enable; 2024 2025 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 2026 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 2027 } 2028 2029 static int dce_v10_0_afmt_init(struct amdgpu_device *adev) 2030 { 2031 int i; 2032 2033 for (i = 0; i < adev->mode_info.num_dig; i++) 2034 adev->mode_info.afmt[i] = NULL; 2035 2036 /* DCE10 has audio blocks tied to DIG encoders */ 2037 for (i = 0; i < adev->mode_info.num_dig; i++) { 2038 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 2039 if (adev->mode_info.afmt[i]) { 2040 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 2041 adev->mode_info.afmt[i]->id = i; 2042 } else { 2043 int j; 2044 for (j = 0; j < i; j++) { 2045 kfree(adev->mode_info.afmt[j]); 2046 adev->mode_info.afmt[j] = NULL; 2047 } 2048 return -ENOMEM; 2049 } 2050 } 2051 return 0; 2052 } 2053 2054 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 2055 { 2056 int i; 2057 2058 for (i = 0; i < adev->mode_info.num_dig; i++) { 2059 kfree(adev->mode_info.afmt[i]); 2060 adev->mode_info.afmt[i] = NULL; 2061 } 2062 } 2063 2064 static const u32 vga_control_regs[6] = 2065 { 2066 mmD1VGA_CONTROL, 2067 mmD2VGA_CONTROL, 2068 mmD3VGA_CONTROL, 2069 mmD4VGA_CONTROL, 2070 mmD5VGA_CONTROL, 2071 mmD6VGA_CONTROL, 2072 }; 2073 2074 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) 2075 { 2076 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2077 struct drm_device *dev = crtc->dev; 2078 struct amdgpu_device *adev = dev->dev_private; 2079 u32 vga_control; 2080 2081 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 2082 if (enable) 2083 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 2084 else 2085 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 2086 } 2087 2088 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 2089 { 2090 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2091 struct drm_device *dev = crtc->dev; 2092 struct amdgpu_device *adev = dev->dev_private; 2093 2094 if (enable) 2095 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 2096 else 2097 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 2098 } 2099 2100 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 2101 struct drm_framebuffer *fb, 2102 int x, int y, int atomic) 2103 { 2104 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2105 struct drm_device *dev = crtc->dev; 2106 struct amdgpu_device *adev = dev->dev_private; 2107 struct amdgpu_framebuffer *amdgpu_fb; 2108 struct drm_framebuffer *target_fb; 2109 struct drm_gem_object *obj; 2110 struct amdgpu_bo *abo; 2111 uint64_t fb_location, tiling_flags; 2112 uint32_t fb_format, fb_pitch_pixels; 2113 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 2114 u32 pipe_config; 2115 u32 tmp, viewport_w, viewport_h; 2116 int r; 2117 bool bypass_lut = false; 2118 char *format_name; 2119 2120 /* no fb bound */ 2121 if (!atomic && !crtc->primary->fb) { 2122 DRM_DEBUG_KMS("No FB bound\n"); 2123 return 0; 2124 } 2125 2126 if (atomic) { 2127 amdgpu_fb = to_amdgpu_framebuffer(fb); 2128 target_fb = fb; 2129 } else { 2130 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2131 target_fb = crtc->primary->fb; 2132 } 2133 2134 /* If atomic, assume fb object is pinned & idle & fenced and 2135 * just update base pointers 2136 */ 2137 obj = amdgpu_fb->obj; 2138 abo = gem_to_amdgpu_bo(obj); 2139 r = amdgpu_bo_reserve(abo, false); 2140 if (unlikely(r != 0)) 2141 return r; 2142 2143 if (atomic) { 2144 fb_location = amdgpu_bo_gpu_offset(abo); 2145 } else { 2146 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 2147 if (unlikely(r != 0)) { 2148 amdgpu_bo_unreserve(abo); 2149 return -EINVAL; 2150 } 2151 } 2152 2153 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 2154 amdgpu_bo_unreserve(abo); 2155 2156 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2157 2158 switch (target_fb->pixel_format) { 2159 case DRM_FORMAT_C8: 2160 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 2161 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2162 break; 2163 case DRM_FORMAT_XRGB4444: 2164 case DRM_FORMAT_ARGB4444: 2165 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2166 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 2167 #ifdef __BIG_ENDIAN 2168 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2169 ENDIAN_8IN16); 2170 #endif 2171 break; 2172 case DRM_FORMAT_XRGB1555: 2173 case DRM_FORMAT_ARGB1555: 2174 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2175 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2176 #ifdef __BIG_ENDIAN 2177 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2178 ENDIAN_8IN16); 2179 #endif 2180 break; 2181 case DRM_FORMAT_BGRX5551: 2182 case DRM_FORMAT_BGRA5551: 2183 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2184 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 2185 #ifdef __BIG_ENDIAN 2186 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2187 ENDIAN_8IN16); 2188 #endif 2189 break; 2190 case DRM_FORMAT_RGB565: 2191 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 2192 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2193 #ifdef __BIG_ENDIAN 2194 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2195 ENDIAN_8IN16); 2196 #endif 2197 break; 2198 case DRM_FORMAT_XRGB8888: 2199 case DRM_FORMAT_ARGB8888: 2200 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2201 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 2202 #ifdef __BIG_ENDIAN 2203 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2204 ENDIAN_8IN32); 2205 #endif 2206 break; 2207 case DRM_FORMAT_XRGB2101010: 2208 case DRM_FORMAT_ARGB2101010: 2209 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2210 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 2211 #ifdef __BIG_ENDIAN 2212 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2213 ENDIAN_8IN32); 2214 #endif 2215 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2216 bypass_lut = true; 2217 break; 2218 case DRM_FORMAT_BGRX1010102: 2219 case DRM_FORMAT_BGRA1010102: 2220 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 2221 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 2222 #ifdef __BIG_ENDIAN 2223 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 2224 ENDIAN_8IN32); 2225 #endif 2226 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 2227 bypass_lut = true; 2228 break; 2229 default: 2230 format_name = drm_get_format_name(target_fb->pixel_format); 2231 DRM_ERROR("Unsupported screen format %s\n", format_name); 2232 kfree(format_name); 2233 return -EINVAL; 2234 } 2235 2236 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2237 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 2238 2239 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2240 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2241 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2242 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2243 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2244 2245 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 2246 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2247 ARRAY_2D_TILED_THIN1); 2248 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 2249 tile_split); 2250 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 2251 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 2252 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 2253 mtaspect); 2254 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 2255 ADDR_SURF_MICRO_TILING_DISPLAY); 2256 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 2257 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 2258 ARRAY_1D_TILED_THIN1); 2259 } 2260 2261 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 2262 pipe_config); 2263 2264 dce_v10_0_vga_enable(crtc, false); 2265 2266 /* Make sure surface address is updated at vertical blank rather than 2267 * horizontal blank 2268 */ 2269 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 2270 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 2271 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 2272 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2273 2274 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2275 upper_32_bits(fb_location)); 2276 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2277 upper_32_bits(fb_location)); 2278 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2279 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 2280 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2281 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 2282 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 2283 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 2284 2285 /* 2286 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2287 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2288 * retain the full precision throughout the pipeline. 2289 */ 2290 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2291 if (bypass_lut) 2292 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2293 else 2294 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2295 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2296 2297 if (bypass_lut) 2298 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2299 2300 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2301 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2302 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2303 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2304 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2305 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2306 2307 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); 2308 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2309 2310 dce_v10_0_grph_enable(crtc, true); 2311 2312 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2313 target_fb->height); 2314 2315 x &= ~3; 2316 y &= ~1; 2317 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2318 (x << 16) | y); 2319 viewport_w = crtc->mode.hdisplay; 2320 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2321 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2322 (viewport_w << 16) | viewport_h); 2323 2324 /* set pageflip to happen anywhere in vblank interval */ 2325 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2326 2327 if (!atomic && fb && fb != crtc->primary->fb) { 2328 amdgpu_fb = to_amdgpu_framebuffer(fb); 2329 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2330 r = amdgpu_bo_reserve(abo, false); 2331 if (unlikely(r != 0)) 2332 return r; 2333 amdgpu_bo_unpin(abo); 2334 amdgpu_bo_unreserve(abo); 2335 } 2336 2337 /* Bytes per pixel may have changed */ 2338 dce_v10_0_bandwidth_update(adev); 2339 2340 return 0; 2341 } 2342 2343 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, 2344 struct drm_display_mode *mode) 2345 { 2346 struct drm_device *dev = crtc->dev; 2347 struct amdgpu_device *adev = dev->dev_private; 2348 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2349 u32 tmp; 2350 2351 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2352 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2353 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2354 else 2355 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2356 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2357 } 2358 2359 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) 2360 { 2361 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2362 struct drm_device *dev = crtc->dev; 2363 struct amdgpu_device *adev = dev->dev_private; 2364 int i; 2365 u32 tmp; 2366 2367 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2368 2369 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2370 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2371 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); 2372 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2373 2374 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2375 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2376 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2377 2378 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); 2379 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); 2380 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2381 2382 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2383 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2384 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); 2385 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2386 2387 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2388 2389 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2390 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2391 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2392 2393 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2394 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2395 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2396 2397 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2398 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2399 2400 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2401 for (i = 0; i < 256; i++) { 2402 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2403 (amdgpu_crtc->lut_r[i] << 20) | 2404 (amdgpu_crtc->lut_g[i] << 10) | 2405 (amdgpu_crtc->lut_b[i] << 0)); 2406 } 2407 2408 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2409 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2410 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); 2411 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2412 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2413 2414 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2415 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2416 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); 2417 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2418 2419 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2420 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2421 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); 2422 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2423 2424 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2425 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2426 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); 2427 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2428 2429 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2430 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2431 /* XXX this only needs to be programmed once per crtc at startup, 2432 * not sure where the best place for it is 2433 */ 2434 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2435 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2436 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2437 } 2438 2439 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) 2440 { 2441 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2442 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2443 2444 switch (amdgpu_encoder->encoder_id) { 2445 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2446 if (dig->linkb) 2447 return 1; 2448 else 2449 return 0; 2450 break; 2451 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2452 if (dig->linkb) 2453 return 3; 2454 else 2455 return 2; 2456 break; 2457 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2458 if (dig->linkb) 2459 return 5; 2460 else 2461 return 4; 2462 break; 2463 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2464 return 6; 2465 break; 2466 default: 2467 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2468 return 0; 2469 } 2470 } 2471 2472 /** 2473 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. 2474 * 2475 * @crtc: drm crtc 2476 * 2477 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2478 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2479 * monitors a dedicated PPLL must be used. If a particular board has 2480 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2481 * as there is no need to program the PLL itself. If we are not able to 2482 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2483 * avoid messing up an existing monitor. 2484 * 2485 * Asic specific PLL information 2486 * 2487 * DCE 10.x 2488 * Tonga 2489 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2490 * CI 2491 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2492 * 2493 */ 2494 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) 2495 { 2496 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2497 struct drm_device *dev = crtc->dev; 2498 struct amdgpu_device *adev = dev->dev_private; 2499 u32 pll_in_use; 2500 int pll; 2501 2502 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2503 if (adev->clock.dp_extclk) 2504 /* skip PPLL programming if using ext clock */ 2505 return ATOM_PPLL_INVALID; 2506 else { 2507 /* use the same PPLL for all DP monitors */ 2508 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2509 if (pll != ATOM_PPLL_INVALID) 2510 return pll; 2511 } 2512 } else { 2513 /* use the same PPLL for all monitors with the same clock */ 2514 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2515 if (pll != ATOM_PPLL_INVALID) 2516 return pll; 2517 } 2518 2519 /* DCE10 has PPLL0, PPLL1, and PPLL2 */ 2520 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2521 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2522 return ATOM_PPLL2; 2523 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2524 return ATOM_PPLL1; 2525 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2526 return ATOM_PPLL0; 2527 DRM_ERROR("unable to allocate a PPLL\n"); 2528 return ATOM_PPLL_INVALID; 2529 } 2530 2531 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2532 { 2533 struct amdgpu_device *adev = crtc->dev->dev_private; 2534 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2535 uint32_t cur_lock; 2536 2537 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2538 if (lock) 2539 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2540 else 2541 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2542 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2543 } 2544 2545 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 2546 { 2547 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2548 struct amdgpu_device *adev = crtc->dev->dev_private; 2549 u32 tmp; 2550 2551 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2552 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2553 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2554 } 2555 2556 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 2557 { 2558 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2559 struct amdgpu_device *adev = crtc->dev->dev_private; 2560 u32 tmp; 2561 2562 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2563 upper_32_bits(amdgpu_crtc->cursor_addr)); 2564 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2565 lower_32_bits(amdgpu_crtc->cursor_addr)); 2566 2567 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2568 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2569 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2570 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2571 } 2572 2573 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 2574 int x, int y) 2575 { 2576 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2577 struct amdgpu_device *adev = crtc->dev->dev_private; 2578 int xorigin = 0, yorigin = 0; 2579 2580 /* avivo cursor are offset into the total surface */ 2581 x += crtc->x; 2582 y += crtc->y; 2583 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2584 2585 if (x < 0) { 2586 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2587 x = 0; 2588 } 2589 if (y < 0) { 2590 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2591 y = 0; 2592 } 2593 2594 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2595 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2596 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2597 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2598 2599 amdgpu_crtc->cursor_x = x; 2600 amdgpu_crtc->cursor_y = y; 2601 2602 return 0; 2603 } 2604 2605 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, 2606 int x, int y) 2607 { 2608 int ret; 2609 2610 dce_v10_0_lock_cursor(crtc, true); 2611 ret = dce_v10_0_cursor_move_locked(crtc, x, y); 2612 dce_v10_0_lock_cursor(crtc, false); 2613 2614 return ret; 2615 } 2616 2617 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 2618 struct drm_file *file_priv, 2619 uint32_t handle, 2620 uint32_t width, 2621 uint32_t height, 2622 int32_t hot_x, 2623 int32_t hot_y) 2624 { 2625 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2626 struct drm_gem_object *obj; 2627 struct amdgpu_bo *aobj; 2628 int ret; 2629 2630 if (!handle) { 2631 /* turn off cursor */ 2632 dce_v10_0_hide_cursor(crtc); 2633 obj = NULL; 2634 goto unpin; 2635 } 2636 2637 if ((width > amdgpu_crtc->max_cursor_width) || 2638 (height > amdgpu_crtc->max_cursor_height)) { 2639 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2640 return -EINVAL; 2641 } 2642 2643 obj = drm_gem_object_lookup(file_priv, handle); 2644 if (!obj) { 2645 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2646 return -ENOENT; 2647 } 2648 2649 aobj = gem_to_amdgpu_bo(obj); 2650 ret = amdgpu_bo_reserve(aobj, false); 2651 if (ret != 0) { 2652 drm_gem_object_unreference_unlocked(obj); 2653 return ret; 2654 } 2655 2656 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2657 amdgpu_bo_unreserve(aobj); 2658 if (ret) { 2659 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2660 drm_gem_object_unreference_unlocked(obj); 2661 return ret; 2662 } 2663 2664 amdgpu_crtc->cursor_width = width; 2665 amdgpu_crtc->cursor_height = height; 2666 2667 dce_v10_0_lock_cursor(crtc, true); 2668 2669 if (hot_x != amdgpu_crtc->cursor_hot_x || 2670 hot_y != amdgpu_crtc->cursor_hot_y) { 2671 int x, y; 2672 2673 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2674 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2675 2676 dce_v10_0_cursor_move_locked(crtc, x, y); 2677 2678 amdgpu_crtc->cursor_hot_x = hot_x; 2679 amdgpu_crtc->cursor_hot_y = hot_y; 2680 } 2681 2682 dce_v10_0_show_cursor(crtc); 2683 dce_v10_0_lock_cursor(crtc, false); 2684 2685 unpin: 2686 if (amdgpu_crtc->cursor_bo) { 2687 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2688 ret = amdgpu_bo_reserve(aobj, false); 2689 if (likely(ret == 0)) { 2690 amdgpu_bo_unpin(aobj); 2691 amdgpu_bo_unreserve(aobj); 2692 } 2693 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); 2694 } 2695 2696 amdgpu_crtc->cursor_bo = obj; 2697 return 0; 2698 } 2699 2700 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 2701 { 2702 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2703 2704 if (amdgpu_crtc->cursor_bo) { 2705 dce_v10_0_lock_cursor(crtc, true); 2706 2707 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2708 amdgpu_crtc->cursor_y); 2709 2710 dce_v10_0_show_cursor(crtc); 2711 2712 dce_v10_0_lock_cursor(crtc, false); 2713 } 2714 } 2715 2716 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2717 u16 *blue, uint32_t size) 2718 { 2719 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2720 int i; 2721 2722 /* userspace palettes are always correct as is */ 2723 for (i = 0; i < size; i++) { 2724 amdgpu_crtc->lut_r[i] = red[i] >> 6; 2725 amdgpu_crtc->lut_g[i] = green[i] >> 6; 2726 amdgpu_crtc->lut_b[i] = blue[i] >> 6; 2727 } 2728 dce_v10_0_crtc_load_lut(crtc); 2729 2730 return 0; 2731 } 2732 2733 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) 2734 { 2735 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2736 2737 drm_crtc_cleanup(crtc); 2738 kfree(amdgpu_crtc); 2739 } 2740 2741 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { 2742 .cursor_set2 = dce_v10_0_crtc_cursor_set2, 2743 .cursor_move = dce_v10_0_crtc_cursor_move, 2744 .gamma_set = dce_v10_0_crtc_gamma_set, 2745 .set_config = amdgpu_crtc_set_config, 2746 .destroy = dce_v10_0_crtc_destroy, 2747 .page_flip_target = amdgpu_crtc_page_flip_target, 2748 }; 2749 2750 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2751 { 2752 struct drm_device *dev = crtc->dev; 2753 struct amdgpu_device *adev = dev->dev_private; 2754 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2755 unsigned type; 2756 2757 switch (mode) { 2758 case DRM_MODE_DPMS_ON: 2759 amdgpu_crtc->enabled = true; 2760 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2761 dce_v10_0_vga_enable(crtc, true); 2762 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2763 dce_v10_0_vga_enable(crtc, false); 2764 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2765 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id); 2766 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2767 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2768 drm_crtc_vblank_on(crtc); 2769 dce_v10_0_crtc_load_lut(crtc); 2770 break; 2771 case DRM_MODE_DPMS_STANDBY: 2772 case DRM_MODE_DPMS_SUSPEND: 2773 case DRM_MODE_DPMS_OFF: 2774 drm_crtc_vblank_off(crtc); 2775 if (amdgpu_crtc->enabled) { 2776 dce_v10_0_vga_enable(crtc, true); 2777 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2778 dce_v10_0_vga_enable(crtc, false); 2779 } 2780 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2781 amdgpu_crtc->enabled = false; 2782 break; 2783 } 2784 /* adjust pm to dpms */ 2785 amdgpu_pm_compute_clocks(adev); 2786 } 2787 2788 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) 2789 { 2790 /* disable crtc pair power gating before programming */ 2791 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2792 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2793 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2794 } 2795 2796 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) 2797 { 2798 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2799 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2800 } 2801 2802 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) 2803 { 2804 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2805 struct drm_device *dev = crtc->dev; 2806 struct amdgpu_device *adev = dev->dev_private; 2807 struct amdgpu_atom_ss ss; 2808 int i; 2809 2810 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2811 if (crtc->primary->fb) { 2812 int r; 2813 struct amdgpu_framebuffer *amdgpu_fb; 2814 struct amdgpu_bo *abo; 2815 2816 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 2817 abo = gem_to_amdgpu_bo(amdgpu_fb->obj); 2818 r = amdgpu_bo_reserve(abo, false); 2819 if (unlikely(r)) 2820 DRM_ERROR("failed to reserve abo before unpin\n"); 2821 else { 2822 amdgpu_bo_unpin(abo); 2823 amdgpu_bo_unreserve(abo); 2824 } 2825 } 2826 /* disable the GRPH */ 2827 dce_v10_0_grph_enable(crtc, false); 2828 2829 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2830 2831 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2832 if (adev->mode_info.crtcs[i] && 2833 adev->mode_info.crtcs[i]->enabled && 2834 i != amdgpu_crtc->crtc_id && 2835 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2836 /* one other crtc is using this pll don't turn 2837 * off the pll 2838 */ 2839 goto done; 2840 } 2841 } 2842 2843 switch (amdgpu_crtc->pll_id) { 2844 case ATOM_PPLL0: 2845 case ATOM_PPLL1: 2846 case ATOM_PPLL2: 2847 /* disable the ppll */ 2848 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2849 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2850 break; 2851 default: 2852 break; 2853 } 2854 done: 2855 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2856 amdgpu_crtc->adjusted_clock = 0; 2857 amdgpu_crtc->encoder = NULL; 2858 amdgpu_crtc->connector = NULL; 2859 } 2860 2861 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 2862 struct drm_display_mode *mode, 2863 struct drm_display_mode *adjusted_mode, 2864 int x, int y, struct drm_framebuffer *old_fb) 2865 { 2866 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2867 2868 if (!amdgpu_crtc->adjusted_clock) 2869 return -EINVAL; 2870 2871 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2872 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2873 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2874 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2875 amdgpu_atombios_crtc_scaler_setup(crtc); 2876 dce_v10_0_cursor_reset(crtc); 2877 /* update the hw version fpr dpm */ 2878 amdgpu_crtc->hw_mode = *adjusted_mode; 2879 2880 return 0; 2881 } 2882 2883 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 2884 const struct drm_display_mode *mode, 2885 struct drm_display_mode *adjusted_mode) 2886 { 2887 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2888 struct drm_device *dev = crtc->dev; 2889 struct drm_encoder *encoder; 2890 2891 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2892 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2893 if (encoder->crtc == crtc) { 2894 amdgpu_crtc->encoder = encoder; 2895 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2896 break; 2897 } 2898 } 2899 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2900 amdgpu_crtc->encoder = NULL; 2901 amdgpu_crtc->connector = NULL; 2902 return false; 2903 } 2904 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2905 return false; 2906 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2907 return false; 2908 /* pick pll */ 2909 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); 2910 /* if we can't get a PPLL for a non-DP encoder, fail */ 2911 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2912 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2913 return false; 2914 2915 return true; 2916 } 2917 2918 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2919 struct drm_framebuffer *old_fb) 2920 { 2921 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2922 } 2923 2924 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2925 struct drm_framebuffer *fb, 2926 int x, int y, enum mode_set_atomic state) 2927 { 2928 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); 2929 } 2930 2931 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 2932 .dpms = dce_v10_0_crtc_dpms, 2933 .mode_fixup = dce_v10_0_crtc_mode_fixup, 2934 .mode_set = dce_v10_0_crtc_mode_set, 2935 .mode_set_base = dce_v10_0_crtc_set_base, 2936 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, 2937 .prepare = dce_v10_0_crtc_prepare, 2938 .commit = dce_v10_0_crtc_commit, 2939 .load_lut = dce_v10_0_crtc_load_lut, 2940 .disable = dce_v10_0_crtc_disable, 2941 }; 2942 2943 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) 2944 { 2945 struct amdgpu_crtc *amdgpu_crtc; 2946 int i; 2947 2948 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2949 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2950 if (amdgpu_crtc == NULL) 2951 return -ENOMEM; 2952 2953 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); 2954 2955 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2956 amdgpu_crtc->crtc_id = index; 2957 adev->mode_info.crtcs[index] = amdgpu_crtc; 2958 2959 amdgpu_crtc->max_cursor_width = 128; 2960 amdgpu_crtc->max_cursor_height = 128; 2961 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2962 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2963 2964 for (i = 0; i < 256; i++) { 2965 amdgpu_crtc->lut_r[i] = i << 2; 2966 amdgpu_crtc->lut_g[i] = i << 2; 2967 amdgpu_crtc->lut_b[i] = i << 2; 2968 } 2969 2970 switch (amdgpu_crtc->crtc_id) { 2971 case 0: 2972 default: 2973 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2974 break; 2975 case 1: 2976 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2977 break; 2978 case 2: 2979 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2980 break; 2981 case 3: 2982 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2983 break; 2984 case 4: 2985 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2986 break; 2987 case 5: 2988 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2989 break; 2990 } 2991 2992 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2993 amdgpu_crtc->adjusted_clock = 0; 2994 amdgpu_crtc->encoder = NULL; 2995 amdgpu_crtc->connector = NULL; 2996 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); 2997 2998 return 0; 2999 } 3000 3001 static int dce_v10_0_early_init(void *handle) 3002 { 3003 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3004 3005 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 3006 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 3007 3008 dce_v10_0_set_display_funcs(adev); 3009 dce_v10_0_set_irq_funcs(adev); 3010 3011 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); 3012 3013 switch (adev->asic_type) { 3014 case CHIP_FIJI: 3015 case CHIP_TONGA: 3016 adev->mode_info.num_hpd = 6; 3017 adev->mode_info.num_dig = 7; 3018 break; 3019 default: 3020 /* FIXME: not supported yet */ 3021 return -EINVAL; 3022 } 3023 3024 return 0; 3025 } 3026 3027 static int dce_v10_0_sw_init(void *handle) 3028 { 3029 int r, i; 3030 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3031 3032 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3033 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); 3034 if (r) 3035 return r; 3036 } 3037 3038 for (i = 8; i < 20; i += 2) { 3039 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); 3040 if (r) 3041 return r; 3042 } 3043 3044 /* HPD hotplug */ 3045 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); 3046 if (r) 3047 return r; 3048 3049 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 3050 3051 adev->ddev->mode_config.async_page_flip = true; 3052 3053 adev->ddev->mode_config.max_width = 16384; 3054 adev->ddev->mode_config.max_height = 16384; 3055 3056 adev->ddev->mode_config.preferred_depth = 24; 3057 adev->ddev->mode_config.prefer_shadow = 1; 3058 3059 adev->ddev->mode_config.fb_base = adev->mc.aper_base; 3060 3061 r = amdgpu_modeset_create_props(adev); 3062 if (r) 3063 return r; 3064 3065 adev->ddev->mode_config.max_width = 16384; 3066 adev->ddev->mode_config.max_height = 16384; 3067 3068 /* allocate crtcs */ 3069 for (i = 0; i < adev->mode_info.num_crtc; i++) { 3070 r = dce_v10_0_crtc_init(adev, i); 3071 if (r) 3072 return r; 3073 } 3074 3075 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 3076 amdgpu_print_display_setup(adev->ddev); 3077 else 3078 return -EINVAL; 3079 3080 /* setup afmt */ 3081 r = dce_v10_0_afmt_init(adev); 3082 if (r) 3083 return r; 3084 3085 r = dce_v10_0_audio_init(adev); 3086 if (r) 3087 return r; 3088 3089 drm_kms_helper_poll_init(adev->ddev); 3090 3091 adev->mode_info.mode_config_initialized = true; 3092 return 0; 3093 } 3094 3095 static int dce_v10_0_sw_fini(void *handle) 3096 { 3097 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3098 3099 kfree(adev->mode_info.bios_hardcoded_edid); 3100 3101 drm_kms_helper_poll_fini(adev->ddev); 3102 3103 dce_v10_0_audio_fini(adev); 3104 3105 dce_v10_0_afmt_fini(adev); 3106 3107 drm_mode_config_cleanup(adev->ddev); 3108 adev->mode_info.mode_config_initialized = false; 3109 3110 return 0; 3111 } 3112 3113 static int dce_v10_0_hw_init(void *handle) 3114 { 3115 int i; 3116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3117 3118 dce_v10_0_init_golden_registers(adev); 3119 3120 /* init dig PHYs, disp eng pll */ 3121 amdgpu_atombios_encoder_init_dig(adev); 3122 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 3123 3124 /* initialize hpd */ 3125 dce_v10_0_hpd_init(adev); 3126 3127 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3128 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3129 } 3130 3131 dce_v10_0_pageflip_interrupt_init(adev); 3132 3133 return 0; 3134 } 3135 3136 static int dce_v10_0_hw_fini(void *handle) 3137 { 3138 int i; 3139 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3140 3141 dce_v10_0_hpd_fini(adev); 3142 3143 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 3144 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 3145 } 3146 3147 dce_v10_0_pageflip_interrupt_fini(adev); 3148 3149 return 0; 3150 } 3151 3152 static int dce_v10_0_suspend(void *handle) 3153 { 3154 return dce_v10_0_hw_fini(handle); 3155 } 3156 3157 static int dce_v10_0_resume(void *handle) 3158 { 3159 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3160 int ret; 3161 3162 ret = dce_v10_0_hw_init(handle); 3163 3164 /* turn on the BL */ 3165 if (adev->mode_info.bl_encoder) { 3166 u8 bl_level = amdgpu_display_backlight_get_level(adev, 3167 adev->mode_info.bl_encoder); 3168 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 3169 bl_level); 3170 } 3171 3172 return ret; 3173 } 3174 3175 static bool dce_v10_0_is_idle(void *handle) 3176 { 3177 return true; 3178 } 3179 3180 static int dce_v10_0_wait_for_idle(void *handle) 3181 { 3182 return 0; 3183 } 3184 3185 static bool dce_v10_0_check_soft_reset(void *handle) 3186 { 3187 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3188 3189 return dce_v10_0_is_display_hung(adev); 3190 } 3191 3192 static int dce_v10_0_soft_reset(void *handle) 3193 { 3194 u32 srbm_soft_reset = 0, tmp; 3195 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3196 3197 if (dce_v10_0_is_display_hung(adev)) 3198 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3199 3200 if (srbm_soft_reset) { 3201 tmp = RREG32(mmSRBM_SOFT_RESET); 3202 tmp |= srbm_soft_reset; 3203 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3204 WREG32(mmSRBM_SOFT_RESET, tmp); 3205 tmp = RREG32(mmSRBM_SOFT_RESET); 3206 3207 udelay(50); 3208 3209 tmp &= ~srbm_soft_reset; 3210 WREG32(mmSRBM_SOFT_RESET, tmp); 3211 tmp = RREG32(mmSRBM_SOFT_RESET); 3212 3213 /* Wait a little for things to settle down */ 3214 udelay(50); 3215 } 3216 return 0; 3217 } 3218 3219 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 3220 int crtc, 3221 enum amdgpu_interrupt_state state) 3222 { 3223 u32 lb_interrupt_mask; 3224 3225 if (crtc >= adev->mode_info.num_crtc) { 3226 DRM_DEBUG("invalid crtc %d\n", crtc); 3227 return; 3228 } 3229 3230 switch (state) { 3231 case AMDGPU_IRQ_STATE_DISABLE: 3232 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3233 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3234 VBLANK_INTERRUPT_MASK, 0); 3235 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3236 break; 3237 case AMDGPU_IRQ_STATE_ENABLE: 3238 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3239 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3240 VBLANK_INTERRUPT_MASK, 1); 3241 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3242 break; 3243 default: 3244 break; 3245 } 3246 } 3247 3248 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 3249 int crtc, 3250 enum amdgpu_interrupt_state state) 3251 { 3252 u32 lb_interrupt_mask; 3253 3254 if (crtc >= adev->mode_info.num_crtc) { 3255 DRM_DEBUG("invalid crtc %d\n", crtc); 3256 return; 3257 } 3258 3259 switch (state) { 3260 case AMDGPU_IRQ_STATE_DISABLE: 3261 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3262 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3263 VLINE_INTERRUPT_MASK, 0); 3264 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3265 break; 3266 case AMDGPU_IRQ_STATE_ENABLE: 3267 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 3268 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 3269 VLINE_INTERRUPT_MASK, 1); 3270 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 3271 break; 3272 default: 3273 break; 3274 } 3275 } 3276 3277 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, 3278 struct amdgpu_irq_src *source, 3279 unsigned hpd, 3280 enum amdgpu_interrupt_state state) 3281 { 3282 u32 tmp; 3283 3284 if (hpd >= adev->mode_info.num_hpd) { 3285 DRM_DEBUG("invalid hdp %d\n", hpd); 3286 return 0; 3287 } 3288 3289 switch (state) { 3290 case AMDGPU_IRQ_STATE_DISABLE: 3291 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3292 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3293 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3294 break; 3295 case AMDGPU_IRQ_STATE_ENABLE: 3296 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3297 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3298 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3299 break; 3300 default: 3301 break; 3302 } 3303 3304 return 0; 3305 } 3306 3307 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, 3308 struct amdgpu_irq_src *source, 3309 unsigned type, 3310 enum amdgpu_interrupt_state state) 3311 { 3312 switch (type) { 3313 case AMDGPU_CRTC_IRQ_VBLANK1: 3314 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3315 break; 3316 case AMDGPU_CRTC_IRQ_VBLANK2: 3317 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3318 break; 3319 case AMDGPU_CRTC_IRQ_VBLANK3: 3320 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3321 break; 3322 case AMDGPU_CRTC_IRQ_VBLANK4: 3323 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3324 break; 3325 case AMDGPU_CRTC_IRQ_VBLANK5: 3326 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3327 break; 3328 case AMDGPU_CRTC_IRQ_VBLANK6: 3329 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3330 break; 3331 case AMDGPU_CRTC_IRQ_VLINE1: 3332 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); 3333 break; 3334 case AMDGPU_CRTC_IRQ_VLINE2: 3335 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); 3336 break; 3337 case AMDGPU_CRTC_IRQ_VLINE3: 3338 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); 3339 break; 3340 case AMDGPU_CRTC_IRQ_VLINE4: 3341 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); 3342 break; 3343 case AMDGPU_CRTC_IRQ_VLINE5: 3344 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); 3345 break; 3346 case AMDGPU_CRTC_IRQ_VLINE6: 3347 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); 3348 break; 3349 default: 3350 break; 3351 } 3352 return 0; 3353 } 3354 3355 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3356 struct amdgpu_irq_src *src, 3357 unsigned type, 3358 enum amdgpu_interrupt_state state) 3359 { 3360 u32 reg; 3361 3362 if (type >= adev->mode_info.num_crtc) { 3363 DRM_ERROR("invalid pageflip crtc %d\n", type); 3364 return -EINVAL; 3365 } 3366 3367 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3368 if (state == AMDGPU_IRQ_STATE_DISABLE) 3369 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3370 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3371 else 3372 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3373 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3374 3375 return 0; 3376 } 3377 3378 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, 3379 struct amdgpu_irq_src *source, 3380 struct amdgpu_iv_entry *entry) 3381 { 3382 unsigned long flags; 3383 unsigned crtc_id; 3384 struct amdgpu_crtc *amdgpu_crtc; 3385 struct amdgpu_flip_work *works; 3386 3387 crtc_id = (entry->src_id - 8) >> 1; 3388 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3389 3390 if (crtc_id >= adev->mode_info.num_crtc) { 3391 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3392 return -EINVAL; 3393 } 3394 3395 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3396 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3397 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3398 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3399 3400 /* IRQ could occur when in initial stage */ 3401 if (amdgpu_crtc == NULL) 3402 return 0; 3403 3404 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3405 works = amdgpu_crtc->pflip_works; 3406 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3407 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3408 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3409 amdgpu_crtc->pflip_status, 3410 AMDGPU_FLIP_SUBMITTED); 3411 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3412 return 0; 3413 } 3414 3415 /* page flip completed. clean up */ 3416 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3417 amdgpu_crtc->pflip_works = NULL; 3418 3419 /* wakeup usersapce */ 3420 if (works->event) 3421 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3422 3423 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3424 3425 drm_crtc_vblank_put(&amdgpu_crtc->base); 3426 schedule_work(&works->unpin_work); 3427 3428 return 0; 3429 } 3430 3431 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, 3432 int hpd) 3433 { 3434 u32 tmp; 3435 3436 if (hpd >= adev->mode_info.num_hpd) { 3437 DRM_DEBUG("invalid hdp %d\n", hpd); 3438 return; 3439 } 3440 3441 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3442 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3443 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3444 } 3445 3446 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3447 int crtc) 3448 { 3449 u32 tmp; 3450 3451 if (crtc >= adev->mode_info.num_crtc) { 3452 DRM_DEBUG("invalid crtc %d\n", crtc); 3453 return; 3454 } 3455 3456 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3457 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3458 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3459 } 3460 3461 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3462 int crtc) 3463 { 3464 u32 tmp; 3465 3466 if (crtc >= adev->mode_info.num_crtc) { 3467 DRM_DEBUG("invalid crtc %d\n", crtc); 3468 return; 3469 } 3470 3471 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3472 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3473 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3474 } 3475 3476 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 3477 struct amdgpu_irq_src *source, 3478 struct amdgpu_iv_entry *entry) 3479 { 3480 unsigned crtc = entry->src_id - 1; 3481 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3482 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); 3483 3484 switch (entry->src_data) { 3485 case 0: /* vblank */ 3486 if (disp_int & interrupt_status_offsets[crtc].vblank) 3487 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3488 else 3489 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3490 3491 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3492 drm_handle_vblank(adev->ddev, crtc); 3493 } 3494 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3495 3496 break; 3497 case 1: /* vline */ 3498 if (disp_int & interrupt_status_offsets[crtc].vline) 3499 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3500 else 3501 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3502 3503 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3504 3505 break; 3506 default: 3507 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3508 break; 3509 } 3510 3511 return 0; 3512 } 3513 3514 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 3515 struct amdgpu_irq_src *source, 3516 struct amdgpu_iv_entry *entry) 3517 { 3518 uint32_t disp_int, mask; 3519 unsigned hpd; 3520 3521 if (entry->src_data >= adev->mode_info.num_hpd) { 3522 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); 3523 return 0; 3524 } 3525 3526 hpd = entry->src_data; 3527 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3528 mask = interrupt_status_offsets[hpd].hpd; 3529 3530 if (disp_int & mask) { 3531 dce_v10_0_hpd_int_ack(adev, hpd); 3532 schedule_work(&adev->hotplug_work); 3533 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3534 } 3535 3536 return 0; 3537 } 3538 3539 static int dce_v10_0_set_clockgating_state(void *handle, 3540 enum amd_clockgating_state state) 3541 { 3542 return 0; 3543 } 3544 3545 static int dce_v10_0_set_powergating_state(void *handle, 3546 enum amd_powergating_state state) 3547 { 3548 return 0; 3549 } 3550 3551 const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3552 .name = "dce_v10_0", 3553 .early_init = dce_v10_0_early_init, 3554 .late_init = NULL, 3555 .sw_init = dce_v10_0_sw_init, 3556 .sw_fini = dce_v10_0_sw_fini, 3557 .hw_init = dce_v10_0_hw_init, 3558 .hw_fini = dce_v10_0_hw_fini, 3559 .suspend = dce_v10_0_suspend, 3560 .resume = dce_v10_0_resume, 3561 .is_idle = dce_v10_0_is_idle, 3562 .wait_for_idle = dce_v10_0_wait_for_idle, 3563 .check_soft_reset = dce_v10_0_check_soft_reset, 3564 .soft_reset = dce_v10_0_soft_reset, 3565 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3566 .set_powergating_state = dce_v10_0_set_powergating_state, 3567 }; 3568 3569 static void 3570 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, 3571 struct drm_display_mode *mode, 3572 struct drm_display_mode *adjusted_mode) 3573 { 3574 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3575 3576 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3577 3578 /* need to call this here rather than in prepare() since we need some crtc info */ 3579 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3580 3581 /* set scaler clears this on some chips */ 3582 dce_v10_0_set_interleave(encoder->crtc, mode); 3583 3584 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3585 dce_v10_0_afmt_enable(encoder, true); 3586 dce_v10_0_afmt_setmode(encoder, adjusted_mode); 3587 } 3588 } 3589 3590 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) 3591 { 3592 struct amdgpu_device *adev = encoder->dev->dev_private; 3593 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3594 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3595 3596 if ((amdgpu_encoder->active_device & 3597 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3598 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3599 ENCODER_OBJECT_ID_NONE)) { 3600 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3601 if (dig) { 3602 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); 3603 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3604 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3605 } 3606 } 3607 3608 amdgpu_atombios_scratch_regs_lock(adev, true); 3609 3610 if (connector) { 3611 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3612 3613 /* select the clock/data port if it uses a router */ 3614 if (amdgpu_connector->router.cd_valid) 3615 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3616 3617 /* turn eDP panel on for mode set */ 3618 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3619 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3620 ATOM_TRANSMITTER_ACTION_POWER_ON); 3621 } 3622 3623 /* this is needed for the pll/ss setup to work correctly in some cases */ 3624 amdgpu_atombios_encoder_set_crtc_source(encoder); 3625 /* set up the FMT blocks */ 3626 dce_v10_0_program_fmt(encoder); 3627 } 3628 3629 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) 3630 { 3631 struct drm_device *dev = encoder->dev; 3632 struct amdgpu_device *adev = dev->dev_private; 3633 3634 /* need to call this here as we need the crtc set up */ 3635 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3636 amdgpu_atombios_scratch_regs_lock(adev, false); 3637 } 3638 3639 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) 3640 { 3641 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3642 struct amdgpu_encoder_atom_dig *dig; 3643 3644 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3645 3646 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3647 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3648 dce_v10_0_afmt_enable(encoder, false); 3649 dig = amdgpu_encoder->enc_priv; 3650 dig->dig_encoder = -1; 3651 } 3652 amdgpu_encoder->active_device = 0; 3653 } 3654 3655 /* these are handled by the primary encoders */ 3656 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) 3657 { 3658 3659 } 3660 3661 static void dce_v10_0_ext_commit(struct drm_encoder *encoder) 3662 { 3663 3664 } 3665 3666 static void 3667 dce_v10_0_ext_mode_set(struct drm_encoder *encoder, 3668 struct drm_display_mode *mode, 3669 struct drm_display_mode *adjusted_mode) 3670 { 3671 3672 } 3673 3674 static void dce_v10_0_ext_disable(struct drm_encoder *encoder) 3675 { 3676 3677 } 3678 3679 static void 3680 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) 3681 { 3682 3683 } 3684 3685 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { 3686 .dpms = dce_v10_0_ext_dpms, 3687 .prepare = dce_v10_0_ext_prepare, 3688 .mode_set = dce_v10_0_ext_mode_set, 3689 .commit = dce_v10_0_ext_commit, 3690 .disable = dce_v10_0_ext_disable, 3691 /* no detect for TMDS/LVDS yet */ 3692 }; 3693 3694 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { 3695 .dpms = amdgpu_atombios_encoder_dpms, 3696 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3697 .prepare = dce_v10_0_encoder_prepare, 3698 .mode_set = dce_v10_0_encoder_mode_set, 3699 .commit = dce_v10_0_encoder_commit, 3700 .disable = dce_v10_0_encoder_disable, 3701 .detect = amdgpu_atombios_encoder_dig_detect, 3702 }; 3703 3704 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { 3705 .dpms = amdgpu_atombios_encoder_dpms, 3706 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3707 .prepare = dce_v10_0_encoder_prepare, 3708 .mode_set = dce_v10_0_encoder_mode_set, 3709 .commit = dce_v10_0_encoder_commit, 3710 .detect = amdgpu_atombios_encoder_dac_detect, 3711 }; 3712 3713 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) 3714 { 3715 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3716 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3717 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3718 kfree(amdgpu_encoder->enc_priv); 3719 drm_encoder_cleanup(encoder); 3720 kfree(amdgpu_encoder); 3721 } 3722 3723 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { 3724 .destroy = dce_v10_0_encoder_destroy, 3725 }; 3726 3727 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, 3728 uint32_t encoder_enum, 3729 uint32_t supported_device, 3730 u16 caps) 3731 { 3732 struct drm_device *dev = adev->ddev; 3733 struct drm_encoder *encoder; 3734 struct amdgpu_encoder *amdgpu_encoder; 3735 3736 /* see if we already added it */ 3737 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3738 amdgpu_encoder = to_amdgpu_encoder(encoder); 3739 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3740 amdgpu_encoder->devices |= supported_device; 3741 return; 3742 } 3743 3744 } 3745 3746 /* add a new one */ 3747 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3748 if (!amdgpu_encoder) 3749 return; 3750 3751 encoder = &amdgpu_encoder->base; 3752 switch (adev->mode_info.num_crtc) { 3753 case 1: 3754 encoder->possible_crtcs = 0x1; 3755 break; 3756 case 2: 3757 default: 3758 encoder->possible_crtcs = 0x3; 3759 break; 3760 case 4: 3761 encoder->possible_crtcs = 0xf; 3762 break; 3763 case 6: 3764 encoder->possible_crtcs = 0x3f; 3765 break; 3766 } 3767 3768 amdgpu_encoder->enc_priv = NULL; 3769 3770 amdgpu_encoder->encoder_enum = encoder_enum; 3771 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3772 amdgpu_encoder->devices = supported_device; 3773 amdgpu_encoder->rmx_type = RMX_OFF; 3774 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3775 amdgpu_encoder->is_ext_encoder = false; 3776 amdgpu_encoder->caps = caps; 3777 3778 switch (amdgpu_encoder->encoder_id) { 3779 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3780 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3781 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3782 DRM_MODE_ENCODER_DAC, NULL); 3783 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); 3784 break; 3785 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3786 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3787 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3788 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3789 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3790 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3791 amdgpu_encoder->rmx_type = RMX_FULL; 3792 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3793 DRM_MODE_ENCODER_LVDS, NULL); 3794 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3795 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3796 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3797 DRM_MODE_ENCODER_DAC, NULL); 3798 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3799 } else { 3800 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3801 DRM_MODE_ENCODER_TMDS, NULL); 3802 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3803 } 3804 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); 3805 break; 3806 case ENCODER_OBJECT_ID_SI170B: 3807 case ENCODER_OBJECT_ID_CH7303: 3808 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3809 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3810 case ENCODER_OBJECT_ID_TITFP513: 3811 case ENCODER_OBJECT_ID_VT1623: 3812 case ENCODER_OBJECT_ID_HDMI_SI1930: 3813 case ENCODER_OBJECT_ID_TRAVIS: 3814 case ENCODER_OBJECT_ID_NUTMEG: 3815 /* these are handled by the primary encoders */ 3816 amdgpu_encoder->is_ext_encoder = true; 3817 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3818 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3819 DRM_MODE_ENCODER_LVDS, NULL); 3820 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3821 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3822 DRM_MODE_ENCODER_DAC, NULL); 3823 else 3824 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3825 DRM_MODE_ENCODER_TMDS, NULL); 3826 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); 3827 break; 3828 } 3829 } 3830 3831 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 3832 .set_vga_render_state = &dce_v10_0_set_vga_render_state, 3833 .bandwidth_update = &dce_v10_0_bandwidth_update, 3834 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3835 .vblank_wait = &dce_v10_0_vblank_wait, 3836 .is_display_hung = &dce_v10_0_is_display_hung, 3837 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3838 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3839 .hpd_sense = &dce_v10_0_hpd_sense, 3840 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, 3841 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, 3842 .page_flip = &dce_v10_0_page_flip, 3843 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, 3844 .add_encoder = &dce_v10_0_encoder_add, 3845 .add_connector = &amdgpu_connector_add, 3846 .stop_mc_access = &dce_v10_0_stop_mc_access, 3847 .resume_mc_access = &dce_v10_0_resume_mc_access, 3848 }; 3849 3850 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) 3851 { 3852 if (adev->mode_info.funcs == NULL) 3853 adev->mode_info.funcs = &dce_v10_0_display_funcs; 3854 } 3855 3856 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { 3857 .set = dce_v10_0_set_crtc_irq_state, 3858 .process = dce_v10_0_crtc_irq, 3859 }; 3860 3861 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { 3862 .set = dce_v10_0_set_pageflip_irq_state, 3863 .process = dce_v10_0_pageflip_irq, 3864 }; 3865 3866 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { 3867 .set = dce_v10_0_set_hpd_irq_state, 3868 .process = dce_v10_0_hpd_irq, 3869 }; 3870 3871 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 3872 { 3873 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; 3874 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; 3875 3876 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; 3877 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; 3878 3879 adev->hpd_irq.num_types = AMDGPU_HPD_LAST; 3880 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3881 } 3882