1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_pm.h" 26 #include "amdgpu_i2c.h" 27 #include "vid.h" 28 #include "atom.h" 29 #include "amdgpu_atombios.h" 30 #include "atombios_crtc.h" 31 #include "atombios_encoders.h" 32 #include "amdgpu_pll.h" 33 #include "amdgpu_connectors.h" 34 #include "dce_v10_0.h" 35 36 #include "dce/dce_10_0_d.h" 37 #include "dce/dce_10_0_sh_mask.h" 38 #include "dce/dce_10_0_enum.h" 39 #include "oss/oss_3_0_d.h" 40 #include "oss/oss_3_0_sh_mask.h" 41 #include "gmc/gmc_8_1_d.h" 42 #include "gmc/gmc_8_1_sh_mask.h" 43 44 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev); 45 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev); 46 47 static const u32 crtc_offsets[] = 48 { 49 CRTC0_REGISTER_OFFSET, 50 CRTC1_REGISTER_OFFSET, 51 CRTC2_REGISTER_OFFSET, 52 CRTC3_REGISTER_OFFSET, 53 CRTC4_REGISTER_OFFSET, 54 CRTC5_REGISTER_OFFSET, 55 CRTC6_REGISTER_OFFSET 56 }; 57 58 static const u32 hpd_offsets[] = 59 { 60 HPD0_REGISTER_OFFSET, 61 HPD1_REGISTER_OFFSET, 62 HPD2_REGISTER_OFFSET, 63 HPD3_REGISTER_OFFSET, 64 HPD4_REGISTER_OFFSET, 65 HPD5_REGISTER_OFFSET 66 }; 67 68 static const uint32_t dig_offsets[] = { 69 DIG0_REGISTER_OFFSET, 70 DIG1_REGISTER_OFFSET, 71 DIG2_REGISTER_OFFSET, 72 DIG3_REGISTER_OFFSET, 73 DIG4_REGISTER_OFFSET, 74 DIG5_REGISTER_OFFSET, 75 DIG6_REGISTER_OFFSET 76 }; 77 78 static const struct { 79 uint32_t reg; 80 uint32_t vblank; 81 uint32_t vline; 82 uint32_t hpd; 83 84 } interrupt_status_offsets[] = { { 85 .reg = mmDISP_INTERRUPT_STATUS, 86 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, 87 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, 88 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK 89 }, { 90 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, 91 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, 92 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, 93 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK 94 }, { 95 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, 96 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, 97 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, 98 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK 99 }, { 100 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, 101 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, 102 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, 103 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK 104 }, { 105 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, 106 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, 107 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, 108 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK 109 }, { 110 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, 111 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, 112 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, 113 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK 114 } }; 115 116 static const u32 golden_settings_tonga_a11[] = 117 { 118 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 119 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 120 mmFBC_MISC, 0x1f311fff, 0x12300000, 121 mmHDMI_CONTROL, 0x31000111, 0x00000011, 122 }; 123 124 static const u32 tonga_mgcg_cgcg_init[] = 125 { 126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 128 }; 129 130 static const u32 golden_settings_fiji_a10[] = 131 { 132 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 133 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 134 mmFBC_MISC, 0x1f311fff, 0x12300000, 135 mmHDMI_CONTROL, 0x31000111, 0x00000011, 136 }; 137 138 static const u32 fiji_mgcg_cgcg_init[] = 139 { 140 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 141 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 142 }; 143 144 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) 145 { 146 switch (adev->asic_type) { 147 case CHIP_FIJI: 148 amdgpu_device_program_register_sequence(adev, 149 fiji_mgcg_cgcg_init, 150 ARRAY_SIZE(fiji_mgcg_cgcg_init)); 151 amdgpu_device_program_register_sequence(adev, 152 golden_settings_fiji_a10, 153 ARRAY_SIZE(golden_settings_fiji_a10)); 154 break; 155 case CHIP_TONGA: 156 amdgpu_device_program_register_sequence(adev, 157 tonga_mgcg_cgcg_init, 158 ARRAY_SIZE(tonga_mgcg_cgcg_init)); 159 amdgpu_device_program_register_sequence(adev, 160 golden_settings_tonga_a11, 161 ARRAY_SIZE(golden_settings_tonga_a11)); 162 break; 163 default: 164 break; 165 } 166 } 167 168 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev, 169 u32 block_offset, u32 reg) 170 { 171 unsigned long flags; 172 u32 r; 173 174 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 175 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 176 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); 177 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 178 179 return r; 180 } 181 182 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev, 183 u32 block_offset, u32 reg, u32 v) 184 { 185 unsigned long flags; 186 187 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); 188 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 189 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); 190 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); 191 } 192 193 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) 194 { 195 if (crtc >= adev->mode_info.num_crtc) 196 return 0; 197 else 198 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); 199 } 200 201 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev) 202 { 203 unsigned i; 204 205 /* Enable pflip interrupts */ 206 for (i = 0; i < adev->mode_info.num_crtc; i++) 207 amdgpu_irq_get(adev, &adev->pageflip_irq, i); 208 } 209 210 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev) 211 { 212 unsigned i; 213 214 /* Disable pflip interrupts */ 215 for (i = 0; i < adev->mode_info.num_crtc; i++) 216 amdgpu_irq_put(adev, &adev->pageflip_irq, i); 217 } 218 219 /** 220 * dce_v10_0_page_flip - pageflip callback. 221 * 222 * @adev: amdgpu_device pointer 223 * @crtc_id: crtc to cleanup pageflip on 224 * @crtc_base: new address of the crtc (GPU MC address) 225 * 226 * Triggers the actual pageflip by updating the primary 227 * surface base address. 228 */ 229 static void dce_v10_0_page_flip(struct amdgpu_device *adev, 230 int crtc_id, u64 crtc_base, bool async) 231 { 232 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 233 u32 tmp; 234 235 /* flip at hsync for async, default is vsync */ 236 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 237 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 238 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); 239 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 240 /* update the primary scanout address */ 241 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 242 upper_32_bits(crtc_base)); 243 /* writing to the low address triggers the update */ 244 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 245 lower_32_bits(crtc_base)); 246 /* post the write */ 247 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset); 248 } 249 250 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, 251 u32 *vbl, u32 *position) 252 { 253 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) 254 return -EINVAL; 255 256 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); 257 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); 258 259 return 0; 260 } 261 262 /** 263 * dce_v10_0_hpd_sense - hpd sense callback. 264 * 265 * @adev: amdgpu_device pointer 266 * @hpd: hpd (hotplug detect) pin 267 * 268 * Checks if a digital monitor is connected (evergreen+). 269 * Returns true if connected, false if not connected. 270 */ 271 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev, 272 enum amdgpu_hpd_id hpd) 273 { 274 bool connected = false; 275 276 if (hpd >= adev->mode_info.num_hpd) 277 return connected; 278 279 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) & 280 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) 281 connected = true; 282 283 return connected; 284 } 285 286 /** 287 * dce_v10_0_hpd_set_polarity - hpd set polarity callback. 288 * 289 * @adev: amdgpu_device pointer 290 * @hpd: hpd (hotplug detect) pin 291 * 292 * Set the polarity of the hpd pin (evergreen+). 293 */ 294 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev, 295 enum amdgpu_hpd_id hpd) 296 { 297 u32 tmp; 298 bool connected = dce_v10_0_hpd_sense(adev, hpd); 299 300 if (hpd >= adev->mode_info.num_hpd) 301 return; 302 303 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 304 if (connected) 305 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); 306 else 307 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); 308 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 309 } 310 311 /** 312 * dce_v10_0_hpd_init - hpd setup callback. 313 * 314 * @adev: amdgpu_device pointer 315 * 316 * Setup the hpd pins used by the card (evergreen+). 317 * Enable the pin, set the polarity, and enable the hpd interrupts. 318 */ 319 static void dce_v10_0_hpd_init(struct amdgpu_device *adev) 320 { 321 struct drm_device *dev = adev->ddev; 322 struct drm_connector *connector; 323 u32 tmp; 324 325 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 326 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 327 328 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 329 continue; 330 331 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || 332 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { 333 /* don't try to enable hpd on eDP or LVDS avoid breaking the 334 * aux dp channel on imac and help (but not completely fix) 335 * https://bugzilla.redhat.com/show_bug.cgi?id=726143 336 * also avoid interrupt storms during dpms. 337 */ 338 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 339 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 340 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 341 continue; 342 } 343 344 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 345 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); 346 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 347 348 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]); 349 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 350 DC_HPD_CONNECT_INT_DELAY, 351 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); 352 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, 353 DC_HPD_DISCONNECT_INT_DELAY, 354 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); 355 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 356 357 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); 358 amdgpu_irq_get(adev, &adev->hpd_irq, 359 amdgpu_connector->hpd.hpd); 360 } 361 } 362 363 /** 364 * dce_v10_0_hpd_fini - hpd tear down callback. 365 * 366 * @adev: amdgpu_device pointer 367 * 368 * Tear down the hpd pins used by the card (evergreen+). 369 * Disable the hpd interrupts. 370 */ 371 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) 372 { 373 struct drm_device *dev = adev->ddev; 374 struct drm_connector *connector; 375 u32 tmp; 376 377 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 378 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 379 380 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) 381 continue; 382 383 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]); 384 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); 385 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp); 386 387 amdgpu_irq_put(adev, &adev->hpd_irq, 388 amdgpu_connector->hpd.hpd); 389 } 390 } 391 392 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) 393 { 394 return mmDC_GPIO_HPD_A; 395 } 396 397 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev) 398 { 399 u32 crtc_hung = 0; 400 u32 crtc_status[6]; 401 u32 i, j, tmp; 402 403 for (i = 0; i < adev->mode_info.num_crtc; i++) { 404 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 405 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { 406 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 407 crtc_hung |= (1 << i); 408 } 409 } 410 411 for (j = 0; j < 10; j++) { 412 for (i = 0; i < adev->mode_info.num_crtc; i++) { 413 if (crtc_hung & (1 << i)) { 414 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); 415 if (tmp != crtc_status[i]) 416 crtc_hung &= ~(1 << i); 417 } 418 } 419 if (crtc_hung == 0) 420 return false; 421 udelay(100); 422 } 423 424 return true; 425 } 426 427 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev, 428 bool render) 429 { 430 u32 tmp; 431 432 /* Lockout access through VGA aperture*/ 433 tmp = RREG32(mmVGA_HDP_CONTROL); 434 if (render) 435 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); 436 else 437 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); 438 WREG32(mmVGA_HDP_CONTROL, tmp); 439 440 /* disable VGA render */ 441 tmp = RREG32(mmVGA_RENDER_CONTROL); 442 if (render) 443 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); 444 else 445 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); 446 WREG32(mmVGA_RENDER_CONTROL, tmp); 447 } 448 449 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev) 450 { 451 int num_crtc = 0; 452 453 switch (adev->asic_type) { 454 case CHIP_FIJI: 455 case CHIP_TONGA: 456 num_crtc = 6; 457 break; 458 default: 459 num_crtc = 0; 460 } 461 return num_crtc; 462 } 463 464 void dce_v10_0_disable_dce(struct amdgpu_device *adev) 465 { 466 /*Disable VGA render and enabled crtc, if has DCE engine*/ 467 if (amdgpu_atombios_has_dce_engine_info(adev)) { 468 u32 tmp; 469 int crtc_enabled, i; 470 471 dce_v10_0_set_vga_render_state(adev, false); 472 473 /*Disable crtc*/ 474 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) { 475 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), 476 CRTC_CONTROL, CRTC_MASTER_EN); 477 if (crtc_enabled) { 478 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); 479 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); 480 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); 481 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); 482 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); 483 } 484 } 485 } 486 } 487 488 static void dce_v10_0_program_fmt(struct drm_encoder *encoder) 489 { 490 struct drm_device *dev = encoder->dev; 491 struct amdgpu_device *adev = dev->dev_private; 492 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 493 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 494 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 495 int bpc = 0; 496 u32 tmp = 0; 497 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; 498 499 if (connector) { 500 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 501 bpc = amdgpu_connector_get_monitor_bpc(connector); 502 dither = amdgpu_connector->dither; 503 } 504 505 /* LVDS/eDP FMT is set up by atom */ 506 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) 507 return; 508 509 /* not needed for analog */ 510 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || 511 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) 512 return; 513 514 if (bpc == 0) 515 return; 516 517 switch (bpc) { 518 case 6: 519 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 520 /* XXX sort out optimal dither settings */ 521 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 522 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 523 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 524 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); 525 } else { 526 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 527 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); 528 } 529 break; 530 case 8: 531 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 532 /* XXX sort out optimal dither settings */ 533 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 534 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 535 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 536 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); 538 } else { 539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); 541 } 542 break; 543 case 10: 544 if (dither == AMDGPU_FMT_DITHER_ENABLE) { 545 /* XXX sort out optimal dither settings */ 546 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); 547 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); 548 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); 549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); 550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); 551 } else { 552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); 553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); 554 } 555 break; 556 default: 557 /* not needed */ 558 break; 559 } 560 561 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 562 } 563 564 565 /* display watermark setup */ 566 /** 567 * dce_v10_0_line_buffer_adjust - Set up the line buffer 568 * 569 * @adev: amdgpu_device pointer 570 * @amdgpu_crtc: the selected display controller 571 * @mode: the current display mode on the selected display 572 * controller 573 * 574 * Setup up the line buffer allocation for 575 * the selected display controller (CIK). 576 * Returns the line buffer size in pixels. 577 */ 578 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev, 579 struct amdgpu_crtc *amdgpu_crtc, 580 struct drm_display_mode *mode) 581 { 582 u32 tmp, buffer_alloc, i, mem_cfg; 583 u32 pipe_offset = amdgpu_crtc->crtc_id; 584 /* 585 * Line Buffer Setup 586 * There are 6 line buffers, one for each display controllers. 587 * There are 3 partitions per LB. Select the number of partitions 588 * to enable based on the display width. For display widths larger 589 * than 4096, you need use to use 2 display controllers and combine 590 * them using the stereo blender. 591 */ 592 if (amdgpu_crtc->base.enabled && mode) { 593 if (mode->crtc_hdisplay < 1920) { 594 mem_cfg = 1; 595 buffer_alloc = 2; 596 } else if (mode->crtc_hdisplay < 2560) { 597 mem_cfg = 2; 598 buffer_alloc = 2; 599 } else if (mode->crtc_hdisplay < 4096) { 600 mem_cfg = 0; 601 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 602 } else { 603 DRM_DEBUG_KMS("Mode too big for LB!\n"); 604 mem_cfg = 0; 605 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4; 606 } 607 } else { 608 mem_cfg = 1; 609 buffer_alloc = 0; 610 } 611 612 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); 613 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); 614 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); 615 616 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 617 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); 618 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); 619 620 for (i = 0; i < adev->usec_timeout; i++) { 621 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); 622 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) 623 break; 624 udelay(1); 625 } 626 627 if (amdgpu_crtc->base.enabled && mode) { 628 switch (mem_cfg) { 629 case 0: 630 default: 631 return 4096 * 2; 632 case 1: 633 return 1920 * 2; 634 case 2: 635 return 2560 * 2; 636 } 637 } 638 639 /* controller not enabled, so no lb used */ 640 return 0; 641 } 642 643 /** 644 * cik_get_number_of_dram_channels - get the number of dram channels 645 * 646 * @adev: amdgpu_device pointer 647 * 648 * Look up the number of video ram channels (CIK). 649 * Used for display watermark bandwidth calculations 650 * Returns the number of dram channels 651 */ 652 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) 653 { 654 u32 tmp = RREG32(mmMC_SHARED_CHMAP); 655 656 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { 657 case 0: 658 default: 659 return 1; 660 case 1: 661 return 2; 662 case 2: 663 return 4; 664 case 3: 665 return 8; 666 case 4: 667 return 3; 668 case 5: 669 return 6; 670 case 6: 671 return 10; 672 case 7: 673 return 12; 674 case 8: 675 return 16; 676 } 677 } 678 679 struct dce10_wm_params { 680 u32 dram_channels; /* number of dram channels */ 681 u32 yclk; /* bandwidth per dram data pin in kHz */ 682 u32 sclk; /* engine clock in kHz */ 683 u32 disp_clk; /* display clock in kHz */ 684 u32 src_width; /* viewport width */ 685 u32 active_time; /* active display time in ns */ 686 u32 blank_time; /* blank time in ns */ 687 bool interlaced; /* mode is interlaced */ 688 fixed20_12 vsc; /* vertical scale ratio */ 689 u32 num_heads; /* number of active crtcs */ 690 u32 bytes_per_pixel; /* bytes per pixel display + overlay */ 691 u32 lb_size; /* line buffer allocated to pipe */ 692 u32 vtaps; /* vertical scaler taps */ 693 }; 694 695 /** 696 * dce_v10_0_dram_bandwidth - get the dram bandwidth 697 * 698 * @wm: watermark calculation data 699 * 700 * Calculate the raw dram bandwidth (CIK). 701 * Used for display watermark bandwidth calculations 702 * Returns the dram bandwidth in MBytes/s 703 */ 704 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) 705 { 706 /* Calculate raw DRAM Bandwidth */ 707 fixed20_12 dram_efficiency; /* 0.7 */ 708 fixed20_12 yclk, dram_channels, bandwidth; 709 fixed20_12 a; 710 711 a.full = dfixed_const(1000); 712 yclk.full = dfixed_const(wm->yclk); 713 yclk.full = dfixed_div(yclk, a); 714 dram_channels.full = dfixed_const(wm->dram_channels * 4); 715 a.full = dfixed_const(10); 716 dram_efficiency.full = dfixed_const(7); 717 dram_efficiency.full = dfixed_div(dram_efficiency, a); 718 bandwidth.full = dfixed_mul(dram_channels, yclk); 719 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); 720 721 return dfixed_trunc(bandwidth); 722 } 723 724 /** 725 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display 726 * 727 * @wm: watermark calculation data 728 * 729 * Calculate the dram bandwidth used for display (CIK). 730 * Used for display watermark bandwidth calculations 731 * Returns the dram bandwidth for display in MBytes/s 732 */ 733 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) 734 { 735 /* Calculate DRAM Bandwidth and the part allocated to display. */ 736 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ 737 fixed20_12 yclk, dram_channels, bandwidth; 738 fixed20_12 a; 739 740 a.full = dfixed_const(1000); 741 yclk.full = dfixed_const(wm->yclk); 742 yclk.full = dfixed_div(yclk, a); 743 dram_channels.full = dfixed_const(wm->dram_channels * 4); 744 a.full = dfixed_const(10); 745 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ 746 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); 747 bandwidth.full = dfixed_mul(dram_channels, yclk); 748 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); 749 750 return dfixed_trunc(bandwidth); 751 } 752 753 /** 754 * dce_v10_0_data_return_bandwidth - get the data return bandwidth 755 * 756 * @wm: watermark calculation data 757 * 758 * Calculate the data return bandwidth used for display (CIK). 759 * Used for display watermark bandwidth calculations 760 * Returns the data return bandwidth in MBytes/s 761 */ 762 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) 763 { 764 /* Calculate the display Data return Bandwidth */ 765 fixed20_12 return_efficiency; /* 0.8 */ 766 fixed20_12 sclk, bandwidth; 767 fixed20_12 a; 768 769 a.full = dfixed_const(1000); 770 sclk.full = dfixed_const(wm->sclk); 771 sclk.full = dfixed_div(sclk, a); 772 a.full = dfixed_const(10); 773 return_efficiency.full = dfixed_const(8); 774 return_efficiency.full = dfixed_div(return_efficiency, a); 775 a.full = dfixed_const(32); 776 bandwidth.full = dfixed_mul(a, sclk); 777 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); 778 779 return dfixed_trunc(bandwidth); 780 } 781 782 /** 783 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth 784 * 785 * @wm: watermark calculation data 786 * 787 * Calculate the dmif bandwidth used for display (CIK). 788 * Used for display watermark bandwidth calculations 789 * Returns the dmif bandwidth in MBytes/s 790 */ 791 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) 792 { 793 /* Calculate the DMIF Request Bandwidth */ 794 fixed20_12 disp_clk_request_efficiency; /* 0.8 */ 795 fixed20_12 disp_clk, bandwidth; 796 fixed20_12 a, b; 797 798 a.full = dfixed_const(1000); 799 disp_clk.full = dfixed_const(wm->disp_clk); 800 disp_clk.full = dfixed_div(disp_clk, a); 801 a.full = dfixed_const(32); 802 b.full = dfixed_mul(a, disp_clk); 803 804 a.full = dfixed_const(10); 805 disp_clk_request_efficiency.full = dfixed_const(8); 806 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); 807 808 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); 809 810 return dfixed_trunc(bandwidth); 811 } 812 813 /** 814 * dce_v10_0_available_bandwidth - get the min available bandwidth 815 * 816 * @wm: watermark calculation data 817 * 818 * Calculate the min available bandwidth used for display (CIK). 819 * Used for display watermark bandwidth calculations 820 * Returns the min available bandwidth in MBytes/s 821 */ 822 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) 823 { 824 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ 825 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); 826 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); 827 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); 828 829 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); 830 } 831 832 /** 833 * dce_v10_0_average_bandwidth - get the average available bandwidth 834 * 835 * @wm: watermark calculation data 836 * 837 * Calculate the average available bandwidth used for display (CIK). 838 * Used for display watermark bandwidth calculations 839 * Returns the average available bandwidth in MBytes/s 840 */ 841 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) 842 { 843 /* Calculate the display mode Average Bandwidth 844 * DisplayMode should contain the source and destination dimensions, 845 * timing, etc. 846 */ 847 fixed20_12 bpp; 848 fixed20_12 line_time; 849 fixed20_12 src_width; 850 fixed20_12 bandwidth; 851 fixed20_12 a; 852 853 a.full = dfixed_const(1000); 854 line_time.full = dfixed_const(wm->active_time + wm->blank_time); 855 line_time.full = dfixed_div(line_time, a); 856 bpp.full = dfixed_const(wm->bytes_per_pixel); 857 src_width.full = dfixed_const(wm->src_width); 858 bandwidth.full = dfixed_mul(src_width, bpp); 859 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); 860 bandwidth.full = dfixed_div(bandwidth, line_time); 861 862 return dfixed_trunc(bandwidth); 863 } 864 865 /** 866 * dce_v10_0_latency_watermark - get the latency watermark 867 * 868 * @wm: watermark calculation data 869 * 870 * Calculate the latency watermark (CIK). 871 * Used for display watermark bandwidth calculations 872 * Returns the latency watermark in ns 873 */ 874 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) 875 { 876 /* First calculate the latency in ns */ 877 u32 mc_latency = 2000; /* 2000 ns. */ 878 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); 879 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; 880 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; 881 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ 882 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + 883 (wm->num_heads * cursor_line_pair_return_time); 884 u32 latency = mc_latency + other_heads_data_return_time + dc_latency; 885 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; 886 u32 tmp, dmif_size = 12288; 887 fixed20_12 a, b, c; 888 889 if (wm->num_heads == 0) 890 return 0; 891 892 a.full = dfixed_const(2); 893 b.full = dfixed_const(1); 894 if ((wm->vsc.full > a.full) || 895 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || 896 (wm->vtaps >= 5) || 897 ((wm->vsc.full >= a.full) && wm->interlaced)) 898 max_src_lines_per_dst_line = 4; 899 else 900 max_src_lines_per_dst_line = 2; 901 902 a.full = dfixed_const(available_bandwidth); 903 b.full = dfixed_const(wm->num_heads); 904 a.full = dfixed_div(a, b); 905 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); 906 tmp = min(dfixed_trunc(a), tmp); 907 908 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); 909 910 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); 911 b.full = dfixed_const(1000); 912 c.full = dfixed_const(lb_fill_bw); 913 b.full = dfixed_div(c, b); 914 a.full = dfixed_div(a, b); 915 line_fill_time = dfixed_trunc(a); 916 917 if (line_fill_time < wm->active_time) 918 return latency; 919 else 920 return latency + (line_fill_time - wm->active_time); 921 922 } 923 924 /** 925 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check 926 * average and available dram bandwidth 927 * 928 * @wm: watermark calculation data 929 * 930 * Check if the display average bandwidth fits in the display 931 * dram bandwidth (CIK). 932 * Used for display watermark bandwidth calculations 933 * Returns true if the display fits, false if not. 934 */ 935 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) 936 { 937 if (dce_v10_0_average_bandwidth(wm) <= 938 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) 939 return true; 940 else 941 return false; 942 } 943 944 /** 945 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check 946 * average and available bandwidth 947 * 948 * @wm: watermark calculation data 949 * 950 * Check if the display average bandwidth fits in the display 951 * available bandwidth (CIK). 952 * Used for display watermark bandwidth calculations 953 * Returns true if the display fits, false if not. 954 */ 955 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) 956 { 957 if (dce_v10_0_average_bandwidth(wm) <= 958 (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) 959 return true; 960 else 961 return false; 962 } 963 964 /** 965 * dce_v10_0_check_latency_hiding - check latency hiding 966 * 967 * @wm: watermark calculation data 968 * 969 * Check latency hiding (CIK). 970 * Used for display watermark bandwidth calculations 971 * Returns true if the display fits, false if not. 972 */ 973 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) 974 { 975 u32 lb_partitions = wm->lb_size / wm->src_width; 976 u32 line_time = wm->active_time + wm->blank_time; 977 u32 latency_tolerant_lines; 978 u32 latency_hiding; 979 fixed20_12 a; 980 981 a.full = dfixed_const(1); 982 if (wm->vsc.full > a.full) 983 latency_tolerant_lines = 1; 984 else { 985 if (lb_partitions <= (wm->vtaps + 1)) 986 latency_tolerant_lines = 1; 987 else 988 latency_tolerant_lines = 2; 989 } 990 991 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); 992 993 if (dce_v10_0_latency_watermark(wm) <= latency_hiding) 994 return true; 995 else 996 return false; 997 } 998 999 /** 1000 * dce_v10_0_program_watermarks - program display watermarks 1001 * 1002 * @adev: amdgpu_device pointer 1003 * @amdgpu_crtc: the selected display controller 1004 * @lb_size: line buffer size 1005 * @num_heads: number of display controllers in use 1006 * 1007 * Calculate and program the display watermarks for the 1008 * selected display controller (CIK). 1009 */ 1010 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev, 1011 struct amdgpu_crtc *amdgpu_crtc, 1012 u32 lb_size, u32 num_heads) 1013 { 1014 struct drm_display_mode *mode = &amdgpu_crtc->base.mode; 1015 struct dce10_wm_params wm_low, wm_high; 1016 u32 active_time; 1017 u32 line_time = 0; 1018 u32 latency_watermark_a = 0, latency_watermark_b = 0; 1019 u32 tmp, wm_mask, lb_vblank_lead_lines = 0; 1020 1021 if (amdgpu_crtc->base.enabled && num_heads && mode) { 1022 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000, 1023 (u32)mode->clock); 1024 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000, 1025 (u32)mode->clock); 1026 line_time = min(line_time, (u32)65535); 1027 1028 /* watermark for high clocks */ 1029 if (adev->pm.dpm_enabled) { 1030 wm_high.yclk = 1031 amdgpu_dpm_get_mclk(adev, false) * 10; 1032 wm_high.sclk = 1033 amdgpu_dpm_get_sclk(adev, false) * 10; 1034 } else { 1035 wm_high.yclk = adev->pm.current_mclk * 10; 1036 wm_high.sclk = adev->pm.current_sclk * 10; 1037 } 1038 1039 wm_high.disp_clk = mode->clock; 1040 wm_high.src_width = mode->crtc_hdisplay; 1041 wm_high.active_time = active_time; 1042 wm_high.blank_time = line_time - wm_high.active_time; 1043 wm_high.interlaced = false; 1044 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1045 wm_high.interlaced = true; 1046 wm_high.vsc = amdgpu_crtc->vsc; 1047 wm_high.vtaps = 1; 1048 if (amdgpu_crtc->rmx_type != RMX_OFF) 1049 wm_high.vtaps = 2; 1050 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1051 wm_high.lb_size = lb_size; 1052 wm_high.dram_channels = cik_get_number_of_dram_channels(adev); 1053 wm_high.num_heads = num_heads; 1054 1055 /* set for high clocks */ 1056 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535); 1057 1058 /* possibly force display priority to high */ 1059 /* should really do this at mode validation time... */ 1060 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || 1061 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) || 1062 !dce_v10_0_check_latency_hiding(&wm_high) || 1063 (adev->mode_info.disp_priority == 2)) { 1064 DRM_DEBUG_KMS("force priority to high\n"); 1065 } 1066 1067 /* watermark for low clocks */ 1068 if (adev->pm.dpm_enabled) { 1069 wm_low.yclk = 1070 amdgpu_dpm_get_mclk(adev, true) * 10; 1071 wm_low.sclk = 1072 amdgpu_dpm_get_sclk(adev, true) * 10; 1073 } else { 1074 wm_low.yclk = adev->pm.current_mclk * 10; 1075 wm_low.sclk = adev->pm.current_sclk * 10; 1076 } 1077 1078 wm_low.disp_clk = mode->clock; 1079 wm_low.src_width = mode->crtc_hdisplay; 1080 wm_low.active_time = active_time; 1081 wm_low.blank_time = line_time - wm_low.active_time; 1082 wm_low.interlaced = false; 1083 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1084 wm_low.interlaced = true; 1085 wm_low.vsc = amdgpu_crtc->vsc; 1086 wm_low.vtaps = 1; 1087 if (amdgpu_crtc->rmx_type != RMX_OFF) 1088 wm_low.vtaps = 2; 1089 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ 1090 wm_low.lb_size = lb_size; 1091 wm_low.dram_channels = cik_get_number_of_dram_channels(adev); 1092 wm_low.num_heads = num_heads; 1093 1094 /* set for low clocks */ 1095 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535); 1096 1097 /* possibly force display priority to high */ 1098 /* should really do this at mode validation time... */ 1099 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || 1100 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) || 1101 !dce_v10_0_check_latency_hiding(&wm_low) || 1102 (adev->mode_info.disp_priority == 2)) { 1103 DRM_DEBUG_KMS("force priority to high\n"); 1104 } 1105 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay); 1106 } 1107 1108 /* select wm A */ 1109 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); 1110 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); 1111 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1112 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1113 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); 1114 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1115 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1116 /* select wm B */ 1117 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); 1118 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1119 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); 1120 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b); 1121 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); 1122 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1123 /* restore original selection */ 1124 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); 1125 1126 /* save values for DPM */ 1127 amdgpu_crtc->line_time = line_time; 1128 amdgpu_crtc->wm_high = latency_watermark_a; 1129 amdgpu_crtc->wm_low = latency_watermark_b; 1130 /* Save number of lines the linebuffer leads before the scanout */ 1131 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines; 1132 } 1133 1134 /** 1135 * dce_v10_0_bandwidth_update - program display watermarks 1136 * 1137 * @adev: amdgpu_device pointer 1138 * 1139 * Calculate and program the display watermarks and line 1140 * buffer allocation (CIK). 1141 */ 1142 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev) 1143 { 1144 struct drm_display_mode *mode = NULL; 1145 u32 num_heads = 0, lb_size; 1146 int i; 1147 1148 amdgpu_display_update_priority(adev); 1149 1150 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1151 if (adev->mode_info.crtcs[i]->base.enabled) 1152 num_heads++; 1153 } 1154 for (i = 0; i < adev->mode_info.num_crtc; i++) { 1155 mode = &adev->mode_info.crtcs[i]->base.mode; 1156 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); 1157 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i], 1158 lb_size, num_heads); 1159 } 1160 } 1161 1162 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev) 1163 { 1164 int i; 1165 u32 offset, tmp; 1166 1167 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1168 offset = adev->mode_info.audio.pin[i].offset; 1169 tmp = RREG32_AUDIO_ENDPT(offset, 1170 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 1171 if (((tmp & 1172 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> 1173 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) 1174 adev->mode_info.audio.pin[i].connected = false; 1175 else 1176 adev->mode_info.audio.pin[i].connected = true; 1177 } 1178 } 1179 1180 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev) 1181 { 1182 int i; 1183 1184 dce_v10_0_audio_get_connected_pins(adev); 1185 1186 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1187 if (adev->mode_info.audio.pin[i].connected) 1188 return &adev->mode_info.audio.pin[i]; 1189 } 1190 DRM_ERROR("No connected audio pins found!\n"); 1191 return NULL; 1192 } 1193 1194 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder) 1195 { 1196 struct amdgpu_device *adev = encoder->dev->dev_private; 1197 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1199 u32 tmp; 1200 1201 if (!dig || !dig->afmt || !dig->afmt->pin) 1202 return; 1203 1204 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); 1205 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); 1206 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); 1207 } 1208 1209 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, 1210 struct drm_display_mode *mode) 1211 { 1212 struct amdgpu_device *adev = encoder->dev->dev_private; 1213 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1214 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1215 struct drm_connector *connector; 1216 struct amdgpu_connector *amdgpu_connector = NULL; 1217 u32 tmp; 1218 int interlace = 0; 1219 1220 if (!dig || !dig->afmt || !dig->afmt->pin) 1221 return; 1222 1223 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1224 if (connector->encoder == encoder) { 1225 amdgpu_connector = to_amdgpu_connector(connector); 1226 break; 1227 } 1228 } 1229 1230 if (!amdgpu_connector) { 1231 DRM_ERROR("Couldn't find encoder's connector\n"); 1232 return; 1233 } 1234 1235 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 1236 interlace = 1; 1237 if (connector->latency_present[interlace]) { 1238 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1239 VIDEO_LIPSYNC, connector->video_latency[interlace]); 1240 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1241 AUDIO_LIPSYNC, connector->audio_latency[interlace]); 1242 } else { 1243 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1244 VIDEO_LIPSYNC, 0); 1245 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 1246 AUDIO_LIPSYNC, 0); 1247 } 1248 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1249 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 1250 } 1251 1252 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder) 1253 { 1254 struct amdgpu_device *adev = encoder->dev->dev_private; 1255 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1256 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1257 struct drm_connector *connector; 1258 struct amdgpu_connector *amdgpu_connector = NULL; 1259 u32 tmp; 1260 u8 *sadb = NULL; 1261 int sad_count; 1262 1263 if (!dig || !dig->afmt || !dig->afmt->pin) 1264 return; 1265 1266 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1267 if (connector->encoder == encoder) { 1268 amdgpu_connector = to_amdgpu_connector(connector); 1269 break; 1270 } 1271 } 1272 1273 if (!amdgpu_connector) { 1274 DRM_ERROR("Couldn't find encoder's connector\n"); 1275 return; 1276 } 1277 1278 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); 1279 if (sad_count < 0) { 1280 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); 1281 sad_count = 0; 1282 } 1283 1284 /* program the speaker allocation */ 1285 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1286 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 1287 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1288 DP_CONNECTION, 0); 1289 /* set HDMI mode */ 1290 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1291 HDMI_CONNECTION, 1); 1292 if (sad_count) 1293 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1294 SPEAKER_ALLOCATION, sadb[0]); 1295 else 1296 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 1297 SPEAKER_ALLOCATION, 5); /* stereo */ 1298 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, 1299 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 1300 1301 kfree(sadb); 1302 } 1303 1304 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) 1305 { 1306 struct amdgpu_device *adev = encoder->dev->dev_private; 1307 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1308 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1309 struct drm_connector *connector; 1310 struct amdgpu_connector *amdgpu_connector = NULL; 1311 struct cea_sad *sads; 1312 int i, sad_count; 1313 1314 static const u16 eld_reg_to_type[][2] = { 1315 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 1316 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 1317 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 1318 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 1319 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 1320 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 1321 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 1322 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 1323 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 1324 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 1325 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 1326 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 1327 }; 1328 1329 if (!dig || !dig->afmt || !dig->afmt->pin) 1330 return; 1331 1332 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { 1333 if (connector->encoder == encoder) { 1334 amdgpu_connector = to_amdgpu_connector(connector); 1335 break; 1336 } 1337 } 1338 1339 if (!amdgpu_connector) { 1340 DRM_ERROR("Couldn't find encoder's connector\n"); 1341 return; 1342 } 1343 1344 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); 1345 if (sad_count <= 0) { 1346 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 1347 return; 1348 } 1349 BUG_ON(!sads); 1350 1351 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 1352 u32 tmp = 0; 1353 u8 stereo_freqs = 0; 1354 int max_channels = -1; 1355 int j; 1356 1357 for (j = 0; j < sad_count; j++) { 1358 struct cea_sad *sad = &sads[j]; 1359 1360 if (sad->format == eld_reg_to_type[i][1]) { 1361 if (sad->channels > max_channels) { 1362 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1363 MAX_CHANNELS, sad->channels); 1364 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1365 DESCRIPTOR_BYTE_2, sad->byte2); 1366 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1367 SUPPORTED_FREQUENCIES, sad->freq); 1368 max_channels = sad->channels; 1369 } 1370 1371 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 1372 stereo_freqs |= sad->freq; 1373 else 1374 break; 1375 } 1376 } 1377 1378 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 1379 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); 1380 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); 1381 } 1382 1383 kfree(sads); 1384 } 1385 1386 static void dce_v10_0_audio_enable(struct amdgpu_device *adev, 1387 struct amdgpu_audio_pin *pin, 1388 bool enable) 1389 { 1390 if (!pin) 1391 return; 1392 1393 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 1394 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); 1395 } 1396 1397 static const u32 pin_offsets[] = 1398 { 1399 AUD0_REGISTER_OFFSET, 1400 AUD1_REGISTER_OFFSET, 1401 AUD2_REGISTER_OFFSET, 1402 AUD3_REGISTER_OFFSET, 1403 AUD4_REGISTER_OFFSET, 1404 AUD5_REGISTER_OFFSET, 1405 AUD6_REGISTER_OFFSET, 1406 }; 1407 1408 static int dce_v10_0_audio_init(struct amdgpu_device *adev) 1409 { 1410 int i; 1411 1412 if (!amdgpu_audio) 1413 return 0; 1414 1415 adev->mode_info.audio.enabled = true; 1416 1417 adev->mode_info.audio.num_pins = 7; 1418 1419 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 1420 adev->mode_info.audio.pin[i].channels = -1; 1421 adev->mode_info.audio.pin[i].rate = -1; 1422 adev->mode_info.audio.pin[i].bits_per_sample = -1; 1423 adev->mode_info.audio.pin[i].status_bits = 0; 1424 adev->mode_info.audio.pin[i].category_code = 0; 1425 adev->mode_info.audio.pin[i].connected = false; 1426 adev->mode_info.audio.pin[i].offset = pin_offsets[i]; 1427 adev->mode_info.audio.pin[i].id = i; 1428 /* disable audio. it will be set up later */ 1429 /* XXX remove once we switch to ip funcs */ 1430 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1431 } 1432 1433 return 0; 1434 } 1435 1436 static void dce_v10_0_audio_fini(struct amdgpu_device *adev) 1437 { 1438 int i; 1439 1440 if (!amdgpu_audio) 1441 return; 1442 1443 if (!adev->mode_info.audio.enabled) 1444 return; 1445 1446 for (i = 0; i < adev->mode_info.audio.num_pins; i++) 1447 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 1448 1449 adev->mode_info.audio.enabled = false; 1450 } 1451 1452 /* 1453 * update the N and CTS parameters for a given pixel clock rate 1454 */ 1455 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) 1456 { 1457 struct drm_device *dev = encoder->dev; 1458 struct amdgpu_device *adev = dev->dev_private; 1459 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); 1460 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1461 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1462 u32 tmp; 1463 1464 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); 1465 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); 1466 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); 1467 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); 1468 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); 1469 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); 1470 1471 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); 1472 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); 1473 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); 1474 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); 1475 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); 1476 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); 1477 1478 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); 1479 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); 1480 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); 1481 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); 1482 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); 1483 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); 1484 1485 } 1486 1487 /* 1488 * build a HDMI Video Info Frame 1489 */ 1490 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, 1491 void *buffer, size_t size) 1492 { 1493 struct drm_device *dev = encoder->dev; 1494 struct amdgpu_device *adev = dev->dev_private; 1495 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1496 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1497 uint8_t *frame = buffer + 3; 1498 uint8_t *header = buffer; 1499 1500 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, 1501 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 1502 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, 1503 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 1504 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, 1505 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 1506 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, 1507 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); 1508 } 1509 1510 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) 1511 { 1512 struct drm_device *dev = encoder->dev; 1513 struct amdgpu_device *adev = dev->dev_private; 1514 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1515 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1516 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1517 u32 dto_phase = 24 * 1000; 1518 u32 dto_modulo = clock; 1519 u32 tmp; 1520 1521 if (!dig || !dig->afmt) 1522 return; 1523 1524 /* XXX two dtos; generally use dto0 for hdmi */ 1525 /* Express [24MHz / target pixel clock] as an exact rational 1526 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 1527 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 1528 */ 1529 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); 1530 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, 1531 amdgpu_crtc->crtc_id); 1532 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); 1533 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); 1534 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); 1535 } 1536 1537 /* 1538 * update the info frames with the data from the current display mode 1539 */ 1540 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, 1541 struct drm_display_mode *mode) 1542 { 1543 struct drm_device *dev = encoder->dev; 1544 struct amdgpu_device *adev = dev->dev_private; 1545 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1546 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1547 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 1548 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; 1549 struct hdmi_avi_infoframe frame; 1550 ssize_t err; 1551 u32 tmp; 1552 int bpc = 8; 1553 1554 if (!dig || !dig->afmt) 1555 return; 1556 1557 /* Silent, r600_hdmi_enable will raise WARN for us */ 1558 if (!dig->afmt->enabled) 1559 return; 1560 1561 /* hdmi deep color mode general control packets setup, if bpc > 8 */ 1562 if (encoder->crtc) { 1563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); 1564 bpc = amdgpu_crtc->bpc; 1565 } 1566 1567 /* disable audio prior to setting up hw */ 1568 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); 1569 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1570 1571 dce_v10_0_audio_set_dto(encoder, mode->clock); 1572 1573 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1574 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); 1575 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ 1576 1577 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); 1578 1579 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); 1580 switch (bpc) { 1581 case 0: 1582 case 6: 1583 case 8: 1584 case 16: 1585 default: 1586 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); 1587 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 1588 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", 1589 connector->name, bpc); 1590 break; 1591 case 10: 1592 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1593 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); 1594 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", 1595 connector->name); 1596 break; 1597 case 12: 1598 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); 1599 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); 1600 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", 1601 connector->name); 1602 break; 1603 } 1604 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); 1605 1606 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); 1607 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ 1608 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ 1609 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ 1610 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); 1611 1612 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1613 /* enable audio info frames (frames won't be set until audio is enabled) */ 1614 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 1615 /* required for audio info values to be updated */ 1616 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); 1617 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1618 1619 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); 1620 /* required for audio info values to be updated */ 1621 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1622 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1623 1624 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1625 /* anything other than 0 */ 1626 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); 1627 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1628 1629 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ 1630 1631 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1632 /* set the default audio delay */ 1633 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); 1634 /* should be suffient for all audio modes and small enough for all hblanks */ 1635 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); 1636 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1637 1638 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1639 /* allow 60958 channel status fields to be updated */ 1640 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1641 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1642 1643 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); 1644 if (bpc > 8) 1645 /* clear SW CTS value */ 1646 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); 1647 else 1648 /* select SW CTS value */ 1649 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); 1650 /* allow hw to sent ACR packets when required */ 1651 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); 1652 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); 1653 1654 dce_v10_0_afmt_update_ACR(encoder, mode->clock); 1655 1656 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); 1657 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); 1658 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); 1659 1660 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); 1661 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1662 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); 1663 1664 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); 1665 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); 1666 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); 1667 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); 1668 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); 1669 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); 1670 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1671 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); 1672 1673 dce_v10_0_audio_write_speaker_allocation(encoder); 1674 1675 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, 1676 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); 1677 1678 dce_v10_0_afmt_audio_select_pin(encoder); 1679 dce_v10_0_audio_write_sad_regs(encoder); 1680 dce_v10_0_audio_write_latency_fields(encoder, mode); 1681 1682 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); 1683 if (err < 0) { 1684 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 1685 return; 1686 } 1687 1688 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1689 if (err < 0) { 1690 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); 1691 return; 1692 } 1693 1694 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 1695 1696 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); 1697 /* enable AVI info frames */ 1698 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); 1699 /* required for audio info values to be updated */ 1700 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); 1701 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); 1702 1703 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); 1704 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); 1705 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); 1706 1707 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); 1708 /* send audio packets */ 1709 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); 1710 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); 1711 1712 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); 1713 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); 1714 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); 1715 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); 1716 1717 /* enable audio after to setting up hw */ 1718 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); 1719 } 1720 1721 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable) 1722 { 1723 struct drm_device *dev = encoder->dev; 1724 struct amdgpu_device *adev = dev->dev_private; 1725 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 1726 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 1727 1728 if (!dig || !dig->afmt) 1729 return; 1730 1731 /* Silent, r600_hdmi_enable will raise WARN for us */ 1732 if (enable && dig->afmt->enabled) 1733 return; 1734 if (!enable && !dig->afmt->enabled) 1735 return; 1736 1737 if (!enable && dig->afmt->pin) { 1738 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); 1739 dig->afmt->pin = NULL; 1740 } 1741 1742 dig->afmt->enabled = enable; 1743 1744 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", 1745 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); 1746 } 1747 1748 static int dce_v10_0_afmt_init(struct amdgpu_device *adev) 1749 { 1750 int i; 1751 1752 for (i = 0; i < adev->mode_info.num_dig; i++) 1753 adev->mode_info.afmt[i] = NULL; 1754 1755 /* DCE10 has audio blocks tied to DIG encoders */ 1756 for (i = 0; i < adev->mode_info.num_dig; i++) { 1757 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); 1758 if (adev->mode_info.afmt[i]) { 1759 adev->mode_info.afmt[i]->offset = dig_offsets[i]; 1760 adev->mode_info.afmt[i]->id = i; 1761 } else { 1762 int j; 1763 for (j = 0; j < i; j++) { 1764 kfree(adev->mode_info.afmt[j]); 1765 adev->mode_info.afmt[j] = NULL; 1766 } 1767 return -ENOMEM; 1768 } 1769 } 1770 return 0; 1771 } 1772 1773 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev) 1774 { 1775 int i; 1776 1777 for (i = 0; i < adev->mode_info.num_dig; i++) { 1778 kfree(adev->mode_info.afmt[i]); 1779 adev->mode_info.afmt[i] = NULL; 1780 } 1781 } 1782 1783 static const u32 vga_control_regs[6] = 1784 { 1785 mmD1VGA_CONTROL, 1786 mmD2VGA_CONTROL, 1787 mmD3VGA_CONTROL, 1788 mmD4VGA_CONTROL, 1789 mmD5VGA_CONTROL, 1790 mmD6VGA_CONTROL, 1791 }; 1792 1793 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable) 1794 { 1795 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1796 struct drm_device *dev = crtc->dev; 1797 struct amdgpu_device *adev = dev->dev_private; 1798 u32 vga_control; 1799 1800 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; 1801 if (enable) 1802 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); 1803 else 1804 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); 1805 } 1806 1807 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable) 1808 { 1809 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1810 struct drm_device *dev = crtc->dev; 1811 struct amdgpu_device *adev = dev->dev_private; 1812 1813 if (enable) 1814 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); 1815 else 1816 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); 1817 } 1818 1819 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, 1820 struct drm_framebuffer *fb, 1821 int x, int y, int atomic) 1822 { 1823 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 1824 struct drm_device *dev = crtc->dev; 1825 struct amdgpu_device *adev = dev->dev_private; 1826 struct drm_framebuffer *target_fb; 1827 struct drm_gem_object *obj; 1828 struct amdgpu_bo *abo; 1829 uint64_t fb_location, tiling_flags; 1830 uint32_t fb_format, fb_pitch_pixels; 1831 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); 1832 u32 pipe_config; 1833 u32 tmp, viewport_w, viewport_h; 1834 int r; 1835 bool bypass_lut = false; 1836 struct drm_format_name_buf format_name; 1837 1838 /* no fb bound */ 1839 if (!atomic && !crtc->primary->fb) { 1840 DRM_DEBUG_KMS("No FB bound\n"); 1841 return 0; 1842 } 1843 1844 if (atomic) 1845 target_fb = fb; 1846 else 1847 target_fb = crtc->primary->fb; 1848 1849 /* If atomic, assume fb object is pinned & idle & fenced and 1850 * just update base pointers 1851 */ 1852 obj = target_fb->obj[0]; 1853 abo = gem_to_amdgpu_bo(obj); 1854 r = amdgpu_bo_reserve(abo, false); 1855 if (unlikely(r != 0)) 1856 return r; 1857 1858 if (atomic) { 1859 fb_location = amdgpu_bo_gpu_offset(abo); 1860 } else { 1861 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); 1862 if (unlikely(r != 0)) { 1863 amdgpu_bo_unreserve(abo); 1864 return -EINVAL; 1865 } 1866 } 1867 1868 amdgpu_bo_get_tiling_flags(abo, &tiling_flags); 1869 amdgpu_bo_unreserve(abo); 1870 1871 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1872 1873 switch (target_fb->format->format) { 1874 case DRM_FORMAT_C8: 1875 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); 1876 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1877 break; 1878 case DRM_FORMAT_XRGB4444: 1879 case DRM_FORMAT_ARGB4444: 1880 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1881 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); 1882 #ifdef __BIG_ENDIAN 1883 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1884 ENDIAN_8IN16); 1885 #endif 1886 break; 1887 case DRM_FORMAT_XRGB1555: 1888 case DRM_FORMAT_ARGB1555: 1889 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1890 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1891 #ifdef __BIG_ENDIAN 1892 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1893 ENDIAN_8IN16); 1894 #endif 1895 break; 1896 case DRM_FORMAT_BGRX5551: 1897 case DRM_FORMAT_BGRA5551: 1898 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1899 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); 1900 #ifdef __BIG_ENDIAN 1901 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1902 ENDIAN_8IN16); 1903 #endif 1904 break; 1905 case DRM_FORMAT_RGB565: 1906 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); 1907 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1908 #ifdef __BIG_ENDIAN 1909 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1910 ENDIAN_8IN16); 1911 #endif 1912 break; 1913 case DRM_FORMAT_XRGB8888: 1914 case DRM_FORMAT_ARGB8888: 1915 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1916 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); 1917 #ifdef __BIG_ENDIAN 1918 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1919 ENDIAN_8IN32); 1920 #endif 1921 break; 1922 case DRM_FORMAT_XRGB2101010: 1923 case DRM_FORMAT_ARGB2101010: 1924 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1925 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); 1926 #ifdef __BIG_ENDIAN 1927 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1928 ENDIAN_8IN32); 1929 #endif 1930 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1931 bypass_lut = true; 1932 break; 1933 case DRM_FORMAT_BGRX1010102: 1934 case DRM_FORMAT_BGRA1010102: 1935 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); 1936 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); 1937 #ifdef __BIG_ENDIAN 1938 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, 1939 ENDIAN_8IN32); 1940 #endif 1941 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1942 bypass_lut = true; 1943 break; 1944 default: 1945 DRM_ERROR("Unsupported screen format %s\n", 1946 drm_get_format_name(target_fb->format->format, &format_name)); 1947 return -EINVAL; 1948 } 1949 1950 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1951 unsigned bankw, bankh, mtaspect, tile_split, num_banks; 1952 1953 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1954 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1955 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1956 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1957 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1958 1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); 1960 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 1961 ARRAY_2D_TILED_THIN1); 1962 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, 1963 tile_split); 1964 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); 1965 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); 1966 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, 1967 mtaspect); 1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, 1969 ADDR_SURF_MICRO_TILING_DISPLAY); 1970 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1971 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, 1972 ARRAY_1D_TILED_THIN1); 1973 } 1974 1975 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, 1976 pipe_config); 1977 1978 dce_v10_0_vga_enable(crtc, false); 1979 1980 /* Make sure surface address is updated at vertical blank rather than 1981 * horizontal blank 1982 */ 1983 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); 1984 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, 1985 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); 1986 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 1987 1988 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1989 upper_32_bits(fb_location)); 1990 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 1991 upper_32_bits(fb_location)); 1992 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1993 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); 1994 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 1995 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); 1996 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); 1997 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); 1998 1999 /* 2000 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 2001 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 2002 * retain the full precision throughout the pipeline. 2003 */ 2004 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); 2005 if (bypass_lut) 2006 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); 2007 else 2008 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); 2009 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); 2010 2011 if (bypass_lut) 2012 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 2013 2014 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); 2015 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); 2016 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); 2017 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); 2018 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); 2019 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); 2020 2021 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 2022 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); 2023 2024 dce_v10_0_grph_enable(crtc, true); 2025 2026 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, 2027 target_fb->height); 2028 2029 x &= ~3; 2030 y &= ~1; 2031 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, 2032 (x << 16) | y); 2033 viewport_w = crtc->mode.hdisplay; 2034 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 2035 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, 2036 (viewport_w << 16) | viewport_h); 2037 2038 /* set pageflip to happen anywhere in vblank interval */ 2039 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); 2040 2041 if (!atomic && fb && fb != crtc->primary->fb) { 2042 abo = gem_to_amdgpu_bo(fb->obj[0]); 2043 r = amdgpu_bo_reserve(abo, true); 2044 if (unlikely(r != 0)) 2045 return r; 2046 amdgpu_bo_unpin(abo); 2047 amdgpu_bo_unreserve(abo); 2048 } 2049 2050 /* Bytes per pixel may have changed */ 2051 dce_v10_0_bandwidth_update(adev); 2052 2053 return 0; 2054 } 2055 2056 static void dce_v10_0_set_interleave(struct drm_crtc *crtc, 2057 struct drm_display_mode *mode) 2058 { 2059 struct drm_device *dev = crtc->dev; 2060 struct amdgpu_device *adev = dev->dev_private; 2061 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2062 u32 tmp; 2063 2064 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); 2065 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 2066 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); 2067 else 2068 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); 2069 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); 2070 } 2071 2072 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc) 2073 { 2074 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2075 struct drm_device *dev = crtc->dev; 2076 struct amdgpu_device *adev = dev->dev_private; 2077 u16 *r, *g, *b; 2078 int i; 2079 u32 tmp; 2080 2081 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); 2082 2083 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2084 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); 2085 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0); 2086 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2087 2088 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); 2089 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); 2090 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2091 2092 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset); 2093 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1); 2094 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2095 2096 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2097 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); 2098 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0); 2099 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2100 2101 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); 2102 2103 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); 2104 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); 2105 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); 2106 2107 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); 2108 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); 2109 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); 2110 2111 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); 2112 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); 2113 2114 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); 2115 r = crtc->gamma_store; 2116 g = r + crtc->gamma_size; 2117 b = g + crtc->gamma_size; 2118 for (i = 0; i < 256; i++) { 2119 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, 2120 ((*r++ & 0xffc0) << 14) | 2121 ((*g++ & 0xffc0) << 4) | 2122 (*b++ >> 6)); 2123 } 2124 2125 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2126 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); 2127 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0); 2128 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); 2129 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2130 2131 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); 2132 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); 2133 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0); 2134 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2135 2136 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); 2137 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); 2138 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0); 2139 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2140 2141 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); 2142 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); 2143 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0); 2144 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2145 2146 /* XXX match this to the depth of the crtc fmt block, move to modeset? */ 2147 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); 2148 /* XXX this only needs to be programmed once per crtc at startup, 2149 * not sure where the best place for it is 2150 */ 2151 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); 2152 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); 2153 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2154 } 2155 2156 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder) 2157 { 2158 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 2159 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 2160 2161 switch (amdgpu_encoder->encoder_id) { 2162 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 2163 if (dig->linkb) 2164 return 1; 2165 else 2166 return 0; 2167 break; 2168 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 2169 if (dig->linkb) 2170 return 3; 2171 else 2172 return 2; 2173 break; 2174 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 2175 if (dig->linkb) 2176 return 5; 2177 else 2178 return 4; 2179 break; 2180 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 2181 return 6; 2182 break; 2183 default: 2184 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); 2185 return 0; 2186 } 2187 } 2188 2189 /** 2190 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc. 2191 * 2192 * @crtc: drm crtc 2193 * 2194 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 2195 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 2196 * monitors a dedicated PPLL must be used. If a particular board has 2197 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 2198 * as there is no need to program the PLL itself. If we are not able to 2199 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 2200 * avoid messing up an existing monitor. 2201 * 2202 * Asic specific PLL information 2203 * 2204 * DCE 10.x 2205 * Tonga 2206 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 2207 * CI 2208 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 2209 * 2210 */ 2211 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc) 2212 { 2213 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2214 struct drm_device *dev = crtc->dev; 2215 struct amdgpu_device *adev = dev->dev_private; 2216 u32 pll_in_use; 2217 int pll; 2218 2219 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { 2220 if (adev->clock.dp_extclk) 2221 /* skip PPLL programming if using ext clock */ 2222 return ATOM_PPLL_INVALID; 2223 else { 2224 /* use the same PPLL for all DP monitors */ 2225 pll = amdgpu_pll_get_shared_dp_ppll(crtc); 2226 if (pll != ATOM_PPLL_INVALID) 2227 return pll; 2228 } 2229 } else { 2230 /* use the same PPLL for all monitors with the same clock */ 2231 pll = amdgpu_pll_get_shared_nondp_ppll(crtc); 2232 if (pll != ATOM_PPLL_INVALID) 2233 return pll; 2234 } 2235 2236 /* DCE10 has PPLL0, PPLL1, and PPLL2 */ 2237 pll_in_use = amdgpu_pll_get_use_mask(crtc); 2238 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2239 return ATOM_PPLL2; 2240 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2241 return ATOM_PPLL1; 2242 if (!(pll_in_use & (1 << ATOM_PPLL0))) 2243 return ATOM_PPLL0; 2244 DRM_ERROR("unable to allocate a PPLL\n"); 2245 return ATOM_PPLL_INVALID; 2246 } 2247 2248 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock) 2249 { 2250 struct amdgpu_device *adev = crtc->dev->dev_private; 2251 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2252 uint32_t cur_lock; 2253 2254 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); 2255 if (lock) 2256 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); 2257 else 2258 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); 2259 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); 2260 } 2261 2262 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc) 2263 { 2264 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2265 struct amdgpu_device *adev = crtc->dev->dev_private; 2266 u32 tmp; 2267 2268 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2269 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); 2270 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2271 } 2272 2273 static void dce_v10_0_show_cursor(struct drm_crtc *crtc) 2274 { 2275 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2276 struct amdgpu_device *adev = crtc->dev->dev_private; 2277 u32 tmp; 2278 2279 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, 2280 upper_32_bits(amdgpu_crtc->cursor_addr)); 2281 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, 2282 lower_32_bits(amdgpu_crtc->cursor_addr)); 2283 2284 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); 2285 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); 2286 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); 2287 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); 2288 } 2289 2290 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc, 2291 int x, int y) 2292 { 2293 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2294 struct amdgpu_device *adev = crtc->dev->dev_private; 2295 int xorigin = 0, yorigin = 0; 2296 2297 amdgpu_crtc->cursor_x = x; 2298 amdgpu_crtc->cursor_y = y; 2299 2300 /* avivo cursor are offset into the total surface */ 2301 x += crtc->x; 2302 y += crtc->y; 2303 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); 2304 2305 if (x < 0) { 2306 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); 2307 x = 0; 2308 } 2309 if (y < 0) { 2310 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); 2311 y = 0; 2312 } 2313 2314 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); 2315 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); 2316 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, 2317 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); 2318 2319 return 0; 2320 } 2321 2322 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc, 2323 int x, int y) 2324 { 2325 int ret; 2326 2327 dce_v10_0_lock_cursor(crtc, true); 2328 ret = dce_v10_0_cursor_move_locked(crtc, x, y); 2329 dce_v10_0_lock_cursor(crtc, false); 2330 2331 return ret; 2332 } 2333 2334 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, 2335 struct drm_file *file_priv, 2336 uint32_t handle, 2337 uint32_t width, 2338 uint32_t height, 2339 int32_t hot_x, 2340 int32_t hot_y) 2341 { 2342 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2343 struct drm_gem_object *obj; 2344 struct amdgpu_bo *aobj; 2345 int ret; 2346 2347 if (!handle) { 2348 /* turn off cursor */ 2349 dce_v10_0_hide_cursor(crtc); 2350 obj = NULL; 2351 goto unpin; 2352 } 2353 2354 if ((width > amdgpu_crtc->max_cursor_width) || 2355 (height > amdgpu_crtc->max_cursor_height)) { 2356 DRM_ERROR("bad cursor width or height %d x %d\n", width, height); 2357 return -EINVAL; 2358 } 2359 2360 obj = drm_gem_object_lookup(file_priv, handle); 2361 if (!obj) { 2362 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); 2363 return -ENOENT; 2364 } 2365 2366 aobj = gem_to_amdgpu_bo(obj); 2367 ret = amdgpu_bo_reserve(aobj, false); 2368 if (ret != 0) { 2369 drm_gem_object_put_unlocked(obj); 2370 return ret; 2371 } 2372 2373 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr); 2374 amdgpu_bo_unreserve(aobj); 2375 if (ret) { 2376 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret); 2377 drm_gem_object_put_unlocked(obj); 2378 return ret; 2379 } 2380 2381 dce_v10_0_lock_cursor(crtc, true); 2382 2383 if (width != amdgpu_crtc->cursor_width || 2384 height != amdgpu_crtc->cursor_height || 2385 hot_x != amdgpu_crtc->cursor_hot_x || 2386 hot_y != amdgpu_crtc->cursor_hot_y) { 2387 int x, y; 2388 2389 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x; 2390 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y; 2391 2392 dce_v10_0_cursor_move_locked(crtc, x, y); 2393 2394 amdgpu_crtc->cursor_width = width; 2395 amdgpu_crtc->cursor_height = height; 2396 amdgpu_crtc->cursor_hot_x = hot_x; 2397 amdgpu_crtc->cursor_hot_y = hot_y; 2398 } 2399 2400 dce_v10_0_show_cursor(crtc); 2401 dce_v10_0_lock_cursor(crtc, false); 2402 2403 unpin: 2404 if (amdgpu_crtc->cursor_bo) { 2405 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); 2406 ret = amdgpu_bo_reserve(aobj, true); 2407 if (likely(ret == 0)) { 2408 amdgpu_bo_unpin(aobj); 2409 amdgpu_bo_unreserve(aobj); 2410 } 2411 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo); 2412 } 2413 2414 amdgpu_crtc->cursor_bo = obj; 2415 return 0; 2416 } 2417 2418 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) 2419 { 2420 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2421 2422 if (amdgpu_crtc->cursor_bo) { 2423 dce_v10_0_lock_cursor(crtc, true); 2424 2425 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x, 2426 amdgpu_crtc->cursor_y); 2427 2428 dce_v10_0_show_cursor(crtc); 2429 2430 dce_v10_0_lock_cursor(crtc, false); 2431 } 2432 } 2433 2434 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, 2435 u16 *blue, uint32_t size, 2436 struct drm_modeset_acquire_ctx *ctx) 2437 { 2438 dce_v10_0_crtc_load_lut(crtc); 2439 2440 return 0; 2441 } 2442 2443 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) 2444 { 2445 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2446 2447 drm_crtc_cleanup(crtc); 2448 kfree(amdgpu_crtc); 2449 } 2450 2451 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { 2452 .cursor_set2 = dce_v10_0_crtc_cursor_set2, 2453 .cursor_move = dce_v10_0_crtc_cursor_move, 2454 .gamma_set = dce_v10_0_crtc_gamma_set, 2455 .set_config = amdgpu_display_crtc_set_config, 2456 .destroy = dce_v10_0_crtc_destroy, 2457 .page_flip_target = amdgpu_display_crtc_page_flip_target, 2458 }; 2459 2460 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) 2461 { 2462 struct drm_device *dev = crtc->dev; 2463 struct amdgpu_device *adev = dev->dev_private; 2464 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2465 unsigned type; 2466 2467 switch (mode) { 2468 case DRM_MODE_DPMS_ON: 2469 amdgpu_crtc->enabled = true; 2470 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); 2471 dce_v10_0_vga_enable(crtc, true); 2472 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); 2473 dce_v10_0_vga_enable(crtc, false); 2474 /* Make sure VBLANK and PFLIP interrupts are still enabled */ 2475 type = amdgpu_display_crtc_idx_to_irq_type(adev, 2476 amdgpu_crtc->crtc_id); 2477 amdgpu_irq_update(adev, &adev->crtc_irq, type); 2478 amdgpu_irq_update(adev, &adev->pageflip_irq, type); 2479 drm_crtc_vblank_on(crtc); 2480 dce_v10_0_crtc_load_lut(crtc); 2481 break; 2482 case DRM_MODE_DPMS_STANDBY: 2483 case DRM_MODE_DPMS_SUSPEND: 2484 case DRM_MODE_DPMS_OFF: 2485 drm_crtc_vblank_off(crtc); 2486 if (amdgpu_crtc->enabled) { 2487 dce_v10_0_vga_enable(crtc, true); 2488 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); 2489 dce_v10_0_vga_enable(crtc, false); 2490 } 2491 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); 2492 amdgpu_crtc->enabled = false; 2493 break; 2494 } 2495 /* adjust pm to dpms */ 2496 amdgpu_pm_compute_clocks(adev); 2497 } 2498 2499 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc) 2500 { 2501 /* disable crtc pair power gating before programming */ 2502 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); 2503 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); 2504 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2505 } 2506 2507 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc) 2508 { 2509 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2510 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); 2511 } 2512 2513 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) 2514 { 2515 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2516 struct drm_device *dev = crtc->dev; 2517 struct amdgpu_device *adev = dev->dev_private; 2518 struct amdgpu_atom_ss ss; 2519 int i; 2520 2521 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2522 if (crtc->primary->fb) { 2523 int r; 2524 struct amdgpu_bo *abo; 2525 2526 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); 2527 r = amdgpu_bo_reserve(abo, true); 2528 if (unlikely(r)) 2529 DRM_ERROR("failed to reserve abo before unpin\n"); 2530 else { 2531 amdgpu_bo_unpin(abo); 2532 amdgpu_bo_unreserve(abo); 2533 } 2534 } 2535 /* disable the GRPH */ 2536 dce_v10_0_grph_enable(crtc, false); 2537 2538 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); 2539 2540 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2541 if (adev->mode_info.crtcs[i] && 2542 adev->mode_info.crtcs[i]->enabled && 2543 i != amdgpu_crtc->crtc_id && 2544 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { 2545 /* one other crtc is using this pll don't turn 2546 * off the pll 2547 */ 2548 goto done; 2549 } 2550 } 2551 2552 switch (amdgpu_crtc->pll_id) { 2553 case ATOM_PPLL0: 2554 case ATOM_PPLL1: 2555 case ATOM_PPLL2: 2556 /* disable the ppll */ 2557 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, 2558 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2559 break; 2560 default: 2561 break; 2562 } 2563 done: 2564 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2565 amdgpu_crtc->adjusted_clock = 0; 2566 amdgpu_crtc->encoder = NULL; 2567 amdgpu_crtc->connector = NULL; 2568 } 2569 2570 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc, 2571 struct drm_display_mode *mode, 2572 struct drm_display_mode *adjusted_mode, 2573 int x, int y, struct drm_framebuffer *old_fb) 2574 { 2575 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2576 2577 if (!amdgpu_crtc->adjusted_clock) 2578 return -EINVAL; 2579 2580 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); 2581 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); 2582 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2583 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); 2584 amdgpu_atombios_crtc_scaler_setup(crtc); 2585 dce_v10_0_cursor_reset(crtc); 2586 /* update the hw version fpr dpm */ 2587 amdgpu_crtc->hw_mode = *adjusted_mode; 2588 2589 return 0; 2590 } 2591 2592 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc, 2593 const struct drm_display_mode *mode, 2594 struct drm_display_mode *adjusted_mode) 2595 { 2596 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 2597 struct drm_device *dev = crtc->dev; 2598 struct drm_encoder *encoder; 2599 2600 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ 2601 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2602 if (encoder->crtc == crtc) { 2603 amdgpu_crtc->encoder = encoder; 2604 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); 2605 break; 2606 } 2607 } 2608 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { 2609 amdgpu_crtc->encoder = NULL; 2610 amdgpu_crtc->connector = NULL; 2611 return false; 2612 } 2613 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2614 return false; 2615 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2616 return false; 2617 /* pick pll */ 2618 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc); 2619 /* if we can't get a PPLL for a non-DP encoder, fail */ 2620 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && 2621 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) 2622 return false; 2623 2624 return true; 2625 } 2626 2627 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, 2628 struct drm_framebuffer *old_fb) 2629 { 2630 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0); 2631 } 2632 2633 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc, 2634 struct drm_framebuffer *fb, 2635 int x, int y, enum mode_set_atomic state) 2636 { 2637 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1); 2638 } 2639 2640 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { 2641 .dpms = dce_v10_0_crtc_dpms, 2642 .mode_fixup = dce_v10_0_crtc_mode_fixup, 2643 .mode_set = dce_v10_0_crtc_mode_set, 2644 .mode_set_base = dce_v10_0_crtc_set_base, 2645 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic, 2646 .prepare = dce_v10_0_crtc_prepare, 2647 .commit = dce_v10_0_crtc_commit, 2648 .disable = dce_v10_0_crtc_disable, 2649 }; 2650 2651 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) 2652 { 2653 struct amdgpu_crtc *amdgpu_crtc; 2654 2655 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + 2656 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); 2657 if (amdgpu_crtc == NULL) 2658 return -ENOMEM; 2659 2660 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v10_0_crtc_funcs); 2661 2662 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); 2663 amdgpu_crtc->crtc_id = index; 2664 adev->mode_info.crtcs[index] = amdgpu_crtc; 2665 2666 amdgpu_crtc->max_cursor_width = 128; 2667 amdgpu_crtc->max_cursor_height = 128; 2668 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; 2669 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; 2670 2671 switch (amdgpu_crtc->crtc_id) { 2672 case 0: 2673 default: 2674 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; 2675 break; 2676 case 1: 2677 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; 2678 break; 2679 case 2: 2680 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; 2681 break; 2682 case 3: 2683 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; 2684 break; 2685 case 4: 2686 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; 2687 break; 2688 case 5: 2689 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; 2690 break; 2691 } 2692 2693 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; 2694 amdgpu_crtc->adjusted_clock = 0; 2695 amdgpu_crtc->encoder = NULL; 2696 amdgpu_crtc->connector = NULL; 2697 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs); 2698 2699 return 0; 2700 } 2701 2702 static int dce_v10_0_early_init(void *handle) 2703 { 2704 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2705 2706 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; 2707 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; 2708 2709 dce_v10_0_set_display_funcs(adev); 2710 2711 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev); 2712 2713 switch (adev->asic_type) { 2714 case CHIP_FIJI: 2715 case CHIP_TONGA: 2716 adev->mode_info.num_hpd = 6; 2717 adev->mode_info.num_dig = 7; 2718 break; 2719 default: 2720 /* FIXME: not supported yet */ 2721 return -EINVAL; 2722 } 2723 2724 dce_v10_0_set_irq_funcs(adev); 2725 2726 return 0; 2727 } 2728 2729 static int dce_v10_0_sw_init(void *handle) 2730 { 2731 int r, i; 2732 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2733 2734 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2735 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); 2736 if (r) 2737 return r; 2738 } 2739 2740 for (i = 8; i < 20; i += 2) { 2741 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); 2742 if (r) 2743 return r; 2744 } 2745 2746 /* HPD hotplug */ 2747 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq); 2748 if (r) 2749 return r; 2750 2751 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; 2752 2753 adev->ddev->mode_config.async_page_flip = true; 2754 2755 adev->ddev->mode_config.max_width = 16384; 2756 adev->ddev->mode_config.max_height = 16384; 2757 2758 adev->ddev->mode_config.preferred_depth = 24; 2759 adev->ddev->mode_config.prefer_shadow = 1; 2760 2761 adev->ddev->mode_config.fb_base = adev->gmc.aper_base; 2762 2763 r = amdgpu_display_modeset_create_props(adev); 2764 if (r) 2765 return r; 2766 2767 adev->ddev->mode_config.max_width = 16384; 2768 adev->ddev->mode_config.max_height = 16384; 2769 2770 /* allocate crtcs */ 2771 for (i = 0; i < adev->mode_info.num_crtc; i++) { 2772 r = dce_v10_0_crtc_init(adev, i); 2773 if (r) 2774 return r; 2775 } 2776 2777 if (amdgpu_atombios_get_connector_info_from_object_table(adev)) 2778 amdgpu_display_print_display_setup(adev->ddev); 2779 else 2780 return -EINVAL; 2781 2782 /* setup afmt */ 2783 r = dce_v10_0_afmt_init(adev); 2784 if (r) 2785 return r; 2786 2787 r = dce_v10_0_audio_init(adev); 2788 if (r) 2789 return r; 2790 2791 drm_kms_helper_poll_init(adev->ddev); 2792 2793 adev->mode_info.mode_config_initialized = true; 2794 return 0; 2795 } 2796 2797 static int dce_v10_0_sw_fini(void *handle) 2798 { 2799 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2800 2801 kfree(adev->mode_info.bios_hardcoded_edid); 2802 2803 drm_kms_helper_poll_fini(adev->ddev); 2804 2805 dce_v10_0_audio_fini(adev); 2806 2807 dce_v10_0_afmt_fini(adev); 2808 2809 drm_mode_config_cleanup(adev->ddev); 2810 adev->mode_info.mode_config_initialized = false; 2811 2812 return 0; 2813 } 2814 2815 static int dce_v10_0_hw_init(void *handle) 2816 { 2817 int i; 2818 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2819 2820 dce_v10_0_init_golden_registers(adev); 2821 2822 /* disable vga render */ 2823 dce_v10_0_set_vga_render_state(adev, false); 2824 /* init dig PHYs, disp eng pll */ 2825 amdgpu_atombios_encoder_init_dig(adev); 2826 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); 2827 2828 /* initialize hpd */ 2829 dce_v10_0_hpd_init(adev); 2830 2831 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2832 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2833 } 2834 2835 dce_v10_0_pageflip_interrupt_init(adev); 2836 2837 return 0; 2838 } 2839 2840 static int dce_v10_0_hw_fini(void *handle) 2841 { 2842 int i; 2843 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2844 2845 dce_v10_0_hpd_fini(adev); 2846 2847 for (i = 0; i < adev->mode_info.audio.num_pins; i++) { 2848 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); 2849 } 2850 2851 dce_v10_0_pageflip_interrupt_fini(adev); 2852 2853 return 0; 2854 } 2855 2856 static int dce_v10_0_suspend(void *handle) 2857 { 2858 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2859 2860 adev->mode_info.bl_level = 2861 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); 2862 2863 return dce_v10_0_hw_fini(handle); 2864 } 2865 2866 static int dce_v10_0_resume(void *handle) 2867 { 2868 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2869 int ret; 2870 2871 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, 2872 adev->mode_info.bl_level); 2873 2874 ret = dce_v10_0_hw_init(handle); 2875 2876 /* turn on the BL */ 2877 if (adev->mode_info.bl_encoder) { 2878 u8 bl_level = amdgpu_display_backlight_get_level(adev, 2879 adev->mode_info.bl_encoder); 2880 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, 2881 bl_level); 2882 } 2883 2884 return ret; 2885 } 2886 2887 static bool dce_v10_0_is_idle(void *handle) 2888 { 2889 return true; 2890 } 2891 2892 static int dce_v10_0_wait_for_idle(void *handle) 2893 { 2894 return 0; 2895 } 2896 2897 static bool dce_v10_0_check_soft_reset(void *handle) 2898 { 2899 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2900 2901 return dce_v10_0_is_display_hung(adev); 2902 } 2903 2904 static int dce_v10_0_soft_reset(void *handle) 2905 { 2906 u32 srbm_soft_reset = 0, tmp; 2907 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2908 2909 if (dce_v10_0_is_display_hung(adev)) 2910 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 2911 2912 if (srbm_soft_reset) { 2913 tmp = RREG32(mmSRBM_SOFT_RESET); 2914 tmp |= srbm_soft_reset; 2915 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 2916 WREG32(mmSRBM_SOFT_RESET, tmp); 2917 tmp = RREG32(mmSRBM_SOFT_RESET); 2918 2919 udelay(50); 2920 2921 tmp &= ~srbm_soft_reset; 2922 WREG32(mmSRBM_SOFT_RESET, tmp); 2923 tmp = RREG32(mmSRBM_SOFT_RESET); 2924 2925 /* Wait a little for things to settle down */ 2926 udelay(50); 2927 } 2928 return 0; 2929 } 2930 2931 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, 2932 int crtc, 2933 enum amdgpu_interrupt_state state) 2934 { 2935 u32 lb_interrupt_mask; 2936 2937 if (crtc >= adev->mode_info.num_crtc) { 2938 DRM_DEBUG("invalid crtc %d\n", crtc); 2939 return; 2940 } 2941 2942 switch (state) { 2943 case AMDGPU_IRQ_STATE_DISABLE: 2944 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2945 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2946 VBLANK_INTERRUPT_MASK, 0); 2947 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2948 break; 2949 case AMDGPU_IRQ_STATE_ENABLE: 2950 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2951 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2952 VBLANK_INTERRUPT_MASK, 1); 2953 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2954 break; 2955 default: 2956 break; 2957 } 2958 } 2959 2960 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, 2961 int crtc, 2962 enum amdgpu_interrupt_state state) 2963 { 2964 u32 lb_interrupt_mask; 2965 2966 if (crtc >= adev->mode_info.num_crtc) { 2967 DRM_DEBUG("invalid crtc %d\n", crtc); 2968 return; 2969 } 2970 2971 switch (state) { 2972 case AMDGPU_IRQ_STATE_DISABLE: 2973 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2974 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2975 VLINE_INTERRUPT_MASK, 0); 2976 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2977 break; 2978 case AMDGPU_IRQ_STATE_ENABLE: 2979 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); 2980 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, 2981 VLINE_INTERRUPT_MASK, 1); 2982 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); 2983 break; 2984 default: 2985 break; 2986 } 2987 } 2988 2989 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev, 2990 struct amdgpu_irq_src *source, 2991 unsigned hpd, 2992 enum amdgpu_interrupt_state state) 2993 { 2994 u32 tmp; 2995 2996 if (hpd >= adev->mode_info.num_hpd) { 2997 DRM_DEBUG("invalid hdp %d\n", hpd); 2998 return 0; 2999 } 3000 3001 switch (state) { 3002 case AMDGPU_IRQ_STATE_DISABLE: 3003 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3004 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); 3005 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3006 break; 3007 case AMDGPU_IRQ_STATE_ENABLE: 3008 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3009 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); 3010 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3011 break; 3012 default: 3013 break; 3014 } 3015 3016 return 0; 3017 } 3018 3019 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev, 3020 struct amdgpu_irq_src *source, 3021 unsigned type, 3022 enum amdgpu_interrupt_state state) 3023 { 3024 switch (type) { 3025 case AMDGPU_CRTC_IRQ_VBLANK1: 3026 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state); 3027 break; 3028 case AMDGPU_CRTC_IRQ_VBLANK2: 3029 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state); 3030 break; 3031 case AMDGPU_CRTC_IRQ_VBLANK3: 3032 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state); 3033 break; 3034 case AMDGPU_CRTC_IRQ_VBLANK4: 3035 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state); 3036 break; 3037 case AMDGPU_CRTC_IRQ_VBLANK5: 3038 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state); 3039 break; 3040 case AMDGPU_CRTC_IRQ_VBLANK6: 3041 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state); 3042 break; 3043 case AMDGPU_CRTC_IRQ_VLINE1: 3044 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state); 3045 break; 3046 case AMDGPU_CRTC_IRQ_VLINE2: 3047 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state); 3048 break; 3049 case AMDGPU_CRTC_IRQ_VLINE3: 3050 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state); 3051 break; 3052 case AMDGPU_CRTC_IRQ_VLINE4: 3053 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state); 3054 break; 3055 case AMDGPU_CRTC_IRQ_VLINE5: 3056 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state); 3057 break; 3058 case AMDGPU_CRTC_IRQ_VLINE6: 3059 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state); 3060 break; 3061 default: 3062 break; 3063 } 3064 return 0; 3065 } 3066 3067 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev, 3068 struct amdgpu_irq_src *src, 3069 unsigned type, 3070 enum amdgpu_interrupt_state state) 3071 { 3072 u32 reg; 3073 3074 if (type >= adev->mode_info.num_crtc) { 3075 DRM_ERROR("invalid pageflip crtc %d\n", type); 3076 return -EINVAL; 3077 } 3078 3079 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]); 3080 if (state == AMDGPU_IRQ_STATE_DISABLE) 3081 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3082 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3083 else 3084 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], 3085 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); 3086 3087 return 0; 3088 } 3089 3090 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev, 3091 struct amdgpu_irq_src *source, 3092 struct amdgpu_iv_entry *entry) 3093 { 3094 unsigned long flags; 3095 unsigned crtc_id; 3096 struct amdgpu_crtc *amdgpu_crtc; 3097 struct amdgpu_flip_work *works; 3098 3099 crtc_id = (entry->src_id - 8) >> 1; 3100 amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; 3101 3102 if (crtc_id >= adev->mode_info.num_crtc) { 3103 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); 3104 return -EINVAL; 3105 } 3106 3107 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) & 3108 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) 3109 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id], 3110 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); 3111 3112 /* IRQ could occur when in initial stage */ 3113 if (amdgpu_crtc == NULL) 3114 return 0; 3115 3116 spin_lock_irqsave(&adev->ddev->event_lock, flags); 3117 works = amdgpu_crtc->pflip_works; 3118 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) { 3119 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " 3120 "AMDGPU_FLIP_SUBMITTED(%d)\n", 3121 amdgpu_crtc->pflip_status, 3122 AMDGPU_FLIP_SUBMITTED); 3123 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3124 return 0; 3125 } 3126 3127 /* page flip completed. clean up */ 3128 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; 3129 amdgpu_crtc->pflip_works = NULL; 3130 3131 /* wakeup usersapce */ 3132 if (works->event) 3133 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event); 3134 3135 spin_unlock_irqrestore(&adev->ddev->event_lock, flags); 3136 3137 drm_crtc_vblank_put(&amdgpu_crtc->base); 3138 schedule_work(&works->unpin_work); 3139 3140 return 0; 3141 } 3142 3143 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, 3144 int hpd) 3145 { 3146 u32 tmp; 3147 3148 if (hpd >= adev->mode_info.num_hpd) { 3149 DRM_DEBUG("invalid hdp %d\n", hpd); 3150 return; 3151 } 3152 3153 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); 3154 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); 3155 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); 3156 } 3157 3158 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev, 3159 int crtc) 3160 { 3161 u32 tmp; 3162 3163 if (crtc >= adev->mode_info.num_crtc) { 3164 DRM_DEBUG("invalid crtc %d\n", crtc); 3165 return; 3166 } 3167 3168 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); 3169 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); 3170 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); 3171 } 3172 3173 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev, 3174 int crtc) 3175 { 3176 u32 tmp; 3177 3178 if (crtc >= adev->mode_info.num_crtc) { 3179 DRM_DEBUG("invalid crtc %d\n", crtc); 3180 return; 3181 } 3182 3183 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); 3184 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); 3185 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); 3186 } 3187 3188 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev, 3189 struct amdgpu_irq_src *source, 3190 struct amdgpu_iv_entry *entry) 3191 { 3192 unsigned crtc = entry->src_id - 1; 3193 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); 3194 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc); 3195 3196 switch (entry->src_data[0]) { 3197 case 0: /* vblank */ 3198 if (disp_int & interrupt_status_offsets[crtc].vblank) 3199 dce_v10_0_crtc_vblank_int_ack(adev, crtc); 3200 else 3201 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3202 3203 if (amdgpu_irq_enabled(adev, source, irq_type)) { 3204 drm_handle_vblank(adev->ddev, crtc); 3205 } 3206 DRM_DEBUG("IH: D%d vblank\n", crtc + 1); 3207 3208 break; 3209 case 1: /* vline */ 3210 if (disp_int & interrupt_status_offsets[crtc].vline) 3211 dce_v10_0_crtc_vline_int_ack(adev, crtc); 3212 else 3213 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n"); 3214 3215 DRM_DEBUG("IH: D%d vline\n", crtc + 1); 3216 3217 break; 3218 default: 3219 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3220 break; 3221 } 3222 3223 return 0; 3224 } 3225 3226 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev, 3227 struct amdgpu_irq_src *source, 3228 struct amdgpu_iv_entry *entry) 3229 { 3230 uint32_t disp_int, mask; 3231 unsigned hpd; 3232 3233 if (entry->src_data[0] >= adev->mode_info.num_hpd) { 3234 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]); 3235 return 0; 3236 } 3237 3238 hpd = entry->src_data[0]; 3239 disp_int = RREG32(interrupt_status_offsets[hpd].reg); 3240 mask = interrupt_status_offsets[hpd].hpd; 3241 3242 if (disp_int & mask) { 3243 dce_v10_0_hpd_int_ack(adev, hpd); 3244 schedule_work(&adev->hotplug_work); 3245 DRM_DEBUG("IH: HPD%d\n", hpd + 1); 3246 } 3247 3248 return 0; 3249 } 3250 3251 static int dce_v10_0_set_clockgating_state(void *handle, 3252 enum amd_clockgating_state state) 3253 { 3254 return 0; 3255 } 3256 3257 static int dce_v10_0_set_powergating_state(void *handle, 3258 enum amd_powergating_state state) 3259 { 3260 return 0; 3261 } 3262 3263 static const struct amd_ip_funcs dce_v10_0_ip_funcs = { 3264 .name = "dce_v10_0", 3265 .early_init = dce_v10_0_early_init, 3266 .late_init = NULL, 3267 .sw_init = dce_v10_0_sw_init, 3268 .sw_fini = dce_v10_0_sw_fini, 3269 .hw_init = dce_v10_0_hw_init, 3270 .hw_fini = dce_v10_0_hw_fini, 3271 .suspend = dce_v10_0_suspend, 3272 .resume = dce_v10_0_resume, 3273 .is_idle = dce_v10_0_is_idle, 3274 .wait_for_idle = dce_v10_0_wait_for_idle, 3275 .check_soft_reset = dce_v10_0_check_soft_reset, 3276 .soft_reset = dce_v10_0_soft_reset, 3277 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3278 .set_powergating_state = dce_v10_0_set_powergating_state, 3279 }; 3280 3281 static void 3282 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder, 3283 struct drm_display_mode *mode, 3284 struct drm_display_mode *adjusted_mode) 3285 { 3286 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3287 3288 amdgpu_encoder->pixel_clock = adjusted_mode->clock; 3289 3290 /* need to call this here rather than in prepare() since we need some crtc info */ 3291 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3292 3293 /* set scaler clears this on some chips */ 3294 dce_v10_0_set_interleave(encoder->crtc, mode); 3295 3296 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 3297 dce_v10_0_afmt_enable(encoder, true); 3298 dce_v10_0_afmt_setmode(encoder, adjusted_mode); 3299 } 3300 } 3301 3302 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder) 3303 { 3304 struct amdgpu_device *adev = encoder->dev->dev_private; 3305 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3306 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); 3307 3308 if ((amdgpu_encoder->active_device & 3309 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || 3310 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != 3311 ENCODER_OBJECT_ID_NONE)) { 3312 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 3313 if (dig) { 3314 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); 3315 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) 3316 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; 3317 } 3318 } 3319 3320 amdgpu_atombios_scratch_regs_lock(adev, true); 3321 3322 if (connector) { 3323 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 3324 3325 /* select the clock/data port if it uses a router */ 3326 if (amdgpu_connector->router.cd_valid) 3327 amdgpu_i2c_router_select_cd_port(amdgpu_connector); 3328 3329 /* turn eDP panel on for mode set */ 3330 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3331 amdgpu_atombios_encoder_set_edp_panel_power(connector, 3332 ATOM_TRANSMITTER_ACTION_POWER_ON); 3333 } 3334 3335 /* this is needed for the pll/ss setup to work correctly in some cases */ 3336 amdgpu_atombios_encoder_set_crtc_source(encoder); 3337 /* set up the FMT blocks */ 3338 dce_v10_0_program_fmt(encoder); 3339 } 3340 3341 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder) 3342 { 3343 struct drm_device *dev = encoder->dev; 3344 struct amdgpu_device *adev = dev->dev_private; 3345 3346 /* need to call this here as we need the crtc set up */ 3347 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); 3348 amdgpu_atombios_scratch_regs_lock(adev, false); 3349 } 3350 3351 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder) 3352 { 3353 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3354 struct amdgpu_encoder_atom_dig *dig; 3355 3356 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); 3357 3358 if (amdgpu_atombios_encoder_is_digital(encoder)) { 3359 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 3360 dce_v10_0_afmt_enable(encoder, false); 3361 dig = amdgpu_encoder->enc_priv; 3362 dig->dig_encoder = -1; 3363 } 3364 amdgpu_encoder->active_device = 0; 3365 } 3366 3367 /* these are handled by the primary encoders */ 3368 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder) 3369 { 3370 3371 } 3372 3373 static void dce_v10_0_ext_commit(struct drm_encoder *encoder) 3374 { 3375 3376 } 3377 3378 static void 3379 dce_v10_0_ext_mode_set(struct drm_encoder *encoder, 3380 struct drm_display_mode *mode, 3381 struct drm_display_mode *adjusted_mode) 3382 { 3383 3384 } 3385 3386 static void dce_v10_0_ext_disable(struct drm_encoder *encoder) 3387 { 3388 3389 } 3390 3391 static void 3392 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode) 3393 { 3394 3395 } 3396 3397 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = { 3398 .dpms = dce_v10_0_ext_dpms, 3399 .prepare = dce_v10_0_ext_prepare, 3400 .mode_set = dce_v10_0_ext_mode_set, 3401 .commit = dce_v10_0_ext_commit, 3402 .disable = dce_v10_0_ext_disable, 3403 /* no detect for TMDS/LVDS yet */ 3404 }; 3405 3406 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = { 3407 .dpms = amdgpu_atombios_encoder_dpms, 3408 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3409 .prepare = dce_v10_0_encoder_prepare, 3410 .mode_set = dce_v10_0_encoder_mode_set, 3411 .commit = dce_v10_0_encoder_commit, 3412 .disable = dce_v10_0_encoder_disable, 3413 .detect = amdgpu_atombios_encoder_dig_detect, 3414 }; 3415 3416 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = { 3417 .dpms = amdgpu_atombios_encoder_dpms, 3418 .mode_fixup = amdgpu_atombios_encoder_mode_fixup, 3419 .prepare = dce_v10_0_encoder_prepare, 3420 .mode_set = dce_v10_0_encoder_mode_set, 3421 .commit = dce_v10_0_encoder_commit, 3422 .detect = amdgpu_atombios_encoder_dac_detect, 3423 }; 3424 3425 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder) 3426 { 3427 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 3428 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3429 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); 3430 kfree(amdgpu_encoder->enc_priv); 3431 drm_encoder_cleanup(encoder); 3432 kfree(amdgpu_encoder); 3433 } 3434 3435 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = { 3436 .destroy = dce_v10_0_encoder_destroy, 3437 }; 3438 3439 static void dce_v10_0_encoder_add(struct amdgpu_device *adev, 3440 uint32_t encoder_enum, 3441 uint32_t supported_device, 3442 u16 caps) 3443 { 3444 struct drm_device *dev = adev->ddev; 3445 struct drm_encoder *encoder; 3446 struct amdgpu_encoder *amdgpu_encoder; 3447 3448 /* see if we already added it */ 3449 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 3450 amdgpu_encoder = to_amdgpu_encoder(encoder); 3451 if (amdgpu_encoder->encoder_enum == encoder_enum) { 3452 amdgpu_encoder->devices |= supported_device; 3453 return; 3454 } 3455 3456 } 3457 3458 /* add a new one */ 3459 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); 3460 if (!amdgpu_encoder) 3461 return; 3462 3463 encoder = &amdgpu_encoder->base; 3464 switch (adev->mode_info.num_crtc) { 3465 case 1: 3466 encoder->possible_crtcs = 0x1; 3467 break; 3468 case 2: 3469 default: 3470 encoder->possible_crtcs = 0x3; 3471 break; 3472 case 4: 3473 encoder->possible_crtcs = 0xf; 3474 break; 3475 case 6: 3476 encoder->possible_crtcs = 0x3f; 3477 break; 3478 } 3479 3480 amdgpu_encoder->enc_priv = NULL; 3481 3482 amdgpu_encoder->encoder_enum = encoder_enum; 3483 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 3484 amdgpu_encoder->devices = supported_device; 3485 amdgpu_encoder->rmx_type = RMX_OFF; 3486 amdgpu_encoder->underscan_type = UNDERSCAN_OFF; 3487 amdgpu_encoder->is_ext_encoder = false; 3488 amdgpu_encoder->caps = caps; 3489 3490 switch (amdgpu_encoder->encoder_id) { 3491 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: 3492 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: 3493 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3494 DRM_MODE_ENCODER_DAC, NULL); 3495 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs); 3496 break; 3497 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 3498 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: 3499 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: 3500 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: 3501 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: 3502 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3503 amdgpu_encoder->rmx_type = RMX_FULL; 3504 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3505 DRM_MODE_ENCODER_LVDS, NULL); 3506 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); 3507 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3508 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3509 DRM_MODE_ENCODER_DAC, NULL); 3510 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3511 } else { 3512 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3513 DRM_MODE_ENCODER_TMDS, NULL); 3514 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); 3515 } 3516 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs); 3517 break; 3518 case ENCODER_OBJECT_ID_SI170B: 3519 case ENCODER_OBJECT_ID_CH7303: 3520 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: 3521 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: 3522 case ENCODER_OBJECT_ID_TITFP513: 3523 case ENCODER_OBJECT_ID_VT1623: 3524 case ENCODER_OBJECT_ID_HDMI_SI1930: 3525 case ENCODER_OBJECT_ID_TRAVIS: 3526 case ENCODER_OBJECT_ID_NUTMEG: 3527 /* these are handled by the primary encoders */ 3528 amdgpu_encoder->is_ext_encoder = true; 3529 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 3530 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3531 DRM_MODE_ENCODER_LVDS, NULL); 3532 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) 3533 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3534 DRM_MODE_ENCODER_DAC, NULL); 3535 else 3536 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs, 3537 DRM_MODE_ENCODER_TMDS, NULL); 3538 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs); 3539 break; 3540 } 3541 } 3542 3543 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = { 3544 .bandwidth_update = &dce_v10_0_bandwidth_update, 3545 .vblank_get_counter = &dce_v10_0_vblank_get_counter, 3546 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, 3547 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, 3548 .hpd_sense = &dce_v10_0_hpd_sense, 3549 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity, 3550 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg, 3551 .page_flip = &dce_v10_0_page_flip, 3552 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos, 3553 .add_encoder = &dce_v10_0_encoder_add, 3554 .add_connector = &amdgpu_connector_add, 3555 }; 3556 3557 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev) 3558 { 3559 if (adev->mode_info.funcs == NULL) 3560 adev->mode_info.funcs = &dce_v10_0_display_funcs; 3561 } 3562 3563 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = { 3564 .set = dce_v10_0_set_crtc_irq_state, 3565 .process = dce_v10_0_crtc_irq, 3566 }; 3567 3568 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = { 3569 .set = dce_v10_0_set_pageflip_irq_state, 3570 .process = dce_v10_0_pageflip_irq, 3571 }; 3572 3573 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = { 3574 .set = dce_v10_0_set_hpd_irq_state, 3575 .process = dce_v10_0_hpd_irq, 3576 }; 3577 3578 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev) 3579 { 3580 if (adev->mode_info.num_crtc > 0) 3581 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc; 3582 else 3583 adev->crtc_irq.num_types = 0; 3584 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs; 3585 3586 adev->pageflip_irq.num_types = adev->mode_info.num_crtc; 3587 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs; 3588 3589 adev->hpd_irq.num_types = adev->mode_info.num_hpd; 3590 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs; 3591 } 3592 3593 const struct amdgpu_ip_block_version dce_v10_0_ip_block = 3594 { 3595 .type = AMD_IP_BLOCK_TYPE_DCE, 3596 .major = 10, 3597 .minor = 0, 3598 .rev = 0, 3599 .funcs = &dce_v10_0_ip_funcs, 3600 }; 3601 3602 const struct amdgpu_ip_block_version dce_v10_1_ip_block = 3603 { 3604 .type = AMD_IP_BLOCK_TYPE_DCE, 3605 .major = 10, 3606 .minor = 1, 3607 .rev = 0, 3608 .funcs = &dce_v10_0_ip_funcs, 3609 }; 3610