1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #include <drm/drm_fourcc.h>
25 #include <drm/drm_modeset_helper.h>
26 #include <drm/drm_modeset_helper_vtables.h>
27 #include <drm/drm_vblank.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_pm.h"
31 #include "amdgpu_i2c.h"
32 #include "vid.h"
33 #include "atom.h"
34 #include "amdgpu_atombios.h"
35 #include "atombios_crtc.h"
36 #include "atombios_encoders.h"
37 #include "amdgpu_pll.h"
38 #include "amdgpu_connectors.h"
39 #include "amdgpu_display.h"
40 #include "dce_v10_0.h"
41 
42 #include "dce/dce_10_0_d.h"
43 #include "dce/dce_10_0_sh_mask.h"
44 #include "dce/dce_10_0_enum.h"
45 #include "oss/oss_3_0_d.h"
46 #include "oss/oss_3_0_sh_mask.h"
47 #include "gmc/gmc_8_1_d.h"
48 #include "gmc/gmc_8_1_sh_mask.h"
49 
50 #include "ivsrcid/ivsrcid_vislands30.h"
51 
52 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
53 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
54 
55 static const u32 crtc_offsets[] = {
56 	CRTC0_REGISTER_OFFSET,
57 	CRTC1_REGISTER_OFFSET,
58 	CRTC2_REGISTER_OFFSET,
59 	CRTC3_REGISTER_OFFSET,
60 	CRTC4_REGISTER_OFFSET,
61 	CRTC5_REGISTER_OFFSET,
62 	CRTC6_REGISTER_OFFSET
63 };
64 
65 static const u32 hpd_offsets[] = {
66 	HPD0_REGISTER_OFFSET,
67 	HPD1_REGISTER_OFFSET,
68 	HPD2_REGISTER_OFFSET,
69 	HPD3_REGISTER_OFFSET,
70 	HPD4_REGISTER_OFFSET,
71 	HPD5_REGISTER_OFFSET
72 };
73 
74 static const uint32_t dig_offsets[] = {
75 	DIG0_REGISTER_OFFSET,
76 	DIG1_REGISTER_OFFSET,
77 	DIG2_REGISTER_OFFSET,
78 	DIG3_REGISTER_OFFSET,
79 	DIG4_REGISTER_OFFSET,
80 	DIG5_REGISTER_OFFSET,
81 	DIG6_REGISTER_OFFSET
82 };
83 
84 static const struct {
85 	uint32_t        reg;
86 	uint32_t        vblank;
87 	uint32_t        vline;
88 	uint32_t        hpd;
89 
90 } interrupt_status_offsets[] = { {
91 	.reg = mmDISP_INTERRUPT_STATUS,
92 	.vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
93 	.vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
94 	.hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
95 }, {
96 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
97 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
98 	.vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
99 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
100 }, {
101 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
102 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
103 	.vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
104 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
105 }, {
106 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
107 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
108 	.vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
109 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
110 }, {
111 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
112 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
113 	.vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
114 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
115 }, {
116 	.reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
117 	.vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
118 	.vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
119 	.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
120 } };
121 
122 static const u32 golden_settings_tonga_a11[] = {
123 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
124 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
125 	mmFBC_MISC, 0x1f311fff, 0x12300000,
126 	mmHDMI_CONTROL, 0x31000111, 0x00000011,
127 };
128 
129 static const u32 tonga_mgcg_cgcg_init[] = {
130 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
131 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
132 };
133 
134 static const u32 golden_settings_fiji_a10[] = {
135 	mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
136 	mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
137 	mmFBC_MISC, 0x1f311fff, 0x12300000,
138 	mmHDMI_CONTROL, 0x31000111, 0x00000011,
139 };
140 
141 static const u32 fiji_mgcg_cgcg_init[] = {
142 	mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
143 	mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
144 };
145 
146 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
147 {
148 	switch (adev->asic_type) {
149 	case CHIP_FIJI:
150 		amdgpu_device_program_register_sequence(adev,
151 							fiji_mgcg_cgcg_init,
152 							ARRAY_SIZE(fiji_mgcg_cgcg_init));
153 		amdgpu_device_program_register_sequence(adev,
154 							golden_settings_fiji_a10,
155 							ARRAY_SIZE(golden_settings_fiji_a10));
156 		break;
157 	case CHIP_TONGA:
158 		amdgpu_device_program_register_sequence(adev,
159 							tonga_mgcg_cgcg_init,
160 							ARRAY_SIZE(tonga_mgcg_cgcg_init));
161 		amdgpu_device_program_register_sequence(adev,
162 							golden_settings_tonga_a11,
163 							ARRAY_SIZE(golden_settings_tonga_a11));
164 		break;
165 	default:
166 		break;
167 	}
168 }
169 
170 static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
171 				     u32 block_offset, u32 reg)
172 {
173 	unsigned long flags;
174 	u32 r;
175 
176 	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
177 	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
178 	r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
179 	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
180 
181 	return r;
182 }
183 
184 static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
185 				      u32 block_offset, u32 reg, u32 v)
186 {
187 	unsigned long flags;
188 
189 	spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
190 	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
191 	WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
192 	spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
193 }
194 
195 static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
196 {
197 	if (crtc >= adev->mode_info.num_crtc)
198 		return 0;
199 	else
200 		return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
201 }
202 
203 static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
204 {
205 	unsigned i;
206 
207 	/* Enable pflip interrupts */
208 	for (i = 0; i < adev->mode_info.num_crtc; i++)
209 		amdgpu_irq_get(adev, &adev->pageflip_irq, i);
210 }
211 
212 static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
213 {
214 	unsigned i;
215 
216 	/* Disable pflip interrupts */
217 	for (i = 0; i < adev->mode_info.num_crtc; i++)
218 		amdgpu_irq_put(adev, &adev->pageflip_irq, i);
219 }
220 
221 /**
222  * dce_v10_0_page_flip - pageflip callback.
223  *
224  * @adev: amdgpu_device pointer
225  * @crtc_id: crtc to cleanup pageflip on
226  * @crtc_base: new address of the crtc (GPU MC address)
227  * @async: asynchronous flip
228  *
229  * Triggers the actual pageflip by updating the primary
230  * surface base address.
231  */
232 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
233 				int crtc_id, u64 crtc_base, bool async)
234 {
235 	struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
236 	struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
237 	u32 tmp;
238 
239 	/* flip at hsync for async, default is vsync */
240 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
241 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
242 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
243 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
244 	/* update pitch */
245 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
246 	       fb->pitches[0] / fb->format->cpp[0]);
247 	/* update the primary scanout address */
248 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
249 	       upper_32_bits(crtc_base));
250 	/* writing to the low address triggers the update */
251 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
252 	       lower_32_bits(crtc_base));
253 	/* post the write */
254 	RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
255 }
256 
257 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
258 					u32 *vbl, u32 *position)
259 {
260 	if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
261 		return -EINVAL;
262 
263 	*vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
264 	*position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
265 
266 	return 0;
267 }
268 
269 /**
270  * dce_v10_0_hpd_sense - hpd sense callback.
271  *
272  * @adev: amdgpu_device pointer
273  * @hpd: hpd (hotplug detect) pin
274  *
275  * Checks if a digital monitor is connected (evergreen+).
276  * Returns true if connected, false if not connected.
277  */
278 static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
279 			       enum amdgpu_hpd_id hpd)
280 {
281 	bool connected = false;
282 
283 	if (hpd >= adev->mode_info.num_hpd)
284 		return connected;
285 
286 	if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
287 	    DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
288 		connected = true;
289 
290 	return connected;
291 }
292 
293 /**
294  * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
295  *
296  * @adev: amdgpu_device pointer
297  * @hpd: hpd (hotplug detect) pin
298  *
299  * Set the polarity of the hpd pin (evergreen+).
300  */
301 static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
302 				      enum amdgpu_hpd_id hpd)
303 {
304 	u32 tmp;
305 	bool connected = dce_v10_0_hpd_sense(adev, hpd);
306 
307 	if (hpd >= adev->mode_info.num_hpd)
308 		return;
309 
310 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
311 	if (connected)
312 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
313 	else
314 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
315 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
316 }
317 
318 /**
319  * dce_v10_0_hpd_init - hpd setup callback.
320  *
321  * @adev: amdgpu_device pointer
322  *
323  * Setup the hpd pins used by the card (evergreen+).
324  * Enable the pin, set the polarity, and enable the hpd interrupts.
325  */
326 static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
327 {
328 	struct drm_device *dev = adev_to_drm(adev);
329 	struct drm_connector *connector;
330 	struct drm_connector_list_iter iter;
331 	u32 tmp;
332 
333 	drm_connector_list_iter_begin(dev, &iter);
334 	drm_for_each_connector_iter(connector, &iter) {
335 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
336 
337 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
338 			continue;
339 
340 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
341 		    connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
342 			/* don't try to enable hpd on eDP or LVDS avoid breaking the
343 			 * aux dp channel on imac and help (but not completely fix)
344 			 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
345 			 * also avoid interrupt storms during dpms.
346 			 */
347 			tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
348 			tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
349 			WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
350 			continue;
351 		}
352 
353 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
354 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
355 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
356 
357 		tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
358 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
359 				    DC_HPD_CONNECT_INT_DELAY,
360 				    AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
361 		tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
362 				    DC_HPD_DISCONNECT_INT_DELAY,
363 				    AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
364 		WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
365 
366 		dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
367 		amdgpu_irq_get(adev, &adev->hpd_irq,
368 			       amdgpu_connector->hpd.hpd);
369 	}
370 	drm_connector_list_iter_end(&iter);
371 }
372 
373 /**
374  * dce_v10_0_hpd_fini - hpd tear down callback.
375  *
376  * @adev: amdgpu_device pointer
377  *
378  * Tear down the hpd pins used by the card (evergreen+).
379  * Disable the hpd interrupts.
380  */
381 static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
382 {
383 	struct drm_device *dev = adev_to_drm(adev);
384 	struct drm_connector *connector;
385 	struct drm_connector_list_iter iter;
386 	u32 tmp;
387 
388 	drm_connector_list_iter_begin(dev, &iter);
389 	drm_for_each_connector_iter(connector, &iter) {
390 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
391 
392 		if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
393 			continue;
394 
395 		tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
396 		tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
397 		WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
398 
399 		amdgpu_irq_put(adev, &adev->hpd_irq,
400 			       amdgpu_connector->hpd.hpd);
401 	}
402 	drm_connector_list_iter_end(&iter);
403 }
404 
405 static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
406 {
407 	return mmDC_GPIO_HPD_A;
408 }
409 
410 static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
411 {
412 	u32 crtc_hung = 0;
413 	u32 crtc_status[6];
414 	u32 i, j, tmp;
415 
416 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
417 		tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
418 		if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
419 			crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
420 			crtc_hung |= (1 << i);
421 		}
422 	}
423 
424 	for (j = 0; j < 10; j++) {
425 		for (i = 0; i < adev->mode_info.num_crtc; i++) {
426 			if (crtc_hung & (1 << i)) {
427 				tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
428 				if (tmp != crtc_status[i])
429 					crtc_hung &= ~(1 << i);
430 			}
431 		}
432 		if (crtc_hung == 0)
433 			return false;
434 		udelay(100);
435 	}
436 
437 	return true;
438 }
439 
440 static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
441 					   bool render)
442 {
443 	u32 tmp;
444 
445 	/* Lockout access through VGA aperture*/
446 	tmp = RREG32(mmVGA_HDP_CONTROL);
447 	if (render)
448 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
449 	else
450 		tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
451 	WREG32(mmVGA_HDP_CONTROL, tmp);
452 
453 	/* disable VGA render */
454 	tmp = RREG32(mmVGA_RENDER_CONTROL);
455 	if (render)
456 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
457 	else
458 		tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
459 	WREG32(mmVGA_RENDER_CONTROL, tmp);
460 }
461 
462 static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
463 {
464 	int num_crtc = 0;
465 
466 	switch (adev->asic_type) {
467 	case CHIP_FIJI:
468 	case CHIP_TONGA:
469 		num_crtc = 6;
470 		break;
471 	default:
472 		num_crtc = 0;
473 	}
474 	return num_crtc;
475 }
476 
477 void dce_v10_0_disable_dce(struct amdgpu_device *adev)
478 {
479 	/*Disable VGA render and enabled crtc, if has DCE engine*/
480 	if (amdgpu_atombios_has_dce_engine_info(adev)) {
481 		u32 tmp;
482 		int crtc_enabled, i;
483 
484 		dce_v10_0_set_vga_render_state(adev, false);
485 
486 		/*Disable crtc*/
487 		for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
488 			crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
489 									 CRTC_CONTROL, CRTC_MASTER_EN);
490 			if (crtc_enabled) {
491 				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
492 				tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
493 				tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
494 				WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
495 				WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
496 			}
497 		}
498 	}
499 }
500 
501 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
502 {
503 	struct drm_device *dev = encoder->dev;
504 	struct amdgpu_device *adev = drm_to_adev(dev);
505 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
506 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
507 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
508 	int bpc = 0;
509 	u32 tmp = 0;
510 	enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
511 
512 	if (connector) {
513 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
514 		bpc = amdgpu_connector_get_monitor_bpc(connector);
515 		dither = amdgpu_connector->dither;
516 	}
517 
518 	/* LVDS/eDP FMT is set up by atom */
519 	if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
520 		return;
521 
522 	/* not needed for analog */
523 	if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
524 	    (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
525 		return;
526 
527 	if (bpc == 0)
528 		return;
529 
530 	switch (bpc) {
531 	case 6:
532 		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
533 			/* XXX sort out optimal dither settings */
534 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
535 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
536 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
537 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
538 		} else {
539 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
540 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
541 		}
542 		break;
543 	case 8:
544 		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
545 			/* XXX sort out optimal dither settings */
546 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
547 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
548 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
549 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
550 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
551 		} else {
552 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
553 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
554 		}
555 		break;
556 	case 10:
557 		if (dither == AMDGPU_FMT_DITHER_ENABLE) {
558 			/* XXX sort out optimal dither settings */
559 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
560 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
561 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
562 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
563 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
564 		} else {
565 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
566 			tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
567 		}
568 		break;
569 	default:
570 		/* not needed */
571 		break;
572 	}
573 
574 	WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
575 }
576 
577 
578 /* display watermark setup */
579 /**
580  * dce_v10_0_line_buffer_adjust - Set up the line buffer
581  *
582  * @adev: amdgpu_device pointer
583  * @amdgpu_crtc: the selected display controller
584  * @mode: the current display mode on the selected display
585  * controller
586  *
587  * Setup up the line buffer allocation for
588  * the selected display controller (CIK).
589  * Returns the line buffer size in pixels.
590  */
591 static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
592 				       struct amdgpu_crtc *amdgpu_crtc,
593 				       struct drm_display_mode *mode)
594 {
595 	u32 tmp, buffer_alloc, i, mem_cfg;
596 	u32 pipe_offset = amdgpu_crtc->crtc_id;
597 	/*
598 	 * Line Buffer Setup
599 	 * There are 6 line buffers, one for each display controllers.
600 	 * There are 3 partitions per LB. Select the number of partitions
601 	 * to enable based on the display width.  For display widths larger
602 	 * than 4096, you need use to use 2 display controllers and combine
603 	 * them using the stereo blender.
604 	 */
605 	if (amdgpu_crtc->base.enabled && mode) {
606 		if (mode->crtc_hdisplay < 1920) {
607 			mem_cfg = 1;
608 			buffer_alloc = 2;
609 		} else if (mode->crtc_hdisplay < 2560) {
610 			mem_cfg = 2;
611 			buffer_alloc = 2;
612 		} else if (mode->crtc_hdisplay < 4096) {
613 			mem_cfg = 0;
614 			buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
615 		} else {
616 			DRM_DEBUG_KMS("Mode too big for LB!\n");
617 			mem_cfg = 0;
618 			buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
619 		}
620 	} else {
621 		mem_cfg = 1;
622 		buffer_alloc = 0;
623 	}
624 
625 	tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
626 	tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
627 	WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
628 
629 	tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
630 	tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
631 	WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
632 
633 	for (i = 0; i < adev->usec_timeout; i++) {
634 		tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
635 		if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
636 			break;
637 		udelay(1);
638 	}
639 
640 	if (amdgpu_crtc->base.enabled && mode) {
641 		switch (mem_cfg) {
642 		case 0:
643 		default:
644 			return 4096 * 2;
645 		case 1:
646 			return 1920 * 2;
647 		case 2:
648 			return 2560 * 2;
649 		}
650 	}
651 
652 	/* controller not enabled, so no lb used */
653 	return 0;
654 }
655 
656 /**
657  * cik_get_number_of_dram_channels - get the number of dram channels
658  *
659  * @adev: amdgpu_device pointer
660  *
661  * Look up the number of video ram channels (CIK).
662  * Used for display watermark bandwidth calculations
663  * Returns the number of dram channels
664  */
665 static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
666 {
667 	u32 tmp = RREG32(mmMC_SHARED_CHMAP);
668 
669 	switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
670 	case 0:
671 	default:
672 		return 1;
673 	case 1:
674 		return 2;
675 	case 2:
676 		return 4;
677 	case 3:
678 		return 8;
679 	case 4:
680 		return 3;
681 	case 5:
682 		return 6;
683 	case 6:
684 		return 10;
685 	case 7:
686 		return 12;
687 	case 8:
688 		return 16;
689 	}
690 }
691 
692 struct dce10_wm_params {
693 	u32 dram_channels; /* number of dram channels */
694 	u32 yclk;          /* bandwidth per dram data pin in kHz */
695 	u32 sclk;          /* engine clock in kHz */
696 	u32 disp_clk;      /* display clock in kHz */
697 	u32 src_width;     /* viewport width */
698 	u32 active_time;   /* active display time in ns */
699 	u32 blank_time;    /* blank time in ns */
700 	bool interlaced;    /* mode is interlaced */
701 	fixed20_12 vsc;    /* vertical scale ratio */
702 	u32 num_heads;     /* number of active crtcs */
703 	u32 bytes_per_pixel; /* bytes per pixel display + overlay */
704 	u32 lb_size;       /* line buffer allocated to pipe */
705 	u32 vtaps;         /* vertical scaler taps */
706 };
707 
708 /**
709  * dce_v10_0_dram_bandwidth - get the dram bandwidth
710  *
711  * @wm: watermark calculation data
712  *
713  * Calculate the raw dram bandwidth (CIK).
714  * Used for display watermark bandwidth calculations
715  * Returns the dram bandwidth in MBytes/s
716  */
717 static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
718 {
719 	/* Calculate raw DRAM Bandwidth */
720 	fixed20_12 dram_efficiency; /* 0.7 */
721 	fixed20_12 yclk, dram_channels, bandwidth;
722 	fixed20_12 a;
723 
724 	a.full = dfixed_const(1000);
725 	yclk.full = dfixed_const(wm->yclk);
726 	yclk.full = dfixed_div(yclk, a);
727 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
728 	a.full = dfixed_const(10);
729 	dram_efficiency.full = dfixed_const(7);
730 	dram_efficiency.full = dfixed_div(dram_efficiency, a);
731 	bandwidth.full = dfixed_mul(dram_channels, yclk);
732 	bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
733 
734 	return dfixed_trunc(bandwidth);
735 }
736 
737 /**
738  * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
739  *
740  * @wm: watermark calculation data
741  *
742  * Calculate the dram bandwidth used for display (CIK).
743  * Used for display watermark bandwidth calculations
744  * Returns the dram bandwidth for display in MBytes/s
745  */
746 static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
747 {
748 	/* Calculate DRAM Bandwidth and the part allocated to display. */
749 	fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
750 	fixed20_12 yclk, dram_channels, bandwidth;
751 	fixed20_12 a;
752 
753 	a.full = dfixed_const(1000);
754 	yclk.full = dfixed_const(wm->yclk);
755 	yclk.full = dfixed_div(yclk, a);
756 	dram_channels.full = dfixed_const(wm->dram_channels * 4);
757 	a.full = dfixed_const(10);
758 	disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
759 	disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
760 	bandwidth.full = dfixed_mul(dram_channels, yclk);
761 	bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
762 
763 	return dfixed_trunc(bandwidth);
764 }
765 
766 /**
767  * dce_v10_0_data_return_bandwidth - get the data return bandwidth
768  *
769  * @wm: watermark calculation data
770  *
771  * Calculate the data return bandwidth used for display (CIK).
772  * Used for display watermark bandwidth calculations
773  * Returns the data return bandwidth in MBytes/s
774  */
775 static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
776 {
777 	/* Calculate the display Data return Bandwidth */
778 	fixed20_12 return_efficiency; /* 0.8 */
779 	fixed20_12 sclk, bandwidth;
780 	fixed20_12 a;
781 
782 	a.full = dfixed_const(1000);
783 	sclk.full = dfixed_const(wm->sclk);
784 	sclk.full = dfixed_div(sclk, a);
785 	a.full = dfixed_const(10);
786 	return_efficiency.full = dfixed_const(8);
787 	return_efficiency.full = dfixed_div(return_efficiency, a);
788 	a.full = dfixed_const(32);
789 	bandwidth.full = dfixed_mul(a, sclk);
790 	bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
791 
792 	return dfixed_trunc(bandwidth);
793 }
794 
795 /**
796  * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
797  *
798  * @wm: watermark calculation data
799  *
800  * Calculate the dmif bandwidth used for display (CIK).
801  * Used for display watermark bandwidth calculations
802  * Returns the dmif bandwidth in MBytes/s
803  */
804 static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
805 {
806 	/* Calculate the DMIF Request Bandwidth */
807 	fixed20_12 disp_clk_request_efficiency; /* 0.8 */
808 	fixed20_12 disp_clk, bandwidth;
809 	fixed20_12 a, b;
810 
811 	a.full = dfixed_const(1000);
812 	disp_clk.full = dfixed_const(wm->disp_clk);
813 	disp_clk.full = dfixed_div(disp_clk, a);
814 	a.full = dfixed_const(32);
815 	b.full = dfixed_mul(a, disp_clk);
816 
817 	a.full = dfixed_const(10);
818 	disp_clk_request_efficiency.full = dfixed_const(8);
819 	disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
820 
821 	bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
822 
823 	return dfixed_trunc(bandwidth);
824 }
825 
826 /**
827  * dce_v10_0_available_bandwidth - get the min available bandwidth
828  *
829  * @wm: watermark calculation data
830  *
831  * Calculate the min available bandwidth used for display (CIK).
832  * Used for display watermark bandwidth calculations
833  * Returns the min available bandwidth in MBytes/s
834  */
835 static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
836 {
837 	/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
838 	u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
839 	u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
840 	u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
841 
842 	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
843 }
844 
845 /**
846  * dce_v10_0_average_bandwidth - get the average available bandwidth
847  *
848  * @wm: watermark calculation data
849  *
850  * Calculate the average available bandwidth used for display (CIK).
851  * Used for display watermark bandwidth calculations
852  * Returns the average available bandwidth in MBytes/s
853  */
854 static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
855 {
856 	/* Calculate the display mode Average Bandwidth
857 	 * DisplayMode should contain the source and destination dimensions,
858 	 * timing, etc.
859 	 */
860 	fixed20_12 bpp;
861 	fixed20_12 line_time;
862 	fixed20_12 src_width;
863 	fixed20_12 bandwidth;
864 	fixed20_12 a;
865 
866 	a.full = dfixed_const(1000);
867 	line_time.full = dfixed_const(wm->active_time + wm->blank_time);
868 	line_time.full = dfixed_div(line_time, a);
869 	bpp.full = dfixed_const(wm->bytes_per_pixel);
870 	src_width.full = dfixed_const(wm->src_width);
871 	bandwidth.full = dfixed_mul(src_width, bpp);
872 	bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
873 	bandwidth.full = dfixed_div(bandwidth, line_time);
874 
875 	return dfixed_trunc(bandwidth);
876 }
877 
878 /**
879  * dce_v10_0_latency_watermark - get the latency watermark
880  *
881  * @wm: watermark calculation data
882  *
883  * Calculate the latency watermark (CIK).
884  * Used for display watermark bandwidth calculations
885  * Returns the latency watermark in ns
886  */
887 static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
888 {
889 	/* First calculate the latency in ns */
890 	u32 mc_latency = 2000; /* 2000 ns. */
891 	u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
892 	u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
893 	u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
894 	u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
895 	u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
896 		(wm->num_heads * cursor_line_pair_return_time);
897 	u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
898 	u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
899 	u32 tmp, dmif_size = 12288;
900 	fixed20_12 a, b, c;
901 
902 	if (wm->num_heads == 0)
903 		return 0;
904 
905 	a.full = dfixed_const(2);
906 	b.full = dfixed_const(1);
907 	if ((wm->vsc.full > a.full) ||
908 	    ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
909 	    (wm->vtaps >= 5) ||
910 	    ((wm->vsc.full >= a.full) && wm->interlaced))
911 		max_src_lines_per_dst_line = 4;
912 	else
913 		max_src_lines_per_dst_line = 2;
914 
915 	a.full = dfixed_const(available_bandwidth);
916 	b.full = dfixed_const(wm->num_heads);
917 	a.full = dfixed_div(a, b);
918 	tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
919 	tmp = min(dfixed_trunc(a), tmp);
920 
921 	lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
922 
923 	a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
924 	b.full = dfixed_const(1000);
925 	c.full = dfixed_const(lb_fill_bw);
926 	b.full = dfixed_div(c, b);
927 	a.full = dfixed_div(a, b);
928 	line_fill_time = dfixed_trunc(a);
929 
930 	if (line_fill_time < wm->active_time)
931 		return latency;
932 	else
933 		return latency + (line_fill_time - wm->active_time);
934 
935 }
936 
937 /**
938  * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
939  * average and available dram bandwidth
940  *
941  * @wm: watermark calculation data
942  *
943  * Check if the display average bandwidth fits in the display
944  * dram bandwidth (CIK).
945  * Used for display watermark bandwidth calculations
946  * Returns true if the display fits, false if not.
947  */
948 static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
949 {
950 	if (dce_v10_0_average_bandwidth(wm) <=
951 	    (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
952 		return true;
953 	else
954 		return false;
955 }
956 
957 /**
958  * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
959  * average and available bandwidth
960  *
961  * @wm: watermark calculation data
962  *
963  * Check if the display average bandwidth fits in the display
964  * available bandwidth (CIK).
965  * Used for display watermark bandwidth calculations
966  * Returns true if the display fits, false if not.
967  */
968 static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
969 {
970 	if (dce_v10_0_average_bandwidth(wm) <=
971 	    (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
972 		return true;
973 	else
974 		return false;
975 }
976 
977 /**
978  * dce_v10_0_check_latency_hiding - check latency hiding
979  *
980  * @wm: watermark calculation data
981  *
982  * Check latency hiding (CIK).
983  * Used for display watermark bandwidth calculations
984  * Returns true if the display fits, false if not.
985  */
986 static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
987 {
988 	u32 lb_partitions = wm->lb_size / wm->src_width;
989 	u32 line_time = wm->active_time + wm->blank_time;
990 	u32 latency_tolerant_lines;
991 	u32 latency_hiding;
992 	fixed20_12 a;
993 
994 	a.full = dfixed_const(1);
995 	if (wm->vsc.full > a.full)
996 		latency_tolerant_lines = 1;
997 	else {
998 		if (lb_partitions <= (wm->vtaps + 1))
999 			latency_tolerant_lines = 1;
1000 		else
1001 			latency_tolerant_lines = 2;
1002 	}
1003 
1004 	latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1005 
1006 	if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1007 		return true;
1008 	else
1009 		return false;
1010 }
1011 
1012 /**
1013  * dce_v10_0_program_watermarks - program display watermarks
1014  *
1015  * @adev: amdgpu_device pointer
1016  * @amdgpu_crtc: the selected display controller
1017  * @lb_size: line buffer size
1018  * @num_heads: number of display controllers in use
1019  *
1020  * Calculate and program the display watermarks for the
1021  * selected display controller (CIK).
1022  */
1023 static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1024 					struct amdgpu_crtc *amdgpu_crtc,
1025 					u32 lb_size, u32 num_heads)
1026 {
1027 	struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1028 	struct dce10_wm_params wm_low, wm_high;
1029 	u32 active_time;
1030 	u32 line_time = 0;
1031 	u32 latency_watermark_a = 0, latency_watermark_b = 0;
1032 	u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1033 
1034 	if (amdgpu_crtc->base.enabled && num_heads && mode) {
1035 		active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1036 					    (u32)mode->clock);
1037 		line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1038 					  (u32)mode->clock);
1039 		line_time = min(line_time, (u32)65535);
1040 
1041 		/* watermark for high clocks */
1042 		if (adev->pm.dpm_enabled) {
1043 			wm_high.yclk =
1044 				amdgpu_dpm_get_mclk(adev, false) * 10;
1045 			wm_high.sclk =
1046 				amdgpu_dpm_get_sclk(adev, false) * 10;
1047 		} else {
1048 			wm_high.yclk = adev->pm.current_mclk * 10;
1049 			wm_high.sclk = adev->pm.current_sclk * 10;
1050 		}
1051 
1052 		wm_high.disp_clk = mode->clock;
1053 		wm_high.src_width = mode->crtc_hdisplay;
1054 		wm_high.active_time = active_time;
1055 		wm_high.blank_time = line_time - wm_high.active_time;
1056 		wm_high.interlaced = false;
1057 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1058 			wm_high.interlaced = true;
1059 		wm_high.vsc = amdgpu_crtc->vsc;
1060 		wm_high.vtaps = 1;
1061 		if (amdgpu_crtc->rmx_type != RMX_OFF)
1062 			wm_high.vtaps = 2;
1063 		wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1064 		wm_high.lb_size = lb_size;
1065 		wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1066 		wm_high.num_heads = num_heads;
1067 
1068 		/* set for high clocks */
1069 		latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1070 
1071 		/* possibly force display priority to high */
1072 		/* should really do this at mode validation time... */
1073 		if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1074 		    !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1075 		    !dce_v10_0_check_latency_hiding(&wm_high) ||
1076 		    (adev->mode_info.disp_priority == 2)) {
1077 			DRM_DEBUG_KMS("force priority to high\n");
1078 		}
1079 
1080 		/* watermark for low clocks */
1081 		if (adev->pm.dpm_enabled) {
1082 			wm_low.yclk =
1083 				amdgpu_dpm_get_mclk(adev, true) * 10;
1084 			wm_low.sclk =
1085 				amdgpu_dpm_get_sclk(adev, true) * 10;
1086 		} else {
1087 			wm_low.yclk = adev->pm.current_mclk * 10;
1088 			wm_low.sclk = adev->pm.current_sclk * 10;
1089 		}
1090 
1091 		wm_low.disp_clk = mode->clock;
1092 		wm_low.src_width = mode->crtc_hdisplay;
1093 		wm_low.active_time = active_time;
1094 		wm_low.blank_time = line_time - wm_low.active_time;
1095 		wm_low.interlaced = false;
1096 		if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1097 			wm_low.interlaced = true;
1098 		wm_low.vsc = amdgpu_crtc->vsc;
1099 		wm_low.vtaps = 1;
1100 		if (amdgpu_crtc->rmx_type != RMX_OFF)
1101 			wm_low.vtaps = 2;
1102 		wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1103 		wm_low.lb_size = lb_size;
1104 		wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1105 		wm_low.num_heads = num_heads;
1106 
1107 		/* set for low clocks */
1108 		latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1109 
1110 		/* possibly force display priority to high */
1111 		/* should really do this at mode validation time... */
1112 		if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1113 		    !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1114 		    !dce_v10_0_check_latency_hiding(&wm_low) ||
1115 		    (adev->mode_info.disp_priority == 2)) {
1116 			DRM_DEBUG_KMS("force priority to high\n");
1117 		}
1118 		lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1119 	}
1120 
1121 	/* select wm A */
1122 	wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1123 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1124 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1125 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1126 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1127 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1128 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1129 	/* select wm B */
1130 	tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1131 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1132 	tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1133 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1134 	tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1135 	WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1136 	/* restore original selection */
1137 	WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1138 
1139 	/* save values for DPM */
1140 	amdgpu_crtc->line_time = line_time;
1141 	amdgpu_crtc->wm_high = latency_watermark_a;
1142 	amdgpu_crtc->wm_low = latency_watermark_b;
1143 	/* Save number of lines the linebuffer leads before the scanout */
1144 	amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1145 }
1146 
1147 /**
1148  * dce_v10_0_bandwidth_update - program display watermarks
1149  *
1150  * @adev: amdgpu_device pointer
1151  *
1152  * Calculate and program the display watermarks and line
1153  * buffer allocation (CIK).
1154  */
1155 static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1156 {
1157 	struct drm_display_mode *mode = NULL;
1158 	u32 num_heads = 0, lb_size;
1159 	int i;
1160 
1161 	amdgpu_display_update_priority(adev);
1162 
1163 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1164 		if (adev->mode_info.crtcs[i]->base.enabled)
1165 			num_heads++;
1166 	}
1167 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
1168 		mode = &adev->mode_info.crtcs[i]->base.mode;
1169 		lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1170 		dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1171 					    lb_size, num_heads);
1172 	}
1173 }
1174 
1175 static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1176 {
1177 	int i;
1178 	u32 offset, tmp;
1179 
1180 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1181 		offset = adev->mode_info.audio.pin[i].offset;
1182 		tmp = RREG32_AUDIO_ENDPT(offset,
1183 					 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1184 		if (((tmp &
1185 		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1186 		AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1187 			adev->mode_info.audio.pin[i].connected = false;
1188 		else
1189 			adev->mode_info.audio.pin[i].connected = true;
1190 	}
1191 }
1192 
1193 static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1194 {
1195 	int i;
1196 
1197 	dce_v10_0_audio_get_connected_pins(adev);
1198 
1199 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1200 		if (adev->mode_info.audio.pin[i].connected)
1201 			return &adev->mode_info.audio.pin[i];
1202 	}
1203 	DRM_ERROR("No connected audio pins found!\n");
1204 	return NULL;
1205 }
1206 
1207 static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1208 {
1209 	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1210 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1211 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1212 	u32 tmp;
1213 
1214 	if (!dig || !dig->afmt || !dig->afmt->pin)
1215 		return;
1216 
1217 	tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1218 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1219 	WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1220 }
1221 
1222 static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1223 						struct drm_display_mode *mode)
1224 {
1225 	struct drm_device *dev = encoder->dev;
1226 	struct amdgpu_device *adev = drm_to_adev(dev);
1227 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1228 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1229 	struct drm_connector *connector;
1230 	struct drm_connector_list_iter iter;
1231 	struct amdgpu_connector *amdgpu_connector = NULL;
1232 	u32 tmp;
1233 	int interlace = 0;
1234 
1235 	if (!dig || !dig->afmt || !dig->afmt->pin)
1236 		return;
1237 
1238 	drm_connector_list_iter_begin(dev, &iter);
1239 	drm_for_each_connector_iter(connector, &iter) {
1240 		if (connector->encoder == encoder) {
1241 			amdgpu_connector = to_amdgpu_connector(connector);
1242 			break;
1243 		}
1244 	}
1245 	drm_connector_list_iter_end(&iter);
1246 
1247 	if (!amdgpu_connector) {
1248 		DRM_ERROR("Couldn't find encoder's connector\n");
1249 		return;
1250 	}
1251 
1252 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1253 		interlace = 1;
1254 	if (connector->latency_present[interlace]) {
1255 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1256 				    VIDEO_LIPSYNC, connector->video_latency[interlace]);
1257 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1258 				    AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1259 	} else {
1260 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1261 				    VIDEO_LIPSYNC, 0);
1262 		tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1263 				    AUDIO_LIPSYNC, 0);
1264 	}
1265 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1266 			   ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1267 }
1268 
1269 static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1270 {
1271 	struct drm_device *dev = encoder->dev;
1272 	struct amdgpu_device *adev = drm_to_adev(dev);
1273 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1274 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1275 	struct drm_connector *connector;
1276 	struct drm_connector_list_iter iter;
1277 	struct amdgpu_connector *amdgpu_connector = NULL;
1278 	u32 tmp;
1279 	u8 *sadb = NULL;
1280 	int sad_count;
1281 
1282 	if (!dig || !dig->afmt || !dig->afmt->pin)
1283 		return;
1284 
1285 	drm_connector_list_iter_begin(dev, &iter);
1286 	drm_for_each_connector_iter(connector, &iter) {
1287 		if (connector->encoder == encoder) {
1288 			amdgpu_connector = to_amdgpu_connector(connector);
1289 			break;
1290 		}
1291 	}
1292 	drm_connector_list_iter_end(&iter);
1293 
1294 	if (!amdgpu_connector) {
1295 		DRM_ERROR("Couldn't find encoder's connector\n");
1296 		return;
1297 	}
1298 
1299 	sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1300 	if (sad_count < 0) {
1301 		DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1302 		sad_count = 0;
1303 	}
1304 
1305 	/* program the speaker allocation */
1306 	tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1307 				 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1308 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1309 			    DP_CONNECTION, 0);
1310 	/* set HDMI mode */
1311 	tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1312 			    HDMI_CONNECTION, 1);
1313 	if (sad_count)
1314 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1315 				    SPEAKER_ALLOCATION, sadb[0]);
1316 	else
1317 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1318 				    SPEAKER_ALLOCATION, 5); /* stereo */
1319 	WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1320 			   ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1321 
1322 	kfree(sadb);
1323 }
1324 
1325 static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1326 {
1327 	struct drm_device *dev = encoder->dev;
1328 	struct amdgpu_device *adev = drm_to_adev(dev);
1329 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1330 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1331 	struct drm_connector *connector;
1332 	struct drm_connector_list_iter iter;
1333 	struct amdgpu_connector *amdgpu_connector = NULL;
1334 	struct cea_sad *sads;
1335 	int i, sad_count;
1336 
1337 	static const u16 eld_reg_to_type[][2] = {
1338 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1339 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1340 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1341 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1342 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1343 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1344 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1345 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1346 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1347 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1348 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1349 		{ ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1350 	};
1351 
1352 	if (!dig || !dig->afmt || !dig->afmt->pin)
1353 		return;
1354 
1355 	drm_connector_list_iter_begin(dev, &iter);
1356 	drm_for_each_connector_iter(connector, &iter) {
1357 		if (connector->encoder == encoder) {
1358 			amdgpu_connector = to_amdgpu_connector(connector);
1359 			break;
1360 		}
1361 	}
1362 	drm_connector_list_iter_end(&iter);
1363 
1364 	if (!amdgpu_connector) {
1365 		DRM_ERROR("Couldn't find encoder's connector\n");
1366 		return;
1367 	}
1368 
1369 	sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1370 	if (sad_count < 0)
1371 		DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1372 	if (sad_count <= 0)
1373 		return;
1374 	BUG_ON(!sads);
1375 
1376 	for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1377 		u32 tmp = 0;
1378 		u8 stereo_freqs = 0;
1379 		int max_channels = -1;
1380 		int j;
1381 
1382 		for (j = 0; j < sad_count; j++) {
1383 			struct cea_sad *sad = &sads[j];
1384 
1385 			if (sad->format == eld_reg_to_type[i][1]) {
1386 				if (sad->channels > max_channels) {
1387 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1388 							    MAX_CHANNELS, sad->channels);
1389 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1390 							    DESCRIPTOR_BYTE_2, sad->byte2);
1391 					tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1392 							    SUPPORTED_FREQUENCIES, sad->freq);
1393 					max_channels = sad->channels;
1394 				}
1395 
1396 				if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1397 					stereo_freqs |= sad->freq;
1398 				else
1399 					break;
1400 			}
1401 		}
1402 
1403 		tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1404 				    SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1405 		WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1406 	}
1407 
1408 	kfree(sads);
1409 }
1410 
1411 static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1412 				  struct amdgpu_audio_pin *pin,
1413 				  bool enable)
1414 {
1415 	if (!pin)
1416 		return;
1417 
1418 	WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1419 			   enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1420 }
1421 
1422 static const u32 pin_offsets[] = {
1423 	AUD0_REGISTER_OFFSET,
1424 	AUD1_REGISTER_OFFSET,
1425 	AUD2_REGISTER_OFFSET,
1426 	AUD3_REGISTER_OFFSET,
1427 	AUD4_REGISTER_OFFSET,
1428 	AUD5_REGISTER_OFFSET,
1429 	AUD6_REGISTER_OFFSET,
1430 };
1431 
1432 static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1433 {
1434 	int i;
1435 
1436 	if (!amdgpu_audio)
1437 		return 0;
1438 
1439 	adev->mode_info.audio.enabled = true;
1440 
1441 	adev->mode_info.audio.num_pins = 7;
1442 
1443 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1444 		adev->mode_info.audio.pin[i].channels = -1;
1445 		adev->mode_info.audio.pin[i].rate = -1;
1446 		adev->mode_info.audio.pin[i].bits_per_sample = -1;
1447 		adev->mode_info.audio.pin[i].status_bits = 0;
1448 		adev->mode_info.audio.pin[i].category_code = 0;
1449 		adev->mode_info.audio.pin[i].connected = false;
1450 		adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1451 		adev->mode_info.audio.pin[i].id = i;
1452 		/* disable audio.  it will be set up later */
1453 		/* XXX remove once we switch to ip funcs */
1454 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1455 	}
1456 
1457 	return 0;
1458 }
1459 
1460 static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1461 {
1462 	int i;
1463 
1464 	if (!amdgpu_audio)
1465 		return;
1466 
1467 	if (!adev->mode_info.audio.enabled)
1468 		return;
1469 
1470 	for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1471 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1472 
1473 	adev->mode_info.audio.enabled = false;
1474 }
1475 
1476 /*
1477  * update the N and CTS parameters for a given pixel clock rate
1478  */
1479 static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1480 {
1481 	struct drm_device *dev = encoder->dev;
1482 	struct amdgpu_device *adev = drm_to_adev(dev);
1483 	struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1484 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1485 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1486 	u32 tmp;
1487 
1488 	tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1489 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1490 	WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1491 	tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1492 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1493 	WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1494 
1495 	tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1496 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1497 	WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1498 	tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1499 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1500 	WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1501 
1502 	tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1503 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1504 	WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1505 	tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1506 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1507 	WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1508 
1509 }
1510 
1511 /*
1512  * build a HDMI Video Info Frame
1513  */
1514 static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1515 					       void *buffer, size_t size)
1516 {
1517 	struct drm_device *dev = encoder->dev;
1518 	struct amdgpu_device *adev = drm_to_adev(dev);
1519 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1520 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1521 	uint8_t *frame = buffer + 3;
1522 	uint8_t *header = buffer;
1523 
1524 	WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1525 		frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1526 	WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1527 		frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1528 	WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1529 		frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1530 	WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1531 		frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1532 }
1533 
1534 static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1535 {
1536 	struct drm_device *dev = encoder->dev;
1537 	struct amdgpu_device *adev = drm_to_adev(dev);
1538 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1539 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1540 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1541 	u32 dto_phase = 24 * 1000;
1542 	u32 dto_modulo = clock;
1543 	u32 tmp;
1544 
1545 	if (!dig || !dig->afmt)
1546 		return;
1547 
1548 	/* XXX two dtos; generally use dto0 for hdmi */
1549 	/* Express [24MHz / target pixel clock] as an exact rational
1550 	 * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
1551 	 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1552 	 */
1553 	tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1554 	tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1555 			    amdgpu_crtc->crtc_id);
1556 	WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1557 	WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1558 	WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1559 }
1560 
1561 /*
1562  * update the info frames with the data from the current display mode
1563  */
1564 static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1565 				  struct drm_display_mode *mode)
1566 {
1567 	struct drm_device *dev = encoder->dev;
1568 	struct amdgpu_device *adev = drm_to_adev(dev);
1569 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1570 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1571 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1572 	u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1573 	struct hdmi_avi_infoframe frame;
1574 	ssize_t err;
1575 	u32 tmp;
1576 	int bpc = 8;
1577 
1578 	if (!dig || !dig->afmt)
1579 		return;
1580 
1581 	/* Silent, r600_hdmi_enable will raise WARN for us */
1582 	if (!dig->afmt->enabled)
1583 		return;
1584 
1585 	/* hdmi deep color mode general control packets setup, if bpc > 8 */
1586 	if (encoder->crtc) {
1587 		struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1588 		bpc = amdgpu_crtc->bpc;
1589 	}
1590 
1591 	/* disable audio prior to setting up hw */
1592 	dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1593 	dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1594 
1595 	dce_v10_0_audio_set_dto(encoder, mode->clock);
1596 
1597 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1598 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1599 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1600 
1601 	WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1602 
1603 	tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1604 	switch (bpc) {
1605 	case 0:
1606 	case 6:
1607 	case 8:
1608 	case 16:
1609 	default:
1610 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1611 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1612 		DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1613 			  connector->name, bpc);
1614 		break;
1615 	case 10:
1616 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1617 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1618 		DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1619 			  connector->name);
1620 		break;
1621 	case 12:
1622 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1623 		tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1624 		DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1625 			  connector->name);
1626 		break;
1627 	}
1628 	WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1629 
1630 	tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1631 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1632 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1633 	tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1634 	WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1635 
1636 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1637 	/* enable audio info frames (frames won't be set until audio is enabled) */
1638 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1639 	/* required for audio info values to be updated */
1640 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1641 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1642 
1643 	tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1644 	/* required for audio info values to be updated */
1645 	tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1646 	WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1647 
1648 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1649 	/* anything other than 0 */
1650 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1651 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1652 
1653 	WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1654 
1655 	tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1656 	/* set the default audio delay */
1657 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1658 	/* should be suffient for all audio modes and small enough for all hblanks */
1659 	tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1660 	WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1661 
1662 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1663 	/* allow 60958 channel status fields to be updated */
1664 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1665 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1666 
1667 	tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1668 	if (bpc > 8)
1669 		/* clear SW CTS value */
1670 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1671 	else
1672 		/* select SW CTS value */
1673 		tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1674 	/* allow hw to sent ACR packets when required */
1675 	tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1676 	WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1677 
1678 	dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1679 
1680 	tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1681 	tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1682 	WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1683 
1684 	tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1685 	tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1686 	WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1687 
1688 	tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1689 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1690 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1691 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1692 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1693 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1694 	tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1695 	WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1696 
1697 	dce_v10_0_audio_write_speaker_allocation(encoder);
1698 
1699 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1700 	       (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1701 
1702 	dce_v10_0_afmt_audio_select_pin(encoder);
1703 	dce_v10_0_audio_write_sad_regs(encoder);
1704 	dce_v10_0_audio_write_latency_fields(encoder, mode);
1705 
1706 	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1707 	if (err < 0) {
1708 		DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1709 		return;
1710 	}
1711 
1712 	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1713 	if (err < 0) {
1714 		DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1715 		return;
1716 	}
1717 
1718 	dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1719 
1720 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1721 	/* enable AVI info frames */
1722 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1723 	/* required for audio info values to be updated */
1724 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1725 	WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1726 
1727 	tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1728 	tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1729 	WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1730 
1731 	tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1732 	/* send audio packets */
1733 	tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1734 	WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1735 
1736 	WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1737 	WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1738 	WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1739 	WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1740 
1741 	/* enable audio after to setting up hw */
1742 	dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1743 }
1744 
1745 static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1746 {
1747 	struct drm_device *dev = encoder->dev;
1748 	struct amdgpu_device *adev = drm_to_adev(dev);
1749 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1750 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1751 
1752 	if (!dig || !dig->afmt)
1753 		return;
1754 
1755 	/* Silent, r600_hdmi_enable will raise WARN for us */
1756 	if (enable && dig->afmt->enabled)
1757 		return;
1758 	if (!enable && !dig->afmt->enabled)
1759 		return;
1760 
1761 	if (!enable && dig->afmt->pin) {
1762 		dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1763 		dig->afmt->pin = NULL;
1764 	}
1765 
1766 	dig->afmt->enabled = enable;
1767 
1768 	DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1769 		  enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1770 }
1771 
1772 static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1773 {
1774 	int i;
1775 
1776 	for (i = 0; i < adev->mode_info.num_dig; i++)
1777 		adev->mode_info.afmt[i] = NULL;
1778 
1779 	/* DCE10 has audio blocks tied to DIG encoders */
1780 	for (i = 0; i < adev->mode_info.num_dig; i++) {
1781 		adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1782 		if (adev->mode_info.afmt[i]) {
1783 			adev->mode_info.afmt[i]->offset = dig_offsets[i];
1784 			adev->mode_info.afmt[i]->id = i;
1785 		} else {
1786 			int j;
1787 			for (j = 0; j < i; j++) {
1788 				kfree(adev->mode_info.afmt[j]);
1789 				adev->mode_info.afmt[j] = NULL;
1790 			}
1791 			return -ENOMEM;
1792 		}
1793 	}
1794 	return 0;
1795 }
1796 
1797 static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1798 {
1799 	int i;
1800 
1801 	for (i = 0; i < adev->mode_info.num_dig; i++) {
1802 		kfree(adev->mode_info.afmt[i]);
1803 		adev->mode_info.afmt[i] = NULL;
1804 	}
1805 }
1806 
1807 static const u32 vga_control_regs[6] = {
1808 	mmD1VGA_CONTROL,
1809 	mmD2VGA_CONTROL,
1810 	mmD3VGA_CONTROL,
1811 	mmD4VGA_CONTROL,
1812 	mmD5VGA_CONTROL,
1813 	mmD6VGA_CONTROL,
1814 };
1815 
1816 static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1817 {
1818 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1819 	struct drm_device *dev = crtc->dev;
1820 	struct amdgpu_device *adev = drm_to_adev(dev);
1821 	u32 vga_control;
1822 
1823 	vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1824 	if (enable)
1825 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1826 	else
1827 		WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1828 }
1829 
1830 static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1831 {
1832 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1833 	struct drm_device *dev = crtc->dev;
1834 	struct amdgpu_device *adev = drm_to_adev(dev);
1835 
1836 	if (enable)
1837 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1838 	else
1839 		WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1840 }
1841 
1842 static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1843 				     struct drm_framebuffer *fb,
1844 				     int x, int y, int atomic)
1845 {
1846 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1847 	struct drm_device *dev = crtc->dev;
1848 	struct amdgpu_device *adev = drm_to_adev(dev);
1849 	struct drm_framebuffer *target_fb;
1850 	struct drm_gem_object *obj;
1851 	struct amdgpu_bo *abo;
1852 	uint64_t fb_location, tiling_flags;
1853 	uint32_t fb_format, fb_pitch_pixels;
1854 	u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1855 	u32 pipe_config;
1856 	u32 tmp, viewport_w, viewport_h;
1857 	int r;
1858 	bool bypass_lut = false;
1859 
1860 	/* no fb bound */
1861 	if (!atomic && !crtc->primary->fb) {
1862 		DRM_DEBUG_KMS("No FB bound\n");
1863 		return 0;
1864 	}
1865 
1866 	if (atomic)
1867 		target_fb = fb;
1868 	else
1869 		target_fb = crtc->primary->fb;
1870 
1871 	/* If atomic, assume fb object is pinned & idle & fenced and
1872 	 * just update base pointers
1873 	 */
1874 	obj = target_fb->obj[0];
1875 	abo = gem_to_amdgpu_bo(obj);
1876 	r = amdgpu_bo_reserve(abo, false);
1877 	if (unlikely(r != 0))
1878 		return r;
1879 
1880 	if (!atomic) {
1881 		r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1882 		if (unlikely(r != 0)) {
1883 			amdgpu_bo_unreserve(abo);
1884 			return -EINVAL;
1885 		}
1886 	}
1887 	fb_location = amdgpu_bo_gpu_offset(abo);
1888 
1889 	amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1890 	amdgpu_bo_unreserve(abo);
1891 
1892 	pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1893 
1894 	switch (target_fb->format->format) {
1895 	case DRM_FORMAT_C8:
1896 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1897 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1898 		break;
1899 	case DRM_FORMAT_XRGB4444:
1900 	case DRM_FORMAT_ARGB4444:
1901 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1902 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1903 #ifdef __BIG_ENDIAN
1904 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1905 					ENDIAN_8IN16);
1906 #endif
1907 		break;
1908 	case DRM_FORMAT_XRGB1555:
1909 	case DRM_FORMAT_ARGB1555:
1910 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1911 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1912 #ifdef __BIG_ENDIAN
1913 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1914 					ENDIAN_8IN16);
1915 #endif
1916 		break;
1917 	case DRM_FORMAT_BGRX5551:
1918 	case DRM_FORMAT_BGRA5551:
1919 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1920 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1921 #ifdef __BIG_ENDIAN
1922 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1923 					ENDIAN_8IN16);
1924 #endif
1925 		break;
1926 	case DRM_FORMAT_RGB565:
1927 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1928 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1929 #ifdef __BIG_ENDIAN
1930 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1931 					ENDIAN_8IN16);
1932 #endif
1933 		break;
1934 	case DRM_FORMAT_XRGB8888:
1935 	case DRM_FORMAT_ARGB8888:
1936 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1937 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1938 #ifdef __BIG_ENDIAN
1939 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1940 					ENDIAN_8IN32);
1941 #endif
1942 		break;
1943 	case DRM_FORMAT_XRGB2101010:
1944 	case DRM_FORMAT_ARGB2101010:
1945 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1946 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1947 #ifdef __BIG_ENDIAN
1948 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1949 					ENDIAN_8IN32);
1950 #endif
1951 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1952 		bypass_lut = true;
1953 		break;
1954 	case DRM_FORMAT_BGRX1010102:
1955 	case DRM_FORMAT_BGRA1010102:
1956 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1957 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1958 #ifdef __BIG_ENDIAN
1959 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1960 					ENDIAN_8IN32);
1961 #endif
1962 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1963 		bypass_lut = true;
1964 		break;
1965 	case DRM_FORMAT_XBGR8888:
1966 	case DRM_FORMAT_ABGR8888:
1967 		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1968 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1969 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1970 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1971 #ifdef __BIG_ENDIAN
1972 		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1973 					ENDIAN_8IN32);
1974 #endif
1975 		break;
1976 	default:
1977 		DRM_ERROR("Unsupported screen format %p4cc\n",
1978 			  &target_fb->format->format);
1979 		return -EINVAL;
1980 	}
1981 
1982 	if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1983 		unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1984 
1985 		bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1986 		bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1987 		mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1988 		tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1989 		num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1990 
1991 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1992 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1993 					  ARRAY_2D_TILED_THIN1);
1994 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1995 					  tile_split);
1996 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
1997 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
1998 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
1999 					  mtaspect);
2000 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2001 					  ADDR_SURF_MICRO_TILING_DISPLAY);
2002 	} else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2003 		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2004 					  ARRAY_1D_TILED_THIN1);
2005 	}
2006 
2007 	fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2008 				  pipe_config);
2009 
2010 	dce_v10_0_vga_enable(crtc, false);
2011 
2012 	/* Make sure surface address is updated at vertical blank rather than
2013 	 * horizontal blank
2014 	 */
2015 	tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2016 	tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2017 			    GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2018 	WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2019 
2020 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2021 	       upper_32_bits(fb_location));
2022 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2023 	       upper_32_bits(fb_location));
2024 	WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2025 	       (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2026 	WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2027 	       (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2028 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2029 	WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2030 
2031 	/*
2032 	 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2033 	 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2034 	 * retain the full precision throughout the pipeline.
2035 	 */
2036 	tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2037 	if (bypass_lut)
2038 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2039 	else
2040 		tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2041 	WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2042 
2043 	if (bypass_lut)
2044 		DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2045 
2046 	WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2047 	WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2048 	WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2049 	WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2050 	WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2051 	WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2052 
2053 	fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2054 	WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2055 
2056 	dce_v10_0_grph_enable(crtc, true);
2057 
2058 	WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2059 	       target_fb->height);
2060 
2061 	x &= ~3;
2062 	y &= ~1;
2063 	WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2064 	       (x << 16) | y);
2065 	viewport_w = crtc->mode.hdisplay;
2066 	viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2067 	WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2068 	       (viewport_w << 16) | viewport_h);
2069 
2070 	/* set pageflip to happen anywhere in vblank interval */
2071 	WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2072 
2073 	if (!atomic && fb && fb != crtc->primary->fb) {
2074 		abo = gem_to_amdgpu_bo(fb->obj[0]);
2075 		r = amdgpu_bo_reserve(abo, true);
2076 		if (unlikely(r != 0))
2077 			return r;
2078 		amdgpu_bo_unpin(abo);
2079 		amdgpu_bo_unreserve(abo);
2080 	}
2081 
2082 	/* Bytes per pixel may have changed */
2083 	dce_v10_0_bandwidth_update(adev);
2084 
2085 	return 0;
2086 }
2087 
2088 static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2089 				     struct drm_display_mode *mode)
2090 {
2091 	struct drm_device *dev = crtc->dev;
2092 	struct amdgpu_device *adev = drm_to_adev(dev);
2093 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2094 	u32 tmp;
2095 
2096 	tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2097 	if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2098 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2099 	else
2100 		tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2101 	WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2102 }
2103 
2104 static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2105 {
2106 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2107 	struct drm_device *dev = crtc->dev;
2108 	struct amdgpu_device *adev = drm_to_adev(dev);
2109 	u16 *r, *g, *b;
2110 	int i;
2111 	u32 tmp;
2112 
2113 	DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2114 
2115 	tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2116 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2117 	tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2118 	WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2119 
2120 	tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2121 	tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2122 	WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2123 
2124 	tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2125 	tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2126 	WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2127 
2128 	tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2129 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2130 	tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2131 	WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2132 
2133 	WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2134 
2135 	WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2136 	WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2137 	WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2138 
2139 	WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2140 	WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2141 	WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2142 
2143 	WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2144 	WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2145 
2146 	WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2147 	r = crtc->gamma_store;
2148 	g = r + crtc->gamma_size;
2149 	b = g + crtc->gamma_size;
2150 	for (i = 0; i < 256; i++) {
2151 		WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2152 		       ((*r++ & 0xffc0) << 14) |
2153 		       ((*g++ & 0xffc0) << 4) |
2154 		       (*b++ >> 6));
2155 	}
2156 
2157 	tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2158 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2159 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2160 	tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2161 	WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2162 
2163 	tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2164 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2165 	tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2166 	WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2167 
2168 	tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2169 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2170 	tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2171 	WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2172 
2173 	tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2174 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2175 	tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2176 	WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2177 
2178 	/* XXX match this to the depth of the crtc fmt block, move to modeset? */
2179 	WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2180 	/* XXX this only needs to be programmed once per crtc at startup,
2181 	 * not sure where the best place for it is
2182 	 */
2183 	tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2184 	tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2185 	WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2186 }
2187 
2188 static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2189 {
2190 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2191 	struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2192 
2193 	switch (amdgpu_encoder->encoder_id) {
2194 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2195 		if (dig->linkb)
2196 			return 1;
2197 		else
2198 			return 0;
2199 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2200 		if (dig->linkb)
2201 			return 3;
2202 		else
2203 			return 2;
2204 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2205 		if (dig->linkb)
2206 			return 5;
2207 		else
2208 			return 4;
2209 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2210 		return 6;
2211 	default:
2212 		DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2213 		return 0;
2214 	}
2215 }
2216 
2217 /**
2218  * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2219  *
2220  * @crtc: drm crtc
2221  *
2222  * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
2223  * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
2224  * monitors a dedicated PPLL must be used.  If a particular board has
2225  * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2226  * as there is no need to program the PLL itself.  If we are not able to
2227  * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2228  * avoid messing up an existing monitor.
2229  *
2230  * Asic specific PLL information
2231  *
2232  * DCE 10.x
2233  * Tonga
2234  * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2235  * CI
2236  * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2237  *
2238  */
2239 static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2240 {
2241 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2242 	struct drm_device *dev = crtc->dev;
2243 	struct amdgpu_device *adev = drm_to_adev(dev);
2244 	u32 pll_in_use;
2245 	int pll;
2246 
2247 	if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2248 		if (adev->clock.dp_extclk)
2249 			/* skip PPLL programming if using ext clock */
2250 			return ATOM_PPLL_INVALID;
2251 		else {
2252 			/* use the same PPLL for all DP monitors */
2253 			pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2254 			if (pll != ATOM_PPLL_INVALID)
2255 				return pll;
2256 		}
2257 	} else {
2258 		/* use the same PPLL for all monitors with the same clock */
2259 		pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2260 		if (pll != ATOM_PPLL_INVALID)
2261 			return pll;
2262 	}
2263 
2264 	/* DCE10 has PPLL0, PPLL1, and PPLL2 */
2265 	pll_in_use = amdgpu_pll_get_use_mask(crtc);
2266 	if (!(pll_in_use & (1 << ATOM_PPLL2)))
2267 		return ATOM_PPLL2;
2268 	if (!(pll_in_use & (1 << ATOM_PPLL1)))
2269 		return ATOM_PPLL1;
2270 	if (!(pll_in_use & (1 << ATOM_PPLL0)))
2271 		return ATOM_PPLL0;
2272 	DRM_ERROR("unable to allocate a PPLL\n");
2273 	return ATOM_PPLL_INVALID;
2274 }
2275 
2276 static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2277 {
2278 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2279 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2280 	uint32_t cur_lock;
2281 
2282 	cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2283 	if (lock)
2284 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2285 	else
2286 		cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2287 	WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2288 }
2289 
2290 static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2291 {
2292 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2293 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2294 	u32 tmp;
2295 
2296 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2297 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2298 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2299 }
2300 
2301 static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2302 {
2303 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2304 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2305 	u32 tmp;
2306 
2307 	WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2308 	       upper_32_bits(amdgpu_crtc->cursor_addr));
2309 	WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2310 	       lower_32_bits(amdgpu_crtc->cursor_addr));
2311 
2312 	tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2313 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2314 	tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2315 	WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2316 }
2317 
2318 static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2319 					int x, int y)
2320 {
2321 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2322 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2323 	int xorigin = 0, yorigin = 0;
2324 
2325 	amdgpu_crtc->cursor_x = x;
2326 	amdgpu_crtc->cursor_y = y;
2327 
2328 	/* avivo cursor are offset into the total surface */
2329 	x += crtc->x;
2330 	y += crtc->y;
2331 	DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2332 
2333 	if (x < 0) {
2334 		xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2335 		x = 0;
2336 	}
2337 	if (y < 0) {
2338 		yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2339 		y = 0;
2340 	}
2341 
2342 	WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2343 	WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2344 	WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2345 	       ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2346 
2347 	return 0;
2348 }
2349 
2350 static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2351 				      int x, int y)
2352 {
2353 	int ret;
2354 
2355 	dce_v10_0_lock_cursor(crtc, true);
2356 	ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2357 	dce_v10_0_lock_cursor(crtc, false);
2358 
2359 	return ret;
2360 }
2361 
2362 static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2363 				      struct drm_file *file_priv,
2364 				      uint32_t handle,
2365 				      uint32_t width,
2366 				      uint32_t height,
2367 				      int32_t hot_x,
2368 				      int32_t hot_y)
2369 {
2370 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2371 	struct drm_gem_object *obj;
2372 	struct amdgpu_bo *aobj;
2373 	int ret;
2374 
2375 	if (!handle) {
2376 		/* turn off cursor */
2377 		dce_v10_0_hide_cursor(crtc);
2378 		obj = NULL;
2379 		goto unpin;
2380 	}
2381 
2382 	if ((width > amdgpu_crtc->max_cursor_width) ||
2383 	    (height > amdgpu_crtc->max_cursor_height)) {
2384 		DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2385 		return -EINVAL;
2386 	}
2387 
2388 	obj = drm_gem_object_lookup(file_priv, handle);
2389 	if (!obj) {
2390 		DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2391 		return -ENOENT;
2392 	}
2393 
2394 	aobj = gem_to_amdgpu_bo(obj);
2395 	ret = amdgpu_bo_reserve(aobj, false);
2396 	if (ret != 0) {
2397 		drm_gem_object_put(obj);
2398 		return ret;
2399 	}
2400 
2401 	ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2402 	amdgpu_bo_unreserve(aobj);
2403 	if (ret) {
2404 		DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2405 		drm_gem_object_put(obj);
2406 		return ret;
2407 	}
2408 	amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2409 
2410 	dce_v10_0_lock_cursor(crtc, true);
2411 
2412 	if (width != amdgpu_crtc->cursor_width ||
2413 	    height != amdgpu_crtc->cursor_height ||
2414 	    hot_x != amdgpu_crtc->cursor_hot_x ||
2415 	    hot_y != amdgpu_crtc->cursor_hot_y) {
2416 		int x, y;
2417 
2418 		x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2419 		y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2420 
2421 		dce_v10_0_cursor_move_locked(crtc, x, y);
2422 
2423 		amdgpu_crtc->cursor_width = width;
2424 		amdgpu_crtc->cursor_height = height;
2425 		amdgpu_crtc->cursor_hot_x = hot_x;
2426 		amdgpu_crtc->cursor_hot_y = hot_y;
2427 	}
2428 
2429 	dce_v10_0_show_cursor(crtc);
2430 	dce_v10_0_lock_cursor(crtc, false);
2431 
2432 unpin:
2433 	if (amdgpu_crtc->cursor_bo) {
2434 		struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2435 		ret = amdgpu_bo_reserve(aobj, true);
2436 		if (likely(ret == 0)) {
2437 			amdgpu_bo_unpin(aobj);
2438 			amdgpu_bo_unreserve(aobj);
2439 		}
2440 		drm_gem_object_put(amdgpu_crtc->cursor_bo);
2441 	}
2442 
2443 	amdgpu_crtc->cursor_bo = obj;
2444 	return 0;
2445 }
2446 
2447 static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2448 {
2449 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2450 
2451 	if (amdgpu_crtc->cursor_bo) {
2452 		dce_v10_0_lock_cursor(crtc, true);
2453 
2454 		dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2455 					     amdgpu_crtc->cursor_y);
2456 
2457 		dce_v10_0_show_cursor(crtc);
2458 
2459 		dce_v10_0_lock_cursor(crtc, false);
2460 	}
2461 }
2462 
2463 static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2464 				    u16 *blue, uint32_t size,
2465 				    struct drm_modeset_acquire_ctx *ctx)
2466 {
2467 	dce_v10_0_crtc_load_lut(crtc);
2468 
2469 	return 0;
2470 }
2471 
2472 static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2473 {
2474 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2475 
2476 	drm_crtc_cleanup(crtc);
2477 	kfree(amdgpu_crtc);
2478 }
2479 
2480 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2481 	.cursor_set2 = dce_v10_0_crtc_cursor_set2,
2482 	.cursor_move = dce_v10_0_crtc_cursor_move,
2483 	.gamma_set = dce_v10_0_crtc_gamma_set,
2484 	.set_config = amdgpu_display_crtc_set_config,
2485 	.destroy = dce_v10_0_crtc_destroy,
2486 	.page_flip_target = amdgpu_display_crtc_page_flip_target,
2487 	.get_vblank_counter = amdgpu_get_vblank_counter_kms,
2488 	.enable_vblank = amdgpu_enable_vblank_kms,
2489 	.disable_vblank = amdgpu_disable_vblank_kms,
2490 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2491 };
2492 
2493 static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2494 {
2495 	struct drm_device *dev = crtc->dev;
2496 	struct amdgpu_device *adev = drm_to_adev(dev);
2497 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2498 	unsigned type;
2499 
2500 	switch (mode) {
2501 	case DRM_MODE_DPMS_ON:
2502 		amdgpu_crtc->enabled = true;
2503 		amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2504 		dce_v10_0_vga_enable(crtc, true);
2505 		amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2506 		dce_v10_0_vga_enable(crtc, false);
2507 		/* Make sure VBLANK and PFLIP interrupts are still enabled */
2508 		type = amdgpu_display_crtc_idx_to_irq_type(adev,
2509 						amdgpu_crtc->crtc_id);
2510 		amdgpu_irq_update(adev, &adev->crtc_irq, type);
2511 		amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2512 		drm_crtc_vblank_on(crtc);
2513 		dce_v10_0_crtc_load_lut(crtc);
2514 		break;
2515 	case DRM_MODE_DPMS_STANDBY:
2516 	case DRM_MODE_DPMS_SUSPEND:
2517 	case DRM_MODE_DPMS_OFF:
2518 		drm_crtc_vblank_off(crtc);
2519 		if (amdgpu_crtc->enabled) {
2520 			dce_v10_0_vga_enable(crtc, true);
2521 			amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2522 			dce_v10_0_vga_enable(crtc, false);
2523 		}
2524 		amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2525 		amdgpu_crtc->enabled = false;
2526 		break;
2527 	}
2528 	/* adjust pm to dpms */
2529 	amdgpu_dpm_compute_clocks(adev);
2530 }
2531 
2532 static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2533 {
2534 	/* disable crtc pair power gating before programming */
2535 	amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2536 	amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2537 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2538 }
2539 
2540 static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2541 {
2542 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2543 	amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2544 }
2545 
2546 static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2547 {
2548 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2549 	struct drm_device *dev = crtc->dev;
2550 	struct amdgpu_device *adev = drm_to_adev(dev);
2551 	struct amdgpu_atom_ss ss;
2552 	int i;
2553 
2554 	dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2555 	if (crtc->primary->fb) {
2556 		int r;
2557 		struct amdgpu_bo *abo;
2558 
2559 		abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2560 		r = amdgpu_bo_reserve(abo, true);
2561 		if (unlikely(r))
2562 			DRM_ERROR("failed to reserve abo before unpin\n");
2563 		else {
2564 			amdgpu_bo_unpin(abo);
2565 			amdgpu_bo_unreserve(abo);
2566 		}
2567 	}
2568 	/* disable the GRPH */
2569 	dce_v10_0_grph_enable(crtc, false);
2570 
2571 	amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2572 
2573 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2574 		if (adev->mode_info.crtcs[i] &&
2575 		    adev->mode_info.crtcs[i]->enabled &&
2576 		    i != amdgpu_crtc->crtc_id &&
2577 		    amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2578 			/* one other crtc is using this pll don't turn
2579 			 * off the pll
2580 			 */
2581 			goto done;
2582 		}
2583 	}
2584 
2585 	switch (amdgpu_crtc->pll_id) {
2586 	case ATOM_PPLL0:
2587 	case ATOM_PPLL1:
2588 	case ATOM_PPLL2:
2589 		/* disable the ppll */
2590 		amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2591 					  0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2592 		break;
2593 	default:
2594 		break;
2595 	}
2596 done:
2597 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2598 	amdgpu_crtc->adjusted_clock = 0;
2599 	amdgpu_crtc->encoder = NULL;
2600 	amdgpu_crtc->connector = NULL;
2601 }
2602 
2603 static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2604 				  struct drm_display_mode *mode,
2605 				  struct drm_display_mode *adjusted_mode,
2606 				  int x, int y, struct drm_framebuffer *old_fb)
2607 {
2608 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2609 
2610 	if (!amdgpu_crtc->adjusted_clock)
2611 		return -EINVAL;
2612 
2613 	amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2614 	amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2615 	dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2616 	amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2617 	amdgpu_atombios_crtc_scaler_setup(crtc);
2618 	dce_v10_0_cursor_reset(crtc);
2619 	/* update the hw version fpr dpm */
2620 	amdgpu_crtc->hw_mode = *adjusted_mode;
2621 
2622 	return 0;
2623 }
2624 
2625 static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2626 				     const struct drm_display_mode *mode,
2627 				     struct drm_display_mode *adjusted_mode)
2628 {
2629 	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2630 	struct drm_device *dev = crtc->dev;
2631 	struct drm_encoder *encoder;
2632 
2633 	/* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2634 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2635 		if (encoder->crtc == crtc) {
2636 			amdgpu_crtc->encoder = encoder;
2637 			amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2638 			break;
2639 		}
2640 	}
2641 	if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2642 		amdgpu_crtc->encoder = NULL;
2643 		amdgpu_crtc->connector = NULL;
2644 		return false;
2645 	}
2646 	if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2647 		return false;
2648 	if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2649 		return false;
2650 	/* pick pll */
2651 	amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2652 	/* if we can't get a PPLL for a non-DP encoder, fail */
2653 	if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2654 	    !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2655 		return false;
2656 
2657 	return true;
2658 }
2659 
2660 static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2661 				  struct drm_framebuffer *old_fb)
2662 {
2663 	return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2664 }
2665 
2666 static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2667 					 struct drm_framebuffer *fb,
2668 					 int x, int y, enum mode_set_atomic state)
2669 {
2670 	return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2671 }
2672 
2673 static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2674 	.dpms = dce_v10_0_crtc_dpms,
2675 	.mode_fixup = dce_v10_0_crtc_mode_fixup,
2676 	.mode_set = dce_v10_0_crtc_mode_set,
2677 	.mode_set_base = dce_v10_0_crtc_set_base,
2678 	.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2679 	.prepare = dce_v10_0_crtc_prepare,
2680 	.commit = dce_v10_0_crtc_commit,
2681 	.disable = dce_v10_0_crtc_disable,
2682 	.get_scanout_position = amdgpu_crtc_get_scanout_position,
2683 };
2684 
2685 static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2686 {
2687 	struct amdgpu_crtc *amdgpu_crtc;
2688 
2689 	amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2690 			      (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2691 	if (amdgpu_crtc == NULL)
2692 		return -ENOMEM;
2693 
2694 	drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2695 
2696 	drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2697 	amdgpu_crtc->crtc_id = index;
2698 	adev->mode_info.crtcs[index] = amdgpu_crtc;
2699 
2700 	amdgpu_crtc->max_cursor_width = 128;
2701 	amdgpu_crtc->max_cursor_height = 128;
2702 	adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2703 	adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2704 
2705 	switch (amdgpu_crtc->crtc_id) {
2706 	case 0:
2707 	default:
2708 		amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2709 		break;
2710 	case 1:
2711 		amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2712 		break;
2713 	case 2:
2714 		amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2715 		break;
2716 	case 3:
2717 		amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2718 		break;
2719 	case 4:
2720 		amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2721 		break;
2722 	case 5:
2723 		amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2724 		break;
2725 	}
2726 
2727 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2728 	amdgpu_crtc->adjusted_clock = 0;
2729 	amdgpu_crtc->encoder = NULL;
2730 	amdgpu_crtc->connector = NULL;
2731 	drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2732 
2733 	return 0;
2734 }
2735 
2736 static int dce_v10_0_early_init(void *handle)
2737 {
2738 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2739 
2740 	adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2741 	adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2742 
2743 	dce_v10_0_set_display_funcs(adev);
2744 
2745 	adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2746 
2747 	switch (adev->asic_type) {
2748 	case CHIP_FIJI:
2749 	case CHIP_TONGA:
2750 		adev->mode_info.num_hpd = 6;
2751 		adev->mode_info.num_dig = 7;
2752 		break;
2753 	default:
2754 		/* FIXME: not supported yet */
2755 		return -EINVAL;
2756 	}
2757 
2758 	dce_v10_0_set_irq_funcs(adev);
2759 
2760 	return 0;
2761 }
2762 
2763 static int dce_v10_0_sw_init(void *handle)
2764 {
2765 	int r, i;
2766 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2767 
2768 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2769 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2770 		if (r)
2771 			return r;
2772 	}
2773 
2774 	for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2775 		r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2776 		if (r)
2777 			return r;
2778 	}
2779 
2780 	/* HPD hotplug */
2781 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2782 	if (r)
2783 		return r;
2784 
2785 	adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2786 
2787 	adev_to_drm(adev)->mode_config.async_page_flip = true;
2788 
2789 	adev_to_drm(adev)->mode_config.max_width = 16384;
2790 	adev_to_drm(adev)->mode_config.max_height = 16384;
2791 
2792 	adev_to_drm(adev)->mode_config.preferred_depth = 24;
2793 	adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2794 
2795 	adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2796 
2797 	r = amdgpu_display_modeset_create_props(adev);
2798 	if (r)
2799 		return r;
2800 
2801 	adev_to_drm(adev)->mode_config.max_width = 16384;
2802 	adev_to_drm(adev)->mode_config.max_height = 16384;
2803 
2804 	/* allocate crtcs */
2805 	for (i = 0; i < adev->mode_info.num_crtc; i++) {
2806 		r = dce_v10_0_crtc_init(adev, i);
2807 		if (r)
2808 			return r;
2809 	}
2810 
2811 	if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2812 		amdgpu_display_print_display_setup(adev_to_drm(adev));
2813 	else
2814 		return -EINVAL;
2815 
2816 	/* setup afmt */
2817 	r = dce_v10_0_afmt_init(adev);
2818 	if (r)
2819 		return r;
2820 
2821 	r = dce_v10_0_audio_init(adev);
2822 	if (r)
2823 		return r;
2824 
2825 	/* Disable vblank IRQs aggressively for power-saving */
2826 	/* XXX: can this be enabled for DC? */
2827 	adev_to_drm(adev)->vblank_disable_immediate = true;
2828 
2829 	r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2830 	if (r)
2831 		return r;
2832 
2833 	INIT_DELAYED_WORK(&adev->hotplug_work,
2834 		  amdgpu_display_hotplug_work_func);
2835 
2836 	drm_kms_helper_poll_init(adev_to_drm(adev));
2837 
2838 	adev->mode_info.mode_config_initialized = true;
2839 	return 0;
2840 }
2841 
2842 static int dce_v10_0_sw_fini(void *handle)
2843 {
2844 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2845 
2846 	kfree(adev->mode_info.bios_hardcoded_edid);
2847 
2848 	drm_kms_helper_poll_fini(adev_to_drm(adev));
2849 
2850 	dce_v10_0_audio_fini(adev);
2851 
2852 	dce_v10_0_afmt_fini(adev);
2853 
2854 	drm_mode_config_cleanup(adev_to_drm(adev));
2855 	adev->mode_info.mode_config_initialized = false;
2856 
2857 	return 0;
2858 }
2859 
2860 static int dce_v10_0_hw_init(void *handle)
2861 {
2862 	int i;
2863 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2864 
2865 	dce_v10_0_init_golden_registers(adev);
2866 
2867 	/* disable vga render */
2868 	dce_v10_0_set_vga_render_state(adev, false);
2869 	/* init dig PHYs, disp eng pll */
2870 	amdgpu_atombios_encoder_init_dig(adev);
2871 	amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2872 
2873 	/* initialize hpd */
2874 	dce_v10_0_hpd_init(adev);
2875 
2876 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2877 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2878 	}
2879 
2880 	dce_v10_0_pageflip_interrupt_init(adev);
2881 
2882 	return 0;
2883 }
2884 
2885 static int dce_v10_0_hw_fini(void *handle)
2886 {
2887 	int i;
2888 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2889 
2890 	dce_v10_0_hpd_fini(adev);
2891 
2892 	for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2893 		dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2894 	}
2895 
2896 	dce_v10_0_pageflip_interrupt_fini(adev);
2897 
2898 	flush_delayed_work(&adev->hotplug_work);
2899 
2900 	return 0;
2901 }
2902 
2903 static int dce_v10_0_suspend(void *handle)
2904 {
2905 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2906 	int r;
2907 
2908 	r = amdgpu_display_suspend_helper(adev);
2909 	if (r)
2910 		return r;
2911 
2912 	adev->mode_info.bl_level =
2913 		amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2914 
2915 	return dce_v10_0_hw_fini(handle);
2916 }
2917 
2918 static int dce_v10_0_resume(void *handle)
2919 {
2920 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2921 	int ret;
2922 
2923 	amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2924 							   adev->mode_info.bl_level);
2925 
2926 	ret = dce_v10_0_hw_init(handle);
2927 
2928 	/* turn on the BL */
2929 	if (adev->mode_info.bl_encoder) {
2930 		u8 bl_level = amdgpu_display_backlight_get_level(adev,
2931 								  adev->mode_info.bl_encoder);
2932 		amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2933 						    bl_level);
2934 	}
2935 	if (ret)
2936 		return ret;
2937 
2938 	return amdgpu_display_resume_helper(adev);
2939 }
2940 
2941 static bool dce_v10_0_is_idle(void *handle)
2942 {
2943 	return true;
2944 }
2945 
2946 static int dce_v10_0_wait_for_idle(void *handle)
2947 {
2948 	return 0;
2949 }
2950 
2951 static bool dce_v10_0_check_soft_reset(void *handle)
2952 {
2953 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2954 
2955 	return dce_v10_0_is_display_hung(adev);
2956 }
2957 
2958 static int dce_v10_0_soft_reset(void *handle)
2959 {
2960 	u32 srbm_soft_reset = 0, tmp;
2961 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2962 
2963 	if (dce_v10_0_is_display_hung(adev))
2964 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2965 
2966 	if (srbm_soft_reset) {
2967 		tmp = RREG32(mmSRBM_SOFT_RESET);
2968 		tmp |= srbm_soft_reset;
2969 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2970 		WREG32(mmSRBM_SOFT_RESET, tmp);
2971 		tmp = RREG32(mmSRBM_SOFT_RESET);
2972 
2973 		udelay(50);
2974 
2975 		tmp &= ~srbm_soft_reset;
2976 		WREG32(mmSRBM_SOFT_RESET, tmp);
2977 		tmp = RREG32(mmSRBM_SOFT_RESET);
2978 
2979 		/* Wait a little for things to settle down */
2980 		udelay(50);
2981 	}
2982 	return 0;
2983 }
2984 
2985 static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2986 						     int crtc,
2987 						     enum amdgpu_interrupt_state state)
2988 {
2989 	u32 lb_interrupt_mask;
2990 
2991 	if (crtc >= adev->mode_info.num_crtc) {
2992 		DRM_DEBUG("invalid crtc %d\n", crtc);
2993 		return;
2994 	}
2995 
2996 	switch (state) {
2997 	case AMDGPU_IRQ_STATE_DISABLE:
2998 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2999 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3000 						  VBLANK_INTERRUPT_MASK, 0);
3001 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3002 		break;
3003 	case AMDGPU_IRQ_STATE_ENABLE:
3004 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3005 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3006 						  VBLANK_INTERRUPT_MASK, 1);
3007 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3008 		break;
3009 	default:
3010 		break;
3011 	}
3012 }
3013 
3014 static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3015 						    int crtc,
3016 						    enum amdgpu_interrupt_state state)
3017 {
3018 	u32 lb_interrupt_mask;
3019 
3020 	if (crtc >= adev->mode_info.num_crtc) {
3021 		DRM_DEBUG("invalid crtc %d\n", crtc);
3022 		return;
3023 	}
3024 
3025 	switch (state) {
3026 	case AMDGPU_IRQ_STATE_DISABLE:
3027 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3028 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3029 						  VLINE_INTERRUPT_MASK, 0);
3030 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3031 		break;
3032 	case AMDGPU_IRQ_STATE_ENABLE:
3033 		lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3034 		lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3035 						  VLINE_INTERRUPT_MASK, 1);
3036 		WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3037 		break;
3038 	default:
3039 		break;
3040 	}
3041 }
3042 
3043 static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3044 				       struct amdgpu_irq_src *source,
3045 				       unsigned hpd,
3046 				       enum amdgpu_interrupt_state state)
3047 {
3048 	u32 tmp;
3049 
3050 	if (hpd >= adev->mode_info.num_hpd) {
3051 		DRM_DEBUG("invalid hdp %d\n", hpd);
3052 		return 0;
3053 	}
3054 
3055 	switch (state) {
3056 	case AMDGPU_IRQ_STATE_DISABLE:
3057 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3058 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3059 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3060 		break;
3061 	case AMDGPU_IRQ_STATE_ENABLE:
3062 		tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3063 		tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3064 		WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3065 		break;
3066 	default:
3067 		break;
3068 	}
3069 
3070 	return 0;
3071 }
3072 
3073 static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3074 					struct amdgpu_irq_src *source,
3075 					unsigned type,
3076 					enum amdgpu_interrupt_state state)
3077 {
3078 	switch (type) {
3079 	case AMDGPU_CRTC_IRQ_VBLANK1:
3080 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3081 		break;
3082 	case AMDGPU_CRTC_IRQ_VBLANK2:
3083 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3084 		break;
3085 	case AMDGPU_CRTC_IRQ_VBLANK3:
3086 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3087 		break;
3088 	case AMDGPU_CRTC_IRQ_VBLANK4:
3089 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3090 		break;
3091 	case AMDGPU_CRTC_IRQ_VBLANK5:
3092 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3093 		break;
3094 	case AMDGPU_CRTC_IRQ_VBLANK6:
3095 		dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3096 		break;
3097 	case AMDGPU_CRTC_IRQ_VLINE1:
3098 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3099 		break;
3100 	case AMDGPU_CRTC_IRQ_VLINE2:
3101 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3102 		break;
3103 	case AMDGPU_CRTC_IRQ_VLINE3:
3104 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3105 		break;
3106 	case AMDGPU_CRTC_IRQ_VLINE4:
3107 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3108 		break;
3109 	case AMDGPU_CRTC_IRQ_VLINE5:
3110 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3111 		break;
3112 	case AMDGPU_CRTC_IRQ_VLINE6:
3113 		dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3114 		break;
3115 	default:
3116 		break;
3117 	}
3118 	return 0;
3119 }
3120 
3121 static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3122 					    struct amdgpu_irq_src *src,
3123 					    unsigned type,
3124 					    enum amdgpu_interrupt_state state)
3125 {
3126 	u32 reg;
3127 
3128 	if (type >= adev->mode_info.num_crtc) {
3129 		DRM_ERROR("invalid pageflip crtc %d\n", type);
3130 		return -EINVAL;
3131 	}
3132 
3133 	reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3134 	if (state == AMDGPU_IRQ_STATE_DISABLE)
3135 		WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3136 		       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3137 	else
3138 		WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3139 		       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3140 
3141 	return 0;
3142 }
3143 
3144 static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3145 				  struct amdgpu_irq_src *source,
3146 				  struct amdgpu_iv_entry *entry)
3147 {
3148 	unsigned long flags;
3149 	unsigned crtc_id;
3150 	struct amdgpu_crtc *amdgpu_crtc;
3151 	struct amdgpu_flip_work *works;
3152 
3153 	crtc_id = (entry->src_id - 8) >> 1;
3154 	amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3155 
3156 	if (crtc_id >= adev->mode_info.num_crtc) {
3157 		DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3158 		return -EINVAL;
3159 	}
3160 
3161 	if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3162 	    GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3163 		WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3164 		       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3165 
3166 	/* IRQ could occur when in initial stage */
3167 	if (amdgpu_crtc == NULL)
3168 		return 0;
3169 
3170 	spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3171 	works = amdgpu_crtc->pflip_works;
3172 	if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3173 		DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3174 						 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3175 						 amdgpu_crtc->pflip_status,
3176 						 AMDGPU_FLIP_SUBMITTED);
3177 		spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3178 		return 0;
3179 	}
3180 
3181 	/* page flip completed. clean up */
3182 	amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3183 	amdgpu_crtc->pflip_works = NULL;
3184 
3185 	/* wakeup usersapce */
3186 	if (works->event)
3187 		drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3188 
3189 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3190 
3191 	drm_crtc_vblank_put(&amdgpu_crtc->base);
3192 	schedule_work(&works->unpin_work);
3193 
3194 	return 0;
3195 }
3196 
3197 static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3198 				  int hpd)
3199 {
3200 	u32 tmp;
3201 
3202 	if (hpd >= adev->mode_info.num_hpd) {
3203 		DRM_DEBUG("invalid hdp %d\n", hpd);
3204 		return;
3205 	}
3206 
3207 	tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3208 	tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3209 	WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3210 }
3211 
3212 static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3213 					  int crtc)
3214 {
3215 	u32 tmp;
3216 
3217 	if (crtc >= adev->mode_info.num_crtc) {
3218 		DRM_DEBUG("invalid crtc %d\n", crtc);
3219 		return;
3220 	}
3221 
3222 	tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3223 	tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3224 	WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3225 }
3226 
3227 static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3228 					 int crtc)
3229 {
3230 	u32 tmp;
3231 
3232 	if (crtc >= adev->mode_info.num_crtc) {
3233 		DRM_DEBUG("invalid crtc %d\n", crtc);
3234 		return;
3235 	}
3236 
3237 	tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3238 	tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3239 	WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3240 }
3241 
3242 static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3243 			      struct amdgpu_irq_src *source,
3244 			      struct amdgpu_iv_entry *entry)
3245 {
3246 	unsigned crtc = entry->src_id - 1;
3247 	uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3248 	unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3249 
3250 	switch (entry->src_data[0]) {
3251 	case 0: /* vblank */
3252 		if (disp_int & interrupt_status_offsets[crtc].vblank)
3253 			dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3254 		else
3255 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3256 
3257 		if (amdgpu_irq_enabled(adev, source, irq_type)) {
3258 			drm_handle_vblank(adev_to_drm(adev), crtc);
3259 		}
3260 		DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3261 
3262 		break;
3263 	case 1: /* vline */
3264 		if (disp_int & interrupt_status_offsets[crtc].vline)
3265 			dce_v10_0_crtc_vline_int_ack(adev, crtc);
3266 		else
3267 			DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3268 
3269 		DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3270 
3271 		break;
3272 	default:
3273 		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3274 		break;
3275 	}
3276 
3277 	return 0;
3278 }
3279 
3280 static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3281 			     struct amdgpu_irq_src *source,
3282 			     struct amdgpu_iv_entry *entry)
3283 {
3284 	uint32_t disp_int, mask;
3285 	unsigned hpd;
3286 
3287 	if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3288 		DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3289 		return 0;
3290 	}
3291 
3292 	hpd = entry->src_data[0];
3293 	disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3294 	mask = interrupt_status_offsets[hpd].hpd;
3295 
3296 	if (disp_int & mask) {
3297 		dce_v10_0_hpd_int_ack(adev, hpd);
3298 		schedule_delayed_work(&adev->hotplug_work, 0);
3299 		DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3300 	}
3301 
3302 	return 0;
3303 }
3304 
3305 static int dce_v10_0_set_clockgating_state(void *handle,
3306 					  enum amd_clockgating_state state)
3307 {
3308 	return 0;
3309 }
3310 
3311 static int dce_v10_0_set_powergating_state(void *handle,
3312 					  enum amd_powergating_state state)
3313 {
3314 	return 0;
3315 }
3316 
3317 static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3318 	.name = "dce_v10_0",
3319 	.early_init = dce_v10_0_early_init,
3320 	.late_init = NULL,
3321 	.sw_init = dce_v10_0_sw_init,
3322 	.sw_fini = dce_v10_0_sw_fini,
3323 	.hw_init = dce_v10_0_hw_init,
3324 	.hw_fini = dce_v10_0_hw_fini,
3325 	.suspend = dce_v10_0_suspend,
3326 	.resume = dce_v10_0_resume,
3327 	.is_idle = dce_v10_0_is_idle,
3328 	.wait_for_idle = dce_v10_0_wait_for_idle,
3329 	.check_soft_reset = dce_v10_0_check_soft_reset,
3330 	.soft_reset = dce_v10_0_soft_reset,
3331 	.set_clockgating_state = dce_v10_0_set_clockgating_state,
3332 	.set_powergating_state = dce_v10_0_set_powergating_state,
3333 };
3334 
3335 static void
3336 dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3337 			  struct drm_display_mode *mode,
3338 			  struct drm_display_mode *adjusted_mode)
3339 {
3340 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3341 
3342 	amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3343 
3344 	/* need to call this here rather than in prepare() since we need some crtc info */
3345 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3346 
3347 	/* set scaler clears this on some chips */
3348 	dce_v10_0_set_interleave(encoder->crtc, mode);
3349 
3350 	if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3351 		dce_v10_0_afmt_enable(encoder, true);
3352 		dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3353 	}
3354 }
3355 
3356 static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3357 {
3358 	struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3359 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3360 	struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3361 
3362 	if ((amdgpu_encoder->active_device &
3363 	     (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3364 	    (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3365 	     ENCODER_OBJECT_ID_NONE)) {
3366 		struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3367 		if (dig) {
3368 			dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3369 			if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3370 				dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3371 		}
3372 	}
3373 
3374 	amdgpu_atombios_scratch_regs_lock(adev, true);
3375 
3376 	if (connector) {
3377 		struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3378 
3379 		/* select the clock/data port if it uses a router */
3380 		if (amdgpu_connector->router.cd_valid)
3381 			amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3382 
3383 		/* turn eDP panel on for mode set */
3384 		if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3385 			amdgpu_atombios_encoder_set_edp_panel_power(connector,
3386 							     ATOM_TRANSMITTER_ACTION_POWER_ON);
3387 	}
3388 
3389 	/* this is needed for the pll/ss setup to work correctly in some cases */
3390 	amdgpu_atombios_encoder_set_crtc_source(encoder);
3391 	/* set up the FMT blocks */
3392 	dce_v10_0_program_fmt(encoder);
3393 }
3394 
3395 static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3396 {
3397 	struct drm_device *dev = encoder->dev;
3398 	struct amdgpu_device *adev = drm_to_adev(dev);
3399 
3400 	/* need to call this here as we need the crtc set up */
3401 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3402 	amdgpu_atombios_scratch_regs_lock(adev, false);
3403 }
3404 
3405 static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3406 {
3407 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3408 	struct amdgpu_encoder_atom_dig *dig;
3409 
3410 	amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3411 
3412 	if (amdgpu_atombios_encoder_is_digital(encoder)) {
3413 		if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3414 			dce_v10_0_afmt_enable(encoder, false);
3415 		dig = amdgpu_encoder->enc_priv;
3416 		dig->dig_encoder = -1;
3417 	}
3418 	amdgpu_encoder->active_device = 0;
3419 }
3420 
3421 /* these are handled by the primary encoders */
3422 static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3423 {
3424 
3425 }
3426 
3427 static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3428 {
3429 
3430 }
3431 
3432 static void
3433 dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3434 		      struct drm_display_mode *mode,
3435 		      struct drm_display_mode *adjusted_mode)
3436 {
3437 
3438 }
3439 
3440 static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3441 {
3442 
3443 }
3444 
3445 static void
3446 dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3447 {
3448 
3449 }
3450 
3451 static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3452 	.dpms = dce_v10_0_ext_dpms,
3453 	.prepare = dce_v10_0_ext_prepare,
3454 	.mode_set = dce_v10_0_ext_mode_set,
3455 	.commit = dce_v10_0_ext_commit,
3456 	.disable = dce_v10_0_ext_disable,
3457 	/* no detect for TMDS/LVDS yet */
3458 };
3459 
3460 static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3461 	.dpms = amdgpu_atombios_encoder_dpms,
3462 	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3463 	.prepare = dce_v10_0_encoder_prepare,
3464 	.mode_set = dce_v10_0_encoder_mode_set,
3465 	.commit = dce_v10_0_encoder_commit,
3466 	.disable = dce_v10_0_encoder_disable,
3467 	.detect = amdgpu_atombios_encoder_dig_detect,
3468 };
3469 
3470 static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3471 	.dpms = amdgpu_atombios_encoder_dpms,
3472 	.mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3473 	.prepare = dce_v10_0_encoder_prepare,
3474 	.mode_set = dce_v10_0_encoder_mode_set,
3475 	.commit = dce_v10_0_encoder_commit,
3476 	.detect = amdgpu_atombios_encoder_dac_detect,
3477 };
3478 
3479 static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3480 {
3481 	struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3482 	if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3483 		amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3484 	kfree(amdgpu_encoder->enc_priv);
3485 	drm_encoder_cleanup(encoder);
3486 	kfree(amdgpu_encoder);
3487 }
3488 
3489 static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3490 	.destroy = dce_v10_0_encoder_destroy,
3491 };
3492 
3493 static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3494 				 uint32_t encoder_enum,
3495 				 uint32_t supported_device,
3496 				 u16 caps)
3497 {
3498 	struct drm_device *dev = adev_to_drm(adev);
3499 	struct drm_encoder *encoder;
3500 	struct amdgpu_encoder *amdgpu_encoder;
3501 
3502 	/* see if we already added it */
3503 	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3504 		amdgpu_encoder = to_amdgpu_encoder(encoder);
3505 		if (amdgpu_encoder->encoder_enum == encoder_enum) {
3506 			amdgpu_encoder->devices |= supported_device;
3507 			return;
3508 		}
3509 
3510 	}
3511 
3512 	/* add a new one */
3513 	amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3514 	if (!amdgpu_encoder)
3515 		return;
3516 
3517 	encoder = &amdgpu_encoder->base;
3518 	switch (adev->mode_info.num_crtc) {
3519 	case 1:
3520 		encoder->possible_crtcs = 0x1;
3521 		break;
3522 	case 2:
3523 	default:
3524 		encoder->possible_crtcs = 0x3;
3525 		break;
3526 	case 4:
3527 		encoder->possible_crtcs = 0xf;
3528 		break;
3529 	case 6:
3530 		encoder->possible_crtcs = 0x3f;
3531 		break;
3532 	}
3533 
3534 	amdgpu_encoder->enc_priv = NULL;
3535 
3536 	amdgpu_encoder->encoder_enum = encoder_enum;
3537 	amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3538 	amdgpu_encoder->devices = supported_device;
3539 	amdgpu_encoder->rmx_type = RMX_OFF;
3540 	amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3541 	amdgpu_encoder->is_ext_encoder = false;
3542 	amdgpu_encoder->caps = caps;
3543 
3544 	switch (amdgpu_encoder->encoder_id) {
3545 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3546 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3547 		drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3548 				 DRM_MODE_ENCODER_DAC, NULL);
3549 		drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3550 		break;
3551 	case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3552 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3553 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3554 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3555 	case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3556 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3557 			amdgpu_encoder->rmx_type = RMX_FULL;
3558 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3559 					 DRM_MODE_ENCODER_LVDS, NULL);
3560 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3561 		} else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3562 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3563 					 DRM_MODE_ENCODER_DAC, NULL);
3564 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3565 		} else {
3566 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3567 					 DRM_MODE_ENCODER_TMDS, NULL);
3568 			amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3569 		}
3570 		drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3571 		break;
3572 	case ENCODER_OBJECT_ID_SI170B:
3573 	case ENCODER_OBJECT_ID_CH7303:
3574 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3575 	case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3576 	case ENCODER_OBJECT_ID_TITFP513:
3577 	case ENCODER_OBJECT_ID_VT1623:
3578 	case ENCODER_OBJECT_ID_HDMI_SI1930:
3579 	case ENCODER_OBJECT_ID_TRAVIS:
3580 	case ENCODER_OBJECT_ID_NUTMEG:
3581 		/* these are handled by the primary encoders */
3582 		amdgpu_encoder->is_ext_encoder = true;
3583 		if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3584 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3585 					 DRM_MODE_ENCODER_LVDS, NULL);
3586 		else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3587 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3588 					 DRM_MODE_ENCODER_DAC, NULL);
3589 		else
3590 			drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3591 					 DRM_MODE_ENCODER_TMDS, NULL);
3592 		drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3593 		break;
3594 	}
3595 }
3596 
3597 static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3598 	.bandwidth_update = &dce_v10_0_bandwidth_update,
3599 	.vblank_get_counter = &dce_v10_0_vblank_get_counter,
3600 	.backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3601 	.backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3602 	.hpd_sense = &dce_v10_0_hpd_sense,
3603 	.hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3604 	.hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3605 	.page_flip = &dce_v10_0_page_flip,
3606 	.page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3607 	.add_encoder = &dce_v10_0_encoder_add,
3608 	.add_connector = &amdgpu_connector_add,
3609 };
3610 
3611 static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3612 {
3613 	adev->mode_info.funcs = &dce_v10_0_display_funcs;
3614 }
3615 
3616 static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3617 	.set = dce_v10_0_set_crtc_irq_state,
3618 	.process = dce_v10_0_crtc_irq,
3619 };
3620 
3621 static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3622 	.set = dce_v10_0_set_pageflip_irq_state,
3623 	.process = dce_v10_0_pageflip_irq,
3624 };
3625 
3626 static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3627 	.set = dce_v10_0_set_hpd_irq_state,
3628 	.process = dce_v10_0_hpd_irq,
3629 };
3630 
3631 static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3632 {
3633 	if (adev->mode_info.num_crtc > 0)
3634 		adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3635 	else
3636 		adev->crtc_irq.num_types = 0;
3637 	adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3638 
3639 	adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3640 	adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3641 
3642 	adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3643 	adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3644 }
3645 
3646 const struct amdgpu_ip_block_version dce_v10_0_ip_block = {
3647 	.type = AMD_IP_BLOCK_TYPE_DCE,
3648 	.major = 10,
3649 	.minor = 0,
3650 	.rev = 0,
3651 	.funcs = &dce_v10_0_ip_funcs,
3652 };
3653 
3654 const struct amdgpu_ip_block_version dce_v10_1_ip_block = {
3655 	.type = AMD_IP_BLOCK_TYPE_DCE,
3656 	.major = 10,
3657 	.minor = 1,
3658 	.rev = 0,
3659 	.funcs = &dce_v10_0_ip_funcs,
3660 };
3661