1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <drm/drmP.h> 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "vid.h" 27 28 #include "oss/oss_3_0_1_d.h" 29 #include "oss/oss_3_0_1_sh_mask.h" 30 31 #include "bif/bif_5_1_d.h" 32 #include "bif/bif_5_1_sh_mask.h" 33 34 /* 35 * Interrupts 36 * Starting with r6xx, interrupts are handled via a ring buffer. 37 * Ring buffers are areas of GPU accessible memory that the GPU 38 * writes interrupt vectors into and the host reads vectors out of. 39 * There is a rptr (read pointer) that determines where the 40 * host is currently reading, and a wptr (write pointer) 41 * which determines where the GPU has written. When the 42 * pointers are equal, the ring is idle. When the GPU 43 * writes vectors to the ring buffer, it increments the 44 * wptr. When there is an interrupt, the host then starts 45 * fetching commands and processing them until the pointers are 46 * equal again at which point it updates the rptr. 47 */ 48 49 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev); 50 51 /** 52 * cz_ih_enable_interrupts - Enable the interrupt ring buffer 53 * 54 * @adev: amdgpu_device pointer 55 * 56 * Enable the interrupt ring buffer (VI). 57 */ 58 static void cz_ih_enable_interrupts(struct amdgpu_device *adev) 59 { 60 u32 ih_cntl = RREG32(mmIH_CNTL); 61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 62 63 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1); 64 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1); 65 WREG32(mmIH_CNTL, ih_cntl); 66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 67 adev->irq.ih.enabled = true; 68 } 69 70 /** 71 * cz_ih_disable_interrupts - Disable the interrupt ring buffer 72 * 73 * @adev: amdgpu_device pointer 74 * 75 * Disable the interrupt ring buffer (VI). 76 */ 77 static void cz_ih_disable_interrupts(struct amdgpu_device *adev) 78 { 79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 80 u32 ih_cntl = RREG32(mmIH_CNTL); 81 82 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0); 83 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0); 84 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 85 WREG32(mmIH_CNTL, ih_cntl); 86 /* set rptr, wptr to 0 */ 87 WREG32(mmIH_RB_RPTR, 0); 88 WREG32(mmIH_RB_WPTR, 0); 89 adev->irq.ih.enabled = false; 90 adev->irq.ih.rptr = 0; 91 } 92 93 /** 94 * cz_ih_irq_init - init and enable the interrupt ring 95 * 96 * @adev: amdgpu_device pointer 97 * 98 * Allocate a ring buffer for the interrupt controller, 99 * enable the RLC, disable interrupts, enable the IH 100 * ring buffer and enable it (VI). 101 * Called at device load and reume. 102 * Returns 0 for success, errors for failure. 103 */ 104 static int cz_ih_irq_init(struct amdgpu_device *adev) 105 { 106 int rb_bufsz; 107 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 108 u64 wptr_off; 109 110 /* disable irqs */ 111 cz_ih_disable_interrupts(adev); 112 113 /* setup interrupt control */ 114 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 116 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 117 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 118 */ 119 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0); 120 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 121 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0); 122 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 123 124 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/ 125 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 126 127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 128 ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1); 129 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 130 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); 131 132 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */ 133 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1); 134 135 /* set the writeback address whether it's enabled or not */ 136 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 137 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); 138 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); 139 140 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 141 142 /* set rptr, wptr to 0 */ 143 WREG32(mmIH_RB_RPTR, 0); 144 WREG32(mmIH_RB_WPTR, 0); 145 146 /* Default settings for IH_CNTL (disabled at first) */ 147 ih_cntl = RREG32(mmIH_CNTL); 148 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0); 149 150 if (adev->irq.msi_enabled) 151 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1); 152 WREG32(mmIH_CNTL, ih_cntl); 153 154 pci_set_master(adev->pdev); 155 156 /* enable interrupts */ 157 cz_ih_enable_interrupts(adev); 158 159 return 0; 160 } 161 162 /** 163 * cz_ih_irq_disable - disable interrupts 164 * 165 * @adev: amdgpu_device pointer 166 * 167 * Disable interrupts on the hw (VI). 168 */ 169 static void cz_ih_irq_disable(struct amdgpu_device *adev) 170 { 171 cz_ih_disable_interrupts(adev); 172 173 /* Wait and acknowledge irq */ 174 mdelay(1); 175 } 176 177 /** 178 * cz_ih_get_wptr - get the IH ring buffer wptr 179 * 180 * @adev: amdgpu_device pointer 181 * 182 * Get the IH ring buffer wptr from either the register 183 * or the writeback memory buffer (VI). Also check for 184 * ring buffer overflow and deal with it. 185 * Used by cz_irq_process(VI). 186 * Returns the value of the wptr. 187 */ 188 static u32 cz_ih_get_wptr(struct amdgpu_device *adev) 189 { 190 u32 wptr, tmp; 191 192 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); 193 194 if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { 195 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); 196 /* When a ring buffer overflow happen start parsing interrupt 197 * from the last not overwritten vector (wptr + 16). Hopefully 198 * this should allow us to catchup. 199 */ 200 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 201 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); 202 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; 203 tmp = RREG32(mmIH_RB_CNTL); 204 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1); 205 WREG32(mmIH_RB_CNTL, tmp); 206 } 207 return (wptr & adev->irq.ih.ptr_mask); 208 } 209 210 /** 211 * cz_ih_prescreen_iv - prescreen an interrupt vector 212 * 213 * @adev: amdgpu_device pointer 214 * 215 * Returns true if the interrupt vector should be further processed. 216 */ 217 static bool cz_ih_prescreen_iv(struct amdgpu_device *adev) 218 { 219 /* Process all interrupts */ 220 return true; 221 } 222 223 /** 224 * cz_ih_decode_iv - decode an interrupt vector 225 * 226 * @adev: amdgpu_device pointer 227 * 228 * Decodes the interrupt vector at the current rptr 229 * position and also advance the position. 230 */ 231 static void cz_ih_decode_iv(struct amdgpu_device *adev, 232 struct amdgpu_iv_entry *entry) 233 { 234 /* wptr/rptr are in bytes! */ 235 u32 ring_index = adev->irq.ih.rptr >> 2; 236 uint32_t dw[4]; 237 238 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 239 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); 240 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); 241 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 242 243 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 244 entry->src_id = dw[0] & 0xff; 245 entry->src_data[0] = dw[1] & 0xfffffff; 246 entry->ring_id = dw[2] & 0xff; 247 entry->vm_id = (dw[2] >> 8) & 0xff; 248 entry->pas_id = (dw[2] >> 16) & 0xffff; 249 250 /* wptr/rptr are in bytes! */ 251 adev->irq.ih.rptr += 16; 252 } 253 254 /** 255 * cz_ih_set_rptr - set the IH ring buffer rptr 256 * 257 * @adev: amdgpu_device pointer 258 * 259 * Set the IH ring buffer rptr. 260 */ 261 static void cz_ih_set_rptr(struct amdgpu_device *adev) 262 { 263 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 264 } 265 266 static int cz_ih_early_init(void *handle) 267 { 268 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 269 int ret; 270 271 ret = amdgpu_irq_add_domain(adev); 272 if (ret) 273 return ret; 274 275 cz_ih_set_interrupt_funcs(adev); 276 277 return 0; 278 } 279 280 static int cz_ih_sw_init(void *handle) 281 { 282 int r; 283 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 284 285 r = amdgpu_ih_ring_init(adev, 64 * 1024, false); 286 if (r) 287 return r; 288 289 r = amdgpu_irq_init(adev); 290 291 return r; 292 } 293 294 static int cz_ih_sw_fini(void *handle) 295 { 296 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 297 298 amdgpu_irq_fini(adev); 299 amdgpu_ih_ring_fini(adev); 300 amdgpu_irq_remove_domain(adev); 301 302 return 0; 303 } 304 305 static int cz_ih_hw_init(void *handle) 306 { 307 int r; 308 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 309 310 r = cz_ih_irq_init(adev); 311 if (r) 312 return r; 313 314 return 0; 315 } 316 317 static int cz_ih_hw_fini(void *handle) 318 { 319 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 320 321 cz_ih_irq_disable(adev); 322 323 return 0; 324 } 325 326 static int cz_ih_suspend(void *handle) 327 { 328 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 329 330 return cz_ih_hw_fini(adev); 331 } 332 333 static int cz_ih_resume(void *handle) 334 { 335 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 336 337 return cz_ih_hw_init(adev); 338 } 339 340 static bool cz_ih_is_idle(void *handle) 341 { 342 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 343 u32 tmp = RREG32(mmSRBM_STATUS); 344 345 if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 346 return false; 347 348 return true; 349 } 350 351 static int cz_ih_wait_for_idle(void *handle) 352 { 353 unsigned i; 354 u32 tmp; 355 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 356 357 for (i = 0; i < adev->usec_timeout; i++) { 358 /* read MC_STATUS */ 359 tmp = RREG32(mmSRBM_STATUS); 360 if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY)) 361 return 0; 362 udelay(1); 363 } 364 return -ETIMEDOUT; 365 } 366 367 static int cz_ih_soft_reset(void *handle) 368 { 369 u32 srbm_soft_reset = 0; 370 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 371 u32 tmp = RREG32(mmSRBM_STATUS); 372 373 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 374 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, 375 SOFT_RESET_IH, 1); 376 377 if (srbm_soft_reset) { 378 tmp = RREG32(mmSRBM_SOFT_RESET); 379 tmp |= srbm_soft_reset; 380 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 381 WREG32(mmSRBM_SOFT_RESET, tmp); 382 tmp = RREG32(mmSRBM_SOFT_RESET); 383 384 udelay(50); 385 386 tmp &= ~srbm_soft_reset; 387 WREG32(mmSRBM_SOFT_RESET, tmp); 388 tmp = RREG32(mmSRBM_SOFT_RESET); 389 390 /* Wait a little for things to settle down */ 391 udelay(50); 392 } 393 394 return 0; 395 } 396 397 static int cz_ih_set_clockgating_state(void *handle, 398 enum amd_clockgating_state state) 399 { 400 // TODO 401 return 0; 402 } 403 404 static int cz_ih_set_powergating_state(void *handle, 405 enum amd_powergating_state state) 406 { 407 // TODO 408 return 0; 409 } 410 411 static const struct amd_ip_funcs cz_ih_ip_funcs = { 412 .name = "cz_ih", 413 .early_init = cz_ih_early_init, 414 .late_init = NULL, 415 .sw_init = cz_ih_sw_init, 416 .sw_fini = cz_ih_sw_fini, 417 .hw_init = cz_ih_hw_init, 418 .hw_fini = cz_ih_hw_fini, 419 .suspend = cz_ih_suspend, 420 .resume = cz_ih_resume, 421 .is_idle = cz_ih_is_idle, 422 .wait_for_idle = cz_ih_wait_for_idle, 423 .soft_reset = cz_ih_soft_reset, 424 .set_clockgating_state = cz_ih_set_clockgating_state, 425 .set_powergating_state = cz_ih_set_powergating_state, 426 }; 427 428 static const struct amdgpu_ih_funcs cz_ih_funcs = { 429 .get_wptr = cz_ih_get_wptr, 430 .prescreen_iv = cz_ih_prescreen_iv, 431 .decode_iv = cz_ih_decode_iv, 432 .set_rptr = cz_ih_set_rptr 433 }; 434 435 static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev) 436 { 437 if (adev->irq.ih_funcs == NULL) 438 adev->irq.ih_funcs = &cz_ih_funcs; 439 } 440 441 const struct amdgpu_ip_block_version cz_ih_ip_block = 442 { 443 .type = AMD_IP_BLOCK_TYPE_IH, 444 .major = 3, 445 .minor = 0, 446 .rev = 0, 447 .funcs = &cz_ih_ip_funcs, 448 }; 449