1 /* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #include <linux/firmware.h> 25 #include <drm/drmP.h> 26 #include "amdgpu.h" 27 #include "amdgpu_ucode.h" 28 #include "amdgpu_trace.h" 29 #include "cikd.h" 30 #include "cik.h" 31 32 #include "bif/bif_4_1_d.h" 33 #include "bif/bif_4_1_sh_mask.h" 34 35 #include "gca/gfx_7_2_d.h" 36 #include "gca/gfx_7_2_enum.h" 37 #include "gca/gfx_7_2_sh_mask.h" 38 39 #include "gmc/gmc_7_1_d.h" 40 #include "gmc/gmc_7_1_sh_mask.h" 41 42 #include "oss/oss_2_0_d.h" 43 #include "oss/oss_2_0_sh_mask.h" 44 45 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = 46 { 47 SDMA0_REGISTER_OFFSET, 48 SDMA1_REGISTER_OFFSET 49 }; 50 51 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); 52 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); 53 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); 54 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); 55 static int cik_sdma_soft_reset(void *handle); 56 57 MODULE_FIRMWARE("radeon/bonaire_sdma.bin"); 58 MODULE_FIRMWARE("radeon/bonaire_sdma1.bin"); 59 MODULE_FIRMWARE("radeon/hawaii_sdma.bin"); 60 MODULE_FIRMWARE("radeon/hawaii_sdma1.bin"); 61 MODULE_FIRMWARE("radeon/kaveri_sdma.bin"); 62 MODULE_FIRMWARE("radeon/kaveri_sdma1.bin"); 63 MODULE_FIRMWARE("radeon/kabini_sdma.bin"); 64 MODULE_FIRMWARE("radeon/kabini_sdma1.bin"); 65 MODULE_FIRMWARE("radeon/mullins_sdma.bin"); 66 MODULE_FIRMWARE("radeon/mullins_sdma1.bin"); 67 68 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev); 69 70 71 static void cik_sdma_free_microcode(struct amdgpu_device *adev) 72 { 73 int i; 74 for (i = 0; i < adev->sdma.num_instances; i++) { 75 release_firmware(adev->sdma.instance[i].fw); 76 adev->sdma.instance[i].fw = NULL; 77 } 78 } 79 80 /* 81 * sDMA - System DMA 82 * Starting with CIK, the GPU has new asynchronous 83 * DMA engines. These engines are used for compute 84 * and gfx. There are two DMA engines (SDMA0, SDMA1) 85 * and each one supports 1 ring buffer used for gfx 86 * and 2 queues used for compute. 87 * 88 * The programming model is very similar to the CP 89 * (ring buffer, IBs, etc.), but sDMA has it's own 90 * packet format that is different from the PM4 format 91 * used by the CP. sDMA supports copying data, writing 92 * embedded data, solid fills, and a number of other 93 * things. It also has support for tiling/detiling of 94 * buffers. 95 */ 96 97 /** 98 * cik_sdma_init_microcode - load ucode images from disk 99 * 100 * @adev: amdgpu_device pointer 101 * 102 * Use the firmware interface to load the ucode images into 103 * the driver (not loaded into hw). 104 * Returns 0 on success, error on failure. 105 */ 106 static int cik_sdma_init_microcode(struct amdgpu_device *adev) 107 { 108 const char *chip_name; 109 char fw_name[30]; 110 int err = 0, i; 111 112 DRM_DEBUG("\n"); 113 114 switch (adev->asic_type) { 115 case CHIP_BONAIRE: 116 chip_name = "bonaire"; 117 break; 118 case CHIP_HAWAII: 119 chip_name = "hawaii"; 120 break; 121 case CHIP_KAVERI: 122 chip_name = "kaveri"; 123 break; 124 case CHIP_KABINI: 125 chip_name = "kabini"; 126 break; 127 case CHIP_MULLINS: 128 chip_name = "mullins"; 129 break; 130 default: BUG(); 131 } 132 133 for (i = 0; i < adev->sdma.num_instances; i++) { 134 if (i == 0) 135 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name); 136 else 137 snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name); 138 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); 139 if (err) 140 goto out; 141 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw); 142 } 143 out: 144 if (err) { 145 pr_err("cik_sdma: Failed to load firmware \"%s\"\n", fw_name); 146 for (i = 0; i < adev->sdma.num_instances; i++) { 147 release_firmware(adev->sdma.instance[i].fw); 148 adev->sdma.instance[i].fw = NULL; 149 } 150 } 151 return err; 152 } 153 154 /** 155 * cik_sdma_ring_get_rptr - get the current read pointer 156 * 157 * @ring: amdgpu ring pointer 158 * 159 * Get the current rptr from the hardware (CIK+). 160 */ 161 static uint64_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring) 162 { 163 u32 rptr; 164 165 rptr = ring->adev->wb.wb[ring->rptr_offs]; 166 167 return (rptr & 0x3fffc) >> 2; 168 } 169 170 /** 171 * cik_sdma_ring_get_wptr - get the current write pointer 172 * 173 * @ring: amdgpu ring pointer 174 * 175 * Get the current wptr from the hardware (CIK+). 176 */ 177 static uint64_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring) 178 { 179 struct amdgpu_device *adev = ring->adev; 180 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 181 182 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2; 183 } 184 185 /** 186 * cik_sdma_ring_set_wptr - commit the write pointer 187 * 188 * @ring: amdgpu ring pointer 189 * 190 * Write the wptr back to the hardware (CIK+). 191 */ 192 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) 193 { 194 struct amdgpu_device *adev = ring->adev; 195 u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1; 196 197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], 198 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); 199 } 200 201 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) 202 { 203 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 204 int i; 205 206 for (i = 0; i < count; i++) 207 if (sdma && sdma->burst_nop && (i == 0)) 208 amdgpu_ring_write(ring, ring->funcs->nop | 209 SDMA_NOP_COUNT(count - 1)); 210 else 211 amdgpu_ring_write(ring, ring->funcs->nop); 212 } 213 214 /** 215 * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine 216 * 217 * @ring: amdgpu ring pointer 218 * @ib: IB object to schedule 219 * 220 * Schedule an IB in the DMA ring (CIK). 221 */ 222 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, 223 struct amdgpu_ib *ib, 224 unsigned vm_id, bool ctx_switch) 225 { 226 u32 extra_bits = vm_id & 0xf; 227 228 /* IB packet must end on a 8 DW boundary */ 229 cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8); 230 231 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 232 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 233 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 234 amdgpu_ring_write(ring, ib->length_dw); 235 236 } 237 238 /** 239 * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring 240 * 241 * @ring: amdgpu ring pointer 242 * 243 * Emit an hdp flush packet on the requested DMA ring. 244 */ 245 static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) 246 { 247 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | 248 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ 249 u32 ref_and_mask; 250 251 if (ring == &ring->adev->sdma.instance[0].ring) 252 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK; 253 else 254 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK; 255 256 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 257 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2); 258 amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2); 259 amdgpu_ring_write(ring, ref_and_mask); /* reference */ 260 amdgpu_ring_write(ring, ref_and_mask); /* mask */ 261 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 262 } 263 264 static void cik_sdma_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) 265 { 266 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 267 amdgpu_ring_write(ring, mmHDP_DEBUG0); 268 amdgpu_ring_write(ring, 1); 269 } 270 271 /** 272 * cik_sdma_ring_emit_fence - emit a fence on the DMA ring 273 * 274 * @ring: amdgpu ring pointer 275 * @fence: amdgpu fence object 276 * 277 * Add a DMA fence packet to the ring to write 278 * the fence seq number and DMA trap packet to generate 279 * an interrupt if needed (CIK). 280 */ 281 static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 282 unsigned flags) 283 { 284 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 285 /* write the fence */ 286 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 287 amdgpu_ring_write(ring, lower_32_bits(addr)); 288 amdgpu_ring_write(ring, upper_32_bits(addr)); 289 amdgpu_ring_write(ring, lower_32_bits(seq)); 290 291 /* optionally write high bits as well */ 292 if (write64bit) { 293 addr += 4; 294 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 295 amdgpu_ring_write(ring, lower_32_bits(addr)); 296 amdgpu_ring_write(ring, upper_32_bits(addr)); 297 amdgpu_ring_write(ring, upper_32_bits(seq)); 298 } 299 300 /* generate an interrupt */ 301 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 302 } 303 304 /** 305 * cik_sdma_gfx_stop - stop the gfx async dma engines 306 * 307 * @adev: amdgpu_device pointer 308 * 309 * Stop the gfx async dma ring buffers (CIK). 310 */ 311 static void cik_sdma_gfx_stop(struct amdgpu_device *adev) 312 { 313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; 314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; 315 u32 rb_cntl; 316 int i; 317 318 if ((adev->mman.buffer_funcs_ring == sdma0) || 319 (adev->mman.buffer_funcs_ring == sdma1)) 320 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size); 321 322 for (i = 0; i < adev->sdma.num_instances; i++) { 323 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); 324 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; 325 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 326 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); 327 } 328 sdma0->ready = false; 329 sdma1->ready = false; 330 } 331 332 /** 333 * cik_sdma_rlc_stop - stop the compute async dma engines 334 * 335 * @adev: amdgpu_device pointer 336 * 337 * Stop the compute async dma queues (CIK). 338 */ 339 static void cik_sdma_rlc_stop(struct amdgpu_device *adev) 340 { 341 /* XXX todo */ 342 } 343 344 /** 345 * cik_ctx_switch_enable - stop the async dma engines context switch 346 * 347 * @adev: amdgpu_device pointer 348 * @enable: enable/disable the DMA MEs context switch. 349 * 350 * Halt or unhalt the async dma engines context switch (VI). 351 */ 352 static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable) 353 { 354 u32 f32_cntl, phase_quantum = 0; 355 int i; 356 357 if (amdgpu_sdma_phase_quantum) { 358 unsigned value = amdgpu_sdma_phase_quantum; 359 unsigned unit = 0; 360 361 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 362 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { 363 value = (value + 1) >> 1; 364 unit++; 365 } 366 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 367 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) { 368 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> 369 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); 370 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >> 371 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT); 372 WARN_ONCE(1, 373 "clamping sdma_phase_quantum to %uK clock cycles\n", 374 value << unit); 375 } 376 phase_quantum = 377 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | 378 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT; 379 } 380 381 for (i = 0; i < adev->sdma.num_instances; i++) { 382 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 383 if (enable) { 384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 385 AUTO_CTXSW_ENABLE, 1); 386 if (amdgpu_sdma_phase_quantum) { 387 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], 388 phase_quantum); 389 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], 390 phase_quantum); 391 } 392 } else { 393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 394 AUTO_CTXSW_ENABLE, 0); 395 } 396 397 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); 398 } 399 } 400 401 /** 402 * cik_sdma_enable - stop the async dma engines 403 * 404 * @adev: amdgpu_device pointer 405 * @enable: enable/disable the DMA MEs. 406 * 407 * Halt or unhalt the async dma engines (CIK). 408 */ 409 static void cik_sdma_enable(struct amdgpu_device *adev, bool enable) 410 { 411 u32 me_cntl; 412 int i; 413 414 if (!enable) { 415 cik_sdma_gfx_stop(adev); 416 cik_sdma_rlc_stop(adev); 417 } 418 419 for (i = 0; i < adev->sdma.num_instances; i++) { 420 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 421 if (enable) 422 me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK; 423 else 424 me_cntl |= SDMA0_F32_CNTL__HALT_MASK; 425 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); 426 } 427 } 428 429 /** 430 * cik_sdma_gfx_resume - setup and start the async dma engines 431 * 432 * @adev: amdgpu_device pointer 433 * 434 * Set up the gfx DMA ring buffers and enable them (CIK). 435 * Returns 0 for success, error for failure. 436 */ 437 static int cik_sdma_gfx_resume(struct amdgpu_device *adev) 438 { 439 struct amdgpu_ring *ring; 440 u32 rb_cntl, ib_cntl; 441 u32 rb_bufsz; 442 u32 wb_offset; 443 int i, j, r; 444 445 for (i = 0; i < adev->sdma.num_instances; i++) { 446 ring = &adev->sdma.instance[i].ring; 447 wb_offset = (ring->rptr_offs * 4); 448 449 mutex_lock(&adev->srbm_mutex); 450 for (j = 0; j < 16; j++) { 451 cik_srbm_select(adev, 0, 0, 0, j); 452 /* SDMA GFX */ 453 WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0); 454 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); 455 /* XXX SDMA RLC - todo */ 456 } 457 cik_srbm_select(adev, 0, 0, 0, 0); 458 mutex_unlock(&adev->srbm_mutex); 459 460 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], 461 adev->gfx.config.gb_addr_config & 0x70); 462 463 WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0); 464 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); 465 466 /* Set ring buffer size in dwords */ 467 rb_bufsz = order_base_2(ring->ring_size / 4); 468 rb_cntl = rb_bufsz << 1; 469 #ifdef __BIG_ENDIAN 470 rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | 471 SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_SWAP_ENABLE_MASK; 472 #endif 473 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); 474 475 /* Initialize the ring buffer's read and write pointers */ 476 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); 477 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); 478 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); 479 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); 480 481 /* set the wb address whether it's enabled or not */ 482 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], 483 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); 484 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i], 485 ((adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); 486 487 rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; 488 489 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8); 490 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40); 491 492 ring->wptr = 0; 493 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); 494 495 /* enable DMA RB */ 496 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], 497 rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); 498 499 ib_cntl = SDMA0_GFX_IB_CNTL__IB_ENABLE_MASK; 500 #ifdef __BIG_ENDIAN 501 ib_cntl |= SDMA0_GFX_IB_CNTL__IB_SWAP_ENABLE_MASK; 502 #endif 503 /* enable DMA IBs */ 504 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); 505 506 ring->ready = true; 507 } 508 509 cik_sdma_enable(adev, true); 510 511 for (i = 0; i < adev->sdma.num_instances; i++) { 512 ring = &adev->sdma.instance[i].ring; 513 r = amdgpu_ring_test_ring(ring); 514 if (r) { 515 ring->ready = false; 516 return r; 517 } 518 519 if (adev->mman.buffer_funcs_ring == ring) 520 amdgpu_ttm_set_active_vram_size(adev, adev->mc.real_vram_size); 521 } 522 523 return 0; 524 } 525 526 /** 527 * cik_sdma_rlc_resume - setup and start the async dma engines 528 * 529 * @adev: amdgpu_device pointer 530 * 531 * Set up the compute DMA queues and enable them (CIK). 532 * Returns 0 for success, error for failure. 533 */ 534 static int cik_sdma_rlc_resume(struct amdgpu_device *adev) 535 { 536 /* XXX todo */ 537 return 0; 538 } 539 540 /** 541 * cik_sdma_load_microcode - load the sDMA ME ucode 542 * 543 * @adev: amdgpu_device pointer 544 * 545 * Loads the sDMA0/1 ucode. 546 * Returns 0 for success, -EINVAL if the ucode is not available. 547 */ 548 static int cik_sdma_load_microcode(struct amdgpu_device *adev) 549 { 550 const struct sdma_firmware_header_v1_0 *hdr; 551 const __le32 *fw_data; 552 u32 fw_size; 553 int i, j; 554 555 /* halt the MEs */ 556 cik_sdma_enable(adev, false); 557 558 for (i = 0; i < adev->sdma.num_instances; i++) { 559 if (!adev->sdma.instance[i].fw) 560 return -EINVAL; 561 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data; 562 amdgpu_ucode_print_sdma_hdr(&hdr->header); 563 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 564 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version); 565 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version); 566 if (adev->sdma.instance[i].feature_version >= 20) 567 adev->sdma.instance[i].burst_nop = true; 568 fw_data = (const __le32 *) 569 (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 570 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0); 571 for (j = 0; j < fw_size; j++) 572 WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++)); 573 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version); 574 } 575 576 return 0; 577 } 578 579 /** 580 * cik_sdma_start - setup and start the async dma engines 581 * 582 * @adev: amdgpu_device pointer 583 * 584 * Set up the DMA engines and enable them (CIK). 585 * Returns 0 for success, error for failure. 586 */ 587 static int cik_sdma_start(struct amdgpu_device *adev) 588 { 589 int r; 590 591 r = cik_sdma_load_microcode(adev); 592 if (r) 593 return r; 594 595 /* halt the engine before programing */ 596 cik_sdma_enable(adev, false); 597 /* enable sdma ring preemption */ 598 cik_ctx_switch_enable(adev, true); 599 600 /* start the gfx rings and rlc compute queues */ 601 r = cik_sdma_gfx_resume(adev); 602 if (r) 603 return r; 604 r = cik_sdma_rlc_resume(adev); 605 if (r) 606 return r; 607 608 return 0; 609 } 610 611 /** 612 * cik_sdma_ring_test_ring - simple async dma engine test 613 * 614 * @ring: amdgpu_ring structure holding ring information 615 * 616 * Test the DMA engine by writing using it to write an 617 * value to memory. (CIK). 618 * Returns 0 for success, error for failure. 619 */ 620 static int cik_sdma_ring_test_ring(struct amdgpu_ring *ring) 621 { 622 struct amdgpu_device *adev = ring->adev; 623 unsigned i; 624 unsigned index; 625 int r; 626 u32 tmp; 627 u64 gpu_addr; 628 629 r = amdgpu_wb_get(adev, &index); 630 if (r) { 631 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r); 632 return r; 633 } 634 635 gpu_addr = adev->wb.gpu_addr + (index * 4); 636 tmp = 0xCAFEDEAD; 637 adev->wb.wb[index] = cpu_to_le32(tmp); 638 639 r = amdgpu_ring_alloc(ring, 5); 640 if (r) { 641 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r); 642 amdgpu_wb_free(adev, index); 643 return r; 644 } 645 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 646 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); 647 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); 648 amdgpu_ring_write(ring, 1); /* number of DWs to follow */ 649 amdgpu_ring_write(ring, 0xDEADBEEF); 650 amdgpu_ring_commit(ring); 651 652 for (i = 0; i < adev->usec_timeout; i++) { 653 tmp = le32_to_cpu(adev->wb.wb[index]); 654 if (tmp == 0xDEADBEEF) 655 break; 656 DRM_UDELAY(1); 657 } 658 659 if (i < adev->usec_timeout) { 660 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i); 661 } else { 662 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n", 663 ring->idx, tmp); 664 r = -EINVAL; 665 } 666 amdgpu_wb_free(adev, index); 667 668 return r; 669 } 670 671 /** 672 * cik_sdma_ring_test_ib - test an IB on the DMA engine 673 * 674 * @ring: amdgpu_ring structure holding ring information 675 * 676 * Test a simple IB in the DMA ring (CIK). 677 * Returns 0 on success, error on failure. 678 */ 679 static int cik_sdma_ring_test_ib(struct amdgpu_ring *ring, long timeout) 680 { 681 struct amdgpu_device *adev = ring->adev; 682 struct amdgpu_ib ib; 683 struct dma_fence *f = NULL; 684 unsigned index; 685 u32 tmp = 0; 686 u64 gpu_addr; 687 long r; 688 689 r = amdgpu_wb_get(adev, &index); 690 if (r) { 691 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r); 692 return r; 693 } 694 695 gpu_addr = adev->wb.gpu_addr + (index * 4); 696 tmp = 0xCAFEDEAD; 697 adev->wb.wb[index] = cpu_to_le32(tmp); 698 memset(&ib, 0, sizeof(ib)); 699 r = amdgpu_ib_get(adev, NULL, 256, &ib); 700 if (r) { 701 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); 702 goto err0; 703 } 704 705 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, 706 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 707 ib.ptr[1] = lower_32_bits(gpu_addr); 708 ib.ptr[2] = upper_32_bits(gpu_addr); 709 ib.ptr[3] = 1; 710 ib.ptr[4] = 0xDEADBEEF; 711 ib.length_dw = 5; 712 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); 713 if (r) 714 goto err1; 715 716 r = dma_fence_wait_timeout(f, false, timeout); 717 if (r == 0) { 718 DRM_ERROR("amdgpu: IB test timed out\n"); 719 r = -ETIMEDOUT; 720 goto err1; 721 } else if (r < 0) { 722 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); 723 goto err1; 724 } 725 tmp = le32_to_cpu(adev->wb.wb[index]); 726 if (tmp == 0xDEADBEEF) { 727 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 728 r = 0; 729 } else { 730 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp); 731 r = -EINVAL; 732 } 733 734 err1: 735 amdgpu_ib_free(adev, &ib, NULL); 736 dma_fence_put(f); 737 err0: 738 amdgpu_wb_free(adev, index); 739 return r; 740 } 741 742 /** 743 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART 744 * 745 * @ib: indirect buffer to fill with commands 746 * @pe: addr of the page entry 747 * @src: src addr to copy from 748 * @count: number of page entries to update 749 * 750 * Update PTEs by copying them from the GART using sDMA (CIK). 751 */ 752 static void cik_sdma_vm_copy_pte(struct amdgpu_ib *ib, 753 uint64_t pe, uint64_t src, 754 unsigned count) 755 { 756 unsigned bytes = count * 8; 757 758 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, 759 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 760 ib->ptr[ib->length_dw++] = bytes; 761 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 762 ib->ptr[ib->length_dw++] = lower_32_bits(src); 763 ib->ptr[ib->length_dw++] = upper_32_bits(src); 764 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 765 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 766 } 767 768 /** 769 * cik_sdma_vm_write_pages - update PTEs by writing them manually 770 * 771 * @ib: indirect buffer to fill with commands 772 * @pe: addr of the page entry 773 * @value: dst addr to write into pe 774 * @count: number of page entries to update 775 * @incr: increase next addr by incr bytes 776 * 777 * Update PTEs by writing them manually using sDMA (CIK). 778 */ 779 static void cik_sdma_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe, 780 uint64_t value, unsigned count, 781 uint32_t incr) 782 { 783 unsigned ndw = count * 2; 784 785 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE, 786 SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 787 ib->ptr[ib->length_dw++] = lower_32_bits(pe); 788 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 789 ib->ptr[ib->length_dw++] = ndw; 790 for (; ndw > 0; ndw -= 2) { 791 ib->ptr[ib->length_dw++] = lower_32_bits(value); 792 ib->ptr[ib->length_dw++] = upper_32_bits(value); 793 value += incr; 794 } 795 } 796 797 /** 798 * cik_sdma_vm_set_pages - update the page tables using sDMA 799 * 800 * @ib: indirect buffer to fill with commands 801 * @pe: addr of the page entry 802 * @addr: dst addr to write into pe 803 * @count: number of page entries to update 804 * @incr: increase next addr by incr bytes 805 * @flags: access flags 806 * 807 * Update the page tables using sDMA (CIK). 808 */ 809 static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe, 810 uint64_t addr, unsigned count, 811 uint32_t incr, uint64_t flags) 812 { 813 /* for physically contiguous pages (vram) */ 814 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0); 815 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */ 816 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 817 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */ 818 ib->ptr[ib->length_dw++] = upper_32_bits(flags); 819 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */ 820 ib->ptr[ib->length_dw++] = upper_32_bits(addr); 821 ib->ptr[ib->length_dw++] = incr; /* increment size */ 822 ib->ptr[ib->length_dw++] = 0; 823 ib->ptr[ib->length_dw++] = count; /* number of entries */ 824 } 825 826 /** 827 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw 828 * 829 * @ib: indirect buffer to fill with padding 830 * 831 */ 832 static void cik_sdma_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) 833 { 834 struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring); 835 u32 pad_count; 836 int i; 837 838 pad_count = (8 - (ib->length_dw & 0x7)) % 8; 839 for (i = 0; i < pad_count; i++) 840 if (sdma && sdma->burst_nop && (i == 0)) 841 ib->ptr[ib->length_dw++] = 842 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0) | 843 SDMA_NOP_COUNT(pad_count - 1); 844 else 845 ib->ptr[ib->length_dw++] = 846 SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0); 847 } 848 849 /** 850 * cik_sdma_ring_emit_pipeline_sync - sync the pipeline 851 * 852 * @ring: amdgpu_ring pointer 853 * 854 * Make sure all previous operations are completed (CIK). 855 */ 856 static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 857 { 858 uint32_t seq = ring->fence_drv.sync_seq; 859 uint64_t addr = ring->fence_drv.gpu_addr; 860 861 /* wait for idle */ 862 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, 863 SDMA_POLL_REG_MEM_EXTRA_OP(0) | 864 SDMA_POLL_REG_MEM_EXTRA_FUNC(3) | /* equal */ 865 SDMA_POLL_REG_MEM_EXTRA_M)); 866 amdgpu_ring_write(ring, addr & 0xfffffffc); 867 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 868 amdgpu_ring_write(ring, seq); /* reference */ 869 amdgpu_ring_write(ring, 0xfffffff); /* mask */ 870 amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */ 871 } 872 873 /** 874 * cik_sdma_ring_emit_vm_flush - cik vm flush using sDMA 875 * 876 * @ring: amdgpu_ring pointer 877 * @vm: amdgpu_vm pointer 878 * 879 * Update the page table base and flush the VM TLB 880 * using sDMA (CIK). 881 */ 882 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, 883 unsigned vm_id, uint64_t pd_addr) 884 { 885 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) | 886 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */ 887 888 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 889 if (vm_id < 8) { 890 amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id)); 891 } else { 892 amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8)); 893 } 894 amdgpu_ring_write(ring, pd_addr >> 12); 895 896 /* flush TLB */ 897 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); 898 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST); 899 amdgpu_ring_write(ring, 1 << vm_id); 900 901 amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); 902 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2); 903 amdgpu_ring_write(ring, 0); 904 amdgpu_ring_write(ring, 0); /* reference */ 905 amdgpu_ring_write(ring, 0); /* mask */ 906 amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ 907 } 908 909 static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, 910 bool enable) 911 { 912 u32 orig, data; 913 914 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) { 915 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); 916 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); 917 } else { 918 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); 919 data |= 0xff000000; 920 if (data != orig) 921 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); 922 923 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); 924 data |= 0xff000000; 925 if (data != orig) 926 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); 927 } 928 } 929 930 static void cik_enable_sdma_mgls(struct amdgpu_device *adev, 931 bool enable) 932 { 933 u32 orig, data; 934 935 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) { 936 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 937 data |= 0x100; 938 if (orig != data) 939 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 940 941 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 942 data |= 0x100; 943 if (orig != data) 944 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 945 } else { 946 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 947 data &= ~0x100; 948 if (orig != data) 949 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 950 951 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 952 data &= ~0x100; 953 if (orig != data) 954 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 955 } 956 } 957 958 static int cik_sdma_early_init(void *handle) 959 { 960 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 961 962 adev->sdma.num_instances = SDMA_MAX_INSTANCE; 963 964 cik_sdma_set_ring_funcs(adev); 965 cik_sdma_set_irq_funcs(adev); 966 cik_sdma_set_buffer_funcs(adev); 967 cik_sdma_set_vm_pte_funcs(adev); 968 969 return 0; 970 } 971 972 static int cik_sdma_sw_init(void *handle) 973 { 974 struct amdgpu_ring *ring; 975 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 976 int r, i; 977 978 r = cik_sdma_init_microcode(adev); 979 if (r) { 980 DRM_ERROR("Failed to load sdma firmware!\n"); 981 return r; 982 } 983 984 /* SDMA trap event */ 985 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, 986 &adev->sdma.trap_irq); 987 if (r) 988 return r; 989 990 /* SDMA Privileged inst */ 991 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, 992 &adev->sdma.illegal_inst_irq); 993 if (r) 994 return r; 995 996 /* SDMA Privileged inst */ 997 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, 998 &adev->sdma.illegal_inst_irq); 999 if (r) 1000 return r; 1001 1002 for (i = 0; i < adev->sdma.num_instances; i++) { 1003 ring = &adev->sdma.instance[i].ring; 1004 ring->ring_obj = NULL; 1005 sprintf(ring->name, "sdma%d", i); 1006 r = amdgpu_ring_init(adev, ring, 1024, 1007 &adev->sdma.trap_irq, 1008 (i == 0) ? 1009 AMDGPU_SDMA_IRQ_TRAP0 : 1010 AMDGPU_SDMA_IRQ_TRAP1); 1011 if (r) 1012 return r; 1013 } 1014 1015 return r; 1016 } 1017 1018 static int cik_sdma_sw_fini(void *handle) 1019 { 1020 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1021 int i; 1022 1023 for (i = 0; i < adev->sdma.num_instances; i++) 1024 amdgpu_ring_fini(&adev->sdma.instance[i].ring); 1025 1026 cik_sdma_free_microcode(adev); 1027 return 0; 1028 } 1029 1030 static int cik_sdma_hw_init(void *handle) 1031 { 1032 int r; 1033 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1034 1035 r = cik_sdma_start(adev); 1036 if (r) 1037 return r; 1038 1039 return r; 1040 } 1041 1042 static int cik_sdma_hw_fini(void *handle) 1043 { 1044 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1045 1046 cik_ctx_switch_enable(adev, false); 1047 cik_sdma_enable(adev, false); 1048 1049 return 0; 1050 } 1051 1052 static int cik_sdma_suspend(void *handle) 1053 { 1054 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1055 1056 return cik_sdma_hw_fini(adev); 1057 } 1058 1059 static int cik_sdma_resume(void *handle) 1060 { 1061 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1062 1063 cik_sdma_soft_reset(handle); 1064 1065 return cik_sdma_hw_init(adev); 1066 } 1067 1068 static bool cik_sdma_is_idle(void *handle) 1069 { 1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1071 u32 tmp = RREG32(mmSRBM_STATUS2); 1072 1073 if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK | 1074 SRBM_STATUS2__SDMA1_BUSY_MASK)) 1075 return false; 1076 1077 return true; 1078 } 1079 1080 static int cik_sdma_wait_for_idle(void *handle) 1081 { 1082 unsigned i; 1083 u32 tmp; 1084 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1085 1086 for (i = 0; i < adev->usec_timeout; i++) { 1087 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | 1088 SRBM_STATUS2__SDMA1_BUSY_MASK); 1089 1090 if (!tmp) 1091 return 0; 1092 udelay(1); 1093 } 1094 return -ETIMEDOUT; 1095 } 1096 1097 static int cik_sdma_soft_reset(void *handle) 1098 { 1099 u32 srbm_soft_reset = 0; 1100 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1101 u32 tmp = RREG32(mmSRBM_STATUS2); 1102 1103 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { 1104 /* sdma0 */ 1105 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1106 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1107 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1108 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1109 } 1110 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) { 1111 /* sdma1 */ 1112 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1113 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1114 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1115 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1116 } 1117 1118 if (srbm_soft_reset) { 1119 tmp = RREG32(mmSRBM_SOFT_RESET); 1120 tmp |= srbm_soft_reset; 1121 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1122 WREG32(mmSRBM_SOFT_RESET, tmp); 1123 tmp = RREG32(mmSRBM_SOFT_RESET); 1124 1125 udelay(50); 1126 1127 tmp &= ~srbm_soft_reset; 1128 WREG32(mmSRBM_SOFT_RESET, tmp); 1129 tmp = RREG32(mmSRBM_SOFT_RESET); 1130 1131 /* Wait a little for things to settle down */ 1132 udelay(50); 1133 } 1134 1135 return 0; 1136 } 1137 1138 static int cik_sdma_set_trap_irq_state(struct amdgpu_device *adev, 1139 struct amdgpu_irq_src *src, 1140 unsigned type, 1141 enum amdgpu_interrupt_state state) 1142 { 1143 u32 sdma_cntl; 1144 1145 switch (type) { 1146 case AMDGPU_SDMA_IRQ_TRAP0: 1147 switch (state) { 1148 case AMDGPU_IRQ_STATE_DISABLE: 1149 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1150 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1151 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1152 break; 1153 case AMDGPU_IRQ_STATE_ENABLE: 1154 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); 1155 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1156 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); 1157 break; 1158 default: 1159 break; 1160 } 1161 break; 1162 case AMDGPU_SDMA_IRQ_TRAP1: 1163 switch (state) { 1164 case AMDGPU_IRQ_STATE_DISABLE: 1165 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1166 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; 1167 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1168 break; 1169 case AMDGPU_IRQ_STATE_ENABLE: 1170 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET); 1171 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; 1172 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); 1173 break; 1174 default: 1175 break; 1176 } 1177 break; 1178 default: 1179 break; 1180 } 1181 return 0; 1182 } 1183 1184 static int cik_sdma_process_trap_irq(struct amdgpu_device *adev, 1185 struct amdgpu_irq_src *source, 1186 struct amdgpu_iv_entry *entry) 1187 { 1188 u8 instance_id, queue_id; 1189 1190 instance_id = (entry->ring_id & 0x3) >> 0; 1191 queue_id = (entry->ring_id & 0xc) >> 2; 1192 DRM_DEBUG("IH: SDMA trap\n"); 1193 switch (instance_id) { 1194 case 0: 1195 switch (queue_id) { 1196 case 0: 1197 amdgpu_fence_process(&adev->sdma.instance[0].ring); 1198 break; 1199 case 1: 1200 /* XXX compute */ 1201 break; 1202 case 2: 1203 /* XXX compute */ 1204 break; 1205 } 1206 break; 1207 case 1: 1208 switch (queue_id) { 1209 case 0: 1210 amdgpu_fence_process(&adev->sdma.instance[1].ring); 1211 break; 1212 case 1: 1213 /* XXX compute */ 1214 break; 1215 case 2: 1216 /* XXX compute */ 1217 break; 1218 } 1219 break; 1220 } 1221 1222 return 0; 1223 } 1224 1225 static int cik_sdma_process_illegal_inst_irq(struct amdgpu_device *adev, 1226 struct amdgpu_irq_src *source, 1227 struct amdgpu_iv_entry *entry) 1228 { 1229 DRM_ERROR("Illegal instruction in SDMA command stream\n"); 1230 schedule_work(&adev->reset_work); 1231 return 0; 1232 } 1233 1234 static int cik_sdma_set_clockgating_state(void *handle, 1235 enum amd_clockgating_state state) 1236 { 1237 bool gate = false; 1238 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1239 1240 if (state == AMD_CG_STATE_GATE) 1241 gate = true; 1242 1243 cik_enable_sdma_mgcg(adev, gate); 1244 cik_enable_sdma_mgls(adev, gate); 1245 1246 return 0; 1247 } 1248 1249 static int cik_sdma_set_powergating_state(void *handle, 1250 enum amd_powergating_state state) 1251 { 1252 return 0; 1253 } 1254 1255 static const struct amd_ip_funcs cik_sdma_ip_funcs = { 1256 .name = "cik_sdma", 1257 .early_init = cik_sdma_early_init, 1258 .late_init = NULL, 1259 .sw_init = cik_sdma_sw_init, 1260 .sw_fini = cik_sdma_sw_fini, 1261 .hw_init = cik_sdma_hw_init, 1262 .hw_fini = cik_sdma_hw_fini, 1263 .suspend = cik_sdma_suspend, 1264 .resume = cik_sdma_resume, 1265 .is_idle = cik_sdma_is_idle, 1266 .wait_for_idle = cik_sdma_wait_for_idle, 1267 .soft_reset = cik_sdma_soft_reset, 1268 .set_clockgating_state = cik_sdma_set_clockgating_state, 1269 .set_powergating_state = cik_sdma_set_powergating_state, 1270 }; 1271 1272 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { 1273 .type = AMDGPU_RING_TYPE_SDMA, 1274 .align_mask = 0xf, 1275 .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 1276 .support_64bit_ptrs = false, 1277 .get_rptr = cik_sdma_ring_get_rptr, 1278 .get_wptr = cik_sdma_ring_get_wptr, 1279 .set_wptr = cik_sdma_ring_set_wptr, 1280 .emit_frame_size = 1281 6 + /* cik_sdma_ring_emit_hdp_flush */ 1282 3 + /* cik_sdma_ring_emit_hdp_invalidate */ 1283 6 + /* cik_sdma_ring_emit_pipeline_sync */ 1284 12 + /* cik_sdma_ring_emit_vm_flush */ 1285 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ 1286 .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ 1287 .emit_ib = cik_sdma_ring_emit_ib, 1288 .emit_fence = cik_sdma_ring_emit_fence, 1289 .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, 1290 .emit_vm_flush = cik_sdma_ring_emit_vm_flush, 1291 .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, 1292 .emit_hdp_invalidate = cik_sdma_ring_emit_hdp_invalidate, 1293 .test_ring = cik_sdma_ring_test_ring, 1294 .test_ib = cik_sdma_ring_test_ib, 1295 .insert_nop = cik_sdma_ring_insert_nop, 1296 .pad_ib = cik_sdma_ring_pad_ib, 1297 }; 1298 1299 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) 1300 { 1301 int i; 1302 1303 for (i = 0; i < adev->sdma.num_instances; i++) 1304 adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs; 1305 } 1306 1307 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = { 1308 .set = cik_sdma_set_trap_irq_state, 1309 .process = cik_sdma_process_trap_irq, 1310 }; 1311 1312 static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = { 1313 .process = cik_sdma_process_illegal_inst_irq, 1314 }; 1315 1316 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev) 1317 { 1318 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST; 1319 adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs; 1320 adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs; 1321 } 1322 1323 /** 1324 * cik_sdma_emit_copy_buffer - copy buffer using the sDMA engine 1325 * 1326 * @ring: amdgpu_ring structure holding ring information 1327 * @src_offset: src GPU address 1328 * @dst_offset: dst GPU address 1329 * @byte_count: number of bytes to xfer 1330 * 1331 * Copy GPU buffers using the DMA engine (CIK). 1332 * Used by the amdgpu ttm implementation to move pages if 1333 * registered as the asic copy callback. 1334 */ 1335 static void cik_sdma_emit_copy_buffer(struct amdgpu_ib *ib, 1336 uint64_t src_offset, 1337 uint64_t dst_offset, 1338 uint32_t byte_count) 1339 { 1340 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); 1341 ib->ptr[ib->length_dw++] = byte_count; 1342 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 1343 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset); 1344 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset); 1345 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1346 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1347 } 1348 1349 /** 1350 * cik_sdma_emit_fill_buffer - fill buffer using the sDMA engine 1351 * 1352 * @ring: amdgpu_ring structure holding ring information 1353 * @src_data: value to write to buffer 1354 * @dst_offset: dst GPU address 1355 * @byte_count: number of bytes to xfer 1356 * 1357 * Fill GPU buffers using the DMA engine (CIK). 1358 */ 1359 static void cik_sdma_emit_fill_buffer(struct amdgpu_ib *ib, 1360 uint32_t src_data, 1361 uint64_t dst_offset, 1362 uint32_t byte_count) 1363 { 1364 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, 0); 1365 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); 1366 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); 1367 ib->ptr[ib->length_dw++] = src_data; 1368 ib->ptr[ib->length_dw++] = byte_count; 1369 } 1370 1371 static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = { 1372 .copy_max_bytes = 0x1fffff, 1373 .copy_num_dw = 7, 1374 .emit_copy_buffer = cik_sdma_emit_copy_buffer, 1375 1376 .fill_max_bytes = 0x1fffff, 1377 .fill_num_dw = 5, 1378 .emit_fill_buffer = cik_sdma_emit_fill_buffer, 1379 }; 1380 1381 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev) 1382 { 1383 if (adev->mman.buffer_funcs == NULL) { 1384 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs; 1385 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; 1386 } 1387 } 1388 1389 static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = { 1390 .copy_pte_num_dw = 7, 1391 .copy_pte = cik_sdma_vm_copy_pte, 1392 1393 .write_pte = cik_sdma_vm_write_pte, 1394 1395 .set_max_nums_pte_pde = 0x1fffff >> 3, 1396 .set_pte_pde_num_dw = 10, 1397 .set_pte_pde = cik_sdma_vm_set_pte_pde, 1398 }; 1399 1400 static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev) 1401 { 1402 unsigned i; 1403 1404 if (adev->vm_manager.vm_pte_funcs == NULL) { 1405 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs; 1406 for (i = 0; i < adev->sdma.num_instances; i++) 1407 adev->vm_manager.vm_pte_rings[i] = 1408 &adev->sdma.instance[i].ring; 1409 1410 adev->vm_manager.vm_pte_num_rings = adev->sdma.num_instances; 1411 } 1412 } 1413 1414 const struct amdgpu_ip_block_version cik_sdma_ip_block = 1415 { 1416 .type = AMD_IP_BLOCK_TYPE_SDMA, 1417 .major = 2, 1418 .minor = 0, 1419 .rev = 0, 1420 .funcs = &cik_sdma_ip_funcs, 1421 }; 1422