1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include "drmP.h" 24 #include "amdgpu.h" 25 #include "amdgpu_ih.h" 26 #include "cikd.h" 27 28 #include "bif/bif_4_1_d.h" 29 #include "bif/bif_4_1_sh_mask.h" 30 31 #include "oss/oss_2_0_d.h" 32 #include "oss/oss_2_0_sh_mask.h" 33 34 /* 35 * Interrupts 36 * Starting with r6xx, interrupts are handled via a ring buffer. 37 * Ring buffers are areas of GPU accessible memory that the GPU 38 * writes interrupt vectors into and the host reads vectors out of. 39 * There is a rptr (read pointer) that determines where the 40 * host is currently reading, and a wptr (write pointer) 41 * which determines where the GPU has written. When the 42 * pointers are equal, the ring is idle. When the GPU 43 * writes vectors to the ring buffer, it increments the 44 * wptr. When there is an interrupt, the host then starts 45 * fetching commands and processing them until the pointers are 46 * equal again at which point it updates the rptr. 47 */ 48 49 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev); 50 51 /** 52 * cik_ih_enable_interrupts - Enable the interrupt ring buffer 53 * 54 * @adev: amdgpu_device pointer 55 * 56 * Enable the interrupt ring buffer (CIK). 57 */ 58 static void cik_ih_enable_interrupts(struct amdgpu_device *adev) 59 { 60 u32 ih_cntl = RREG32(mmIH_CNTL); 61 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 62 63 ih_cntl |= IH_CNTL__ENABLE_INTR_MASK; 64 ih_rb_cntl |= IH_RB_CNTL__RB_ENABLE_MASK; 65 WREG32(mmIH_CNTL, ih_cntl); 66 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 67 adev->irq.ih.enabled = true; 68 } 69 70 /** 71 * cik_ih_disable_interrupts - Disable the interrupt ring buffer 72 * 73 * @adev: amdgpu_device pointer 74 * 75 * Disable the interrupt ring buffer (CIK). 76 */ 77 static void cik_ih_disable_interrupts(struct amdgpu_device *adev) 78 { 79 u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL); 80 u32 ih_cntl = RREG32(mmIH_CNTL); 81 82 ih_rb_cntl &= ~IH_RB_CNTL__RB_ENABLE_MASK; 83 ih_cntl &= ~IH_CNTL__ENABLE_INTR_MASK; 84 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 85 WREG32(mmIH_CNTL, ih_cntl); 86 /* set rptr, wptr to 0 */ 87 WREG32(mmIH_RB_RPTR, 0); 88 WREG32(mmIH_RB_WPTR, 0); 89 adev->irq.ih.enabled = false; 90 adev->irq.ih.rptr = 0; 91 } 92 93 /** 94 * cik_ih_irq_init - init and enable the interrupt ring 95 * 96 * @adev: amdgpu_device pointer 97 * 98 * Allocate a ring buffer for the interrupt controller, 99 * enable the RLC, disable interrupts, enable the IH 100 * ring buffer and enable it (CIK). 101 * Called at device load and reume. 102 * Returns 0 for success, errors for failure. 103 */ 104 static int cik_ih_irq_init(struct amdgpu_device *adev) 105 { 106 int rb_bufsz; 107 u32 interrupt_cntl, ih_cntl, ih_rb_cntl; 108 u64 wptr_off; 109 110 /* disable irqs */ 111 cik_ih_disable_interrupts(adev); 112 113 /* setup interrupt control */ 114 WREG32(mmINTERRUPT_CNTL2, adev->dummy_page.addr >> 8); 115 interrupt_cntl = RREG32(mmINTERRUPT_CNTL); 116 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi 117 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN 118 */ 119 interrupt_cntl &= ~INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK; 120 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */ 121 interrupt_cntl &= ~INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK; 122 WREG32(mmINTERRUPT_CNTL, interrupt_cntl); 123 124 WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8); 125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); 126 127 ih_rb_cntl = (IH_RB_CNTL__WPTR_OVERFLOW_ENABLE_MASK | 128 IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK | 129 (rb_bufsz << 1)); 130 131 ih_rb_cntl |= IH_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK; 132 133 /* set the writeback address whether it's enabled or not */ 134 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); 135 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off)); 136 WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF); 137 138 WREG32(mmIH_RB_CNTL, ih_rb_cntl); 139 140 /* set rptr, wptr to 0 */ 141 WREG32(mmIH_RB_RPTR, 0); 142 WREG32(mmIH_RB_WPTR, 0); 143 144 /* Default settings for IH_CNTL (disabled at first) */ 145 ih_cntl = (0x10 << IH_CNTL__MC_WRREQ_CREDIT__SHIFT) | 146 (0x10 << IH_CNTL__MC_WR_CLEAN_CNT__SHIFT) | 147 (0 << IH_CNTL__MC_VMID__SHIFT); 148 /* IH_CNTL__RPTR_REARM_MASK only works if msi's are enabled */ 149 if (adev->irq.msi_enabled) 150 ih_cntl |= IH_CNTL__RPTR_REARM_MASK; 151 WREG32(mmIH_CNTL, ih_cntl); 152 153 pci_set_master(adev->pdev); 154 155 /* enable irqs */ 156 cik_ih_enable_interrupts(adev); 157 158 return 0; 159 } 160 161 /** 162 * cik_ih_irq_disable - disable interrupts 163 * 164 * @adev: amdgpu_device pointer 165 * 166 * Disable interrupts on the hw (CIK). 167 */ 168 static void cik_ih_irq_disable(struct amdgpu_device *adev) 169 { 170 cik_ih_disable_interrupts(adev); 171 /* Wait and acknowledge irq */ 172 mdelay(1); 173 } 174 175 /** 176 * cik_ih_get_wptr - get the IH ring buffer wptr 177 * 178 * @adev: amdgpu_device pointer 179 * 180 * Get the IH ring buffer wptr from either the register 181 * or the writeback memory buffer (CIK). Also check for 182 * ring buffer overflow and deal with it. 183 * Used by cik_irq_process(). 184 * Returns the value of the wptr. 185 */ 186 static u32 cik_ih_get_wptr(struct amdgpu_device *adev) 187 { 188 u32 wptr, tmp; 189 190 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); 191 192 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { 193 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; 194 /* When a ring buffer overflow happen start parsing interrupt 195 * from the last not overwritten vector (wptr + 16). Hopefully 196 * this should allow us to catchup. 197 */ 198 dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", 199 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); 200 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; 201 tmp = RREG32(mmIH_RB_CNTL); 202 tmp |= IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK; 203 WREG32(mmIH_RB_CNTL, tmp); 204 } 205 return (wptr & adev->irq.ih.ptr_mask); 206 } 207 208 /* CIK IV Ring 209 * Each IV ring entry is 128 bits: 210 * [7:0] - interrupt source id 211 * [31:8] - reserved 212 * [59:32] - interrupt source data 213 * [63:60] - reserved 214 * [71:64] - RINGID 215 * CP: 216 * ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0] 217 * QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher 218 * - for gfx, hw shader state (0=PS...5=LS, 6=CS) 219 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes 220 * PIPE_ID - ME0 0=3D 221 * - ME1&2 compute dispatcher (4 pipes each) 222 * SDMA: 223 * INSTANCE_ID [1:0], QUEUE_ID[1:0] 224 * INSTANCE_ID - 0 = sdma0, 1 = sdma1 225 * QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1 226 * [79:72] - VMID 227 * [95:80] - PASID 228 * [127:96] - reserved 229 */ 230 231 /** 232 * cik_ih_decode_iv - decode an interrupt vector 233 * 234 * @adev: amdgpu_device pointer 235 * 236 * Decodes the interrupt vector at the current rptr 237 * position and also advance the position. 238 */ 239 static void cik_ih_decode_iv(struct amdgpu_device *adev, 240 struct amdgpu_iv_entry *entry) 241 { 242 /* wptr/rptr are in bytes! */ 243 u32 ring_index = adev->irq.ih.rptr >> 2; 244 uint32_t dw[4]; 245 246 dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]); 247 dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]); 248 dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]); 249 dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]); 250 251 entry->client_id = AMDGPU_IH_CLIENTID_LEGACY; 252 entry->src_id = dw[0] & 0xff; 253 entry->src_data[0] = dw[1] & 0xfffffff; 254 entry->ring_id = dw[2] & 0xff; 255 entry->vm_id = (dw[2] >> 8) & 0xff; 256 entry->pas_id = (dw[2] >> 16) & 0xffff; 257 258 /* wptr/rptr are in bytes! */ 259 adev->irq.ih.rptr += 16; 260 } 261 262 /** 263 * cik_ih_set_rptr - set the IH ring buffer rptr 264 * 265 * @adev: amdgpu_device pointer 266 * 267 * Set the IH ring buffer rptr. 268 */ 269 static void cik_ih_set_rptr(struct amdgpu_device *adev) 270 { 271 WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr); 272 } 273 274 static int cik_ih_early_init(void *handle) 275 { 276 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 277 int ret; 278 279 ret = amdgpu_irq_add_domain(adev); 280 if (ret) 281 return ret; 282 283 cik_ih_set_interrupt_funcs(adev); 284 285 return 0; 286 } 287 288 static int cik_ih_sw_init(void *handle) 289 { 290 int r; 291 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 292 293 r = amdgpu_ih_ring_init(adev, 64 * 1024, false); 294 if (r) 295 return r; 296 297 r = amdgpu_irq_init(adev); 298 299 return r; 300 } 301 302 static int cik_ih_sw_fini(void *handle) 303 { 304 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 305 306 amdgpu_irq_fini(adev); 307 amdgpu_ih_ring_fini(adev); 308 amdgpu_irq_remove_domain(adev); 309 310 return 0; 311 } 312 313 static int cik_ih_hw_init(void *handle) 314 { 315 int r; 316 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 317 318 r = cik_ih_irq_init(adev); 319 if (r) 320 return r; 321 322 return 0; 323 } 324 325 static int cik_ih_hw_fini(void *handle) 326 { 327 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 328 329 cik_ih_irq_disable(adev); 330 331 return 0; 332 } 333 334 static int cik_ih_suspend(void *handle) 335 { 336 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 337 338 return cik_ih_hw_fini(adev); 339 } 340 341 static int cik_ih_resume(void *handle) 342 { 343 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 344 345 return cik_ih_hw_init(adev); 346 } 347 348 static bool cik_ih_is_idle(void *handle) 349 { 350 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 351 u32 tmp = RREG32(mmSRBM_STATUS); 352 353 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 354 return false; 355 356 return true; 357 } 358 359 static int cik_ih_wait_for_idle(void *handle) 360 { 361 unsigned i; 362 u32 tmp; 363 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 364 365 for (i = 0; i < adev->usec_timeout; i++) { 366 /* read MC_STATUS */ 367 tmp = RREG32(mmSRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK; 368 if (!tmp) 369 return 0; 370 udelay(1); 371 } 372 return -ETIMEDOUT; 373 } 374 375 static int cik_ih_soft_reset(void *handle) 376 { 377 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 378 379 u32 srbm_soft_reset = 0; 380 u32 tmp = RREG32(mmSRBM_STATUS); 381 382 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 383 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 384 385 if (srbm_soft_reset) { 386 tmp = RREG32(mmSRBM_SOFT_RESET); 387 tmp |= srbm_soft_reset; 388 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 389 WREG32(mmSRBM_SOFT_RESET, tmp); 390 tmp = RREG32(mmSRBM_SOFT_RESET); 391 392 udelay(50); 393 394 tmp &= ~srbm_soft_reset; 395 WREG32(mmSRBM_SOFT_RESET, tmp); 396 tmp = RREG32(mmSRBM_SOFT_RESET); 397 398 /* Wait a little for things to settle down */ 399 udelay(50); 400 } 401 402 return 0; 403 } 404 405 static int cik_ih_set_clockgating_state(void *handle, 406 enum amd_clockgating_state state) 407 { 408 return 0; 409 } 410 411 static int cik_ih_set_powergating_state(void *handle, 412 enum amd_powergating_state state) 413 { 414 return 0; 415 } 416 417 static const struct amd_ip_funcs cik_ih_ip_funcs = { 418 .name = "cik_ih", 419 .early_init = cik_ih_early_init, 420 .late_init = NULL, 421 .sw_init = cik_ih_sw_init, 422 .sw_fini = cik_ih_sw_fini, 423 .hw_init = cik_ih_hw_init, 424 .hw_fini = cik_ih_hw_fini, 425 .suspend = cik_ih_suspend, 426 .resume = cik_ih_resume, 427 .is_idle = cik_ih_is_idle, 428 .wait_for_idle = cik_ih_wait_for_idle, 429 .soft_reset = cik_ih_soft_reset, 430 .set_clockgating_state = cik_ih_set_clockgating_state, 431 .set_powergating_state = cik_ih_set_powergating_state, 432 }; 433 434 static const struct amdgpu_ih_funcs cik_ih_funcs = { 435 .get_wptr = cik_ih_get_wptr, 436 .decode_iv = cik_ih_decode_iv, 437 .set_rptr = cik_ih_set_rptr 438 }; 439 440 static void cik_ih_set_interrupt_funcs(struct amdgpu_device *adev) 441 { 442 if (adev->irq.ih_funcs == NULL) 443 adev->irq.ih_funcs = &cik_ih_funcs; 444 } 445 446 const struct amdgpu_ip_block_version cik_ih_ip_block = 447 { 448 .type = AMD_IP_BLOCK_TYPE_IH, 449 .major = 2, 450 .minor = 0, 451 .rev = 0, 452 .funcs = &cik_ih_ip_funcs, 453 }; 454