xref: /openbmc/linux/drivers/gpu/drm/amd/amdgpu/cik.c (revision 6dfcd296) 
1 /*
2  * Copyright 2012 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include "drmP.h"
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "cikd.h"
34 #include "atom.h"
35 #include "amd_pcie.h"
36 
37 #include "cik.h"
38 #include "gmc_v7_0.h"
39 #include "cik_ih.h"
40 #include "dce_v8_0.h"
41 #include "gfx_v7_0.h"
42 #include "cik_sdma.h"
43 #include "uvd_v4_2.h"
44 #include "vce_v2_0.h"
45 #include "cik_dpm.h"
46 
47 #include "uvd/uvd_4_2_d.h"
48 
49 #include "smu/smu_7_0_1_d.h"
50 #include "smu/smu_7_0_1_sh_mask.h"
51 
52 #include "dce/dce_8_0_d.h"
53 #include "dce/dce_8_0_sh_mask.h"
54 
55 #include "bif/bif_4_1_d.h"
56 #include "bif/bif_4_1_sh_mask.h"
57 
58 #include "gca/gfx_7_2_d.h"
59 #include "gca/gfx_7_2_enum.h"
60 #include "gca/gfx_7_2_sh_mask.h"
61 
62 #include "gmc/gmc_7_1_d.h"
63 #include "gmc/gmc_7_1_sh_mask.h"
64 
65 #include "oss/oss_2_0_d.h"
66 #include "oss/oss_2_0_sh_mask.h"
67 
68 #include "amdgpu_amdkfd.h"
69 #include "amdgpu_powerplay.h"
70 #include "dce_virtual.h"
71 
72 /*
73  * Indirect registers accessor
74  */
75 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
76 {
77 	unsigned long flags;
78 	u32 r;
79 
80 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
81 	WREG32(mmPCIE_INDEX, reg);
82 	(void)RREG32(mmPCIE_INDEX);
83 	r = RREG32(mmPCIE_DATA);
84 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
85 	return r;
86 }
87 
88 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
89 {
90 	unsigned long flags;
91 
92 	spin_lock_irqsave(&adev->pcie_idx_lock, flags);
93 	WREG32(mmPCIE_INDEX, reg);
94 	(void)RREG32(mmPCIE_INDEX);
95 	WREG32(mmPCIE_DATA, v);
96 	(void)RREG32(mmPCIE_DATA);
97 	spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
98 }
99 
100 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
101 {
102 	unsigned long flags;
103 	u32 r;
104 
105 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
106 	WREG32(mmSMC_IND_INDEX_0, (reg));
107 	r = RREG32(mmSMC_IND_DATA_0);
108 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
109 	return r;
110 }
111 
112 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
113 {
114 	unsigned long flags;
115 
116 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
117 	WREG32(mmSMC_IND_INDEX_0, (reg));
118 	WREG32(mmSMC_IND_DATA_0, (v));
119 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
120 }
121 
122 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
123 {
124 	unsigned long flags;
125 	u32 r;
126 
127 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
128 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
129 	r = RREG32(mmUVD_CTX_DATA);
130 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
131 	return r;
132 }
133 
134 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
135 {
136 	unsigned long flags;
137 
138 	spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
139 	WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff));
140 	WREG32(mmUVD_CTX_DATA, (v));
141 	spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
142 }
143 
144 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)
145 {
146 	unsigned long flags;
147 	u32 r;
148 
149 	spin_lock_irqsave(&adev->didt_idx_lock, flags);
150 	WREG32(mmDIDT_IND_INDEX, (reg));
151 	r = RREG32(mmDIDT_IND_DATA);
152 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
153 	return r;
154 }
155 
156 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
157 {
158 	unsigned long flags;
159 
160 	spin_lock_irqsave(&adev->didt_idx_lock, flags);
161 	WREG32(mmDIDT_IND_INDEX, (reg));
162 	WREG32(mmDIDT_IND_DATA, (v));
163 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
164 }
165 
166 static const u32 bonaire_golden_spm_registers[] =
167 {
168 	0xc200, 0xe0ffffff, 0xe0000000
169 };
170 
171 static const u32 bonaire_golden_common_registers[] =
172 {
173 	0x31dc, 0xffffffff, 0x00000800,
174 	0x31dd, 0xffffffff, 0x00000800,
175 	0x31e6, 0xffffffff, 0x00007fbf,
176 	0x31e7, 0xffffffff, 0x00007faf
177 };
178 
179 static const u32 bonaire_golden_registers[] =
180 {
181 	0xcd5, 0x00000333, 0x00000333,
182 	0xcd4, 0x000c0fc0, 0x00040200,
183 	0x2684, 0x00010000, 0x00058208,
184 	0xf000, 0xffff1fff, 0x00140000,
185 	0xf080, 0xfdfc0fff, 0x00000100,
186 	0xf08d, 0x40000000, 0x40000200,
187 	0x260c, 0xffffffff, 0x00000000,
188 	0x260d, 0xf00fffff, 0x00000400,
189 	0x260e, 0x0002021c, 0x00020200,
190 	0x31e, 0x00000080, 0x00000000,
191 	0x16ec, 0x000000f0, 0x00000070,
192 	0x16f0, 0xf0311fff, 0x80300000,
193 	0x263e, 0x73773777, 0x12010001,
194 	0xd43, 0x00810000, 0x408af000,
195 	0x1c0c, 0x31000111, 0x00000011,
196 	0xbd2, 0x73773777, 0x12010001,
197 	0x883, 0x00007fb6, 0x0021a1b1,
198 	0x884, 0x00007fb6, 0x002021b1,
199 	0x860, 0x00007fb6, 0x00002191,
200 	0x886, 0x00007fb6, 0x002121b1,
201 	0x887, 0x00007fb6, 0x002021b1,
202 	0x877, 0x00007fb6, 0x00002191,
203 	0x878, 0x00007fb6, 0x00002191,
204 	0xd8a, 0x0000003f, 0x0000000a,
205 	0xd8b, 0x0000003f, 0x0000000a,
206 	0xab9, 0x00073ffe, 0x000022a2,
207 	0x903, 0x000007ff, 0x00000000,
208 	0x2285, 0xf000003f, 0x00000007,
209 	0x22fc, 0x00002001, 0x00000001,
210 	0x22c9, 0xffffffff, 0x00ffffff,
211 	0xc281, 0x0000ff0f, 0x00000000,
212 	0xa293, 0x07ffffff, 0x06000000,
213 	0x136, 0x00000fff, 0x00000100,
214 	0xf9e, 0x00000001, 0x00000002,
215 	0x2440, 0x03000000, 0x0362c688,
216 	0x2300, 0x000000ff, 0x00000001,
217 	0x390, 0x00001fff, 0x00001fff,
218 	0x2418, 0x0000007f, 0x00000020,
219 	0x2542, 0x00010000, 0x00010000,
220 	0x2b05, 0x000003ff, 0x000000f3,
221 	0x2b03, 0xffffffff, 0x00001032
222 };
223 
224 static const u32 bonaire_mgcg_cgcg_init[] =
225 {
226 	0x3108, 0xffffffff, 0xfffffffc,
227 	0xc200, 0xffffffff, 0xe0000000,
228 	0xf0a8, 0xffffffff, 0x00000100,
229 	0xf082, 0xffffffff, 0x00000100,
230 	0xf0b0, 0xffffffff, 0xc0000100,
231 	0xf0b2, 0xffffffff, 0xc0000100,
232 	0xf0b1, 0xffffffff, 0xc0000100,
233 	0x1579, 0xffffffff, 0x00600100,
234 	0xf0a0, 0xffffffff, 0x00000100,
235 	0xf085, 0xffffffff, 0x06000100,
236 	0xf088, 0xffffffff, 0x00000100,
237 	0xf086, 0xffffffff, 0x06000100,
238 	0xf081, 0xffffffff, 0x00000100,
239 	0xf0b8, 0xffffffff, 0x00000100,
240 	0xf089, 0xffffffff, 0x00000100,
241 	0xf080, 0xffffffff, 0x00000100,
242 	0xf08c, 0xffffffff, 0x00000100,
243 	0xf08d, 0xffffffff, 0x00000100,
244 	0xf094, 0xffffffff, 0x00000100,
245 	0xf095, 0xffffffff, 0x00000100,
246 	0xf096, 0xffffffff, 0x00000100,
247 	0xf097, 0xffffffff, 0x00000100,
248 	0xf098, 0xffffffff, 0x00000100,
249 	0xf09f, 0xffffffff, 0x00000100,
250 	0xf09e, 0xffffffff, 0x00000100,
251 	0xf084, 0xffffffff, 0x06000100,
252 	0xf0a4, 0xffffffff, 0x00000100,
253 	0xf09d, 0xffffffff, 0x00000100,
254 	0xf0ad, 0xffffffff, 0x00000100,
255 	0xf0ac, 0xffffffff, 0x00000100,
256 	0xf09c, 0xffffffff, 0x00000100,
257 	0xc200, 0xffffffff, 0xe0000000,
258 	0xf008, 0xffffffff, 0x00010000,
259 	0xf009, 0xffffffff, 0x00030002,
260 	0xf00a, 0xffffffff, 0x00040007,
261 	0xf00b, 0xffffffff, 0x00060005,
262 	0xf00c, 0xffffffff, 0x00090008,
263 	0xf00d, 0xffffffff, 0x00010000,
264 	0xf00e, 0xffffffff, 0x00030002,
265 	0xf00f, 0xffffffff, 0x00040007,
266 	0xf010, 0xffffffff, 0x00060005,
267 	0xf011, 0xffffffff, 0x00090008,
268 	0xf012, 0xffffffff, 0x00010000,
269 	0xf013, 0xffffffff, 0x00030002,
270 	0xf014, 0xffffffff, 0x00040007,
271 	0xf015, 0xffffffff, 0x00060005,
272 	0xf016, 0xffffffff, 0x00090008,
273 	0xf017, 0xffffffff, 0x00010000,
274 	0xf018, 0xffffffff, 0x00030002,
275 	0xf019, 0xffffffff, 0x00040007,
276 	0xf01a, 0xffffffff, 0x00060005,
277 	0xf01b, 0xffffffff, 0x00090008,
278 	0xf01c, 0xffffffff, 0x00010000,
279 	0xf01d, 0xffffffff, 0x00030002,
280 	0xf01e, 0xffffffff, 0x00040007,
281 	0xf01f, 0xffffffff, 0x00060005,
282 	0xf020, 0xffffffff, 0x00090008,
283 	0xf021, 0xffffffff, 0x00010000,
284 	0xf022, 0xffffffff, 0x00030002,
285 	0xf023, 0xffffffff, 0x00040007,
286 	0xf024, 0xffffffff, 0x00060005,
287 	0xf025, 0xffffffff, 0x00090008,
288 	0xf026, 0xffffffff, 0x00010000,
289 	0xf027, 0xffffffff, 0x00030002,
290 	0xf028, 0xffffffff, 0x00040007,
291 	0xf029, 0xffffffff, 0x00060005,
292 	0xf02a, 0xffffffff, 0x00090008,
293 	0xf000, 0xffffffff, 0x96e00200,
294 	0x21c2, 0xffffffff, 0x00900100,
295 	0x3109, 0xffffffff, 0x0020003f,
296 	0xe, 0xffffffff, 0x0140001c,
297 	0xf, 0x000f0000, 0x000f0000,
298 	0x88, 0xffffffff, 0xc060000c,
299 	0x89, 0xc0000fff, 0x00000100,
300 	0x3e4, 0xffffffff, 0x00000100,
301 	0x3e6, 0x00000101, 0x00000000,
302 	0x82a, 0xffffffff, 0x00000104,
303 	0x1579, 0xff000fff, 0x00000100,
304 	0xc33, 0xc0000fff, 0x00000104,
305 	0x3079, 0x00000001, 0x00000001,
306 	0x3403, 0xff000ff0, 0x00000100,
307 	0x3603, 0xff000ff0, 0x00000100
308 };
309 
310 static const u32 spectre_golden_spm_registers[] =
311 {
312 	0xc200, 0xe0ffffff, 0xe0000000
313 };
314 
315 static const u32 spectre_golden_common_registers[] =
316 {
317 	0x31dc, 0xffffffff, 0x00000800,
318 	0x31dd, 0xffffffff, 0x00000800,
319 	0x31e6, 0xffffffff, 0x00007fbf,
320 	0x31e7, 0xffffffff, 0x00007faf
321 };
322 
323 static const u32 spectre_golden_registers[] =
324 {
325 	0xf000, 0xffff1fff, 0x96940200,
326 	0xf003, 0xffff0001, 0xff000000,
327 	0xf080, 0xfffc0fff, 0x00000100,
328 	0x1bb6, 0x00010101, 0x00010000,
329 	0x260d, 0xf00fffff, 0x00000400,
330 	0x260e, 0xfffffffc, 0x00020200,
331 	0x16ec, 0x000000f0, 0x00000070,
332 	0x16f0, 0xf0311fff, 0x80300000,
333 	0x263e, 0x73773777, 0x12010001,
334 	0x26df, 0x00ff0000, 0x00fc0000,
335 	0xbd2, 0x73773777, 0x12010001,
336 	0x2285, 0xf000003f, 0x00000007,
337 	0x22c9, 0xffffffff, 0x00ffffff,
338 	0xa0d4, 0x3f3f3fff, 0x00000082,
339 	0xa0d5, 0x0000003f, 0x00000000,
340 	0xf9e, 0x00000001, 0x00000002,
341 	0x244f, 0xffff03df, 0x00000004,
342 	0x31da, 0x00000008, 0x00000008,
343 	0x2300, 0x000008ff, 0x00000800,
344 	0x2542, 0x00010000, 0x00010000,
345 	0x2b03, 0xffffffff, 0x54763210,
346 	0x853e, 0x01ff01ff, 0x00000002,
347 	0x8526, 0x007ff800, 0x00200000,
348 	0x8057, 0xffffffff, 0x00000f40,
349 	0xc24d, 0xffffffff, 0x00000001
350 };
351 
352 static const u32 spectre_mgcg_cgcg_init[] =
353 {
354 	0x3108, 0xffffffff, 0xfffffffc,
355 	0xc200, 0xffffffff, 0xe0000000,
356 	0xf0a8, 0xffffffff, 0x00000100,
357 	0xf082, 0xffffffff, 0x00000100,
358 	0xf0b0, 0xffffffff, 0x00000100,
359 	0xf0b2, 0xffffffff, 0x00000100,
360 	0xf0b1, 0xffffffff, 0x00000100,
361 	0x1579, 0xffffffff, 0x00600100,
362 	0xf0a0, 0xffffffff, 0x00000100,
363 	0xf085, 0xffffffff, 0x06000100,
364 	0xf088, 0xffffffff, 0x00000100,
365 	0xf086, 0xffffffff, 0x06000100,
366 	0xf081, 0xffffffff, 0x00000100,
367 	0xf0b8, 0xffffffff, 0x00000100,
368 	0xf089, 0xffffffff, 0x00000100,
369 	0xf080, 0xffffffff, 0x00000100,
370 	0xf08c, 0xffffffff, 0x00000100,
371 	0xf08d, 0xffffffff, 0x00000100,
372 	0xf094, 0xffffffff, 0x00000100,
373 	0xf095, 0xffffffff, 0x00000100,
374 	0xf096, 0xffffffff, 0x00000100,
375 	0xf097, 0xffffffff, 0x00000100,
376 	0xf098, 0xffffffff, 0x00000100,
377 	0xf09f, 0xffffffff, 0x00000100,
378 	0xf09e, 0xffffffff, 0x00000100,
379 	0xf084, 0xffffffff, 0x06000100,
380 	0xf0a4, 0xffffffff, 0x00000100,
381 	0xf09d, 0xffffffff, 0x00000100,
382 	0xf0ad, 0xffffffff, 0x00000100,
383 	0xf0ac, 0xffffffff, 0x00000100,
384 	0xf09c, 0xffffffff, 0x00000100,
385 	0xc200, 0xffffffff, 0xe0000000,
386 	0xf008, 0xffffffff, 0x00010000,
387 	0xf009, 0xffffffff, 0x00030002,
388 	0xf00a, 0xffffffff, 0x00040007,
389 	0xf00b, 0xffffffff, 0x00060005,
390 	0xf00c, 0xffffffff, 0x00090008,
391 	0xf00d, 0xffffffff, 0x00010000,
392 	0xf00e, 0xffffffff, 0x00030002,
393 	0xf00f, 0xffffffff, 0x00040007,
394 	0xf010, 0xffffffff, 0x00060005,
395 	0xf011, 0xffffffff, 0x00090008,
396 	0xf012, 0xffffffff, 0x00010000,
397 	0xf013, 0xffffffff, 0x00030002,
398 	0xf014, 0xffffffff, 0x00040007,
399 	0xf015, 0xffffffff, 0x00060005,
400 	0xf016, 0xffffffff, 0x00090008,
401 	0xf017, 0xffffffff, 0x00010000,
402 	0xf018, 0xffffffff, 0x00030002,
403 	0xf019, 0xffffffff, 0x00040007,
404 	0xf01a, 0xffffffff, 0x00060005,
405 	0xf01b, 0xffffffff, 0x00090008,
406 	0xf01c, 0xffffffff, 0x00010000,
407 	0xf01d, 0xffffffff, 0x00030002,
408 	0xf01e, 0xffffffff, 0x00040007,
409 	0xf01f, 0xffffffff, 0x00060005,
410 	0xf020, 0xffffffff, 0x00090008,
411 	0xf021, 0xffffffff, 0x00010000,
412 	0xf022, 0xffffffff, 0x00030002,
413 	0xf023, 0xffffffff, 0x00040007,
414 	0xf024, 0xffffffff, 0x00060005,
415 	0xf025, 0xffffffff, 0x00090008,
416 	0xf026, 0xffffffff, 0x00010000,
417 	0xf027, 0xffffffff, 0x00030002,
418 	0xf028, 0xffffffff, 0x00040007,
419 	0xf029, 0xffffffff, 0x00060005,
420 	0xf02a, 0xffffffff, 0x00090008,
421 	0xf02b, 0xffffffff, 0x00010000,
422 	0xf02c, 0xffffffff, 0x00030002,
423 	0xf02d, 0xffffffff, 0x00040007,
424 	0xf02e, 0xffffffff, 0x00060005,
425 	0xf02f, 0xffffffff, 0x00090008,
426 	0xf000, 0xffffffff, 0x96e00200,
427 	0x21c2, 0xffffffff, 0x00900100,
428 	0x3109, 0xffffffff, 0x0020003f,
429 	0xe, 0xffffffff, 0x0140001c,
430 	0xf, 0x000f0000, 0x000f0000,
431 	0x88, 0xffffffff, 0xc060000c,
432 	0x89, 0xc0000fff, 0x00000100,
433 	0x3e4, 0xffffffff, 0x00000100,
434 	0x3e6, 0x00000101, 0x00000000,
435 	0x82a, 0xffffffff, 0x00000104,
436 	0x1579, 0xff000fff, 0x00000100,
437 	0xc33, 0xc0000fff, 0x00000104,
438 	0x3079, 0x00000001, 0x00000001,
439 	0x3403, 0xff000ff0, 0x00000100,
440 	0x3603, 0xff000ff0, 0x00000100
441 };
442 
443 static const u32 kalindi_golden_spm_registers[] =
444 {
445 	0xc200, 0xe0ffffff, 0xe0000000
446 };
447 
448 static const u32 kalindi_golden_common_registers[] =
449 {
450 	0x31dc, 0xffffffff, 0x00000800,
451 	0x31dd, 0xffffffff, 0x00000800,
452 	0x31e6, 0xffffffff, 0x00007fbf,
453 	0x31e7, 0xffffffff, 0x00007faf
454 };
455 
456 static const u32 kalindi_golden_registers[] =
457 {
458 	0xf000, 0xffffdfff, 0x6e944040,
459 	0x1579, 0xff607fff, 0xfc000100,
460 	0xf088, 0xff000fff, 0x00000100,
461 	0xf089, 0xff000fff, 0x00000100,
462 	0xf080, 0xfffc0fff, 0x00000100,
463 	0x1bb6, 0x00010101, 0x00010000,
464 	0x260c, 0xffffffff, 0x00000000,
465 	0x260d, 0xf00fffff, 0x00000400,
466 	0x16ec, 0x000000f0, 0x00000070,
467 	0x16f0, 0xf0311fff, 0x80300000,
468 	0x263e, 0x73773777, 0x12010001,
469 	0x263f, 0xffffffff, 0x00000010,
470 	0x26df, 0x00ff0000, 0x00fc0000,
471 	0x200c, 0x00001f0f, 0x0000100a,
472 	0xbd2, 0x73773777, 0x12010001,
473 	0x902, 0x000fffff, 0x000c007f,
474 	0x2285, 0xf000003f, 0x00000007,
475 	0x22c9, 0x3fff3fff, 0x00ffcfff,
476 	0xc281, 0x0000ff0f, 0x00000000,
477 	0xa293, 0x07ffffff, 0x06000000,
478 	0x136, 0x00000fff, 0x00000100,
479 	0xf9e, 0x00000001, 0x00000002,
480 	0x31da, 0x00000008, 0x00000008,
481 	0x2300, 0x000000ff, 0x00000003,
482 	0x853e, 0x01ff01ff, 0x00000002,
483 	0x8526, 0x007ff800, 0x00200000,
484 	0x8057, 0xffffffff, 0x00000f40,
485 	0x2231, 0x001f3ae3, 0x00000082,
486 	0x2235, 0x0000001f, 0x00000010,
487 	0xc24d, 0xffffffff, 0x00000000
488 };
489 
490 static const u32 kalindi_mgcg_cgcg_init[] =
491 {
492 	0x3108, 0xffffffff, 0xfffffffc,
493 	0xc200, 0xffffffff, 0xe0000000,
494 	0xf0a8, 0xffffffff, 0x00000100,
495 	0xf082, 0xffffffff, 0x00000100,
496 	0xf0b0, 0xffffffff, 0x00000100,
497 	0xf0b2, 0xffffffff, 0x00000100,
498 	0xf0b1, 0xffffffff, 0x00000100,
499 	0x1579, 0xffffffff, 0x00600100,
500 	0xf0a0, 0xffffffff, 0x00000100,
501 	0xf085, 0xffffffff, 0x06000100,
502 	0xf088, 0xffffffff, 0x00000100,
503 	0xf086, 0xffffffff, 0x06000100,
504 	0xf081, 0xffffffff, 0x00000100,
505 	0xf0b8, 0xffffffff, 0x00000100,
506 	0xf089, 0xffffffff, 0x00000100,
507 	0xf080, 0xffffffff, 0x00000100,
508 	0xf08c, 0xffffffff, 0x00000100,
509 	0xf08d, 0xffffffff, 0x00000100,
510 	0xf094, 0xffffffff, 0x00000100,
511 	0xf095, 0xffffffff, 0x00000100,
512 	0xf096, 0xffffffff, 0x00000100,
513 	0xf097, 0xffffffff, 0x00000100,
514 	0xf098, 0xffffffff, 0x00000100,
515 	0xf09f, 0xffffffff, 0x00000100,
516 	0xf09e, 0xffffffff, 0x00000100,
517 	0xf084, 0xffffffff, 0x06000100,
518 	0xf0a4, 0xffffffff, 0x00000100,
519 	0xf09d, 0xffffffff, 0x00000100,
520 	0xf0ad, 0xffffffff, 0x00000100,
521 	0xf0ac, 0xffffffff, 0x00000100,
522 	0xf09c, 0xffffffff, 0x00000100,
523 	0xc200, 0xffffffff, 0xe0000000,
524 	0xf008, 0xffffffff, 0x00010000,
525 	0xf009, 0xffffffff, 0x00030002,
526 	0xf00a, 0xffffffff, 0x00040007,
527 	0xf00b, 0xffffffff, 0x00060005,
528 	0xf00c, 0xffffffff, 0x00090008,
529 	0xf00d, 0xffffffff, 0x00010000,
530 	0xf00e, 0xffffffff, 0x00030002,
531 	0xf00f, 0xffffffff, 0x00040007,
532 	0xf010, 0xffffffff, 0x00060005,
533 	0xf011, 0xffffffff, 0x00090008,
534 	0xf000, 0xffffffff, 0x96e00200,
535 	0x21c2, 0xffffffff, 0x00900100,
536 	0x3109, 0xffffffff, 0x0020003f,
537 	0xe, 0xffffffff, 0x0140001c,
538 	0xf, 0x000f0000, 0x000f0000,
539 	0x88, 0xffffffff, 0xc060000c,
540 	0x89, 0xc0000fff, 0x00000100,
541 	0x82a, 0xffffffff, 0x00000104,
542 	0x1579, 0xff000fff, 0x00000100,
543 	0xc33, 0xc0000fff, 0x00000104,
544 	0x3079, 0x00000001, 0x00000001,
545 	0x3403, 0xff000ff0, 0x00000100,
546 	0x3603, 0xff000ff0, 0x00000100
547 };
548 
549 static const u32 hawaii_golden_spm_registers[] =
550 {
551 	0xc200, 0xe0ffffff, 0xe0000000
552 };
553 
554 static const u32 hawaii_golden_common_registers[] =
555 {
556 	0xc200, 0xffffffff, 0xe0000000,
557 	0xa0d4, 0xffffffff, 0x3a00161a,
558 	0xa0d5, 0xffffffff, 0x0000002e,
559 	0x2684, 0xffffffff, 0x00018208,
560 	0x263e, 0xffffffff, 0x12011003
561 };
562 
563 static const u32 hawaii_golden_registers[] =
564 {
565 	0xcd5, 0x00000333, 0x00000333,
566 	0x2684, 0x00010000, 0x00058208,
567 	0x260c, 0xffffffff, 0x00000000,
568 	0x260d, 0xf00fffff, 0x00000400,
569 	0x260e, 0x0002021c, 0x00020200,
570 	0x31e, 0x00000080, 0x00000000,
571 	0x16ec, 0x000000f0, 0x00000070,
572 	0x16f0, 0xf0311fff, 0x80300000,
573 	0xd43, 0x00810000, 0x408af000,
574 	0x1c0c, 0x31000111, 0x00000011,
575 	0xbd2, 0x73773777, 0x12010001,
576 	0x848, 0x0000007f, 0x0000001b,
577 	0x877, 0x00007fb6, 0x00002191,
578 	0xd8a, 0x0000003f, 0x0000000a,
579 	0xd8b, 0x0000003f, 0x0000000a,
580 	0xab9, 0x00073ffe, 0x000022a2,
581 	0x903, 0x000007ff, 0x00000000,
582 	0x22fc, 0x00002001, 0x00000001,
583 	0x22c9, 0xffffffff, 0x00ffffff,
584 	0xc281, 0x0000ff0f, 0x00000000,
585 	0xa293, 0x07ffffff, 0x06000000,
586 	0xf9e, 0x00000001, 0x00000002,
587 	0x31da, 0x00000008, 0x00000008,
588 	0x31dc, 0x00000f00, 0x00000800,
589 	0x31dd, 0x00000f00, 0x00000800,
590 	0x31e6, 0x00ffffff, 0x00ff7fbf,
591 	0x31e7, 0x00ffffff, 0x00ff7faf,
592 	0x2300, 0x000000ff, 0x00000800,
593 	0x390, 0x00001fff, 0x00001fff,
594 	0x2418, 0x0000007f, 0x00000020,
595 	0x2542, 0x00010000, 0x00010000,
596 	0x2b80, 0x00100000, 0x000ff07c,
597 	0x2b05, 0x000003ff, 0x0000000f,
598 	0x2b04, 0xffffffff, 0x7564fdec,
599 	0x2b03, 0xffffffff, 0x3120b9a8,
600 	0x2b02, 0x20000000, 0x0f9c0000
601 };
602 
603 static const u32 hawaii_mgcg_cgcg_init[] =
604 {
605 	0x3108, 0xffffffff, 0xfffffffd,
606 	0xc200, 0xffffffff, 0xe0000000,
607 	0xf0a8, 0xffffffff, 0x00000100,
608 	0xf082, 0xffffffff, 0x00000100,
609 	0xf0b0, 0xffffffff, 0x00000100,
610 	0xf0b2, 0xffffffff, 0x00000100,
611 	0xf0b1, 0xffffffff, 0x00000100,
612 	0x1579, 0xffffffff, 0x00200100,
613 	0xf0a0, 0xffffffff, 0x00000100,
614 	0xf085, 0xffffffff, 0x06000100,
615 	0xf088, 0xffffffff, 0x00000100,
616 	0xf086, 0xffffffff, 0x06000100,
617 	0xf081, 0xffffffff, 0x00000100,
618 	0xf0b8, 0xffffffff, 0x00000100,
619 	0xf089, 0xffffffff, 0x00000100,
620 	0xf080, 0xffffffff, 0x00000100,
621 	0xf08c, 0xffffffff, 0x00000100,
622 	0xf08d, 0xffffffff, 0x00000100,
623 	0xf094, 0xffffffff, 0x00000100,
624 	0xf095, 0xffffffff, 0x00000100,
625 	0xf096, 0xffffffff, 0x00000100,
626 	0xf097, 0xffffffff, 0x00000100,
627 	0xf098, 0xffffffff, 0x00000100,
628 	0xf09f, 0xffffffff, 0x00000100,
629 	0xf09e, 0xffffffff, 0x00000100,
630 	0xf084, 0xffffffff, 0x06000100,
631 	0xf0a4, 0xffffffff, 0x00000100,
632 	0xf09d, 0xffffffff, 0x00000100,
633 	0xf0ad, 0xffffffff, 0x00000100,
634 	0xf0ac, 0xffffffff, 0x00000100,
635 	0xf09c, 0xffffffff, 0x00000100,
636 	0xc200, 0xffffffff, 0xe0000000,
637 	0xf008, 0xffffffff, 0x00010000,
638 	0xf009, 0xffffffff, 0x00030002,
639 	0xf00a, 0xffffffff, 0x00040007,
640 	0xf00b, 0xffffffff, 0x00060005,
641 	0xf00c, 0xffffffff, 0x00090008,
642 	0xf00d, 0xffffffff, 0x00010000,
643 	0xf00e, 0xffffffff, 0x00030002,
644 	0xf00f, 0xffffffff, 0x00040007,
645 	0xf010, 0xffffffff, 0x00060005,
646 	0xf011, 0xffffffff, 0x00090008,
647 	0xf012, 0xffffffff, 0x00010000,
648 	0xf013, 0xffffffff, 0x00030002,
649 	0xf014, 0xffffffff, 0x00040007,
650 	0xf015, 0xffffffff, 0x00060005,
651 	0xf016, 0xffffffff, 0x00090008,
652 	0xf017, 0xffffffff, 0x00010000,
653 	0xf018, 0xffffffff, 0x00030002,
654 	0xf019, 0xffffffff, 0x00040007,
655 	0xf01a, 0xffffffff, 0x00060005,
656 	0xf01b, 0xffffffff, 0x00090008,
657 	0xf01c, 0xffffffff, 0x00010000,
658 	0xf01d, 0xffffffff, 0x00030002,
659 	0xf01e, 0xffffffff, 0x00040007,
660 	0xf01f, 0xffffffff, 0x00060005,
661 	0xf020, 0xffffffff, 0x00090008,
662 	0xf021, 0xffffffff, 0x00010000,
663 	0xf022, 0xffffffff, 0x00030002,
664 	0xf023, 0xffffffff, 0x00040007,
665 	0xf024, 0xffffffff, 0x00060005,
666 	0xf025, 0xffffffff, 0x00090008,
667 	0xf026, 0xffffffff, 0x00010000,
668 	0xf027, 0xffffffff, 0x00030002,
669 	0xf028, 0xffffffff, 0x00040007,
670 	0xf029, 0xffffffff, 0x00060005,
671 	0xf02a, 0xffffffff, 0x00090008,
672 	0xf02b, 0xffffffff, 0x00010000,
673 	0xf02c, 0xffffffff, 0x00030002,
674 	0xf02d, 0xffffffff, 0x00040007,
675 	0xf02e, 0xffffffff, 0x00060005,
676 	0xf02f, 0xffffffff, 0x00090008,
677 	0xf030, 0xffffffff, 0x00010000,
678 	0xf031, 0xffffffff, 0x00030002,
679 	0xf032, 0xffffffff, 0x00040007,
680 	0xf033, 0xffffffff, 0x00060005,
681 	0xf034, 0xffffffff, 0x00090008,
682 	0xf035, 0xffffffff, 0x00010000,
683 	0xf036, 0xffffffff, 0x00030002,
684 	0xf037, 0xffffffff, 0x00040007,
685 	0xf038, 0xffffffff, 0x00060005,
686 	0xf039, 0xffffffff, 0x00090008,
687 	0xf03a, 0xffffffff, 0x00010000,
688 	0xf03b, 0xffffffff, 0x00030002,
689 	0xf03c, 0xffffffff, 0x00040007,
690 	0xf03d, 0xffffffff, 0x00060005,
691 	0xf03e, 0xffffffff, 0x00090008,
692 	0x30c6, 0xffffffff, 0x00020200,
693 	0xcd4, 0xffffffff, 0x00000200,
694 	0x570, 0xffffffff, 0x00000400,
695 	0x157a, 0xffffffff, 0x00000000,
696 	0xbd4, 0xffffffff, 0x00000902,
697 	0xf000, 0xffffffff, 0x96940200,
698 	0x21c2, 0xffffffff, 0x00900100,
699 	0x3109, 0xffffffff, 0x0020003f,
700 	0xe, 0xffffffff, 0x0140001c,
701 	0xf, 0x000f0000, 0x000f0000,
702 	0x88, 0xffffffff, 0xc060000c,
703 	0x89, 0xc0000fff, 0x00000100,
704 	0x3e4, 0xffffffff, 0x00000100,
705 	0x3e6, 0x00000101, 0x00000000,
706 	0x82a, 0xffffffff, 0x00000104,
707 	0x1579, 0xff000fff, 0x00000100,
708 	0xc33, 0xc0000fff, 0x00000104,
709 	0x3079, 0x00000001, 0x00000001,
710 	0x3403, 0xff000ff0, 0x00000100,
711 	0x3603, 0xff000ff0, 0x00000100
712 };
713 
714 static const u32 godavari_golden_registers[] =
715 {
716 	0x1579, 0xff607fff, 0xfc000100,
717 	0x1bb6, 0x00010101, 0x00010000,
718 	0x260c, 0xffffffff, 0x00000000,
719 	0x260c0, 0xf00fffff, 0x00000400,
720 	0x184c, 0xffffffff, 0x00010000,
721 	0x16ec, 0x000000f0, 0x00000070,
722 	0x16f0, 0xf0311fff, 0x80300000,
723 	0x263e, 0x73773777, 0x12010001,
724 	0x263f, 0xffffffff, 0x00000010,
725 	0x200c, 0x00001f0f, 0x0000100a,
726 	0xbd2, 0x73773777, 0x12010001,
727 	0x902, 0x000fffff, 0x000c007f,
728 	0x2285, 0xf000003f, 0x00000007,
729 	0x22c9, 0xffffffff, 0x00ff0fff,
730 	0xc281, 0x0000ff0f, 0x00000000,
731 	0xa293, 0x07ffffff, 0x06000000,
732 	0x136, 0x00000fff, 0x00000100,
733 	0x3405, 0x00010000, 0x00810001,
734 	0x3605, 0x00010000, 0x00810001,
735 	0xf9e, 0x00000001, 0x00000002,
736 	0x31da, 0x00000008, 0x00000008,
737 	0x31dc, 0x00000f00, 0x00000800,
738 	0x31dd, 0x00000f00, 0x00000800,
739 	0x31e6, 0x00ffffff, 0x00ff7fbf,
740 	0x31e7, 0x00ffffff, 0x00ff7faf,
741 	0x2300, 0x000000ff, 0x00000001,
742 	0x853e, 0x01ff01ff, 0x00000002,
743 	0x8526, 0x007ff800, 0x00200000,
744 	0x8057, 0xffffffff, 0x00000f40,
745 	0x2231, 0x001f3ae3, 0x00000082,
746 	0x2235, 0x0000001f, 0x00000010,
747 	0xc24d, 0xffffffff, 0x00000000
748 };
749 
750 static void cik_init_golden_registers(struct amdgpu_device *adev)
751 {
752 	/* Some of the registers might be dependent on GRBM_GFX_INDEX */
753 	mutex_lock(&adev->grbm_idx_mutex);
754 
755 	switch (adev->asic_type) {
756 	case CHIP_BONAIRE:
757 		amdgpu_program_register_sequence(adev,
758 						 bonaire_mgcg_cgcg_init,
759 						 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
760 		amdgpu_program_register_sequence(adev,
761 						 bonaire_golden_registers,
762 						 (const u32)ARRAY_SIZE(bonaire_golden_registers));
763 		amdgpu_program_register_sequence(adev,
764 						 bonaire_golden_common_registers,
765 						 (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
766 		amdgpu_program_register_sequence(adev,
767 						 bonaire_golden_spm_registers,
768 						 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
769 		break;
770 	case CHIP_KABINI:
771 		amdgpu_program_register_sequence(adev,
772 						 kalindi_mgcg_cgcg_init,
773 						 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
774 		amdgpu_program_register_sequence(adev,
775 						 kalindi_golden_registers,
776 						 (const u32)ARRAY_SIZE(kalindi_golden_registers));
777 		amdgpu_program_register_sequence(adev,
778 						 kalindi_golden_common_registers,
779 						 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
780 		amdgpu_program_register_sequence(adev,
781 						 kalindi_golden_spm_registers,
782 						 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
783 		break;
784 	case CHIP_MULLINS:
785 		amdgpu_program_register_sequence(adev,
786 						 kalindi_mgcg_cgcg_init,
787 						 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
788 		amdgpu_program_register_sequence(adev,
789 						 godavari_golden_registers,
790 						 (const u32)ARRAY_SIZE(godavari_golden_registers));
791 		amdgpu_program_register_sequence(adev,
792 						 kalindi_golden_common_registers,
793 						 (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
794 		amdgpu_program_register_sequence(adev,
795 						 kalindi_golden_spm_registers,
796 						 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
797 		break;
798 	case CHIP_KAVERI:
799 		amdgpu_program_register_sequence(adev,
800 						 spectre_mgcg_cgcg_init,
801 						 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
802 		amdgpu_program_register_sequence(adev,
803 						 spectre_golden_registers,
804 						 (const u32)ARRAY_SIZE(spectre_golden_registers));
805 		amdgpu_program_register_sequence(adev,
806 						 spectre_golden_common_registers,
807 						 (const u32)ARRAY_SIZE(spectre_golden_common_registers));
808 		amdgpu_program_register_sequence(adev,
809 						 spectre_golden_spm_registers,
810 						 (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
811 		break;
812 	case CHIP_HAWAII:
813 		amdgpu_program_register_sequence(adev,
814 						 hawaii_mgcg_cgcg_init,
815 						 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
816 		amdgpu_program_register_sequence(adev,
817 						 hawaii_golden_registers,
818 						 (const u32)ARRAY_SIZE(hawaii_golden_registers));
819 		amdgpu_program_register_sequence(adev,
820 						 hawaii_golden_common_registers,
821 						 (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
822 		amdgpu_program_register_sequence(adev,
823 						 hawaii_golden_spm_registers,
824 						 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
825 		break;
826 	default:
827 		break;
828 	}
829 	mutex_unlock(&adev->grbm_idx_mutex);
830 }
831 
832 /**
833  * cik_get_xclk - get the xclk
834  *
835  * @adev: amdgpu_device pointer
836  *
837  * Returns the reference clock used by the gfx engine
838  * (CIK).
839  */
840 static u32 cik_get_xclk(struct amdgpu_device *adev)
841 {
842 	u32 reference_clock = adev->clock.spll.reference_freq;
843 
844 	if (adev->flags & AMD_IS_APU) {
845 		if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
846 			return reference_clock / 2;
847 	} else {
848 		if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK)
849 			return reference_clock / 4;
850 	}
851 	return reference_clock;
852 }
853 
854 /**
855  * cik_srbm_select - select specific register instances
856  *
857  * @adev: amdgpu_device pointer
858  * @me: selected ME (micro engine)
859  * @pipe: pipe
860  * @queue: queue
861  * @vmid: VMID
862  *
863  * Switches the currently active registers instances.  Some
864  * registers are instanced per VMID, others are instanced per
865  * me/pipe/queue combination.
866  */
867 void cik_srbm_select(struct amdgpu_device *adev,
868 		     u32 me, u32 pipe, u32 queue, u32 vmid)
869 {
870 	u32 srbm_gfx_cntl =
871 		(((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)|
872 		((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)|
873 		((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)|
874 		((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK));
875 	WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl);
876 }
877 
878 static void cik_vga_set_state(struct amdgpu_device *adev, bool state)
879 {
880 	uint32_t tmp;
881 
882 	tmp = RREG32(mmCONFIG_CNTL);
883 	if (!state)
884 		tmp |= CONFIG_CNTL__VGA_DIS_MASK;
885 	else
886 		tmp &= ~CONFIG_CNTL__VGA_DIS_MASK;
887 	WREG32(mmCONFIG_CNTL, tmp);
888 }
889 
890 static bool cik_read_disabled_bios(struct amdgpu_device *adev)
891 {
892 	u32 bus_cntl;
893 	u32 d1vga_control = 0;
894 	u32 d2vga_control = 0;
895 	u32 vga_render_control = 0;
896 	u32 rom_cntl;
897 	bool r;
898 
899 	bus_cntl = RREG32(mmBUS_CNTL);
900 	if (adev->mode_info.num_crtc) {
901 		d1vga_control = RREG32(mmD1VGA_CONTROL);
902 		d2vga_control = RREG32(mmD2VGA_CONTROL);
903 		vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
904 	}
905 	rom_cntl = RREG32_SMC(ixROM_CNTL);
906 
907 	/* enable the rom */
908 	WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK));
909 	if (adev->mode_info.num_crtc) {
910 		/* Disable VGA mode */
911 		WREG32(mmD1VGA_CONTROL,
912 		       (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
913 					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
914 		WREG32(mmD2VGA_CONTROL,
915 		       (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK |
916 					  D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK)));
917 		WREG32(mmVGA_RENDER_CONTROL,
918 		       (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK));
919 	}
920 	WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK);
921 
922 	r = amdgpu_read_bios(adev);
923 
924 	/* restore regs */
925 	WREG32(mmBUS_CNTL, bus_cntl);
926 	if (adev->mode_info.num_crtc) {
927 		WREG32(mmD1VGA_CONTROL, d1vga_control);
928 		WREG32(mmD2VGA_CONTROL, d2vga_control);
929 		WREG32(mmVGA_RENDER_CONTROL, vga_render_control);
930 	}
931 	WREG32_SMC(ixROM_CNTL, rom_cntl);
932 	return r;
933 }
934 
935 static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
936 				   u8 *bios, u32 length_bytes)
937 {
938 	u32 *dw_ptr;
939 	unsigned long flags;
940 	u32 i, length_dw;
941 
942 	if (bios == NULL)
943 		return false;
944 	if (length_bytes == 0)
945 		return false;
946 	/* APU vbios image is part of sbios image */
947 	if (adev->flags & AMD_IS_APU)
948 		return false;
949 
950 	dw_ptr = (u32 *)bios;
951 	length_dw = ALIGN(length_bytes, 4) / 4;
952 	/* take the smc lock since we are using the smc index */
953 	spin_lock_irqsave(&adev->smc_idx_lock, flags);
954 	/* set rom index to 0 */
955 	WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX);
956 	WREG32(mmSMC_IND_DATA_0, 0);
957 	/* set index to data for continous read */
958 	WREG32(mmSMC_IND_INDEX_0, ixROM_DATA);
959 	for (i = 0; i < length_dw; i++)
960 		dw_ptr[i] = RREG32(mmSMC_IND_DATA_0);
961 	spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
962 
963 	return true;
964 }
965 
966 static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = {
967 	{mmGRBM_STATUS, false},
968 	{mmGB_ADDR_CONFIG, false},
969 	{mmMC_ARB_RAMCFG, false},
970 	{mmGB_TILE_MODE0, false},
971 	{mmGB_TILE_MODE1, false},
972 	{mmGB_TILE_MODE2, false},
973 	{mmGB_TILE_MODE3, false},
974 	{mmGB_TILE_MODE4, false},
975 	{mmGB_TILE_MODE5, false},
976 	{mmGB_TILE_MODE6, false},
977 	{mmGB_TILE_MODE7, false},
978 	{mmGB_TILE_MODE8, false},
979 	{mmGB_TILE_MODE9, false},
980 	{mmGB_TILE_MODE10, false},
981 	{mmGB_TILE_MODE11, false},
982 	{mmGB_TILE_MODE12, false},
983 	{mmGB_TILE_MODE13, false},
984 	{mmGB_TILE_MODE14, false},
985 	{mmGB_TILE_MODE15, false},
986 	{mmGB_TILE_MODE16, false},
987 	{mmGB_TILE_MODE17, false},
988 	{mmGB_TILE_MODE18, false},
989 	{mmGB_TILE_MODE19, false},
990 	{mmGB_TILE_MODE20, false},
991 	{mmGB_TILE_MODE21, false},
992 	{mmGB_TILE_MODE22, false},
993 	{mmGB_TILE_MODE23, false},
994 	{mmGB_TILE_MODE24, false},
995 	{mmGB_TILE_MODE25, false},
996 	{mmGB_TILE_MODE26, false},
997 	{mmGB_TILE_MODE27, false},
998 	{mmGB_TILE_MODE28, false},
999 	{mmGB_TILE_MODE29, false},
1000 	{mmGB_TILE_MODE30, false},
1001 	{mmGB_TILE_MODE31, false},
1002 	{mmGB_MACROTILE_MODE0, false},
1003 	{mmGB_MACROTILE_MODE1, false},
1004 	{mmGB_MACROTILE_MODE2, false},
1005 	{mmGB_MACROTILE_MODE3, false},
1006 	{mmGB_MACROTILE_MODE4, false},
1007 	{mmGB_MACROTILE_MODE5, false},
1008 	{mmGB_MACROTILE_MODE6, false},
1009 	{mmGB_MACROTILE_MODE7, false},
1010 	{mmGB_MACROTILE_MODE8, false},
1011 	{mmGB_MACROTILE_MODE9, false},
1012 	{mmGB_MACROTILE_MODE10, false},
1013 	{mmGB_MACROTILE_MODE11, false},
1014 	{mmGB_MACROTILE_MODE12, false},
1015 	{mmGB_MACROTILE_MODE13, false},
1016 	{mmGB_MACROTILE_MODE14, false},
1017 	{mmGB_MACROTILE_MODE15, false},
1018 	{mmCC_RB_BACKEND_DISABLE, false, true},
1019 	{mmGC_USER_RB_BACKEND_DISABLE, false, true},
1020 	{mmGB_BACKEND_MAP, false, false},
1021 	{mmPA_SC_RASTER_CONFIG, false, true},
1022 	{mmPA_SC_RASTER_CONFIG_1, false, true},
1023 };
1024 
1025 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev,
1026 					  u32 se_num, u32 sh_num,
1027 					  u32 reg_offset)
1028 {
1029 	uint32_t val;
1030 
1031 	mutex_lock(&adev->grbm_idx_mutex);
1032 	if (se_num != 0xffffffff || sh_num != 0xffffffff)
1033 		amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
1034 
1035 	val = RREG32(reg_offset);
1036 
1037 	if (se_num != 0xffffffff || sh_num != 0xffffffff)
1038 		amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1039 	mutex_unlock(&adev->grbm_idx_mutex);
1040 	return val;
1041 }
1042 
1043 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
1044 			     u32 sh_num, u32 reg_offset, u32 *value)
1045 {
1046 	uint32_t i;
1047 
1048 	*value = 0;
1049 	for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) {
1050 		if (reg_offset != cik_allowed_read_registers[i].reg_offset)
1051 			continue;
1052 
1053 		if (!cik_allowed_read_registers[i].untouched)
1054 			*value = cik_allowed_read_registers[i].grbm_indexed ?
1055 				 cik_read_indexed_register(adev, se_num,
1056 							   sh_num, reg_offset) :
1057 				 RREG32(reg_offset);
1058 		return 0;
1059 	}
1060 	return -EINVAL;
1061 }
1062 
1063 struct kv_reset_save_regs {
1064 	u32 gmcon_reng_execute;
1065 	u32 gmcon_misc;
1066 	u32 gmcon_misc3;
1067 };
1068 
1069 static void kv_save_regs_for_reset(struct amdgpu_device *adev,
1070 				   struct kv_reset_save_regs *save)
1071 {
1072 	save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE);
1073 	save->gmcon_misc = RREG32(mmGMCON_MISC);
1074 	save->gmcon_misc3 = RREG32(mmGMCON_MISC3);
1075 
1076 	WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute &
1077 		~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK);
1078 	WREG32(mmGMCON_MISC, save->gmcon_misc &
1079 		~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK |
1080 			GMCON_MISC__STCTRL_STUTTER_EN_MASK));
1081 }
1082 
1083 static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
1084 				      struct kv_reset_save_regs *save)
1085 {
1086 	int i;
1087 
1088 	WREG32(mmGMCON_PGFSM_WRITE, 0);
1089 	WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff);
1090 
1091 	for (i = 0; i < 5; i++)
1092 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1093 
1094 	WREG32(mmGMCON_PGFSM_WRITE, 0);
1095 	WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff);
1096 
1097 	for (i = 0; i < 5; i++)
1098 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1099 
1100 	WREG32(mmGMCON_PGFSM_WRITE, 0x210000);
1101 	WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff);
1102 
1103 	for (i = 0; i < 5; i++)
1104 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1105 
1106 	WREG32(mmGMCON_PGFSM_WRITE, 0x21003);
1107 	WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff);
1108 
1109 	for (i = 0; i < 5; i++)
1110 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1111 
1112 	WREG32(mmGMCON_PGFSM_WRITE, 0x2b00);
1113 	WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff);
1114 
1115 	for (i = 0; i < 5; i++)
1116 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1117 
1118 	WREG32(mmGMCON_PGFSM_WRITE, 0);
1119 	WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff);
1120 
1121 	for (i = 0; i < 5; i++)
1122 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1123 
1124 	WREG32(mmGMCON_PGFSM_WRITE, 0x420000);
1125 	WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff);
1126 
1127 	for (i = 0; i < 5; i++)
1128 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1129 
1130 	WREG32(mmGMCON_PGFSM_WRITE, 0x120202);
1131 	WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff);
1132 
1133 	for (i = 0; i < 5; i++)
1134 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1135 
1136 	WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36);
1137 	WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff);
1138 
1139 	for (i = 0; i < 5; i++)
1140 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1141 
1142 	WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e);
1143 	WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff);
1144 
1145 	for (i = 0; i < 5; i++)
1146 		WREG32(mmGMCON_PGFSM_WRITE, 0);
1147 
1148 	WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332);
1149 	WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff);
1150 
1151 	WREG32(mmGMCON_MISC3, save->gmcon_misc3);
1152 	WREG32(mmGMCON_MISC, save->gmcon_misc);
1153 	WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);
1154 }
1155 
1156 static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
1157 {
1158 	struct kv_reset_save_regs kv_save = { 0 };
1159 	u32 i;
1160 	int r = -EINVAL;
1161 
1162 	dev_info(adev->dev, "GPU pci config reset\n");
1163 
1164 	if (adev->flags & AMD_IS_APU)
1165 		kv_save_regs_for_reset(adev, &kv_save);
1166 
1167 	/* disable BM */
1168 	pci_clear_master(adev->pdev);
1169 	/* reset */
1170 	amdgpu_pci_config_reset(adev);
1171 
1172 	udelay(100);
1173 
1174 	/* wait for asic to come out of reset */
1175 	for (i = 0; i < adev->usec_timeout; i++) {
1176 		if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
1177 			/* enable BM */
1178 			pci_set_master(adev->pdev);
1179 			r = 0;
1180 			break;
1181 		}
1182 		udelay(1);
1183 	}
1184 
1185 	/* does asic init need to be run first??? */
1186 	if (adev->flags & AMD_IS_APU)
1187 		kv_restore_regs_for_reset(adev, &kv_save);
1188 
1189 	return r;
1190 }
1191 
1192 static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
1193 {
1194 	u32 tmp = RREG32(mmBIOS_SCRATCH_3);
1195 
1196 	if (hung)
1197 		tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1198 	else
1199 		tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1200 
1201 	WREG32(mmBIOS_SCRATCH_3, tmp);
1202 }
1203 
1204 /**
1205  * cik_asic_reset - soft reset GPU
1206  *
1207  * @adev: amdgpu_device pointer
1208  *
1209  * Look up which blocks are hung and attempt
1210  * to reset them.
1211  * Returns 0 for success.
1212  */
1213 static int cik_asic_reset(struct amdgpu_device *adev)
1214 {
1215 	int r;
1216 	cik_set_bios_scratch_engine_hung(adev, true);
1217 
1218 	r = cik_gpu_pci_config_reset(adev);
1219 
1220 	cik_set_bios_scratch_engine_hung(adev, false);
1221 
1222 	return r;
1223 }
1224 
1225 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1226 			      u32 cntl_reg, u32 status_reg)
1227 {
1228 	int r, i;
1229 	struct atom_clock_dividers dividers;
1230 	uint32_t tmp;
1231 
1232 	r = amdgpu_atombios_get_clock_dividers(adev,
1233 					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1234 					       clock, false, &dividers);
1235 	if (r)
1236 		return r;
1237 
1238 	tmp = RREG32_SMC(cntl_reg);
1239 	tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK |
1240 		CG_DCLK_CNTL__DCLK_DIVIDER_MASK);
1241 	tmp |= dividers.post_divider;
1242 	WREG32_SMC(cntl_reg, tmp);
1243 
1244 	for (i = 0; i < 100; i++) {
1245 		if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK)
1246 			break;
1247 		mdelay(10);
1248 	}
1249 	if (i == 100)
1250 		return -ETIMEDOUT;
1251 
1252 	return 0;
1253 }
1254 
1255 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1256 {
1257 	int r = 0;
1258 
1259 	r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1260 	if (r)
1261 		return r;
1262 
1263 	r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1264 	return r;
1265 }
1266 
1267 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1268 {
1269 	int r, i;
1270 	struct atom_clock_dividers dividers;
1271 	u32 tmp;
1272 
1273 	r = amdgpu_atombios_get_clock_dividers(adev,
1274 					       COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
1275 					       ecclk, false, &dividers);
1276 	if (r)
1277 		return r;
1278 
1279 	for (i = 0; i < 100; i++) {
1280 		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1281 			break;
1282 		mdelay(10);
1283 	}
1284 	if (i == 100)
1285 		return -ETIMEDOUT;
1286 
1287 	tmp = RREG32_SMC(ixCG_ECLK_CNTL);
1288 	tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK |
1289 		CG_ECLK_CNTL__ECLK_DIVIDER_MASK);
1290 	tmp |= dividers.post_divider;
1291 	WREG32_SMC(ixCG_ECLK_CNTL, tmp);
1292 
1293 	for (i = 0; i < 100; i++) {
1294 		if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK)
1295 			break;
1296 		mdelay(10);
1297 	}
1298 	if (i == 100)
1299 		return -ETIMEDOUT;
1300 
1301 	return 0;
1302 }
1303 
1304 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
1305 {
1306 	struct pci_dev *root = adev->pdev->bus->self;
1307 	int bridge_pos, gpu_pos;
1308 	u32 speed_cntl, current_data_rate;
1309 	int i;
1310 	u16 tmp16;
1311 
1312 	if (pci_is_root_bus(adev->pdev->bus))
1313 		return;
1314 
1315 	if (amdgpu_pcie_gen2 == 0)
1316 		return;
1317 
1318 	if (adev->flags & AMD_IS_APU)
1319 		return;
1320 
1321 	if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1322 					CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
1323 		return;
1324 
1325 	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1326 	current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >>
1327 		PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
1328 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1329 		if (current_data_rate == 2) {
1330 			DRM_INFO("PCIE gen 3 link speeds already enabled\n");
1331 			return;
1332 		}
1333 		DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n");
1334 	} else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1335 		if (current_data_rate == 1) {
1336 			DRM_INFO("PCIE gen 2 link speeds already enabled\n");
1337 			return;
1338 		}
1339 		DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n");
1340 	}
1341 
1342 	bridge_pos = pci_pcie_cap(root);
1343 	if (!bridge_pos)
1344 		return;
1345 
1346 	gpu_pos = pci_pcie_cap(adev->pdev);
1347 	if (!gpu_pos)
1348 		return;
1349 
1350 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1351 		/* re-try equalization if gen3 is not already enabled */
1352 		if (current_data_rate != 2) {
1353 			u16 bridge_cfg, gpu_cfg;
1354 			u16 bridge_cfg2, gpu_cfg2;
1355 			u32 max_lw, current_lw, tmp;
1356 
1357 			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1358 			pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1359 
1360 			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
1361 			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1362 
1363 			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
1364 			pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1365 
1366 			tmp = RREG32_PCIE(ixPCIE_LC_STATUS1);
1367 			max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >>
1368 				PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT;
1369 			current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK)
1370 				>> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT;
1371 
1372 			if (current_lw < max_lw) {
1373 				tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1374 				if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) {
1375 					tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK |
1376 						PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK);
1377 					tmp |= (max_lw <<
1378 						PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT);
1379 					tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK |
1380 					PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK |
1381 					PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK;
1382 					WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp);
1383 				}
1384 			}
1385 
1386 			for (i = 0; i < 10; i++) {
1387 				/* check status */
1388 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
1389 				if (tmp16 & PCI_EXP_DEVSTA_TRPND)
1390 					break;
1391 
1392 				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
1393 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
1394 
1395 				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
1396 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
1397 
1398 				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1399 				tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
1400 				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1401 
1402 				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1403 				tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK;
1404 				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1405 
1406 				mdelay(100);
1407 
1408 				/* linkctl */
1409 				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
1410 				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1411 				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
1412 				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
1413 
1414 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
1415 				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
1416 				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
1417 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
1418 
1419 				/* linkctl2 */
1420 				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
1421 				tmp16 &= ~((1 << 4) | (7 << 9));
1422 				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
1423 				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
1424 
1425 				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1426 				tmp16 &= ~((1 << 4) | (7 << 9));
1427 				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
1428 				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1429 
1430 				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
1431 				tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK;
1432 				WREG32_PCIE(ixPCIE_LC_CNTL4, tmp);
1433 			}
1434 		}
1435 	}
1436 
1437 	/* set the link speed */
1438 	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK |
1439 		PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK;
1440 	speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK;
1441 	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1442 
1443 	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
1444 	tmp16 &= ~0xf;
1445 	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1446 		tmp16 |= 3; /* gen3 */
1447 	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1448 		tmp16 |= 2; /* gen2 */
1449 	else
1450 		tmp16 |= 1; /* gen1 */
1451 	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
1452 
1453 	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1454 	speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
1455 	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
1456 
1457 	for (i = 0; i < adev->usec_timeout; i++) {
1458 		speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);
1459 		if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0)
1460 			break;
1461 		udelay(1);
1462 	}
1463 }
1464 
1465 static void cik_program_aspm(struct amdgpu_device *adev)
1466 {
1467 	u32 data, orig;
1468 	bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
1469 	bool disable_clkreq = false;
1470 
1471 	if (amdgpu_aspm == 0)
1472 		return;
1473 
1474 	if (pci_is_root_bus(adev->pdev->bus))
1475 		return;
1476 
1477 	/* XXX double check APUs */
1478 	if (adev->flags & AMD_IS_APU)
1479 		return;
1480 
1481 	orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1482 	data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1483 	data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) |
1484 		PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
1485 	if (orig != data)
1486 		WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1487 
1488 	orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1489 	data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1490 	if (orig != data)
1491 		WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1492 
1493 	orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1494 	data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1495 	if (orig != data)
1496 		WREG32_PCIE(ixPCIE_P_CNTL, data);
1497 
1498 	orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1499 	data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK |
1500 		PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK);
1501 	data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1502 	if (!disable_l0s)
1503 		data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);
1504 
1505 	if (!disable_l1) {
1506 		data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);
1507 		data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1508 		if (orig != data)
1509 			WREG32_PCIE(ixPCIE_LC_CNTL, data);
1510 
1511 		if (!disable_plloff_in_l1) {
1512 			bool clk_req_support;
1513 
1514 			orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0);
1515 			data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1516 				PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
1517 			data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1518 				(7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
1519 			if (orig != data)
1520 				WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data);
1521 
1522 			orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1);
1523 			data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1524 				PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
1525 			data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1526 				(7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
1527 			if (orig != data)
1528 				WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data);
1529 
1530 			orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0);
1531 			data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1532 				PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK);
1533 			data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1534 				(7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT);
1535 			if (orig != data)
1536 				WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data);
1537 
1538 			orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1);
1539 			data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1540 				PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK);
1541 			data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1542 				(7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT);
1543 			if (orig != data)
1544 				WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data);
1545 
1546 			orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1547 			data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1548 			data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
1549 			if (orig != data)
1550 				WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1551 
1552 			if (!disable_clkreq) {
1553 				struct pci_dev *root = adev->pdev->bus->self;
1554 				u32 lnkcap;
1555 
1556 				clk_req_support = false;
1557 				pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
1558 				if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
1559 					clk_req_support = true;
1560 			} else {
1561 				clk_req_support = false;
1562 			}
1563 
1564 			if (clk_req_support) {
1565 				orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1566 				data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
1567 					PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
1568 				if (orig != data)
1569 					WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1570 
1571 				orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1572 				data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |
1573 					THM_CLK_CNTL__TMON_CLK_SEL_MASK);
1574 				data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1575 					(1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT);
1576 				if (orig != data)
1577 					WREG32_SMC(ixTHM_CLK_CNTL, data);
1578 
1579 				orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1580 				data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1581 					MISC_CLK_CTRL__ZCLK_SEL_MASK);
1582 				data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1583 					(1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT);
1584 				if (orig != data)
1585 					WREG32_SMC(ixMISC_CLK_CTRL, data);
1586 
1587 				orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1588 				data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
1589 				if (orig != data)
1590 					WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1591 
1592 				orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1593 				data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;
1594 				if (orig != data)
1595 					WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
1596 
1597 				orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1598 				data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1599 				data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1600 				if (orig != data)
1601 					WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1602 			}
1603 		}
1604 	} else {
1605 		if (orig != data)
1606 			WREG32_PCIE(ixPCIE_LC_CNTL, data);
1607 	}
1608 
1609 	orig = data = RREG32_PCIE(ixPCIE_CNTL2);
1610 	data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1611 		PCIE_CNTL2__MST_MEM_LS_EN_MASK |
1612 		PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK;
1613 	if (orig != data)
1614 		WREG32_PCIE(ixPCIE_CNTL2, data);
1615 
1616 	if (!disable_l0s) {
1617 		data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1618 		if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) ==
1619 				PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) {
1620 			data = RREG32_PCIE(ixPCIE_LC_STATUS1);
1621 			if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) &&
1622 			(data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {
1623 				orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1624 				data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1625 				if (orig != data)
1626 					WREG32_PCIE(ixPCIE_LC_CNTL, data);
1627 			}
1628 		}
1629 	}
1630 }
1631 
1632 static uint32_t cik_get_rev_id(struct amdgpu_device *adev)
1633 {
1634 	return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
1635 		>> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
1636 }
1637 
1638 static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
1639 {
1640 	if (is_virtual_machine()) /* passthrough mode */
1641 		adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1642 }
1643 
1644 static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
1645 {
1646 	/* ORDER MATTERS! */
1647 	{
1648 		.type = AMD_IP_BLOCK_TYPE_COMMON,
1649 		.major = 1,
1650 		.minor = 0,
1651 		.rev = 0,
1652 		.funcs = &cik_common_ip_funcs,
1653 	},
1654 	{
1655 		.type = AMD_IP_BLOCK_TYPE_GMC,
1656 		.major = 7,
1657 		.minor = 0,
1658 		.rev = 0,
1659 		.funcs = &gmc_v7_0_ip_funcs,
1660 	},
1661 	{
1662 		.type = AMD_IP_BLOCK_TYPE_IH,
1663 		.major = 2,
1664 		.minor = 0,
1665 		.rev = 0,
1666 		.funcs = &cik_ih_ip_funcs,
1667 	},
1668 	{
1669 		.type = AMD_IP_BLOCK_TYPE_SMC,
1670 		.major = 7,
1671 		.minor = 0,
1672 		.rev = 0,
1673 		.funcs = &amdgpu_pp_ip_funcs,
1674 	},
1675 	{
1676 		.type = AMD_IP_BLOCK_TYPE_DCE,
1677 		.major = 8,
1678 		.minor = 2,
1679 		.rev = 0,
1680 		.funcs = &dce_v8_0_ip_funcs,
1681 	},
1682 	{
1683 		.type = AMD_IP_BLOCK_TYPE_GFX,
1684 		.major = 7,
1685 		.minor = 2,
1686 		.rev = 0,
1687 		.funcs = &gfx_v7_0_ip_funcs,
1688 	},
1689 	{
1690 		.type = AMD_IP_BLOCK_TYPE_SDMA,
1691 		.major = 2,
1692 		.minor = 0,
1693 		.rev = 0,
1694 		.funcs = &cik_sdma_ip_funcs,
1695 	},
1696 	{
1697 		.type = AMD_IP_BLOCK_TYPE_UVD,
1698 		.major = 4,
1699 		.minor = 2,
1700 		.rev = 0,
1701 		.funcs = &uvd_v4_2_ip_funcs,
1702 	},
1703 	{
1704 		.type = AMD_IP_BLOCK_TYPE_VCE,
1705 		.major = 2,
1706 		.minor = 0,
1707 		.rev = 0,
1708 		.funcs = &vce_v2_0_ip_funcs,
1709 	},
1710 };
1711 
1712 static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] =
1713 {
1714 	/* ORDER MATTERS! */
1715 	{
1716 		.type = AMD_IP_BLOCK_TYPE_COMMON,
1717 		.major = 1,
1718 		.minor = 0,
1719 		.rev = 0,
1720 		.funcs = &cik_common_ip_funcs,
1721 	},
1722 	{
1723 		.type = AMD_IP_BLOCK_TYPE_GMC,
1724 		.major = 7,
1725 		.minor = 0,
1726 		.rev = 0,
1727 		.funcs = &gmc_v7_0_ip_funcs,
1728 	},
1729 	{
1730 		.type = AMD_IP_BLOCK_TYPE_IH,
1731 		.major = 2,
1732 		.minor = 0,
1733 		.rev = 0,
1734 		.funcs = &cik_ih_ip_funcs,
1735 	},
1736 	{
1737 		.type = AMD_IP_BLOCK_TYPE_SMC,
1738 		.major = 7,
1739 		.minor = 0,
1740 		.rev = 0,
1741 		.funcs = &amdgpu_pp_ip_funcs,
1742 	},
1743 	{
1744 		.type = AMD_IP_BLOCK_TYPE_DCE,
1745 		.major = 8,
1746 		.minor = 2,
1747 		.rev = 0,
1748 		.funcs = &dce_virtual_ip_funcs,
1749 	},
1750 	{
1751 		.type = AMD_IP_BLOCK_TYPE_GFX,
1752 		.major = 7,
1753 		.minor = 2,
1754 		.rev = 0,
1755 		.funcs = &gfx_v7_0_ip_funcs,
1756 	},
1757 	{
1758 		.type = AMD_IP_BLOCK_TYPE_SDMA,
1759 		.major = 2,
1760 		.minor = 0,
1761 		.rev = 0,
1762 		.funcs = &cik_sdma_ip_funcs,
1763 	},
1764 	{
1765 		.type = AMD_IP_BLOCK_TYPE_UVD,
1766 		.major = 4,
1767 		.minor = 2,
1768 		.rev = 0,
1769 		.funcs = &uvd_v4_2_ip_funcs,
1770 	},
1771 	{
1772 		.type = AMD_IP_BLOCK_TYPE_VCE,
1773 		.major = 2,
1774 		.minor = 0,
1775 		.rev = 0,
1776 		.funcs = &vce_v2_0_ip_funcs,
1777 	},
1778 };
1779 
1780 static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
1781 {
1782 	/* ORDER MATTERS! */
1783 	{
1784 		.type = AMD_IP_BLOCK_TYPE_COMMON,
1785 		.major = 1,
1786 		.minor = 0,
1787 		.rev = 0,
1788 		.funcs = &cik_common_ip_funcs,
1789 	},
1790 	{
1791 		.type = AMD_IP_BLOCK_TYPE_GMC,
1792 		.major = 7,
1793 		.minor = 0,
1794 		.rev = 0,
1795 		.funcs = &gmc_v7_0_ip_funcs,
1796 	},
1797 	{
1798 		.type = AMD_IP_BLOCK_TYPE_IH,
1799 		.major = 2,
1800 		.minor = 0,
1801 		.rev = 0,
1802 		.funcs = &cik_ih_ip_funcs,
1803 	},
1804 	{
1805 		.type = AMD_IP_BLOCK_TYPE_SMC,
1806 		.major = 7,
1807 		.minor = 0,
1808 		.rev = 0,
1809 		.funcs = &amdgpu_pp_ip_funcs,
1810 	},
1811 	{
1812 		.type = AMD_IP_BLOCK_TYPE_DCE,
1813 		.major = 8,
1814 		.minor = 5,
1815 		.rev = 0,
1816 		.funcs = &dce_v8_0_ip_funcs,
1817 	},
1818 	{
1819 		.type = AMD_IP_BLOCK_TYPE_GFX,
1820 		.major = 7,
1821 		.minor = 3,
1822 		.rev = 0,
1823 		.funcs = &gfx_v7_0_ip_funcs,
1824 	},
1825 	{
1826 		.type = AMD_IP_BLOCK_TYPE_SDMA,
1827 		.major = 2,
1828 		.minor = 0,
1829 		.rev = 0,
1830 		.funcs = &cik_sdma_ip_funcs,
1831 	},
1832 	{
1833 		.type = AMD_IP_BLOCK_TYPE_UVD,
1834 		.major = 4,
1835 		.minor = 2,
1836 		.rev = 0,
1837 		.funcs = &uvd_v4_2_ip_funcs,
1838 	},
1839 	{
1840 		.type = AMD_IP_BLOCK_TYPE_VCE,
1841 		.major = 2,
1842 		.minor = 0,
1843 		.rev = 0,
1844 		.funcs = &vce_v2_0_ip_funcs,
1845 	},
1846 };
1847 
1848 static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] =
1849 {
1850 	/* ORDER MATTERS! */
1851 	{
1852 		.type = AMD_IP_BLOCK_TYPE_COMMON,
1853 		.major = 1,
1854 		.minor = 0,
1855 		.rev = 0,
1856 		.funcs = &cik_common_ip_funcs,
1857 	},
1858 	{
1859 		.type = AMD_IP_BLOCK_TYPE_GMC,
1860 		.major = 7,
1861 		.minor = 0,
1862 		.rev = 0,
1863 		.funcs = &gmc_v7_0_ip_funcs,
1864 	},
1865 	{
1866 		.type = AMD_IP_BLOCK_TYPE_IH,
1867 		.major = 2,
1868 		.minor = 0,
1869 		.rev = 0,
1870 		.funcs = &cik_ih_ip_funcs,
1871 	},
1872 	{
1873 		.type = AMD_IP_BLOCK_TYPE_SMC,
1874 		.major = 7,
1875 		.minor = 0,
1876 		.rev = 0,
1877 		.funcs = &amdgpu_pp_ip_funcs,
1878 	},
1879 	{
1880 		.type = AMD_IP_BLOCK_TYPE_DCE,
1881 		.major = 8,
1882 		.minor = 5,
1883 		.rev = 0,
1884 		.funcs = &dce_virtual_ip_funcs,
1885 	},
1886 	{
1887 		.type = AMD_IP_BLOCK_TYPE_GFX,
1888 		.major = 7,
1889 		.minor = 3,
1890 		.rev = 0,
1891 		.funcs = &gfx_v7_0_ip_funcs,
1892 	},
1893 	{
1894 		.type = AMD_IP_BLOCK_TYPE_SDMA,
1895 		.major = 2,
1896 		.minor = 0,
1897 		.rev = 0,
1898 		.funcs = &cik_sdma_ip_funcs,
1899 	},
1900 	{
1901 		.type = AMD_IP_BLOCK_TYPE_UVD,
1902 		.major = 4,
1903 		.minor = 2,
1904 		.rev = 0,
1905 		.funcs = &uvd_v4_2_ip_funcs,
1906 	},
1907 	{
1908 		.type = AMD_IP_BLOCK_TYPE_VCE,
1909 		.major = 2,
1910 		.minor = 0,
1911 		.rev = 0,
1912 		.funcs = &vce_v2_0_ip_funcs,
1913 	},
1914 };
1915 
1916 static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
1917 {
1918 	/* ORDER MATTERS! */
1919 	{
1920 		.type = AMD_IP_BLOCK_TYPE_COMMON,
1921 		.major = 1,
1922 		.minor = 0,
1923 		.rev = 0,
1924 		.funcs = &cik_common_ip_funcs,
1925 	},
1926 	{
1927 		.type = AMD_IP_BLOCK_TYPE_GMC,
1928 		.major = 7,
1929 		.minor = 0,
1930 		.rev = 0,
1931 		.funcs = &gmc_v7_0_ip_funcs,
1932 	},
1933 	{
1934 		.type = AMD_IP_BLOCK_TYPE_IH,
1935 		.major = 2,
1936 		.minor = 0,
1937 		.rev = 0,
1938 		.funcs = &cik_ih_ip_funcs,
1939 	},
1940 	{
1941 		.type = AMD_IP_BLOCK_TYPE_SMC,
1942 		.major = 7,
1943 		.minor = 0,
1944 		.rev = 0,
1945 		.funcs = &amdgpu_pp_ip_funcs,
1946 	},
1947 	{
1948 		.type = AMD_IP_BLOCK_TYPE_DCE,
1949 		.major = 8,
1950 		.minor = 3,
1951 		.rev = 0,
1952 		.funcs = &dce_v8_0_ip_funcs,
1953 	},
1954 	{
1955 		.type = AMD_IP_BLOCK_TYPE_GFX,
1956 		.major = 7,
1957 		.minor = 2,
1958 		.rev = 0,
1959 		.funcs = &gfx_v7_0_ip_funcs,
1960 	},
1961 	{
1962 		.type = AMD_IP_BLOCK_TYPE_SDMA,
1963 		.major = 2,
1964 		.minor = 0,
1965 		.rev = 0,
1966 		.funcs = &cik_sdma_ip_funcs,
1967 	},
1968 	{
1969 		.type = AMD_IP_BLOCK_TYPE_UVD,
1970 		.major = 4,
1971 		.minor = 2,
1972 		.rev = 0,
1973 		.funcs = &uvd_v4_2_ip_funcs,
1974 	},
1975 	{
1976 		.type = AMD_IP_BLOCK_TYPE_VCE,
1977 		.major = 2,
1978 		.minor = 0,
1979 		.rev = 0,
1980 		.funcs = &vce_v2_0_ip_funcs,
1981 	},
1982 };
1983 
1984 static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] =
1985 {
1986 	/* ORDER MATTERS! */
1987 	{
1988 		.type = AMD_IP_BLOCK_TYPE_COMMON,
1989 		.major = 1,
1990 		.minor = 0,
1991 		.rev = 0,
1992 		.funcs = &cik_common_ip_funcs,
1993 	},
1994 	{
1995 		.type = AMD_IP_BLOCK_TYPE_GMC,
1996 		.major = 7,
1997 		.minor = 0,
1998 		.rev = 0,
1999 		.funcs = &gmc_v7_0_ip_funcs,
2000 	},
2001 	{
2002 		.type = AMD_IP_BLOCK_TYPE_IH,
2003 		.major = 2,
2004 		.minor = 0,
2005 		.rev = 0,
2006 		.funcs = &cik_ih_ip_funcs,
2007 	},
2008 	{
2009 		.type = AMD_IP_BLOCK_TYPE_SMC,
2010 		.major = 7,
2011 		.minor = 0,
2012 		.rev = 0,
2013 		.funcs = &amdgpu_pp_ip_funcs,
2014 	},
2015 	{
2016 		.type = AMD_IP_BLOCK_TYPE_DCE,
2017 		.major = 8,
2018 		.minor = 3,
2019 		.rev = 0,
2020 		.funcs = &dce_virtual_ip_funcs,
2021 	},
2022 	{
2023 		.type = AMD_IP_BLOCK_TYPE_GFX,
2024 		.major = 7,
2025 		.minor = 2,
2026 		.rev = 0,
2027 		.funcs = &gfx_v7_0_ip_funcs,
2028 	},
2029 	{
2030 		.type = AMD_IP_BLOCK_TYPE_SDMA,
2031 		.major = 2,
2032 		.minor = 0,
2033 		.rev = 0,
2034 		.funcs = &cik_sdma_ip_funcs,
2035 	},
2036 	{
2037 		.type = AMD_IP_BLOCK_TYPE_UVD,
2038 		.major = 4,
2039 		.minor = 2,
2040 		.rev = 0,
2041 		.funcs = &uvd_v4_2_ip_funcs,
2042 	},
2043 	{
2044 		.type = AMD_IP_BLOCK_TYPE_VCE,
2045 		.major = 2,
2046 		.minor = 0,
2047 		.rev = 0,
2048 		.funcs = &vce_v2_0_ip_funcs,
2049 	},
2050 };
2051 
2052 static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
2053 {
2054 	/* ORDER MATTERS! */
2055 	{
2056 		.type = AMD_IP_BLOCK_TYPE_COMMON,
2057 		.major = 1,
2058 		.minor = 0,
2059 		.rev = 0,
2060 		.funcs = &cik_common_ip_funcs,
2061 	},
2062 	{
2063 		.type = AMD_IP_BLOCK_TYPE_GMC,
2064 		.major = 7,
2065 		.minor = 0,
2066 		.rev = 0,
2067 		.funcs = &gmc_v7_0_ip_funcs,
2068 	},
2069 	{
2070 		.type = AMD_IP_BLOCK_TYPE_IH,
2071 		.major = 2,
2072 		.minor = 0,
2073 		.rev = 0,
2074 		.funcs = &cik_ih_ip_funcs,
2075 	},
2076 	{
2077 		.type = AMD_IP_BLOCK_TYPE_SMC,
2078 		.major = 7,
2079 		.minor = 0,
2080 		.rev = 0,
2081 		.funcs = &amdgpu_pp_ip_funcs,
2082 	},
2083 	{
2084 		.type = AMD_IP_BLOCK_TYPE_DCE,
2085 		.major = 8,
2086 		.minor = 3,
2087 		.rev = 0,
2088 		.funcs = &dce_v8_0_ip_funcs,
2089 	},
2090 	{
2091 		.type = AMD_IP_BLOCK_TYPE_GFX,
2092 		.major = 7,
2093 		.minor = 2,
2094 		.rev = 0,
2095 		.funcs = &gfx_v7_0_ip_funcs,
2096 	},
2097 	{
2098 		.type = AMD_IP_BLOCK_TYPE_SDMA,
2099 		.major = 2,
2100 		.minor = 0,
2101 		.rev = 0,
2102 		.funcs = &cik_sdma_ip_funcs,
2103 	},
2104 	{
2105 		.type = AMD_IP_BLOCK_TYPE_UVD,
2106 		.major = 4,
2107 		.minor = 2,
2108 		.rev = 0,
2109 		.funcs = &uvd_v4_2_ip_funcs,
2110 	},
2111 	{
2112 		.type = AMD_IP_BLOCK_TYPE_VCE,
2113 		.major = 2,
2114 		.minor = 0,
2115 		.rev = 0,
2116 		.funcs = &vce_v2_0_ip_funcs,
2117 	},
2118 };
2119 
2120 static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] =
2121 {
2122 	/* ORDER MATTERS! */
2123 	{
2124 		.type = AMD_IP_BLOCK_TYPE_COMMON,
2125 		.major = 1,
2126 		.minor = 0,
2127 		.rev = 0,
2128 		.funcs = &cik_common_ip_funcs,
2129 	},
2130 	{
2131 		.type = AMD_IP_BLOCK_TYPE_GMC,
2132 		.major = 7,
2133 		.minor = 0,
2134 		.rev = 0,
2135 		.funcs = &gmc_v7_0_ip_funcs,
2136 	},
2137 	{
2138 		.type = AMD_IP_BLOCK_TYPE_IH,
2139 		.major = 2,
2140 		.minor = 0,
2141 		.rev = 0,
2142 		.funcs = &cik_ih_ip_funcs,
2143 	},
2144 	{
2145 		.type = AMD_IP_BLOCK_TYPE_SMC,
2146 		.major = 7,
2147 		.minor = 0,
2148 		.rev = 0,
2149 		.funcs = &amdgpu_pp_ip_funcs,
2150 	},
2151 	{
2152 		.type = AMD_IP_BLOCK_TYPE_DCE,
2153 		.major = 8,
2154 		.minor = 3,
2155 		.rev = 0,
2156 		.funcs = &dce_virtual_ip_funcs,
2157 	},
2158 	{
2159 		.type = AMD_IP_BLOCK_TYPE_GFX,
2160 		.major = 7,
2161 		.minor = 2,
2162 		.rev = 0,
2163 		.funcs = &gfx_v7_0_ip_funcs,
2164 	},
2165 	{
2166 		.type = AMD_IP_BLOCK_TYPE_SDMA,
2167 		.major = 2,
2168 		.minor = 0,
2169 		.rev = 0,
2170 		.funcs = &cik_sdma_ip_funcs,
2171 	},
2172 	{
2173 		.type = AMD_IP_BLOCK_TYPE_UVD,
2174 		.major = 4,
2175 		.minor = 2,
2176 		.rev = 0,
2177 		.funcs = &uvd_v4_2_ip_funcs,
2178 	},
2179 	{
2180 		.type = AMD_IP_BLOCK_TYPE_VCE,
2181 		.major = 2,
2182 		.minor = 0,
2183 		.rev = 0,
2184 		.funcs = &vce_v2_0_ip_funcs,
2185 	},
2186 };
2187 
2188 static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
2189 {
2190 	/* ORDER MATTERS! */
2191 	{
2192 		.type = AMD_IP_BLOCK_TYPE_COMMON,
2193 		.major = 1,
2194 		.minor = 0,
2195 		.rev = 0,
2196 		.funcs = &cik_common_ip_funcs,
2197 	},
2198 	{
2199 		.type = AMD_IP_BLOCK_TYPE_GMC,
2200 		.major = 7,
2201 		.minor = 0,
2202 		.rev = 0,
2203 		.funcs = &gmc_v7_0_ip_funcs,
2204 	},
2205 	{
2206 		.type = AMD_IP_BLOCK_TYPE_IH,
2207 		.major = 2,
2208 		.minor = 0,
2209 		.rev = 0,
2210 		.funcs = &cik_ih_ip_funcs,
2211 	},
2212 	{
2213 		.type = AMD_IP_BLOCK_TYPE_SMC,
2214 		.major = 7,
2215 		.minor = 0,
2216 		.rev = 0,
2217 		.funcs = &amdgpu_pp_ip_funcs,
2218 	},
2219 	{
2220 		.type = AMD_IP_BLOCK_TYPE_DCE,
2221 		.major = 8,
2222 		.minor = 1,
2223 		.rev = 0,
2224 		.funcs = &dce_v8_0_ip_funcs,
2225 	},
2226 	{
2227 		.type = AMD_IP_BLOCK_TYPE_GFX,
2228 		.major = 7,
2229 		.minor = 1,
2230 		.rev = 0,
2231 		.funcs = &gfx_v7_0_ip_funcs,
2232 	},
2233 	{
2234 		.type = AMD_IP_BLOCK_TYPE_SDMA,
2235 		.major = 2,
2236 		.minor = 0,
2237 		.rev = 0,
2238 		.funcs = &cik_sdma_ip_funcs,
2239 	},
2240 	{
2241 		.type = AMD_IP_BLOCK_TYPE_UVD,
2242 		.major = 4,
2243 		.minor = 2,
2244 		.rev = 0,
2245 		.funcs = &uvd_v4_2_ip_funcs,
2246 	},
2247 	{
2248 		.type = AMD_IP_BLOCK_TYPE_VCE,
2249 		.major = 2,
2250 		.minor = 0,
2251 		.rev = 0,
2252 		.funcs = &vce_v2_0_ip_funcs,
2253 	},
2254 };
2255 
2256 static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
2257 {
2258 	/* ORDER MATTERS! */
2259 	{
2260 		.type = AMD_IP_BLOCK_TYPE_COMMON,
2261 		.major = 1,
2262 		.minor = 0,
2263 		.rev = 0,
2264 		.funcs = &cik_common_ip_funcs,
2265 	},
2266 	{
2267 		.type = AMD_IP_BLOCK_TYPE_GMC,
2268 		.major = 7,
2269 		.minor = 0,
2270 		.rev = 0,
2271 		.funcs = &gmc_v7_0_ip_funcs,
2272 	},
2273 	{
2274 		.type = AMD_IP_BLOCK_TYPE_IH,
2275 		.major = 2,
2276 		.minor = 0,
2277 		.rev = 0,
2278 		.funcs = &cik_ih_ip_funcs,
2279 	},
2280 	{
2281 		.type = AMD_IP_BLOCK_TYPE_SMC,
2282 		.major = 7,
2283 		.minor = 0,
2284 		.rev = 0,
2285 		.funcs = &amdgpu_pp_ip_funcs,
2286 	},
2287 	{
2288 		.type = AMD_IP_BLOCK_TYPE_DCE,
2289 		.major = 8,
2290 		.minor = 1,
2291 		.rev = 0,
2292 		.funcs = &dce_virtual_ip_funcs,
2293 	},
2294 	{
2295 		.type = AMD_IP_BLOCK_TYPE_GFX,
2296 		.major = 7,
2297 		.minor = 1,
2298 		.rev = 0,
2299 		.funcs = &gfx_v7_0_ip_funcs,
2300 	},
2301 	{
2302 		.type = AMD_IP_BLOCK_TYPE_SDMA,
2303 		.major = 2,
2304 		.minor = 0,
2305 		.rev = 0,
2306 		.funcs = &cik_sdma_ip_funcs,
2307 	},
2308 	{
2309 		.type = AMD_IP_BLOCK_TYPE_UVD,
2310 		.major = 4,
2311 		.minor = 2,
2312 		.rev = 0,
2313 		.funcs = &uvd_v4_2_ip_funcs,
2314 	},
2315 	{
2316 		.type = AMD_IP_BLOCK_TYPE_VCE,
2317 		.major = 2,
2318 		.minor = 0,
2319 		.rev = 0,
2320 		.funcs = &vce_v2_0_ip_funcs,
2321 	},
2322 };
2323 
2324 int cik_set_ip_blocks(struct amdgpu_device *adev)
2325 {
2326 	if (adev->enable_virtual_display) {
2327 		switch (adev->asic_type) {
2328 		case CHIP_BONAIRE:
2329 			adev->ip_blocks = bonaire_ip_blocks_vd;
2330 			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
2331 			break;
2332 		case CHIP_HAWAII:
2333 			adev->ip_blocks = hawaii_ip_blocks_vd;
2334 			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
2335 			break;
2336 		case CHIP_KAVERI:
2337 			adev->ip_blocks = kaveri_ip_blocks_vd;
2338 			adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
2339 			break;
2340 		case CHIP_KABINI:
2341 			adev->ip_blocks = kabini_ip_blocks_vd;
2342 			adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
2343 			break;
2344 		case CHIP_MULLINS:
2345 			adev->ip_blocks = mullins_ip_blocks_vd;
2346 			adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
2347 			break;
2348 		default:
2349 			/* FIXME: not supported yet */
2350 			return -EINVAL;
2351 		}
2352 	} else {
2353 		switch (adev->asic_type) {
2354 		case CHIP_BONAIRE:
2355 			adev->ip_blocks = bonaire_ip_blocks;
2356 			adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
2357 			break;
2358 		case CHIP_HAWAII:
2359 			adev->ip_blocks = hawaii_ip_blocks;
2360 			adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
2361 			break;
2362 		case CHIP_KAVERI:
2363 			adev->ip_blocks = kaveri_ip_blocks;
2364 			adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
2365 			break;
2366 		case CHIP_KABINI:
2367 			adev->ip_blocks = kabini_ip_blocks;
2368 			adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
2369 			break;
2370 		case CHIP_MULLINS:
2371 			adev->ip_blocks = mullins_ip_blocks;
2372 			adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
2373 			break;
2374 		default:
2375 			/* FIXME: not supported yet */
2376 			return -EINVAL;
2377 		}
2378 	}
2379 
2380 	return 0;
2381 }
2382 
2383 static const struct amdgpu_asic_funcs cik_asic_funcs =
2384 {
2385 	.read_disabled_bios = &cik_read_disabled_bios,
2386 	.read_bios_from_rom = &cik_read_bios_from_rom,
2387 	.detect_hw_virtualization = cik_detect_hw_virtualization,
2388 	.read_register = &cik_read_register,
2389 	.reset = &cik_asic_reset,
2390 	.set_vga_state = &cik_vga_set_state,
2391 	.get_xclk = &cik_get_xclk,
2392 	.set_uvd_clocks = &cik_set_uvd_clocks,
2393 	.set_vce_clocks = &cik_set_vce_clocks,
2394 };
2395 
2396 static int cik_common_early_init(void *handle)
2397 {
2398 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2399 
2400 	adev->smc_rreg = &cik_smc_rreg;
2401 	adev->smc_wreg = &cik_smc_wreg;
2402 	adev->pcie_rreg = &cik_pcie_rreg;
2403 	adev->pcie_wreg = &cik_pcie_wreg;
2404 	adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;
2405 	adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;
2406 	adev->didt_rreg = &cik_didt_rreg;
2407 	adev->didt_wreg = &cik_didt_wreg;
2408 
2409 	adev->asic_funcs = &cik_asic_funcs;
2410 
2411 	adev->rev_id = cik_get_rev_id(adev);
2412 	adev->external_rev_id = 0xFF;
2413 	switch (adev->asic_type) {
2414 	case CHIP_BONAIRE:
2415 		adev->cg_flags =
2416 			AMD_CG_SUPPORT_GFX_MGCG |
2417 			AMD_CG_SUPPORT_GFX_MGLS |
2418 			/*AMD_CG_SUPPORT_GFX_CGCG |*/
2419 			AMD_CG_SUPPORT_GFX_CGLS |
2420 			AMD_CG_SUPPORT_GFX_CGTS |
2421 			AMD_CG_SUPPORT_GFX_CGTS_LS |
2422 			AMD_CG_SUPPORT_GFX_CP_LS |
2423 			AMD_CG_SUPPORT_MC_LS |
2424 			AMD_CG_SUPPORT_MC_MGCG |
2425 			AMD_CG_SUPPORT_SDMA_MGCG |
2426 			AMD_CG_SUPPORT_SDMA_LS |
2427 			AMD_CG_SUPPORT_BIF_LS |
2428 			AMD_CG_SUPPORT_VCE_MGCG |
2429 			AMD_CG_SUPPORT_UVD_MGCG |
2430 			AMD_CG_SUPPORT_HDP_LS |
2431 			AMD_CG_SUPPORT_HDP_MGCG;
2432 		adev->pg_flags = 0;
2433 		adev->external_rev_id = adev->rev_id + 0x14;
2434 		break;
2435 	case CHIP_HAWAII:
2436 		adev->cg_flags =
2437 			AMD_CG_SUPPORT_GFX_MGCG |
2438 			AMD_CG_SUPPORT_GFX_MGLS |
2439 			/*AMD_CG_SUPPORT_GFX_CGCG |*/
2440 			AMD_CG_SUPPORT_GFX_CGLS |
2441 			AMD_CG_SUPPORT_GFX_CGTS |
2442 			AMD_CG_SUPPORT_GFX_CP_LS |
2443 			AMD_CG_SUPPORT_MC_LS |
2444 			AMD_CG_SUPPORT_MC_MGCG |
2445 			AMD_CG_SUPPORT_SDMA_MGCG |
2446 			AMD_CG_SUPPORT_SDMA_LS |
2447 			AMD_CG_SUPPORT_BIF_LS |
2448 			AMD_CG_SUPPORT_VCE_MGCG |
2449 			AMD_CG_SUPPORT_UVD_MGCG |
2450 			AMD_CG_SUPPORT_HDP_LS |
2451 			AMD_CG_SUPPORT_HDP_MGCG;
2452 		adev->pg_flags = 0;
2453 		adev->external_rev_id = 0x28;
2454 		break;
2455 	case CHIP_KAVERI:
2456 		adev->cg_flags =
2457 			AMD_CG_SUPPORT_GFX_MGCG |
2458 			AMD_CG_SUPPORT_GFX_MGLS |
2459 			/*AMD_CG_SUPPORT_GFX_CGCG |*/
2460 			AMD_CG_SUPPORT_GFX_CGLS |
2461 			AMD_CG_SUPPORT_GFX_CGTS |
2462 			AMD_CG_SUPPORT_GFX_CGTS_LS |
2463 			AMD_CG_SUPPORT_GFX_CP_LS |
2464 			AMD_CG_SUPPORT_SDMA_MGCG |
2465 			AMD_CG_SUPPORT_SDMA_LS |
2466 			AMD_CG_SUPPORT_BIF_LS |
2467 			AMD_CG_SUPPORT_VCE_MGCG |
2468 			AMD_CG_SUPPORT_UVD_MGCG |
2469 			AMD_CG_SUPPORT_HDP_LS |
2470 			AMD_CG_SUPPORT_HDP_MGCG;
2471 		adev->pg_flags =
2472 			/*AMD_PG_SUPPORT_GFX_PG |
2473 			  AMD_PG_SUPPORT_GFX_SMG |
2474 			  AMD_PG_SUPPORT_GFX_DMG |*/
2475 			AMD_PG_SUPPORT_UVD |
2476 			/*AMD_PG_SUPPORT_VCE |
2477 			  AMD_PG_SUPPORT_CP |
2478 			  AMD_PG_SUPPORT_GDS |
2479 			  AMD_PG_SUPPORT_RLC_SMU_HS |
2480 			  AMD_PG_SUPPORT_ACP |
2481 			  AMD_PG_SUPPORT_SAMU |*/
2482 			0;
2483 		if (adev->pdev->device == 0x1312 ||
2484 			adev->pdev->device == 0x1316 ||
2485 			adev->pdev->device == 0x1317)
2486 			adev->external_rev_id = 0x41;
2487 		else
2488 			adev->external_rev_id = 0x1;
2489 		break;
2490 	case CHIP_KABINI:
2491 	case CHIP_MULLINS:
2492 		adev->cg_flags =
2493 			AMD_CG_SUPPORT_GFX_MGCG |
2494 			AMD_CG_SUPPORT_GFX_MGLS |
2495 			/*AMD_CG_SUPPORT_GFX_CGCG |*/
2496 			AMD_CG_SUPPORT_GFX_CGLS |
2497 			AMD_CG_SUPPORT_GFX_CGTS |
2498 			AMD_CG_SUPPORT_GFX_CGTS_LS |
2499 			AMD_CG_SUPPORT_GFX_CP_LS |
2500 			AMD_CG_SUPPORT_SDMA_MGCG |
2501 			AMD_CG_SUPPORT_SDMA_LS |
2502 			AMD_CG_SUPPORT_BIF_LS |
2503 			AMD_CG_SUPPORT_VCE_MGCG |
2504 			AMD_CG_SUPPORT_UVD_MGCG |
2505 			AMD_CG_SUPPORT_HDP_LS |
2506 			AMD_CG_SUPPORT_HDP_MGCG;
2507 		adev->pg_flags =
2508 			/*AMD_PG_SUPPORT_GFX_PG |
2509 			  AMD_PG_SUPPORT_GFX_SMG | */
2510 			AMD_PG_SUPPORT_UVD |
2511 			/*AMD_PG_SUPPORT_VCE |
2512 			  AMD_PG_SUPPORT_CP |
2513 			  AMD_PG_SUPPORT_GDS |
2514 			  AMD_PG_SUPPORT_RLC_SMU_HS |
2515 			  AMD_PG_SUPPORT_SAMU |*/
2516 			0;
2517 		if (adev->asic_type == CHIP_KABINI) {
2518 			if (adev->rev_id == 0)
2519 				adev->external_rev_id = 0x81;
2520 			else if (adev->rev_id == 1)
2521 				adev->external_rev_id = 0x82;
2522 			else if (adev->rev_id == 2)
2523 				adev->external_rev_id = 0x85;
2524 		} else
2525 			adev->external_rev_id = adev->rev_id + 0xa1;
2526 		break;
2527 	default:
2528 		/* FIXME: not supported yet */
2529 		return -EINVAL;
2530 	}
2531 
2532 	amdgpu_get_pcie_info(adev);
2533 
2534 	return 0;
2535 }
2536 
2537 static int cik_common_sw_init(void *handle)
2538 {
2539 	return 0;
2540 }
2541 
2542 static int cik_common_sw_fini(void *handle)
2543 {
2544 	return 0;
2545 }
2546 
2547 static int cik_common_hw_init(void *handle)
2548 {
2549 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2550 
2551 	/* move the golden regs per IP block */
2552 	cik_init_golden_registers(adev);
2553 	/* enable pcie gen2/3 link */
2554 	cik_pcie_gen3_enable(adev);
2555 	/* enable aspm */
2556 	cik_program_aspm(adev);
2557 
2558 	return 0;
2559 }
2560 
2561 static int cik_common_hw_fini(void *handle)
2562 {
2563 	return 0;
2564 }
2565 
2566 static int cik_common_suspend(void *handle)
2567 {
2568 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2569 
2570 	amdgpu_amdkfd_suspend(adev);
2571 
2572 	return cik_common_hw_fini(adev);
2573 }
2574 
2575 static int cik_common_resume(void *handle)
2576 {
2577 	int r;
2578 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2579 
2580 	r = cik_common_hw_init(adev);
2581 	if (r)
2582 		return r;
2583 
2584 	return amdgpu_amdkfd_resume(adev);
2585 }
2586 
2587 static bool cik_common_is_idle(void *handle)
2588 {
2589 	return true;
2590 }
2591 
2592 static int cik_common_wait_for_idle(void *handle)
2593 {
2594 	return 0;
2595 }
2596 
2597 static int cik_common_soft_reset(void *handle)
2598 {
2599 	/* XXX hard reset?? */
2600 	return 0;
2601 }
2602 
2603 static int cik_common_set_clockgating_state(void *handle,
2604 					    enum amd_clockgating_state state)
2605 {
2606 	return 0;
2607 }
2608 
2609 static int cik_common_set_powergating_state(void *handle,
2610 					    enum amd_powergating_state state)
2611 {
2612 	return 0;
2613 }
2614 
2615 const struct amd_ip_funcs cik_common_ip_funcs = {
2616 	.name = "cik_common",
2617 	.early_init = cik_common_early_init,
2618 	.late_init = NULL,
2619 	.sw_init = cik_common_sw_init,
2620 	.sw_fini = cik_common_sw_fini,
2621 	.hw_init = cik_common_hw_init,
2622 	.hw_fini = cik_common_hw_fini,
2623 	.suspend = cik_common_suspend,
2624 	.resume = cik_common_resume,
2625 	.is_idle = cik_common_is_idle,
2626 	.wait_for_idle = cik_common_wait_for_idle,
2627 	.soft_reset = cik_common_soft_reset,
2628 	.set_clockgating_state = cik_common_set_clockgating_state,
2629 	.set_powergating_state = cik_common_set_powergating_state,
2630 };
2631