1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #include <drm/drmP.h> 28 #include <drm/amdgpu_drm.h> 29 #include "amdgpu.h" 30 31 #include "atom.h" 32 #include "atom-bits.h" 33 #include "atombios_encoders.h" 34 #include "atombios_dp.h" 35 #include "amdgpu_connectors.h" 36 #include "amdgpu_atombios.h" 37 #include <drm/drm_dp_helper.h> 38 39 /* move these to drm_dp_helper.c/h */ 40 #define DP_LINK_CONFIGURATION_SIZE 9 41 #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE 42 43 static char *voltage_names[] = { 44 "0.4V", "0.6V", "0.8V", "1.2V" 45 }; 46 static char *pre_emph_names[] = { 47 "0dB", "3.5dB", "6dB", "9.5dB" 48 }; 49 50 /***** amdgpu AUX functions *****/ 51 52 union aux_channel_transaction { 53 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; 54 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; 55 }; 56 57 static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan, 58 u8 *send, int send_bytes, 59 u8 *recv, int recv_size, 60 u8 delay, u8 *ack) 61 { 62 struct drm_device *dev = chan->dev; 63 struct amdgpu_device *adev = dev->dev_private; 64 union aux_channel_transaction args; 65 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); 66 unsigned char *base; 67 int recv_bytes; 68 int r = 0; 69 70 memset(&args, 0, sizeof(args)); 71 72 mutex_lock(&chan->mutex); 73 74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1); 75 76 amdgpu_atombios_copy_swap(base, send, send_bytes, true); 77 78 args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); 79 args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4)); 80 args.v2.ucDataOutLen = 0; 81 args.v2.ucChannelID = chan->rec.i2c_id; 82 args.v2.ucDelay = delay / 10; 83 args.v2.ucHPD_ID = chan->rec.hpd; 84 85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 86 87 *ack = args.v2.ucReplyStatus; 88 89 /* timeout */ 90 if (args.v2.ucReplyStatus == 1) { 91 DRM_DEBUG_KMS("dp_aux_ch timeout\n"); 92 r = -ETIMEDOUT; 93 goto done; 94 } 95 96 /* flags not zero */ 97 if (args.v2.ucReplyStatus == 2) { 98 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); 99 r = -EIO; 100 goto done; 101 } 102 103 /* error */ 104 if (args.v2.ucReplyStatus == 3) { 105 DRM_DEBUG_KMS("dp_aux_ch error\n"); 106 r = -EIO; 107 goto done; 108 } 109 110 recv_bytes = args.v1.ucDataOutLen; 111 if (recv_bytes > recv_size) 112 recv_bytes = recv_size; 113 114 if (recv && recv_size) 115 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false); 116 117 r = recv_bytes; 118 done: 119 mutex_unlock(&chan->mutex); 120 121 return r; 122 } 123 124 #define BARE_ADDRESS_SIZE 3 125 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 126 127 static ssize_t 128 amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 129 { 130 struct amdgpu_i2c_chan *chan = 131 container_of(aux, struct amdgpu_i2c_chan, aux); 132 int ret; 133 u8 tx_buf[20]; 134 size_t tx_size; 135 u8 ack, delay = 0; 136 137 if (WARN_ON(msg->size > 16)) 138 return -E2BIG; 139 140 tx_buf[0] = msg->address & 0xff; 141 tx_buf[1] = msg->address >> 8; 142 tx_buf[2] = (msg->request << 4) | 143 ((msg->address >> 16) & 0xf); 144 tx_buf[3] = msg->size ? (msg->size - 1) : 0; 145 146 switch (msg->request & ~DP_AUX_I2C_MOT) { 147 case DP_AUX_NATIVE_WRITE: 148 case DP_AUX_I2C_WRITE: 149 /* tx_size needs to be 4 even for bare address packets since the atom 150 * table needs the info in tx_buf[3]. 151 */ 152 tx_size = HEADER_SIZE + msg->size; 153 if (msg->size == 0) 154 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 155 else 156 tx_buf[3] |= tx_size << 4; 157 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size); 158 ret = amdgpu_atombios_dp_process_aux_ch(chan, 159 tx_buf, tx_size, NULL, 0, delay, &ack); 160 if (ret >= 0) 161 /* Return payload size. */ 162 ret = msg->size; 163 break; 164 case DP_AUX_NATIVE_READ: 165 case DP_AUX_I2C_READ: 166 /* tx_size needs to be 4 even for bare address packets since the atom 167 * table needs the info in tx_buf[3]. 168 */ 169 tx_size = HEADER_SIZE; 170 if (msg->size == 0) 171 tx_buf[3] |= BARE_ADDRESS_SIZE << 4; 172 else 173 tx_buf[3] |= tx_size << 4; 174 ret = amdgpu_atombios_dp_process_aux_ch(chan, 175 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack); 176 break; 177 default: 178 ret = -EINVAL; 179 break; 180 } 181 182 if (ret >= 0) 183 msg->reply = ack >> 4; 184 185 return ret; 186 } 187 188 void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) 189 { 190 int ret; 191 192 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; 193 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev; 194 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; 195 ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux); 196 if (!ret) 197 amdgpu_connector->ddc_bus->has_aux = true; 198 199 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret); 200 } 201 202 /***** general DP utility functions *****/ 203 204 #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3 205 #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3 206 207 static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE], 208 int lane_count, 209 u8 train_set[4]) 210 { 211 u8 v = 0; 212 u8 p = 0; 213 int lane; 214 215 for (lane = 0; lane < lane_count; lane++) { 216 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); 217 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 218 219 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", 220 lane, 221 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 222 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 223 224 if (this_v > v) 225 v = this_v; 226 if (this_p > p) 227 p = this_p; 228 } 229 230 if (v >= DP_VOLTAGE_MAX) 231 v |= DP_TRAIN_MAX_SWING_REACHED; 232 233 if (p >= DP_PRE_EMPHASIS_MAX) 234 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 235 236 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", 237 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], 238 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); 239 240 for (lane = 0; lane < 4; lane++) 241 train_set[lane] = v | p; 242 } 243 244 /* convert bits per color to bits per pixel */ 245 /* get bpc from the EDID */ 246 static unsigned amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc) 247 { 248 if (bpc == 0) 249 return 24; 250 else 251 return bpc * 3; 252 } 253 254 /***** amdgpu specific DP functions *****/ 255 256 static int amdgpu_atombios_dp_get_dp_link_config(struct drm_connector *connector, 257 const u8 dpcd[DP_DPCD_SIZE], 258 unsigned pix_clock, 259 unsigned *dp_lanes, unsigned *dp_rate) 260 { 261 unsigned bpp = 262 amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); 263 static const unsigned link_rates[3] = { 162000, 270000, 540000 }; 264 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); 265 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); 266 unsigned lane_num, i, max_pix_clock; 267 268 for (lane_num = 1; lane_num <= max_lane_num; lane_num <<= 1) { 269 for (i = 0; i < ARRAY_SIZE(link_rates) && link_rates[i] <= max_link_rate; i++) { 270 max_pix_clock = (lane_num * link_rates[i] * 8) / bpp; 271 if (max_pix_clock >= pix_clock) { 272 *dp_lanes = lane_num; 273 *dp_rate = link_rates[i]; 274 return 0; 275 } 276 } 277 } 278 279 return -EINVAL; 280 } 281 282 static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev, 283 int action, int dp_clock, 284 u8 ucconfig, u8 lane_num) 285 { 286 DP_ENCODER_SERVICE_PARAMETERS args; 287 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); 288 289 memset(&args, 0, sizeof(args)); 290 args.ucLinkClock = dp_clock / 10; 291 args.ucConfig = ucconfig; 292 args.ucAction = action; 293 args.ucLaneNum = lane_num; 294 args.ucStatus = 0; 295 296 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 297 return args.ucStatus; 298 } 299 300 u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector) 301 { 302 struct drm_device *dev = amdgpu_connector->base.dev; 303 struct amdgpu_device *adev = dev->dev_private; 304 305 return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, 306 amdgpu_connector->ddc_bus->rec.i2c_id, 0); 307 } 308 309 static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector) 310 { 311 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; 312 u8 buf[3]; 313 314 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) 315 return; 316 317 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3) 318 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", 319 buf[0], buf[1], buf[2]); 320 321 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3) 322 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", 323 buf[0], buf[1], buf[2]); 324 } 325 326 int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector) 327 { 328 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv; 329 u8 msg[DP_DPCD_SIZE]; 330 int ret, i; 331 332 for (i = 0; i < 7; i++) { 333 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg, 334 DP_DPCD_SIZE); 335 if (ret == DP_DPCD_SIZE) { 336 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); 337 338 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), 339 dig_connector->dpcd); 340 341 amdgpu_atombios_dp_probe_oui(amdgpu_connector); 342 343 return 0; 344 } 345 } 346 dig_connector->dpcd[0] = 0; 347 return -EINVAL; 348 } 349 350 int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder, 351 struct drm_connector *connector) 352 { 353 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 354 struct amdgpu_connector_atom_dig *dig_connector; 355 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 356 u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector); 357 u8 tmp; 358 359 if (!amdgpu_connector->con_priv) 360 return panel_mode; 361 362 dig_connector = amdgpu_connector->con_priv; 363 364 if (dp_bridge != ENCODER_OBJECT_ID_NONE) { 365 /* DP bridge chips */ 366 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, 367 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 368 if (tmp & 1) 369 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 370 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || 371 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) 372 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; 373 else 374 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; 375 } 376 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { 377 /* eDP */ 378 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, 379 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) { 380 if (tmp & 1) 381 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; 382 } 383 } 384 385 return panel_mode; 386 } 387 388 void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector, 389 const struct drm_display_mode *mode) 390 { 391 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 392 struct amdgpu_connector_atom_dig *dig_connector; 393 int ret; 394 395 if (!amdgpu_connector->con_priv) 396 return; 397 dig_connector = amdgpu_connector->con_priv; 398 399 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 400 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 401 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, 402 mode->clock, 403 &dig_connector->dp_lane_count, 404 &dig_connector->dp_clock); 405 if (ret) { 406 dig_connector->dp_clock = 0; 407 dig_connector->dp_lane_count = 0; 408 } 409 } 410 } 411 412 int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector, 413 struct drm_display_mode *mode) 414 { 415 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 416 struct amdgpu_connector_atom_dig *dig_connector; 417 unsigned dp_lanes, dp_clock; 418 int ret; 419 420 if (!amdgpu_connector->con_priv) 421 return MODE_CLOCK_HIGH; 422 dig_connector = amdgpu_connector->con_priv; 423 424 ret = amdgpu_atombios_dp_get_dp_link_config(connector, dig_connector->dpcd, 425 mode->clock, &dp_lanes, &dp_clock); 426 if (ret) 427 return MODE_CLOCK_HIGH; 428 429 if ((dp_clock == 540000) && 430 (!amdgpu_connector_is_dp12_capable(connector))) 431 return MODE_CLOCK_HIGH; 432 433 return MODE_OK; 434 } 435 436 bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector) 437 { 438 u8 link_status[DP_LINK_STATUS_SIZE]; 439 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv; 440 441 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status) 442 <= 0) 443 return false; 444 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) 445 return false; 446 return true; 447 } 448 449 void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector, 450 u8 power_state) 451 { 452 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); 453 struct amdgpu_connector_atom_dig *dig_connector; 454 455 if (!amdgpu_connector->con_priv) 456 return; 457 458 dig_connector = amdgpu_connector->con_priv; 459 460 /* power up/down the sink */ 461 if (dig_connector->dpcd[0] >= 0x11) { 462 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux, 463 DP_SET_POWER, power_state); 464 usleep_range(1000, 2000); 465 } 466 } 467 468 struct amdgpu_atombios_dp_link_train_info { 469 struct amdgpu_device *adev; 470 struct drm_encoder *encoder; 471 struct drm_connector *connector; 472 int dp_clock; 473 int dp_lane_count; 474 bool tp3_supported; 475 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 476 u8 train_set[4]; 477 u8 link_status[DP_LINK_STATUS_SIZE]; 478 u8 tries; 479 struct drm_dp_aux *aux; 480 }; 481 482 static void 483 amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info) 484 { 485 /* set the initial vs/emph on the source */ 486 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder, 487 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 488 0, dp_info->train_set[0]); /* sets all lanes at once */ 489 490 /* set the vs/emph on the sink */ 491 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET, 492 dp_info->train_set, dp_info->dp_lane_count); 493 } 494 495 static void 496 amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp) 497 { 498 int rtp = 0; 499 500 /* set training pattern on the source */ 501 switch (tp) { 502 case DP_TRAINING_PATTERN_1: 503 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; 504 break; 505 case DP_TRAINING_PATTERN_2: 506 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; 507 break; 508 case DP_TRAINING_PATTERN_3: 509 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; 510 break; 511 } 512 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0); 513 514 /* enable training pattern on the sink */ 515 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp); 516 } 517 518 static int 519 amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info) 520 { 521 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder); 522 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; 523 u8 tmp; 524 525 /* power up the sink */ 526 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); 527 528 /* possibly enable downspread on the sink */ 529 if (dp_info->dpcd[3] & 0x1) 530 drm_dp_dpcd_writeb(dp_info->aux, 531 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); 532 else 533 drm_dp_dpcd_writeb(dp_info->aux, 534 DP_DOWNSPREAD_CTRL, 0); 535 536 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE) 537 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1); 538 539 /* set the lane count on the sink */ 540 tmp = dp_info->dp_lane_count; 541 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) 542 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 543 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp); 544 545 /* set the link rate on the sink */ 546 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); 547 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp); 548 549 /* start training on the source */ 550 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, 551 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); 552 553 /* disable the training pattern on the sink */ 554 drm_dp_dpcd_writeb(dp_info->aux, 555 DP_TRAINING_PATTERN_SET, 556 DP_TRAINING_PATTERN_DISABLE); 557 558 return 0; 559 } 560 561 static int 562 amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info) 563 { 564 udelay(400); 565 566 /* disable the training pattern on the sink */ 567 drm_dp_dpcd_writeb(dp_info->aux, 568 DP_TRAINING_PATTERN_SET, 569 DP_TRAINING_PATTERN_DISABLE); 570 571 /* disable the training pattern on the source */ 572 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, 573 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); 574 575 return 0; 576 } 577 578 static int 579 amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info) 580 { 581 bool clock_recovery; 582 u8 voltage; 583 int i; 584 585 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); 586 memset(dp_info->train_set, 0, 4); 587 amdgpu_atombios_dp_update_vs_emph(dp_info); 588 589 udelay(400); 590 591 /* clock recovery loop */ 592 clock_recovery = false; 593 dp_info->tries = 0; 594 voltage = 0xff; 595 while (1) { 596 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); 597 598 if (drm_dp_dpcd_read_link_status(dp_info->aux, 599 dp_info->link_status) <= 0) { 600 DRM_ERROR("displayport link status failed\n"); 601 break; 602 } 603 604 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { 605 clock_recovery = true; 606 break; 607 } 608 609 for (i = 0; i < dp_info->dp_lane_count; i++) { 610 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) 611 break; 612 } 613 if (i == dp_info->dp_lane_count) { 614 DRM_ERROR("clock recovery reached max voltage\n"); 615 break; 616 } 617 618 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { 619 ++dp_info->tries; 620 if (dp_info->tries == 5) { 621 DRM_ERROR("clock recovery tried 5 times\n"); 622 break; 623 } 624 } else 625 dp_info->tries = 0; 626 627 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 628 629 /* Compute new train_set as requested by sink */ 630 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, 631 dp_info->train_set); 632 633 amdgpu_atombios_dp_update_vs_emph(dp_info); 634 } 635 if (!clock_recovery) { 636 DRM_ERROR("clock recovery failed\n"); 637 return -1; 638 } else { 639 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", 640 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 641 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> 642 DP_TRAIN_PRE_EMPHASIS_SHIFT); 643 return 0; 644 } 645 } 646 647 static int 648 amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info) 649 { 650 bool channel_eq; 651 652 if (dp_info->tp3_supported) 653 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); 654 else 655 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); 656 657 /* channel equalization loop */ 658 dp_info->tries = 0; 659 channel_eq = false; 660 while (1) { 661 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); 662 663 if (drm_dp_dpcd_read_link_status(dp_info->aux, 664 dp_info->link_status) <= 0) { 665 DRM_ERROR("displayport link status failed\n"); 666 break; 667 } 668 669 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { 670 channel_eq = true; 671 break; 672 } 673 674 /* Try 5 times */ 675 if (dp_info->tries > 5) { 676 DRM_ERROR("channel eq failed: 5 tries\n"); 677 break; 678 } 679 680 /* Compute new train_set as requested by sink */ 681 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, 682 dp_info->train_set); 683 684 amdgpu_atombios_dp_update_vs_emph(dp_info); 685 dp_info->tries++; 686 } 687 688 if (!channel_eq) { 689 DRM_ERROR("channel eq failed\n"); 690 return -1; 691 } else { 692 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", 693 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, 694 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) 695 >> DP_TRAIN_PRE_EMPHASIS_SHIFT); 696 return 0; 697 } 698 } 699 700 void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder, 701 struct drm_connector *connector) 702 { 703 struct drm_device *dev = encoder->dev; 704 struct amdgpu_device *adev = dev->dev_private; 705 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); 706 struct amdgpu_encoder_atom_dig *dig; 707 struct amdgpu_connector *amdgpu_connector; 708 struct amdgpu_connector_atom_dig *dig_connector; 709 struct amdgpu_atombios_dp_link_train_info dp_info; 710 u8 tmp; 711 712 if (!amdgpu_encoder->enc_priv) 713 return; 714 dig = amdgpu_encoder->enc_priv; 715 716 amdgpu_connector = to_amdgpu_connector(connector); 717 if (!amdgpu_connector->con_priv) 718 return; 719 dig_connector = amdgpu_connector->con_priv; 720 721 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && 722 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) 723 return; 724 725 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp) 726 == 1) { 727 if (tmp & DP_TPS3_SUPPORTED) 728 dp_info.tp3_supported = true; 729 else 730 dp_info.tp3_supported = false; 731 } else { 732 dp_info.tp3_supported = false; 733 } 734 735 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); 736 dp_info.adev = adev; 737 dp_info.encoder = encoder; 738 dp_info.connector = connector; 739 dp_info.dp_lane_count = dig_connector->dp_lane_count; 740 dp_info.dp_clock = dig_connector->dp_clock; 741 dp_info.aux = &amdgpu_connector->ddc_bus->aux; 742 743 if (amdgpu_atombios_dp_link_train_init(&dp_info)) 744 goto done; 745 if (amdgpu_atombios_dp_link_train_cr(&dp_info)) 746 goto done; 747 if (amdgpu_atombios_dp_link_train_ce(&dp_info)) 748 goto done; 749 done: 750 if (amdgpu_atombios_dp_link_train_finish(&dp_info)) 751 return; 752 } 753