1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "wafl/wafl2_4_0_0_smn.h" 33 #include "wafl/wafl2_4_0_0_sh_mask.h" 34 35 #define smnPCS_XGMI23_PCS_ERROR_STATUS 0x11a01210 36 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 37 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 38 39 static DEFINE_MUTEX(xgmi_mutex); 40 41 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 42 43 static LIST_HEAD(xgmi_hive_list); 44 45 static const int xgmi_pcs_err_status_reg_vg20[] = { 46 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 47 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 48 }; 49 50 static const int wafl_pcs_err_status_reg_vg20[] = { 51 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 52 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 53 }; 54 55 static const int xgmi_pcs_err_status_reg_arct[] = { 56 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 57 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 58 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 59 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 62 }; 63 64 /* same as vg20*/ 65 static const int wafl_pcs_err_status_reg_arct[] = { 66 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 67 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 68 }; 69 70 static const int xgmi23_pcs_err_status_reg_aldebaran[] = { 71 smnPCS_XGMI23_PCS_ERROR_STATUS, 72 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x100000, 73 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x200000, 74 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x300000, 75 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x400000, 76 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x500000, 77 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x600000, 78 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x700000 79 }; 80 81 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 82 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 83 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 84 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 85 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 86 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 87 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 88 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 89 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 90 }; 91 92 static const int walf_pcs_err_status_reg_aldebaran[] = { 93 smnPCS_GOPX1_PCS_ERROR_STATUS, 94 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 95 }; 96 97 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 98 {"XGMI PCS DataLossErr", 99 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 100 {"XGMI PCS TrainingErr", 101 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 102 {"XGMI PCS CRCErr", 103 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 104 {"XGMI PCS BERExceededErr", 105 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 106 {"XGMI PCS TxMetaDataErr", 107 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 108 {"XGMI PCS ReplayBufParityErr", 109 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 110 {"XGMI PCS DataParityErr", 111 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 112 {"XGMI PCS ReplayFifoOverflowErr", 113 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 114 {"XGMI PCS ReplayFifoUnderflowErr", 115 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 116 {"XGMI PCS ElasticFifoOverflowErr", 117 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 118 {"XGMI PCS DeskewErr", 119 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 120 {"XGMI PCS DataStartupLimitErr", 121 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 122 {"XGMI PCS FCInitTimeoutErr", 123 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 124 {"XGMI PCS RecoveryTimeoutErr", 125 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 126 {"XGMI PCS ReadySerialTimeoutErr", 127 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 128 {"XGMI PCS ReadySerialAttemptErr", 129 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 130 {"XGMI PCS RecoveryAttemptErr", 131 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 132 {"XGMI PCS RecoveryRelockAttemptErr", 133 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 134 }; 135 136 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 137 {"WAFL PCS DataLossErr", 138 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 139 {"WAFL PCS TrainingErr", 140 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 141 {"WAFL PCS CRCErr", 142 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 143 {"WAFL PCS BERExceededErr", 144 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 145 {"WAFL PCS TxMetaDataErr", 146 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 147 {"WAFL PCS ReplayBufParityErr", 148 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 149 {"WAFL PCS DataParityErr", 150 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 151 {"WAFL PCS ReplayFifoOverflowErr", 152 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 153 {"WAFL PCS ReplayFifoUnderflowErr", 154 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 155 {"WAFL PCS ElasticFifoOverflowErr", 156 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 157 {"WAFL PCS DeskewErr", 158 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 159 {"WAFL PCS DataStartupLimitErr", 160 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 161 {"WAFL PCS FCInitTimeoutErr", 162 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 163 {"WAFL PCS RecoveryTimeoutErr", 164 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 165 {"WAFL PCS ReadySerialTimeoutErr", 166 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 167 {"WAFL PCS ReadySerialAttemptErr", 168 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 169 {"WAFL PCS RecoveryAttemptErr", 170 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 171 {"WAFL PCS RecoveryRelockAttemptErr", 172 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 173 }; 174 175 /** 176 * DOC: AMDGPU XGMI Support 177 * 178 * XGMI is a high speed interconnect that joins multiple GPU cards 179 * into a homogeneous memory space that is organized by a collective 180 * hive ID and individual node IDs, both of which are 64-bit numbers. 181 * 182 * The file xgmi_device_id contains the unique per GPU device ID and 183 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 184 * 185 * Inside the device directory a sub-directory 'xgmi_hive_info' is 186 * created which contains the hive ID and the list of nodes. 187 * 188 * The hive ID is stored in: 189 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 190 * 191 * The node information is stored in numbered directories: 192 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 193 * 194 * Each device has their own xgmi_hive_info direction with a mirror 195 * set of node sub-directories. 196 * 197 * The XGMI memory space is built by contiguously adding the power of 198 * two padded VRAM space from each node to each other. 199 * 200 */ 201 202 static struct attribute amdgpu_xgmi_hive_id = { 203 .name = "xgmi_hive_id", 204 .mode = S_IRUGO 205 }; 206 207 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 208 &amdgpu_xgmi_hive_id, 209 NULL 210 }; 211 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); 212 213 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 214 struct attribute *attr, char *buf) 215 { 216 struct amdgpu_hive_info *hive = container_of( 217 kobj, struct amdgpu_hive_info, kobj); 218 219 if (attr == &amdgpu_xgmi_hive_id) 220 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 221 222 return 0; 223 } 224 225 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 226 { 227 struct amdgpu_hive_info *hive = container_of( 228 kobj, struct amdgpu_hive_info, kobj); 229 230 mutex_destroy(&hive->hive_lock); 231 kfree(hive); 232 } 233 234 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 235 .show = amdgpu_xgmi_show_attrs, 236 }; 237 238 struct kobj_type amdgpu_xgmi_hive_type = { 239 .release = amdgpu_xgmi_hive_release, 240 .sysfs_ops = &amdgpu_xgmi_hive_ops, 241 .default_groups = amdgpu_xgmi_hive_groups, 242 }; 243 244 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 245 struct device_attribute *attr, 246 char *buf) 247 { 248 struct drm_device *ddev = dev_get_drvdata(dev); 249 struct amdgpu_device *adev = drm_to_adev(ddev); 250 251 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 252 253 } 254 255 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 256 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 257 struct device_attribute *attr, 258 char *buf) 259 { 260 struct drm_device *ddev = dev_get_drvdata(dev); 261 struct amdgpu_device *adev = drm_to_adev(ddev); 262 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 263 uint64_t fica_out; 264 unsigned int error_count = 0; 265 266 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 267 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 268 269 if ((!adev->df.funcs) || 270 (!adev->df.funcs->get_fica) || 271 (!adev->df.funcs->set_fica)) 272 return -EINVAL; 273 274 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 275 if (fica_out != 0x1f) 276 pr_err("xGMI error counters not enabled!\n"); 277 278 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 279 280 if ((fica_out & 0xffff) == 2) 281 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 282 283 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 284 285 return sysfs_emit(buf, "%u\n", error_count); 286 } 287 288 289 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 290 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 291 292 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 293 struct amdgpu_hive_info *hive) 294 { 295 int ret = 0; 296 char node[10] = { 0 }; 297 298 /* Create xgmi device id file */ 299 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 300 if (ret) { 301 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 302 return ret; 303 } 304 305 /* Create xgmi error file */ 306 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 307 if (ret) 308 pr_err("failed to create xgmi_error\n"); 309 310 311 /* Create sysfs link to hive info folder on the first device */ 312 if (hive->kobj.parent != (&adev->dev->kobj)) { 313 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 314 "xgmi_hive_info"); 315 if (ret) { 316 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 317 goto remove_file; 318 } 319 } 320 321 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 322 /* Create sysfs link form the hive folder to yourself */ 323 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 324 if (ret) { 325 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 326 goto remove_link; 327 } 328 329 goto success; 330 331 332 remove_link: 333 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 334 335 remove_file: 336 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 337 338 success: 339 return ret; 340 } 341 342 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 343 struct amdgpu_hive_info *hive) 344 { 345 char node[10]; 346 memset(node, 0, sizeof(node)); 347 348 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 349 device_remove_file(adev->dev, &dev_attr_xgmi_error); 350 351 if (hive->kobj.parent != (&adev->dev->kobj)) 352 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 353 354 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 355 sysfs_remove_link(&hive->kobj, node); 356 357 } 358 359 360 361 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 362 { 363 struct amdgpu_hive_info *hive = NULL; 364 int ret; 365 366 if (!adev->gmc.xgmi.hive_id) 367 return NULL; 368 369 if (adev->hive) { 370 kobject_get(&adev->hive->kobj); 371 return adev->hive; 372 } 373 374 mutex_lock(&xgmi_mutex); 375 376 list_for_each_entry(hive, &xgmi_hive_list, node) { 377 if (hive->hive_id == adev->gmc.xgmi.hive_id) 378 goto pro_end; 379 } 380 381 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 382 if (!hive) { 383 dev_err(adev->dev, "XGMI: allocation failed\n"); 384 hive = NULL; 385 goto pro_end; 386 } 387 388 /* initialize new hive if not exist */ 389 ret = kobject_init_and_add(&hive->kobj, 390 &amdgpu_xgmi_hive_type, 391 &adev->dev->kobj, 392 "%s", "xgmi_hive_info"); 393 if (ret) { 394 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 395 kobject_put(&hive->kobj); 396 kfree(hive); 397 hive = NULL; 398 goto pro_end; 399 } 400 401 hive->hive_id = adev->gmc.xgmi.hive_id; 402 INIT_LIST_HEAD(&hive->device_list); 403 INIT_LIST_HEAD(&hive->node); 404 mutex_init(&hive->hive_lock); 405 atomic_set(&hive->in_reset, 0); 406 atomic_set(&hive->number_devices, 0); 407 task_barrier_init(&hive->tb); 408 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 409 hive->hi_req_gpu = NULL; 410 /* 411 * hive pstate on boot is high in vega20 so we have to go to low 412 * pstate on after boot. 413 */ 414 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 415 list_add_tail(&hive->node, &xgmi_hive_list); 416 417 pro_end: 418 if (hive) 419 kobject_get(&hive->kobj); 420 mutex_unlock(&xgmi_mutex); 421 return hive; 422 } 423 424 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 425 { 426 if (hive) 427 kobject_put(&hive->kobj); 428 } 429 430 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 431 { 432 int ret = 0; 433 struct amdgpu_hive_info *hive; 434 struct amdgpu_device *request_adev; 435 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 436 bool init_low; 437 438 hive = amdgpu_get_xgmi_hive(adev); 439 if (!hive) 440 return 0; 441 442 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 443 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 444 amdgpu_put_xgmi_hive(hive); 445 /* fw bug so temporarily disable pstate switching */ 446 return 0; 447 448 if (!hive || adev->asic_type != CHIP_VEGA20) 449 return 0; 450 451 mutex_lock(&hive->hive_lock); 452 453 if (is_hi_req) 454 hive->hi_req_count++; 455 else 456 hive->hi_req_count--; 457 458 /* 459 * Vega20 only needs single peer to request pstate high for the hive to 460 * go high but all peers must request pstate low for the hive to go low 461 */ 462 if (hive->pstate == pstate || 463 (!is_hi_req && hive->hi_req_count && !init_low)) 464 goto out; 465 466 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 467 468 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 469 if (ret) { 470 dev_err(request_adev->dev, 471 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 472 request_adev->gmc.xgmi.node_id, 473 request_adev->gmc.xgmi.hive_id, ret); 474 goto out; 475 } 476 477 if (init_low) 478 hive->pstate = hive->hi_req_count ? 479 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 480 else { 481 hive->pstate = pstate; 482 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 483 adev : NULL; 484 } 485 out: 486 mutex_unlock(&hive->hive_lock); 487 return ret; 488 } 489 490 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 491 { 492 int ret; 493 494 /* Each psp need to set the latest topology */ 495 ret = psp_xgmi_set_topology_info(&adev->psp, 496 atomic_read(&hive->number_devices), 497 &adev->psp.xgmi_context.top_info); 498 if (ret) 499 dev_err(adev->dev, 500 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 501 adev->gmc.xgmi.node_id, 502 adev->gmc.xgmi.hive_id, ret); 503 504 return ret; 505 } 506 507 508 /* 509 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 510 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 511 * num_hops[5:3] = reserved 512 * num_hops[2:0] = number of hops 513 */ 514 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 515 struct amdgpu_device *peer_adev) 516 { 517 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 518 uint8_t num_hops_mask = 0x7; 519 int i; 520 521 for (i = 0 ; i < top->num_nodes; ++i) 522 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 523 return top->nodes[i].num_hops & num_hops_mask; 524 return -EINVAL; 525 } 526 527 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, 528 struct amdgpu_device *peer_adev) 529 { 530 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 531 int i; 532 533 for (i = 0 ; i < top->num_nodes; ++i) 534 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 535 return top->nodes[i].num_links; 536 return -EINVAL; 537 } 538 539 /* 540 * Devices that support extended data require the entire hive to initialize with 541 * the shared memory buffer flag set. 542 * 543 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 544 */ 545 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 546 bool set_extended_data) 547 { 548 struct amdgpu_device *tmp_adev; 549 int ret; 550 551 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 552 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 553 if (ret) { 554 dev_err(tmp_adev->dev, 555 "XGMI: Failed to initialize xgmi session for data partition %i\n", 556 set_extended_data); 557 return ret; 558 } 559 560 } 561 562 return 0; 563 } 564 565 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 566 { 567 struct psp_xgmi_topology_info *top_info; 568 struct amdgpu_hive_info *hive; 569 struct amdgpu_xgmi *entry; 570 struct amdgpu_device *tmp_adev = NULL; 571 572 int count = 0, ret = 0; 573 574 if (!adev->gmc.xgmi.supported) 575 return 0; 576 577 if (!adev->gmc.xgmi.pending_reset && 578 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 579 ret = psp_xgmi_initialize(&adev->psp, false, true); 580 if (ret) { 581 dev_err(adev->dev, 582 "XGMI: Failed to initialize xgmi session\n"); 583 return ret; 584 } 585 586 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 587 if (ret) { 588 dev_err(adev->dev, 589 "XGMI: Failed to get hive id\n"); 590 return ret; 591 } 592 593 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 594 if (ret) { 595 dev_err(adev->dev, 596 "XGMI: Failed to get node id\n"); 597 return ret; 598 } 599 } else { 600 adev->gmc.xgmi.hive_id = 16; 601 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 602 } 603 604 hive = amdgpu_get_xgmi_hive(adev); 605 if (!hive) { 606 ret = -EINVAL; 607 dev_err(adev->dev, 608 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 609 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 610 goto exit; 611 } 612 mutex_lock(&hive->hive_lock); 613 614 top_info = &adev->psp.xgmi_context.top_info; 615 616 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 617 list_for_each_entry(entry, &hive->device_list, head) 618 top_info->nodes[count++].node_id = entry->node_id; 619 top_info->num_nodes = count; 620 atomic_set(&hive->number_devices, count); 621 622 task_barrier_add_task(&hive->tb); 623 624 if (!adev->gmc.xgmi.pending_reset && 625 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 626 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 627 /* update node list for other device in the hive */ 628 if (tmp_adev != adev) { 629 top_info = &tmp_adev->psp.xgmi_context.top_info; 630 top_info->nodes[count - 1].node_id = 631 adev->gmc.xgmi.node_id; 632 top_info->num_nodes = count; 633 } 634 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 635 if (ret) 636 goto exit_unlock; 637 } 638 639 /* get latest topology info for each device from psp */ 640 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 641 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 642 &tmp_adev->psp.xgmi_context.top_info, false); 643 if (ret) { 644 dev_err(tmp_adev->dev, 645 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 646 tmp_adev->gmc.xgmi.node_id, 647 tmp_adev->gmc.xgmi.hive_id, ret); 648 /* To do : continue with some node failed or disable the whole hive */ 649 goto exit_unlock; 650 } 651 } 652 653 /* get topology again for hives that support extended data */ 654 if (adev->psp.xgmi_context.supports_extended_data) { 655 656 /* initialize the hive to get extended data. */ 657 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 658 if (ret) 659 goto exit_unlock; 660 661 /* get the extended data. */ 662 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 663 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 664 &tmp_adev->psp.xgmi_context.top_info, true); 665 if (ret) { 666 dev_err(tmp_adev->dev, 667 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 668 tmp_adev->gmc.xgmi.node_id, 669 tmp_adev->gmc.xgmi.hive_id, ret); 670 goto exit_unlock; 671 } 672 } 673 674 /* initialize the hive to get non-extended data for the next round. */ 675 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 676 if (ret) 677 goto exit_unlock; 678 679 } 680 } 681 682 if (!ret && !adev->gmc.xgmi.pending_reset) 683 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 684 685 exit_unlock: 686 mutex_unlock(&hive->hive_lock); 687 exit: 688 if (!ret) { 689 adev->hive = hive; 690 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 691 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 692 } else { 693 amdgpu_put_xgmi_hive(hive); 694 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 695 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 696 ret); 697 } 698 699 return ret; 700 } 701 702 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 703 { 704 struct amdgpu_hive_info *hive = adev->hive; 705 706 if (!adev->gmc.xgmi.supported) 707 return -EINVAL; 708 709 if (!hive) 710 return -EINVAL; 711 712 mutex_lock(&hive->hive_lock); 713 task_barrier_rem_task(&hive->tb); 714 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 715 if (hive->hi_req_gpu == adev) 716 hive->hi_req_gpu = NULL; 717 list_del(&adev->gmc.xgmi.head); 718 mutex_unlock(&hive->hive_lock); 719 720 amdgpu_put_xgmi_hive(hive); 721 adev->hive = NULL; 722 723 if (atomic_dec_return(&hive->number_devices) == 0) { 724 /* Remove the hive from global hive list */ 725 mutex_lock(&xgmi_mutex); 726 list_del(&hive->node); 727 mutex_unlock(&xgmi_mutex); 728 729 amdgpu_put_xgmi_hive(hive); 730 } 731 732 return psp_xgmi_terminate(&adev->psp); 733 } 734 735 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev) 736 { 737 int r; 738 struct ras_ih_if ih_info = { 739 .cb = NULL, 740 }; 741 struct ras_fs_if fs_info = { 742 .sysfs_name = "xgmi_wafl_err_count", 743 }; 744 745 if (!adev->gmc.xgmi.supported || 746 adev->gmc.xgmi.num_physical_nodes == 0) 747 return 0; 748 749 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 750 751 if (!adev->gmc.xgmi.ras_if) { 752 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); 753 if (!adev->gmc.xgmi.ras_if) 754 return -ENOMEM; 755 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 756 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 757 adev->gmc.xgmi.ras_if->sub_block_index = 0; 758 } 759 ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if; 760 r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if, 761 &fs_info, &ih_info); 762 if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) { 763 kfree(adev->gmc.xgmi.ras_if); 764 adev->gmc.xgmi.ras_if = NULL; 765 } 766 767 return r; 768 } 769 770 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev) 771 { 772 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) && 773 adev->gmc.xgmi.ras_if) { 774 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if; 775 struct ras_ih_if ih_info = { 776 .cb = NULL, 777 }; 778 779 amdgpu_ras_late_fini(adev, ras_if, &ih_info); 780 kfree(ras_if); 781 } 782 } 783 784 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 785 uint64_t addr) 786 { 787 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 788 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 789 } 790 791 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 792 { 793 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 794 WREG32_PCIE(pcs_status_reg, 0); 795 } 796 797 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 798 { 799 uint32_t i; 800 801 switch (adev->asic_type) { 802 case CHIP_ARCTURUS: 803 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 804 pcs_clear_status(adev, 805 xgmi_pcs_err_status_reg_arct[i]); 806 break; 807 case CHIP_VEGA20: 808 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 809 pcs_clear_status(adev, 810 xgmi_pcs_err_status_reg_vg20[i]); 811 break; 812 case CHIP_ALDEBARAN: 813 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) 814 pcs_clear_status(adev, 815 xgmi23_pcs_err_status_reg_aldebaran[i]); 816 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) 817 pcs_clear_status(adev, 818 xgmi3x16_pcs_err_status_reg_aldebaran[i]); 819 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 820 pcs_clear_status(adev, 821 walf_pcs_err_status_reg_aldebaran[i]); 822 break; 823 default: 824 break; 825 } 826 } 827 828 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 829 uint32_t value, 830 uint32_t *ue_count, 831 uint32_t *ce_count, 832 bool is_xgmi_pcs) 833 { 834 int i; 835 int ue_cnt; 836 837 if (is_xgmi_pcs) { 838 /* query xgmi pcs error status, 839 * only ue is supported */ 840 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) { 841 ue_cnt = (value & 842 xgmi_pcs_ras_fields[i].pcs_err_mask) >> 843 xgmi_pcs_ras_fields[i].pcs_err_shift; 844 if (ue_cnt) { 845 dev_info(adev->dev, "%s detected\n", 846 xgmi_pcs_ras_fields[i].err_name); 847 *ue_count += ue_cnt; 848 } 849 } 850 } else { 851 /* query wafl pcs error status, 852 * only ue is supported */ 853 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) { 854 ue_cnt = (value & 855 wafl_pcs_ras_fields[i].pcs_err_mask) >> 856 wafl_pcs_ras_fields[i].pcs_err_shift; 857 if (ue_cnt) { 858 dev_info(adev->dev, "%s detected\n", 859 wafl_pcs_ras_fields[i].err_name); 860 *ue_count += ue_cnt; 861 } 862 } 863 } 864 865 return 0; 866 } 867 868 static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 869 void *ras_error_status) 870 { 871 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 872 int i; 873 uint32_t data; 874 uint32_t ue_cnt = 0, ce_cnt = 0; 875 876 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 877 return -EINVAL; 878 879 err_data->ue_count = 0; 880 err_data->ce_count = 0; 881 882 switch (adev->asic_type) { 883 case CHIP_ARCTURUS: 884 /* check xgmi pcs error */ 885 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 886 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 887 if (data) 888 amdgpu_xgmi_query_pcs_error_status(adev, 889 data, &ue_cnt, &ce_cnt, true); 890 } 891 /* check wafl pcs error */ 892 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 893 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 894 if (data) 895 amdgpu_xgmi_query_pcs_error_status(adev, 896 data, &ue_cnt, &ce_cnt, false); 897 } 898 break; 899 case CHIP_VEGA20: 900 /* check xgmi pcs error */ 901 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 902 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 903 if (data) 904 amdgpu_xgmi_query_pcs_error_status(adev, 905 data, &ue_cnt, &ce_cnt, true); 906 } 907 /* check wafl pcs error */ 908 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 909 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 910 if (data) 911 amdgpu_xgmi_query_pcs_error_status(adev, 912 data, &ue_cnt, &ce_cnt, false); 913 } 914 break; 915 case CHIP_ALDEBARAN: 916 /* check xgmi23 pcs error */ 917 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) { 918 data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]); 919 if (data) 920 amdgpu_xgmi_query_pcs_error_status(adev, 921 data, &ue_cnt, &ce_cnt, true); 922 } 923 /* check xgmi3x16 pcs error */ 924 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 925 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 926 if (data) 927 amdgpu_xgmi_query_pcs_error_status(adev, 928 data, &ue_cnt, &ce_cnt, true); 929 } 930 /* check wafl pcs error */ 931 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 932 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 933 if (data) 934 amdgpu_xgmi_query_pcs_error_status(adev, 935 data, &ue_cnt, &ce_cnt, false); 936 } 937 break; 938 default: 939 dev_warn(adev->dev, "XGMI RAS error query not supported"); 940 break; 941 } 942 943 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 944 945 err_data->ue_count += ue_cnt; 946 err_data->ce_count += ce_cnt; 947 948 return 0; 949 } 950 951 const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = { 952 .ras_late_init = amdgpu_xgmi_ras_late_init, 953 .ras_fini = amdgpu_xgmi_ras_fini, 954 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 955 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 956 }; 957