1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "wafl/wafl2_4_0_0_smn.h" 33 #include "wafl/wafl2_4_0_0_sh_mask.h" 34 35 #include "amdgpu_reset.h" 36 37 #define smnPCS_XGMI23_PCS_ERROR_STATUS 0x11a01210 38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 39 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 40 41 static DEFINE_MUTEX(xgmi_mutex); 42 43 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 44 45 static LIST_HEAD(xgmi_hive_list); 46 47 static const int xgmi_pcs_err_status_reg_vg20[] = { 48 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 49 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 50 }; 51 52 static const int wafl_pcs_err_status_reg_vg20[] = { 53 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 54 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 55 }; 56 57 static const int xgmi_pcs_err_status_reg_arct[] = { 58 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 59 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 62 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 63 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 64 }; 65 66 /* same as vg20*/ 67 static const int wafl_pcs_err_status_reg_arct[] = { 68 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 69 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 70 }; 71 72 static const int xgmi23_pcs_err_status_reg_aldebaran[] = { 73 smnPCS_XGMI23_PCS_ERROR_STATUS, 74 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x100000, 75 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x200000, 76 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x300000, 77 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x400000, 78 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x500000, 79 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x600000, 80 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x700000 81 }; 82 83 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 84 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 85 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 86 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 87 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 88 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 89 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 90 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 91 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 92 }; 93 94 static const int walf_pcs_err_status_reg_aldebaran[] = { 95 smnPCS_GOPX1_PCS_ERROR_STATUS, 96 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 97 }; 98 99 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 100 {"XGMI PCS DataLossErr", 101 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 102 {"XGMI PCS TrainingErr", 103 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 104 {"XGMI PCS CRCErr", 105 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 106 {"XGMI PCS BERExceededErr", 107 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 108 {"XGMI PCS TxMetaDataErr", 109 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 110 {"XGMI PCS ReplayBufParityErr", 111 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 112 {"XGMI PCS DataParityErr", 113 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 114 {"XGMI PCS ReplayFifoOverflowErr", 115 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 116 {"XGMI PCS ReplayFifoUnderflowErr", 117 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 118 {"XGMI PCS ElasticFifoOverflowErr", 119 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 120 {"XGMI PCS DeskewErr", 121 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 122 {"XGMI PCS DataStartupLimitErr", 123 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 124 {"XGMI PCS FCInitTimeoutErr", 125 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 126 {"XGMI PCS RecoveryTimeoutErr", 127 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 128 {"XGMI PCS ReadySerialTimeoutErr", 129 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 130 {"XGMI PCS ReadySerialAttemptErr", 131 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 132 {"XGMI PCS RecoveryAttemptErr", 133 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 134 {"XGMI PCS RecoveryRelockAttemptErr", 135 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 136 }; 137 138 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 139 {"WAFL PCS DataLossErr", 140 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 141 {"WAFL PCS TrainingErr", 142 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 143 {"WAFL PCS CRCErr", 144 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 145 {"WAFL PCS BERExceededErr", 146 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 147 {"WAFL PCS TxMetaDataErr", 148 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 149 {"WAFL PCS ReplayBufParityErr", 150 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 151 {"WAFL PCS DataParityErr", 152 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 153 {"WAFL PCS ReplayFifoOverflowErr", 154 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 155 {"WAFL PCS ReplayFifoUnderflowErr", 156 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 157 {"WAFL PCS ElasticFifoOverflowErr", 158 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 159 {"WAFL PCS DeskewErr", 160 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 161 {"WAFL PCS DataStartupLimitErr", 162 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 163 {"WAFL PCS FCInitTimeoutErr", 164 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 165 {"WAFL PCS RecoveryTimeoutErr", 166 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 167 {"WAFL PCS ReadySerialTimeoutErr", 168 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 169 {"WAFL PCS ReadySerialAttemptErr", 170 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 171 {"WAFL PCS RecoveryAttemptErr", 172 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 173 {"WAFL PCS RecoveryRelockAttemptErr", 174 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 175 }; 176 177 /** 178 * DOC: AMDGPU XGMI Support 179 * 180 * XGMI is a high speed interconnect that joins multiple GPU cards 181 * into a homogeneous memory space that is organized by a collective 182 * hive ID and individual node IDs, both of which are 64-bit numbers. 183 * 184 * The file xgmi_device_id contains the unique per GPU device ID and 185 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 186 * 187 * Inside the device directory a sub-directory 'xgmi_hive_info' is 188 * created which contains the hive ID and the list of nodes. 189 * 190 * The hive ID is stored in: 191 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 192 * 193 * The node information is stored in numbered directories: 194 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 195 * 196 * Each device has their own xgmi_hive_info direction with a mirror 197 * set of node sub-directories. 198 * 199 * The XGMI memory space is built by contiguously adding the power of 200 * two padded VRAM space from each node to each other. 201 * 202 */ 203 204 static struct attribute amdgpu_xgmi_hive_id = { 205 .name = "xgmi_hive_id", 206 .mode = S_IRUGO 207 }; 208 209 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 210 &amdgpu_xgmi_hive_id, 211 NULL 212 }; 213 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); 214 215 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 216 struct attribute *attr, char *buf) 217 { 218 struct amdgpu_hive_info *hive = container_of( 219 kobj, struct amdgpu_hive_info, kobj); 220 221 if (attr == &amdgpu_xgmi_hive_id) 222 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 223 224 return 0; 225 } 226 227 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 228 { 229 struct amdgpu_hive_info *hive = container_of( 230 kobj, struct amdgpu_hive_info, kobj); 231 232 amdgpu_reset_put_reset_domain(hive->reset_domain); 233 hive->reset_domain = NULL; 234 235 mutex_destroy(&hive->hive_lock); 236 kfree(hive); 237 } 238 239 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 240 .show = amdgpu_xgmi_show_attrs, 241 }; 242 243 struct kobj_type amdgpu_xgmi_hive_type = { 244 .release = amdgpu_xgmi_hive_release, 245 .sysfs_ops = &amdgpu_xgmi_hive_ops, 246 .default_groups = amdgpu_xgmi_hive_groups, 247 }; 248 249 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 250 struct device_attribute *attr, 251 char *buf) 252 { 253 struct drm_device *ddev = dev_get_drvdata(dev); 254 struct amdgpu_device *adev = drm_to_adev(ddev); 255 256 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 257 258 } 259 260 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 261 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 262 struct device_attribute *attr, 263 char *buf) 264 { 265 struct drm_device *ddev = dev_get_drvdata(dev); 266 struct amdgpu_device *adev = drm_to_adev(ddev); 267 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 268 uint64_t fica_out; 269 unsigned int error_count = 0; 270 271 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 272 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 273 274 if ((!adev->df.funcs) || 275 (!adev->df.funcs->get_fica) || 276 (!adev->df.funcs->set_fica)) 277 return -EINVAL; 278 279 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 280 if (fica_out != 0x1f) 281 pr_err("xGMI error counters not enabled!\n"); 282 283 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 284 285 if ((fica_out & 0xffff) == 2) 286 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 287 288 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 289 290 return sysfs_emit(buf, "%u\n", error_count); 291 } 292 293 294 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 295 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 296 297 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 298 struct amdgpu_hive_info *hive) 299 { 300 int ret = 0; 301 char node[10] = { 0 }; 302 303 /* Create xgmi device id file */ 304 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 305 if (ret) { 306 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 307 return ret; 308 } 309 310 /* Create xgmi error file */ 311 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 312 if (ret) 313 pr_err("failed to create xgmi_error\n"); 314 315 316 /* Create sysfs link to hive info folder on the first device */ 317 if (hive->kobj.parent != (&adev->dev->kobj)) { 318 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 319 "xgmi_hive_info"); 320 if (ret) { 321 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 322 goto remove_file; 323 } 324 } 325 326 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 327 /* Create sysfs link form the hive folder to yourself */ 328 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 329 if (ret) { 330 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 331 goto remove_link; 332 } 333 334 goto success; 335 336 337 remove_link: 338 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 339 340 remove_file: 341 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 342 343 success: 344 return ret; 345 } 346 347 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 348 struct amdgpu_hive_info *hive) 349 { 350 char node[10]; 351 memset(node, 0, sizeof(node)); 352 353 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 354 device_remove_file(adev->dev, &dev_attr_xgmi_error); 355 356 if (hive->kobj.parent != (&adev->dev->kobj)) 357 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 358 359 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 360 sysfs_remove_link(&hive->kobj, node); 361 362 } 363 364 365 366 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 367 { 368 struct amdgpu_hive_info *hive = NULL; 369 int ret; 370 371 if (!adev->gmc.xgmi.hive_id) 372 return NULL; 373 374 if (adev->hive) { 375 kobject_get(&adev->hive->kobj); 376 return adev->hive; 377 } 378 379 mutex_lock(&xgmi_mutex); 380 381 list_for_each_entry(hive, &xgmi_hive_list, node) { 382 if (hive->hive_id == adev->gmc.xgmi.hive_id) 383 goto pro_end; 384 } 385 386 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 387 if (!hive) { 388 dev_err(adev->dev, "XGMI: allocation failed\n"); 389 hive = NULL; 390 goto pro_end; 391 } 392 393 /* initialize new hive if not exist */ 394 ret = kobject_init_and_add(&hive->kobj, 395 &amdgpu_xgmi_hive_type, 396 &adev->dev->kobj, 397 "%s", "xgmi_hive_info"); 398 if (ret) { 399 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 400 kobject_put(&hive->kobj); 401 kfree(hive); 402 hive = NULL; 403 goto pro_end; 404 } 405 406 /** 407 * Avoid recreating reset domain when hive is reconstructed for the case 408 * of reset the devices in the XGMI hive during probe for SRIOV 409 * See https://www.spinics.net/lists/amd-gfx/msg58836.html 410 */ 411 if (adev->reset_domain->type != XGMI_HIVE) { 412 hive->reset_domain = amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive"); 413 if (!hive->reset_domain) { 414 dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n"); 415 ret = -ENOMEM; 416 kobject_put(&hive->kobj); 417 kfree(hive); 418 hive = NULL; 419 goto pro_end; 420 } 421 } else { 422 amdgpu_reset_get_reset_domain(adev->reset_domain); 423 hive->reset_domain = adev->reset_domain; 424 } 425 426 hive->hive_id = adev->gmc.xgmi.hive_id; 427 INIT_LIST_HEAD(&hive->device_list); 428 INIT_LIST_HEAD(&hive->node); 429 mutex_init(&hive->hive_lock); 430 atomic_set(&hive->number_devices, 0); 431 task_barrier_init(&hive->tb); 432 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 433 hive->hi_req_gpu = NULL; 434 435 /* 436 * hive pstate on boot is high in vega20 so we have to go to low 437 * pstate on after boot. 438 */ 439 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 440 list_add_tail(&hive->node, &xgmi_hive_list); 441 442 pro_end: 443 if (hive) 444 kobject_get(&hive->kobj); 445 mutex_unlock(&xgmi_mutex); 446 return hive; 447 } 448 449 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 450 { 451 if (hive) 452 kobject_put(&hive->kobj); 453 } 454 455 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 456 { 457 int ret = 0; 458 struct amdgpu_hive_info *hive; 459 struct amdgpu_device *request_adev; 460 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 461 bool init_low; 462 463 hive = amdgpu_get_xgmi_hive(adev); 464 if (!hive) 465 return 0; 466 467 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 468 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 469 amdgpu_put_xgmi_hive(hive); 470 /* fw bug so temporarily disable pstate switching */ 471 return 0; 472 473 if (!hive || adev->asic_type != CHIP_VEGA20) 474 return 0; 475 476 mutex_lock(&hive->hive_lock); 477 478 if (is_hi_req) 479 hive->hi_req_count++; 480 else 481 hive->hi_req_count--; 482 483 /* 484 * Vega20 only needs single peer to request pstate high for the hive to 485 * go high but all peers must request pstate low for the hive to go low 486 */ 487 if (hive->pstate == pstate || 488 (!is_hi_req && hive->hi_req_count && !init_low)) 489 goto out; 490 491 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 492 493 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 494 if (ret) { 495 dev_err(request_adev->dev, 496 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 497 request_adev->gmc.xgmi.node_id, 498 request_adev->gmc.xgmi.hive_id, ret); 499 goto out; 500 } 501 502 if (init_low) 503 hive->pstate = hive->hi_req_count ? 504 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 505 else { 506 hive->pstate = pstate; 507 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 508 adev : NULL; 509 } 510 out: 511 mutex_unlock(&hive->hive_lock); 512 return ret; 513 } 514 515 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 516 { 517 int ret; 518 519 /* Each psp need to set the latest topology */ 520 ret = psp_xgmi_set_topology_info(&adev->psp, 521 atomic_read(&hive->number_devices), 522 &adev->psp.xgmi_context.top_info); 523 if (ret) 524 dev_err(adev->dev, 525 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 526 adev->gmc.xgmi.node_id, 527 adev->gmc.xgmi.hive_id, ret); 528 529 return ret; 530 } 531 532 533 /* 534 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 535 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 536 * num_hops[5:3] = reserved 537 * num_hops[2:0] = number of hops 538 */ 539 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 540 struct amdgpu_device *peer_adev) 541 { 542 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 543 uint8_t num_hops_mask = 0x7; 544 int i; 545 546 for (i = 0 ; i < top->num_nodes; ++i) 547 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 548 return top->nodes[i].num_hops & num_hops_mask; 549 return -EINVAL; 550 } 551 552 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, 553 struct amdgpu_device *peer_adev) 554 { 555 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 556 int i; 557 558 for (i = 0 ; i < top->num_nodes; ++i) 559 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 560 return top->nodes[i].num_links; 561 return -EINVAL; 562 } 563 564 /* 565 * Devices that support extended data require the entire hive to initialize with 566 * the shared memory buffer flag set. 567 * 568 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 569 */ 570 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 571 bool set_extended_data) 572 { 573 struct amdgpu_device *tmp_adev; 574 int ret; 575 576 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 577 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 578 if (ret) { 579 dev_err(tmp_adev->dev, 580 "XGMI: Failed to initialize xgmi session for data partition %i\n", 581 set_extended_data); 582 return ret; 583 } 584 585 } 586 587 return 0; 588 } 589 590 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 591 { 592 struct psp_xgmi_topology_info *top_info; 593 struct amdgpu_hive_info *hive; 594 struct amdgpu_xgmi *entry; 595 struct amdgpu_device *tmp_adev = NULL; 596 597 int count = 0, ret = 0; 598 599 if (!adev->gmc.xgmi.supported) 600 return 0; 601 602 if (!adev->gmc.xgmi.pending_reset && 603 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 604 ret = psp_xgmi_initialize(&adev->psp, false, true); 605 if (ret) { 606 dev_err(adev->dev, 607 "XGMI: Failed to initialize xgmi session\n"); 608 return ret; 609 } 610 611 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 612 if (ret) { 613 dev_err(adev->dev, 614 "XGMI: Failed to get hive id\n"); 615 return ret; 616 } 617 618 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 619 if (ret) { 620 dev_err(adev->dev, 621 "XGMI: Failed to get node id\n"); 622 return ret; 623 } 624 } else { 625 adev->gmc.xgmi.hive_id = 16; 626 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 627 } 628 629 hive = amdgpu_get_xgmi_hive(adev); 630 if (!hive) { 631 ret = -EINVAL; 632 dev_err(adev->dev, 633 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 634 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 635 goto exit; 636 } 637 mutex_lock(&hive->hive_lock); 638 639 top_info = &adev->psp.xgmi_context.top_info; 640 641 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 642 list_for_each_entry(entry, &hive->device_list, head) 643 top_info->nodes[count++].node_id = entry->node_id; 644 top_info->num_nodes = count; 645 atomic_set(&hive->number_devices, count); 646 647 task_barrier_add_task(&hive->tb); 648 649 if (!adev->gmc.xgmi.pending_reset && 650 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 651 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 652 /* update node list for other device in the hive */ 653 if (tmp_adev != adev) { 654 top_info = &tmp_adev->psp.xgmi_context.top_info; 655 top_info->nodes[count - 1].node_id = 656 adev->gmc.xgmi.node_id; 657 top_info->num_nodes = count; 658 } 659 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 660 if (ret) 661 goto exit_unlock; 662 } 663 664 /* get latest topology info for each device from psp */ 665 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 666 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 667 &tmp_adev->psp.xgmi_context.top_info, false); 668 if (ret) { 669 dev_err(tmp_adev->dev, 670 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 671 tmp_adev->gmc.xgmi.node_id, 672 tmp_adev->gmc.xgmi.hive_id, ret); 673 /* To do : continue with some node failed or disable the whole hive */ 674 goto exit_unlock; 675 } 676 } 677 678 /* get topology again for hives that support extended data */ 679 if (adev->psp.xgmi_context.supports_extended_data) { 680 681 /* initialize the hive to get extended data. */ 682 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 683 if (ret) 684 goto exit_unlock; 685 686 /* get the extended data. */ 687 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 688 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 689 &tmp_adev->psp.xgmi_context.top_info, true); 690 if (ret) { 691 dev_err(tmp_adev->dev, 692 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 693 tmp_adev->gmc.xgmi.node_id, 694 tmp_adev->gmc.xgmi.hive_id, ret); 695 goto exit_unlock; 696 } 697 } 698 699 /* initialize the hive to get non-extended data for the next round. */ 700 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 701 if (ret) 702 goto exit_unlock; 703 704 } 705 } 706 707 if (!ret && !adev->gmc.xgmi.pending_reset) 708 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 709 710 exit_unlock: 711 mutex_unlock(&hive->hive_lock); 712 exit: 713 if (!ret) { 714 adev->hive = hive; 715 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 716 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 717 } else { 718 amdgpu_put_xgmi_hive(hive); 719 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 720 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 721 ret); 722 } 723 724 return ret; 725 } 726 727 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 728 { 729 struct amdgpu_hive_info *hive = adev->hive; 730 731 if (!adev->gmc.xgmi.supported) 732 return -EINVAL; 733 734 if (!hive) 735 return -EINVAL; 736 737 mutex_lock(&hive->hive_lock); 738 task_barrier_rem_task(&hive->tb); 739 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 740 if (hive->hi_req_gpu == adev) 741 hive->hi_req_gpu = NULL; 742 list_del(&adev->gmc.xgmi.head); 743 mutex_unlock(&hive->hive_lock); 744 745 amdgpu_put_xgmi_hive(hive); 746 adev->hive = NULL; 747 748 if (atomic_dec_return(&hive->number_devices) == 0) { 749 /* Remove the hive from global hive list */ 750 mutex_lock(&xgmi_mutex); 751 list_del(&hive->node); 752 mutex_unlock(&xgmi_mutex); 753 754 amdgpu_put_xgmi_hive(hive); 755 } 756 757 return psp_xgmi_terminate(&adev->psp); 758 } 759 760 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev) 761 { 762 int r; 763 struct ras_ih_if ih_info = { 764 .cb = NULL, 765 }; 766 struct ras_fs_if fs_info = { 767 .sysfs_name = "xgmi_wafl_err_count", 768 }; 769 770 if (!adev->gmc.xgmi.supported || 771 adev->gmc.xgmi.num_physical_nodes == 0) 772 return 0; 773 774 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 775 776 if (!adev->gmc.xgmi.ras_if) { 777 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); 778 if (!adev->gmc.xgmi.ras_if) 779 return -ENOMEM; 780 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 781 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 782 adev->gmc.xgmi.ras_if->sub_block_index = 0; 783 } 784 ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if; 785 r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if, 786 &fs_info, &ih_info); 787 if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) { 788 kfree(adev->gmc.xgmi.ras_if); 789 adev->gmc.xgmi.ras_if = NULL; 790 } 791 792 return r; 793 } 794 795 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev) 796 { 797 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) && 798 adev->gmc.xgmi.ras_if) { 799 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if; 800 struct ras_ih_if ih_info = { 801 .cb = NULL, 802 }; 803 804 amdgpu_ras_late_fini(adev, ras_if, &ih_info); 805 kfree(ras_if); 806 } 807 } 808 809 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 810 uint64_t addr) 811 { 812 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 813 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 814 } 815 816 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 817 { 818 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 819 WREG32_PCIE(pcs_status_reg, 0); 820 } 821 822 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 823 { 824 uint32_t i; 825 826 switch (adev->asic_type) { 827 case CHIP_ARCTURUS: 828 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 829 pcs_clear_status(adev, 830 xgmi_pcs_err_status_reg_arct[i]); 831 break; 832 case CHIP_VEGA20: 833 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 834 pcs_clear_status(adev, 835 xgmi_pcs_err_status_reg_vg20[i]); 836 break; 837 case CHIP_ALDEBARAN: 838 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) 839 pcs_clear_status(adev, 840 xgmi23_pcs_err_status_reg_aldebaran[i]); 841 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) 842 pcs_clear_status(adev, 843 xgmi3x16_pcs_err_status_reg_aldebaran[i]); 844 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 845 pcs_clear_status(adev, 846 walf_pcs_err_status_reg_aldebaran[i]); 847 break; 848 default: 849 break; 850 } 851 } 852 853 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 854 uint32_t value, 855 uint32_t *ue_count, 856 uint32_t *ce_count, 857 bool is_xgmi_pcs) 858 { 859 int i; 860 int ue_cnt; 861 862 if (is_xgmi_pcs) { 863 /* query xgmi pcs error status, 864 * only ue is supported */ 865 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) { 866 ue_cnt = (value & 867 xgmi_pcs_ras_fields[i].pcs_err_mask) >> 868 xgmi_pcs_ras_fields[i].pcs_err_shift; 869 if (ue_cnt) { 870 dev_info(adev->dev, "%s detected\n", 871 xgmi_pcs_ras_fields[i].err_name); 872 *ue_count += ue_cnt; 873 } 874 } 875 } else { 876 /* query wafl pcs error status, 877 * only ue is supported */ 878 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) { 879 ue_cnt = (value & 880 wafl_pcs_ras_fields[i].pcs_err_mask) >> 881 wafl_pcs_ras_fields[i].pcs_err_shift; 882 if (ue_cnt) { 883 dev_info(adev->dev, "%s detected\n", 884 wafl_pcs_ras_fields[i].err_name); 885 *ue_count += ue_cnt; 886 } 887 } 888 } 889 890 return 0; 891 } 892 893 static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 894 void *ras_error_status) 895 { 896 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 897 int i; 898 uint32_t data; 899 uint32_t ue_cnt = 0, ce_cnt = 0; 900 901 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 902 return -EINVAL; 903 904 err_data->ue_count = 0; 905 err_data->ce_count = 0; 906 907 switch (adev->asic_type) { 908 case CHIP_ARCTURUS: 909 /* check xgmi pcs error */ 910 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 911 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 912 if (data) 913 amdgpu_xgmi_query_pcs_error_status(adev, 914 data, &ue_cnt, &ce_cnt, true); 915 } 916 /* check wafl pcs error */ 917 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 918 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 919 if (data) 920 amdgpu_xgmi_query_pcs_error_status(adev, 921 data, &ue_cnt, &ce_cnt, false); 922 } 923 break; 924 case CHIP_VEGA20: 925 /* check xgmi pcs error */ 926 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 927 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 928 if (data) 929 amdgpu_xgmi_query_pcs_error_status(adev, 930 data, &ue_cnt, &ce_cnt, true); 931 } 932 /* check wafl pcs error */ 933 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 934 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 935 if (data) 936 amdgpu_xgmi_query_pcs_error_status(adev, 937 data, &ue_cnt, &ce_cnt, false); 938 } 939 break; 940 case CHIP_ALDEBARAN: 941 /* check xgmi23 pcs error */ 942 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) { 943 data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]); 944 if (data) 945 amdgpu_xgmi_query_pcs_error_status(adev, 946 data, &ue_cnt, &ce_cnt, true); 947 } 948 /* check xgmi3x16 pcs error */ 949 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 950 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 951 if (data) 952 amdgpu_xgmi_query_pcs_error_status(adev, 953 data, &ue_cnt, &ce_cnt, true); 954 } 955 /* check wafl pcs error */ 956 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 957 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 958 if (data) 959 amdgpu_xgmi_query_pcs_error_status(adev, 960 data, &ue_cnt, &ce_cnt, false); 961 } 962 break; 963 default: 964 dev_warn(adev->dev, "XGMI RAS error query not supported"); 965 break; 966 } 967 968 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 969 970 err_data->ue_count += ue_cnt; 971 err_data->ce_count += ce_cnt; 972 973 return 0; 974 } 975 976 const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = { 977 .ras_late_init = amdgpu_xgmi_ras_late_init, 978 .ras_fini = amdgpu_xgmi_ras_fini, 979 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 980 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 981 }; 982