1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "xgmi/xgmi_6_1_0_sh_mask.h" 33 #include "wafl/wafl2_4_0_0_smn.h" 34 #include "wafl/wafl2_4_0_0_sh_mask.h" 35 36 #include "amdgpu_reset.h" 37 38 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 39 #define smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK 0x11a00218 40 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 41 #define smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK 0x12200218 42 43 static DEFINE_MUTEX(xgmi_mutex); 44 45 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 46 47 static LIST_HEAD(xgmi_hive_list); 48 49 static const int xgmi_pcs_err_status_reg_vg20[] = { 50 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 51 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 52 }; 53 54 static const int wafl_pcs_err_status_reg_vg20[] = { 55 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 56 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 57 }; 58 59 static const int xgmi_pcs_err_status_reg_arct[] = { 60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 62 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 63 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 64 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 65 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 66 }; 67 68 /* same as vg20*/ 69 static const int wafl_pcs_err_status_reg_arct[] = { 70 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 71 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 72 }; 73 74 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 75 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 76 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 77 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 78 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 79 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 80 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 81 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 82 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 83 }; 84 85 static const int xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[] = { 86 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK, 87 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000, 88 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x200000, 89 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x300000, 90 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x400000, 91 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x500000, 92 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x600000, 93 smnPCS_XGMI3X16_PCS_ERROR_NONCORRECTABLE_MASK + 0x700000 94 }; 95 96 static const int walf_pcs_err_status_reg_aldebaran[] = { 97 smnPCS_GOPX1_PCS_ERROR_STATUS, 98 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 99 }; 100 101 static const int walf_pcs_err_noncorrectable_mask_reg_aldebaran[] = { 102 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK, 103 smnPCS_GOPX1_PCS_ERROR_NONCORRECTABLE_MASK + 0x100000 104 }; 105 106 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 107 {"XGMI PCS DataLossErr", 108 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 109 {"XGMI PCS TrainingErr", 110 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 111 {"XGMI PCS CRCErr", 112 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 113 {"XGMI PCS BERExceededErr", 114 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 115 {"XGMI PCS TxMetaDataErr", 116 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 117 {"XGMI PCS ReplayBufParityErr", 118 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 119 {"XGMI PCS DataParityErr", 120 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 121 {"XGMI PCS ReplayFifoOverflowErr", 122 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 123 {"XGMI PCS ReplayFifoUnderflowErr", 124 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 125 {"XGMI PCS ElasticFifoOverflowErr", 126 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 127 {"XGMI PCS DeskewErr", 128 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 129 {"XGMI PCS DataStartupLimitErr", 130 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 131 {"XGMI PCS FCInitTimeoutErr", 132 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 133 {"XGMI PCS RecoveryTimeoutErr", 134 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 135 {"XGMI PCS ReadySerialTimeoutErr", 136 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 137 {"XGMI PCS ReadySerialAttemptErr", 138 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 139 {"XGMI PCS RecoveryAttemptErr", 140 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 141 {"XGMI PCS RecoveryRelockAttemptErr", 142 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 143 }; 144 145 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 146 {"WAFL PCS DataLossErr", 147 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 148 {"WAFL PCS TrainingErr", 149 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 150 {"WAFL PCS CRCErr", 151 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 152 {"WAFL PCS BERExceededErr", 153 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 154 {"WAFL PCS TxMetaDataErr", 155 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 156 {"WAFL PCS ReplayBufParityErr", 157 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 158 {"WAFL PCS DataParityErr", 159 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 160 {"WAFL PCS ReplayFifoOverflowErr", 161 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 162 {"WAFL PCS ReplayFifoUnderflowErr", 163 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 164 {"WAFL PCS ElasticFifoOverflowErr", 165 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 166 {"WAFL PCS DeskewErr", 167 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 168 {"WAFL PCS DataStartupLimitErr", 169 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 170 {"WAFL PCS FCInitTimeoutErr", 171 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 172 {"WAFL PCS RecoveryTimeoutErr", 173 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 174 {"WAFL PCS ReadySerialTimeoutErr", 175 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 176 {"WAFL PCS ReadySerialAttemptErr", 177 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 178 {"WAFL PCS RecoveryAttemptErr", 179 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 180 {"WAFL PCS RecoveryRelockAttemptErr", 181 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 182 }; 183 184 static const struct amdgpu_pcs_ras_field xgmi3x16_pcs_ras_fields[] = { 185 {"XGMI3X16 PCS DataLossErr", 186 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataLossErr)}, 187 {"XGMI3X16 PCS TrainingErr", 188 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TrainingErr)}, 189 {"XGMI3X16 PCS FlowCtrlAckErr", 190 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlAckErr)}, 191 {"XGMI3X16 PCS RxFifoUnderflowErr", 192 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoUnderflowErr)}, 193 {"XGMI3X16 PCS RxFifoOverflowErr", 194 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxFifoOverflowErr)}, 195 {"XGMI3X16 PCS CRCErr", 196 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, CRCErr)}, 197 {"XGMI3X16 PCS BERExceededErr", 198 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, BERExceededErr)}, 199 {"XGMI3X16 PCS TxVcidDataErr", 200 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxVcidDataErr)}, 201 {"XGMI3X16 PCS ReplayBufParityErr", 202 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 203 {"XGMI3X16 PCS DataParityErr", 204 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataParityErr)}, 205 {"XGMI3X16 PCS ReplayFifoOverflowErr", 206 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 207 {"XGMI3X16 PCS ReplayFifoUnderflowErr", 208 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 209 {"XGMI3X16 PCS ElasticFifoOverflowErr", 210 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 211 {"XGMI3X16 PCS DeskewErr", 212 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DeskewErr)}, 213 {"XGMI3X16 PCS FlowCtrlCRCErr", 214 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FlowCtrlCRCErr)}, 215 {"XGMI3X16 PCS DataStartupLimitErr", 216 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 217 {"XGMI3X16 PCS FCInitTimeoutErr", 218 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 219 {"XGMI3X16 PCS RecoveryTimeoutErr", 220 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 221 {"XGMI3X16 PCS ReadySerialTimeoutErr", 222 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 223 {"XGMI3X16 PCS ReadySerialAttemptErr", 224 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 225 {"XGMI3X16 PCS RecoveryAttemptErr", 226 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 227 {"XGMI3X16 PCS RecoveryRelockAttemptErr", 228 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 229 {"XGMI3X16 PCS ReplayAttemptErr", 230 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, ReplayAttemptErr)}, 231 {"XGMI3X16 PCS SyncHdrErr", 232 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, SyncHdrErr)}, 233 {"XGMI3X16 PCS TxReplayTimeoutErr", 234 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, TxReplayTimeoutErr)}, 235 {"XGMI3X16 PCS RxReplayTimeoutErr", 236 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxReplayTimeoutErr)}, 237 {"XGMI3X16 PCS LinkSubTxTimeoutErr", 238 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubTxTimeoutErr)}, 239 {"XGMI3X16 PCS LinkSubRxTimeoutErr", 240 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, LinkSubRxTimeoutErr)}, 241 {"XGMI3X16 PCS RxCMDPktErr", 242 SOC15_REG_FIELD(PCS_XGMI3X16_PCS_ERROR_STATUS, RxCMDPktErr)}, 243 }; 244 245 /** 246 * DOC: AMDGPU XGMI Support 247 * 248 * XGMI is a high speed interconnect that joins multiple GPU cards 249 * into a homogeneous memory space that is organized by a collective 250 * hive ID and individual node IDs, both of which are 64-bit numbers. 251 * 252 * The file xgmi_device_id contains the unique per GPU device ID and 253 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 254 * 255 * Inside the device directory a sub-directory 'xgmi_hive_info' is 256 * created which contains the hive ID and the list of nodes. 257 * 258 * The hive ID is stored in: 259 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 260 * 261 * The node information is stored in numbered directories: 262 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 263 * 264 * Each device has their own xgmi_hive_info direction with a mirror 265 * set of node sub-directories. 266 * 267 * The XGMI memory space is built by contiguously adding the power of 268 * two padded VRAM space from each node to each other. 269 * 270 */ 271 272 static struct attribute amdgpu_xgmi_hive_id = { 273 .name = "xgmi_hive_id", 274 .mode = S_IRUGO 275 }; 276 277 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 278 &amdgpu_xgmi_hive_id, 279 NULL 280 }; 281 ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); 282 283 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 284 struct attribute *attr, char *buf) 285 { 286 struct amdgpu_hive_info *hive = container_of( 287 kobj, struct amdgpu_hive_info, kobj); 288 289 if (attr == &amdgpu_xgmi_hive_id) 290 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 291 292 return 0; 293 } 294 295 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 296 { 297 struct amdgpu_hive_info *hive = container_of( 298 kobj, struct amdgpu_hive_info, kobj); 299 300 amdgpu_reset_put_reset_domain(hive->reset_domain); 301 hive->reset_domain = NULL; 302 303 mutex_destroy(&hive->hive_lock); 304 kfree(hive); 305 } 306 307 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 308 .show = amdgpu_xgmi_show_attrs, 309 }; 310 311 static const struct kobj_type amdgpu_xgmi_hive_type = { 312 .release = amdgpu_xgmi_hive_release, 313 .sysfs_ops = &amdgpu_xgmi_hive_ops, 314 .default_groups = amdgpu_xgmi_hive_groups, 315 }; 316 317 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 318 struct device_attribute *attr, 319 char *buf) 320 { 321 struct drm_device *ddev = dev_get_drvdata(dev); 322 struct amdgpu_device *adev = drm_to_adev(ddev); 323 324 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 325 326 } 327 328 static ssize_t amdgpu_xgmi_show_num_hops(struct device *dev, 329 struct device_attribute *attr, 330 char *buf) 331 { 332 struct drm_device *ddev = dev_get_drvdata(dev); 333 struct amdgpu_device *adev = drm_to_adev(ddev); 334 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 335 int i; 336 337 for (i = 0; i < top->num_nodes; i++) 338 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_hops); 339 340 return sysfs_emit(buf, "%s\n", buf); 341 } 342 343 static ssize_t amdgpu_xgmi_show_num_links(struct device *dev, 344 struct device_attribute *attr, 345 char *buf) 346 { 347 struct drm_device *ddev = dev_get_drvdata(dev); 348 struct amdgpu_device *adev = drm_to_adev(ddev); 349 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 350 int i; 351 352 for (i = 0; i < top->num_nodes; i++) 353 sprintf(buf + 3 * i, "%02x ", top->nodes[i].num_links); 354 355 return sysfs_emit(buf, "%s\n", buf); 356 } 357 358 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 359 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 360 struct device_attribute *attr, 361 char *buf) 362 { 363 struct drm_device *ddev = dev_get_drvdata(dev); 364 struct amdgpu_device *adev = drm_to_adev(ddev); 365 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 366 uint64_t fica_out; 367 unsigned int error_count = 0; 368 369 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 370 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 371 372 if ((!adev->df.funcs) || 373 (!adev->df.funcs->get_fica) || 374 (!adev->df.funcs->set_fica)) 375 return -EINVAL; 376 377 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 378 if (fica_out != 0x1f) 379 pr_err("xGMI error counters not enabled!\n"); 380 381 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 382 383 if ((fica_out & 0xffff) == 2) 384 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 385 386 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 387 388 return sysfs_emit(buf, "%u\n", error_count); 389 } 390 391 392 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 393 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 394 static DEVICE_ATTR(xgmi_num_hops, S_IRUGO, amdgpu_xgmi_show_num_hops, NULL); 395 static DEVICE_ATTR(xgmi_num_links, S_IRUGO, amdgpu_xgmi_show_num_links, NULL); 396 397 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 398 struct amdgpu_hive_info *hive) 399 { 400 int ret = 0; 401 char node[10] = { 0 }; 402 403 /* Create xgmi device id file */ 404 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 405 if (ret) { 406 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 407 return ret; 408 } 409 410 /* Create xgmi error file */ 411 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 412 if (ret) 413 pr_err("failed to create xgmi_error\n"); 414 415 /* Create xgmi num hops file */ 416 ret = device_create_file(adev->dev, &dev_attr_xgmi_num_hops); 417 if (ret) 418 pr_err("failed to create xgmi_num_hops\n"); 419 420 /* Create xgmi num links file */ 421 ret = device_create_file(adev->dev, &dev_attr_xgmi_num_links); 422 if (ret) 423 pr_err("failed to create xgmi_num_links\n"); 424 425 /* Create sysfs link to hive info folder on the first device */ 426 if (hive->kobj.parent != (&adev->dev->kobj)) { 427 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 428 "xgmi_hive_info"); 429 if (ret) { 430 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 431 goto remove_file; 432 } 433 } 434 435 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 436 /* Create sysfs link form the hive folder to yourself */ 437 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 438 if (ret) { 439 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 440 goto remove_link; 441 } 442 443 goto success; 444 445 446 remove_link: 447 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 448 449 remove_file: 450 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 451 device_remove_file(adev->dev, &dev_attr_xgmi_error); 452 device_remove_file(adev->dev, &dev_attr_xgmi_num_hops); 453 device_remove_file(adev->dev, &dev_attr_xgmi_num_links); 454 455 success: 456 return ret; 457 } 458 459 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 460 struct amdgpu_hive_info *hive) 461 { 462 char node[10]; 463 memset(node, 0, sizeof(node)); 464 465 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 466 device_remove_file(adev->dev, &dev_attr_xgmi_error); 467 device_remove_file(adev->dev, &dev_attr_xgmi_num_hops); 468 device_remove_file(adev->dev, &dev_attr_xgmi_num_links); 469 470 if (hive->kobj.parent != (&adev->dev->kobj)) 471 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 472 473 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 474 sysfs_remove_link(&hive->kobj, node); 475 476 } 477 478 479 480 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 481 { 482 struct amdgpu_hive_info *hive = NULL; 483 int ret; 484 485 if (!adev->gmc.xgmi.hive_id) 486 return NULL; 487 488 if (adev->hive) { 489 kobject_get(&adev->hive->kobj); 490 return adev->hive; 491 } 492 493 mutex_lock(&xgmi_mutex); 494 495 list_for_each_entry(hive, &xgmi_hive_list, node) { 496 if (hive->hive_id == adev->gmc.xgmi.hive_id) 497 goto pro_end; 498 } 499 500 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 501 if (!hive) { 502 dev_err(adev->dev, "XGMI: allocation failed\n"); 503 hive = NULL; 504 goto pro_end; 505 } 506 507 /* initialize new hive if not exist */ 508 ret = kobject_init_and_add(&hive->kobj, 509 &amdgpu_xgmi_hive_type, 510 &adev->dev->kobj, 511 "%s", "xgmi_hive_info"); 512 if (ret) { 513 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 514 kobject_put(&hive->kobj); 515 hive = NULL; 516 goto pro_end; 517 } 518 519 /** 520 * Only init hive->reset_domain for none SRIOV configuration. For SRIOV, 521 * Host driver decide how to reset the GPU either through FLR or chain reset. 522 * Guest side will get individual notifications from the host for the FLR 523 * if necessary. 524 */ 525 if (!amdgpu_sriov_vf(adev)) { 526 /** 527 * Avoid recreating reset domain when hive is reconstructed for the case 528 * of reset the devices in the XGMI hive during probe for passthrough GPU 529 * See https://www.spinics.net/lists/amd-gfx/msg58836.html 530 */ 531 if (adev->reset_domain->type != XGMI_HIVE) { 532 hive->reset_domain = 533 amdgpu_reset_create_reset_domain(XGMI_HIVE, "amdgpu-reset-hive"); 534 if (!hive->reset_domain) { 535 dev_err(adev->dev, "XGMI: failed initializing reset domain for xgmi hive\n"); 536 ret = -ENOMEM; 537 kobject_put(&hive->kobj); 538 hive = NULL; 539 goto pro_end; 540 } 541 } else { 542 amdgpu_reset_get_reset_domain(adev->reset_domain); 543 hive->reset_domain = adev->reset_domain; 544 } 545 } 546 547 hive->hive_id = adev->gmc.xgmi.hive_id; 548 INIT_LIST_HEAD(&hive->device_list); 549 INIT_LIST_HEAD(&hive->node); 550 mutex_init(&hive->hive_lock); 551 atomic_set(&hive->number_devices, 0); 552 task_barrier_init(&hive->tb); 553 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 554 hive->hi_req_gpu = NULL; 555 556 /* 557 * hive pstate on boot is high in vega20 so we have to go to low 558 * pstate on after boot. 559 */ 560 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 561 list_add_tail(&hive->node, &xgmi_hive_list); 562 563 pro_end: 564 if (hive) 565 kobject_get(&hive->kobj); 566 mutex_unlock(&xgmi_mutex); 567 return hive; 568 } 569 570 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 571 { 572 if (hive) 573 kobject_put(&hive->kobj); 574 } 575 576 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 577 { 578 int ret = 0; 579 struct amdgpu_hive_info *hive; 580 struct amdgpu_device *request_adev; 581 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 582 bool init_low; 583 584 hive = amdgpu_get_xgmi_hive(adev); 585 if (!hive) 586 return 0; 587 588 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 589 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 590 amdgpu_put_xgmi_hive(hive); 591 /* fw bug so temporarily disable pstate switching */ 592 return 0; 593 594 if (!hive || adev->asic_type != CHIP_VEGA20) 595 return 0; 596 597 mutex_lock(&hive->hive_lock); 598 599 if (is_hi_req) 600 hive->hi_req_count++; 601 else 602 hive->hi_req_count--; 603 604 /* 605 * Vega20 only needs single peer to request pstate high for the hive to 606 * go high but all peers must request pstate low for the hive to go low 607 */ 608 if (hive->pstate == pstate || 609 (!is_hi_req && hive->hi_req_count && !init_low)) 610 goto out; 611 612 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 613 614 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 615 if (ret) { 616 dev_err(request_adev->dev, 617 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 618 request_adev->gmc.xgmi.node_id, 619 request_adev->gmc.xgmi.hive_id, ret); 620 goto out; 621 } 622 623 if (init_low) 624 hive->pstate = hive->hi_req_count ? 625 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 626 else { 627 hive->pstate = pstate; 628 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 629 adev : NULL; 630 } 631 out: 632 mutex_unlock(&hive->hive_lock); 633 return ret; 634 } 635 636 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 637 { 638 int ret; 639 640 if (amdgpu_sriov_vf(adev)) 641 return 0; 642 643 /* Each psp need to set the latest topology */ 644 ret = psp_xgmi_set_topology_info(&adev->psp, 645 atomic_read(&hive->number_devices), 646 &adev->psp.xgmi_context.top_info); 647 if (ret) 648 dev_err(adev->dev, 649 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 650 adev->gmc.xgmi.node_id, 651 adev->gmc.xgmi.hive_id, ret); 652 653 return ret; 654 } 655 656 657 /* 658 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 659 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 660 * num_hops[5:3] = reserved 661 * num_hops[2:0] = number of hops 662 */ 663 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 664 struct amdgpu_device *peer_adev) 665 { 666 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 667 uint8_t num_hops_mask = 0x7; 668 int i; 669 670 for (i = 0 ; i < top->num_nodes; ++i) 671 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 672 return top->nodes[i].num_hops & num_hops_mask; 673 return -EINVAL; 674 } 675 676 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, 677 struct amdgpu_device *peer_adev) 678 { 679 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 680 int i; 681 682 for (i = 0 ; i < top->num_nodes; ++i) 683 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 684 return top->nodes[i].num_links; 685 return -EINVAL; 686 } 687 688 /* 689 * Devices that support extended data require the entire hive to initialize with 690 * the shared memory buffer flag set. 691 * 692 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 693 */ 694 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 695 bool set_extended_data) 696 { 697 struct amdgpu_device *tmp_adev; 698 int ret; 699 700 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 701 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 702 if (ret) { 703 dev_err(tmp_adev->dev, 704 "XGMI: Failed to initialize xgmi session for data partition %i\n", 705 set_extended_data); 706 return ret; 707 } 708 709 } 710 711 return 0; 712 } 713 714 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 715 { 716 struct psp_xgmi_topology_info *top_info; 717 struct amdgpu_hive_info *hive; 718 struct amdgpu_xgmi *entry; 719 struct amdgpu_device *tmp_adev = NULL; 720 721 int count = 0, ret = 0; 722 723 if (!adev->gmc.xgmi.supported) 724 return 0; 725 726 if (!adev->gmc.xgmi.pending_reset && 727 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 728 ret = psp_xgmi_initialize(&adev->psp, false, true); 729 if (ret) { 730 dev_err(adev->dev, 731 "XGMI: Failed to initialize xgmi session\n"); 732 return ret; 733 } 734 735 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 736 if (ret) { 737 dev_err(adev->dev, 738 "XGMI: Failed to get hive id\n"); 739 return ret; 740 } 741 742 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 743 if (ret) { 744 dev_err(adev->dev, 745 "XGMI: Failed to get node id\n"); 746 return ret; 747 } 748 } else { 749 adev->gmc.xgmi.hive_id = 16; 750 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 751 } 752 753 hive = amdgpu_get_xgmi_hive(adev); 754 if (!hive) { 755 ret = -EINVAL; 756 dev_err(adev->dev, 757 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 758 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 759 goto exit; 760 } 761 mutex_lock(&hive->hive_lock); 762 763 top_info = &adev->psp.xgmi_context.top_info; 764 765 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 766 list_for_each_entry(entry, &hive->device_list, head) 767 top_info->nodes[count++].node_id = entry->node_id; 768 top_info->num_nodes = count; 769 atomic_set(&hive->number_devices, count); 770 771 task_barrier_add_task(&hive->tb); 772 773 if (!adev->gmc.xgmi.pending_reset && 774 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 775 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 776 /* update node list for other device in the hive */ 777 if (tmp_adev != adev) { 778 top_info = &tmp_adev->psp.xgmi_context.top_info; 779 top_info->nodes[count - 1].node_id = 780 adev->gmc.xgmi.node_id; 781 top_info->num_nodes = count; 782 } 783 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 784 if (ret) 785 goto exit_unlock; 786 } 787 788 /* get latest topology info for each device from psp */ 789 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 790 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 791 &tmp_adev->psp.xgmi_context.top_info, false); 792 if (ret) { 793 dev_err(tmp_adev->dev, 794 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 795 tmp_adev->gmc.xgmi.node_id, 796 tmp_adev->gmc.xgmi.hive_id, ret); 797 /* To do : continue with some node failed or disable the whole hive */ 798 goto exit_unlock; 799 } 800 } 801 802 /* get topology again for hives that support extended data */ 803 if (adev->psp.xgmi_context.supports_extended_data) { 804 805 /* initialize the hive to get extended data. */ 806 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 807 if (ret) 808 goto exit_unlock; 809 810 /* get the extended data. */ 811 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 812 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 813 &tmp_adev->psp.xgmi_context.top_info, true); 814 if (ret) { 815 dev_err(tmp_adev->dev, 816 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 817 tmp_adev->gmc.xgmi.node_id, 818 tmp_adev->gmc.xgmi.hive_id, ret); 819 goto exit_unlock; 820 } 821 } 822 823 /* initialize the hive to get non-extended data for the next round. */ 824 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 825 if (ret) 826 goto exit_unlock; 827 828 } 829 } 830 831 if (!ret && !adev->gmc.xgmi.pending_reset) 832 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 833 834 exit_unlock: 835 mutex_unlock(&hive->hive_lock); 836 exit: 837 if (!ret) { 838 adev->hive = hive; 839 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 840 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 841 } else { 842 amdgpu_put_xgmi_hive(hive); 843 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 844 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 845 ret); 846 } 847 848 return ret; 849 } 850 851 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 852 { 853 struct amdgpu_hive_info *hive = adev->hive; 854 855 if (!adev->gmc.xgmi.supported) 856 return -EINVAL; 857 858 if (!hive) 859 return -EINVAL; 860 861 mutex_lock(&hive->hive_lock); 862 task_barrier_rem_task(&hive->tb); 863 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 864 if (hive->hi_req_gpu == adev) 865 hive->hi_req_gpu = NULL; 866 list_del(&adev->gmc.xgmi.head); 867 mutex_unlock(&hive->hive_lock); 868 869 amdgpu_put_xgmi_hive(hive); 870 adev->hive = NULL; 871 872 if (atomic_dec_return(&hive->number_devices) == 0) { 873 /* Remove the hive from global hive list */ 874 mutex_lock(&xgmi_mutex); 875 list_del(&hive->node); 876 mutex_unlock(&xgmi_mutex); 877 878 amdgpu_put_xgmi_hive(hive); 879 } 880 881 return 0; 882 } 883 884 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) 885 { 886 if (!adev->gmc.xgmi.supported || 887 adev->gmc.xgmi.num_physical_nodes == 0) 888 return 0; 889 890 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); 891 892 return amdgpu_ras_block_late_init(adev, ras_block); 893 } 894 895 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 896 uint64_t addr) 897 { 898 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 899 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 900 } 901 902 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 903 { 904 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 905 WREG32_PCIE(pcs_status_reg, 0); 906 } 907 908 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 909 { 910 uint32_t i; 911 912 switch (adev->asic_type) { 913 case CHIP_ARCTURUS: 914 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 915 pcs_clear_status(adev, 916 xgmi_pcs_err_status_reg_arct[i]); 917 break; 918 case CHIP_VEGA20: 919 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 920 pcs_clear_status(adev, 921 xgmi_pcs_err_status_reg_vg20[i]); 922 break; 923 case CHIP_ALDEBARAN: 924 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) 925 pcs_clear_status(adev, 926 xgmi3x16_pcs_err_status_reg_aldebaran[i]); 927 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 928 pcs_clear_status(adev, 929 walf_pcs_err_status_reg_aldebaran[i]); 930 break; 931 default: 932 break; 933 } 934 } 935 936 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 937 uint32_t value, 938 uint32_t mask_value, 939 uint32_t *ue_count, 940 uint32_t *ce_count, 941 bool is_xgmi_pcs, 942 bool check_mask) 943 { 944 int i; 945 int ue_cnt = 0; 946 const struct amdgpu_pcs_ras_field *pcs_ras_fields = NULL; 947 uint32_t field_array_size = 0; 948 949 if (is_xgmi_pcs) { 950 if (adev->ip_versions[XGMI_HWIP][0] == IP_VERSION(6, 1, 0)) { 951 pcs_ras_fields = &xgmi3x16_pcs_ras_fields[0]; 952 field_array_size = ARRAY_SIZE(xgmi3x16_pcs_ras_fields); 953 } else { 954 pcs_ras_fields = &xgmi_pcs_ras_fields[0]; 955 field_array_size = ARRAY_SIZE(xgmi_pcs_ras_fields); 956 } 957 } else { 958 pcs_ras_fields = &wafl_pcs_ras_fields[0]; 959 field_array_size = ARRAY_SIZE(wafl_pcs_ras_fields); 960 } 961 962 if (check_mask) 963 value = value & ~mask_value; 964 965 /* query xgmi/walf pcs error status, 966 * only ue is supported */ 967 for (i = 0; value && i < field_array_size; i++) { 968 ue_cnt = (value & 969 pcs_ras_fields[i].pcs_err_mask) >> 970 pcs_ras_fields[i].pcs_err_shift; 971 if (ue_cnt) { 972 dev_info(adev->dev, "%s detected\n", 973 pcs_ras_fields[i].err_name); 974 *ue_count += ue_cnt; 975 } 976 977 /* reset bit value if the bit is checked */ 978 value &= ~(pcs_ras_fields[i].pcs_err_mask); 979 } 980 981 return 0; 982 } 983 984 static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 985 void *ras_error_status) 986 { 987 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 988 int i; 989 uint32_t data, mask_data = 0; 990 uint32_t ue_cnt = 0, ce_cnt = 0; 991 992 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 993 return ; 994 995 err_data->ue_count = 0; 996 err_data->ce_count = 0; 997 998 switch (adev->asic_type) { 999 case CHIP_ARCTURUS: 1000 /* check xgmi pcs error */ 1001 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 1002 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 1003 if (data) 1004 amdgpu_xgmi_query_pcs_error_status(adev, data, 1005 mask_data, &ue_cnt, &ce_cnt, true, false); 1006 } 1007 /* check wafl pcs error */ 1008 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 1009 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 1010 if (data) 1011 amdgpu_xgmi_query_pcs_error_status(adev, data, 1012 mask_data, &ue_cnt, &ce_cnt, false, false); 1013 } 1014 break; 1015 case CHIP_VEGA20: 1016 /* check xgmi pcs error */ 1017 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 1018 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 1019 if (data) 1020 amdgpu_xgmi_query_pcs_error_status(adev, data, 1021 mask_data, &ue_cnt, &ce_cnt, true, false); 1022 } 1023 /* check wafl pcs error */ 1024 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 1025 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 1026 if (data) 1027 amdgpu_xgmi_query_pcs_error_status(adev, data, 1028 mask_data, &ue_cnt, &ce_cnt, false, false); 1029 } 1030 break; 1031 case CHIP_ALDEBARAN: 1032 /* check xgmi3x16 pcs error */ 1033 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 1034 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 1035 mask_data = 1036 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); 1037 if (data) 1038 amdgpu_xgmi_query_pcs_error_status(adev, data, 1039 mask_data, &ue_cnt, &ce_cnt, true, true); 1040 } 1041 /* check wafl pcs error */ 1042 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 1043 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 1044 mask_data = 1045 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); 1046 if (data) 1047 amdgpu_xgmi_query_pcs_error_status(adev, data, 1048 mask_data, &ue_cnt, &ce_cnt, false, true); 1049 } 1050 break; 1051 default: 1052 dev_warn(adev->dev, "XGMI RAS error query not supported"); 1053 break; 1054 } 1055 1056 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); 1057 1058 err_data->ue_count += ue_cnt; 1059 err_data->ce_count += ce_cnt; 1060 } 1061 1062 /* Trigger XGMI/WAFL error */ 1063 static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev, 1064 void *inject_if, uint32_t instance_mask) 1065 { 1066 int ret = 0; 1067 struct ta_ras_trigger_error_input *block_info = 1068 (struct ta_ras_trigger_error_input *)inject_if; 1069 1070 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW)) 1071 dev_warn(adev->dev, "Failed to disallow df cstate"); 1072 1073 if (amdgpu_dpm_allow_xgmi_power_down(adev, false)) 1074 dev_warn(adev->dev, "Failed to disallow XGMI power down"); 1075 1076 ret = psp_ras_trigger_error(&adev->psp, block_info, instance_mask); 1077 1078 if (amdgpu_ras_intr_triggered()) 1079 return ret; 1080 1081 if (amdgpu_dpm_allow_xgmi_power_down(adev, true)) 1082 dev_warn(adev->dev, "Failed to allow XGMI power down"); 1083 1084 if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_ALLOW)) 1085 dev_warn(adev->dev, "Failed to allow df cstate"); 1086 1087 return ret; 1088 } 1089 1090 struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = { 1091 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 1092 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 1093 .ras_error_inject = amdgpu_ras_error_inject_xgmi, 1094 }; 1095 1096 struct amdgpu_xgmi_ras xgmi_ras = { 1097 .ras_block = { 1098 .hw_ops = &xgmi_ras_hw_ops, 1099 .ras_late_init = amdgpu_xgmi_ras_late_init, 1100 }, 1101 }; 1102 1103 int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev) 1104 { 1105 int err; 1106 struct amdgpu_xgmi_ras *ras; 1107 1108 if (!adev->gmc.xgmi.ras) 1109 return 0; 1110 1111 ras = adev->gmc.xgmi.ras; 1112 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); 1113 if (err) { 1114 dev_err(adev->dev, "Failed to register xgmi_wafl_pcs ras block!\n"); 1115 return err; 1116 } 1117 1118 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); 1119 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 1120 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 1121 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; 1122 1123 return 0; 1124 } 1125