1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * 23 */ 24 #include <linux/list.h> 25 #include "amdgpu.h" 26 #include "amdgpu_xgmi.h" 27 #include "amdgpu_ras.h" 28 #include "soc15.h" 29 #include "df/df_3_6_offset.h" 30 #include "xgmi/xgmi_4_0_0_smn.h" 31 #include "xgmi/xgmi_4_0_0_sh_mask.h" 32 #include "wafl/wafl2_4_0_0_smn.h" 33 #include "wafl/wafl2_4_0_0_sh_mask.h" 34 35 #define smnPCS_XGMI23_PCS_ERROR_STATUS 0x11a01210 36 #define smnPCS_XGMI3X16_PCS_ERROR_STATUS 0x11a0020c 37 #define smnPCS_GOPX1_PCS_ERROR_STATUS 0x12200210 38 39 static DEFINE_MUTEX(xgmi_mutex); 40 41 #define AMDGPU_MAX_XGMI_DEVICE_PER_HIVE 4 42 43 static LIST_HEAD(xgmi_hive_list); 44 45 static const int xgmi_pcs_err_status_reg_vg20[] = { 46 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 47 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 48 }; 49 50 static const int wafl_pcs_err_status_reg_vg20[] = { 51 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 52 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 53 }; 54 55 static const int xgmi_pcs_err_status_reg_arct[] = { 56 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS, 57 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x100000, 58 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x500000, 59 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x600000, 60 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x700000, 61 smnXGMI0_PCS_GOPX16_PCS_ERROR_STATUS + 0x800000, 62 }; 63 64 /* same as vg20*/ 65 static const int wafl_pcs_err_status_reg_arct[] = { 66 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, 67 smnPCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS + 0x100000, 68 }; 69 70 static const int xgmi23_pcs_err_status_reg_aldebaran[] = { 71 smnPCS_XGMI23_PCS_ERROR_STATUS, 72 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x100000, 73 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x200000, 74 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x300000, 75 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x400000, 76 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x500000, 77 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x600000, 78 smnPCS_XGMI23_PCS_ERROR_STATUS + 0x700000 79 }; 80 81 static const int xgmi3x16_pcs_err_status_reg_aldebaran[] = { 82 smnPCS_XGMI3X16_PCS_ERROR_STATUS, 83 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x100000, 84 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x200000, 85 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x300000, 86 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x400000, 87 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x500000, 88 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x600000, 89 smnPCS_XGMI3X16_PCS_ERROR_STATUS + 0x700000 90 }; 91 92 static const int walf_pcs_err_status_reg_aldebaran[] = { 93 smnPCS_GOPX1_PCS_ERROR_STATUS, 94 smnPCS_GOPX1_PCS_ERROR_STATUS + 0x100000 95 }; 96 97 static const struct amdgpu_pcs_ras_field xgmi_pcs_ras_fields[] = { 98 {"XGMI PCS DataLossErr", 99 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataLossErr)}, 100 {"XGMI PCS TrainingErr", 101 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TrainingErr)}, 102 {"XGMI PCS CRCErr", 103 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, CRCErr)}, 104 {"XGMI PCS BERExceededErr", 105 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, BERExceededErr)}, 106 {"XGMI PCS TxMetaDataErr", 107 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, TxMetaDataErr)}, 108 {"XGMI PCS ReplayBufParityErr", 109 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayBufParityErr)}, 110 {"XGMI PCS DataParityErr", 111 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataParityErr)}, 112 {"XGMI PCS ReplayFifoOverflowErr", 113 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 114 {"XGMI PCS ReplayFifoUnderflowErr", 115 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 116 {"XGMI PCS ElasticFifoOverflowErr", 117 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 118 {"XGMI PCS DeskewErr", 119 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DeskewErr)}, 120 {"XGMI PCS DataStartupLimitErr", 121 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, DataStartupLimitErr)}, 122 {"XGMI PCS FCInitTimeoutErr", 123 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 124 {"XGMI PCS RecoveryTimeoutErr", 125 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 126 {"XGMI PCS ReadySerialTimeoutErr", 127 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 128 {"XGMI PCS ReadySerialAttemptErr", 129 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 130 {"XGMI PCS RecoveryAttemptErr", 131 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 132 {"XGMI PCS RecoveryRelockAttemptErr", 133 SOC15_REG_FIELD(XGMI0_PCS_GOPX16_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 134 }; 135 136 static const struct amdgpu_pcs_ras_field wafl_pcs_ras_fields[] = { 137 {"WAFL PCS DataLossErr", 138 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataLossErr)}, 139 {"WAFL PCS TrainingErr", 140 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TrainingErr)}, 141 {"WAFL PCS CRCErr", 142 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, CRCErr)}, 143 {"WAFL PCS BERExceededErr", 144 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, BERExceededErr)}, 145 {"WAFL PCS TxMetaDataErr", 146 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, TxMetaDataErr)}, 147 {"WAFL PCS ReplayBufParityErr", 148 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayBufParityErr)}, 149 {"WAFL PCS DataParityErr", 150 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataParityErr)}, 151 {"WAFL PCS ReplayFifoOverflowErr", 152 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoOverflowErr)}, 153 {"WAFL PCS ReplayFifoUnderflowErr", 154 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReplayFifoUnderflowErr)}, 155 {"WAFL PCS ElasticFifoOverflowErr", 156 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ElasticFifoOverflowErr)}, 157 {"WAFL PCS DeskewErr", 158 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DeskewErr)}, 159 {"WAFL PCS DataStartupLimitErr", 160 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, DataStartupLimitErr)}, 161 {"WAFL PCS FCInitTimeoutErr", 162 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, FCInitTimeoutErr)}, 163 {"WAFL PCS RecoveryTimeoutErr", 164 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryTimeoutErr)}, 165 {"WAFL PCS ReadySerialTimeoutErr", 166 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialTimeoutErr)}, 167 {"WAFL PCS ReadySerialAttemptErr", 168 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, ReadySerialAttemptErr)}, 169 {"WAFL PCS RecoveryAttemptErr", 170 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryAttemptErr)}, 171 {"WAFL PCS RecoveryRelockAttemptErr", 172 SOC15_REG_FIELD(PCS_GOPX1_0_PCS_GOPX1_PCS_ERROR_STATUS, RecoveryRelockAttemptErr)}, 173 }; 174 175 /** 176 * DOC: AMDGPU XGMI Support 177 * 178 * XGMI is a high speed interconnect that joins multiple GPU cards 179 * into a homogeneous memory space that is organized by a collective 180 * hive ID and individual node IDs, both of which are 64-bit numbers. 181 * 182 * The file xgmi_device_id contains the unique per GPU device ID and 183 * is stored in the /sys/class/drm/card${cardno}/device/ directory. 184 * 185 * Inside the device directory a sub-directory 'xgmi_hive_info' is 186 * created which contains the hive ID and the list of nodes. 187 * 188 * The hive ID is stored in: 189 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/xgmi_hive_id 190 * 191 * The node information is stored in numbered directories: 192 * /sys/class/drm/card${cardno}/device/xgmi_hive_info/node${nodeno}/xgmi_device_id 193 * 194 * Each device has their own xgmi_hive_info direction with a mirror 195 * set of node sub-directories. 196 * 197 * The XGMI memory space is built by contiguously adding the power of 198 * two padded VRAM space from each node to each other. 199 * 200 */ 201 202 static struct attribute amdgpu_xgmi_hive_id = { 203 .name = "xgmi_hive_id", 204 .mode = S_IRUGO 205 }; 206 207 static struct attribute *amdgpu_xgmi_hive_attrs[] = { 208 &amdgpu_xgmi_hive_id, 209 NULL 210 }; 211 212 static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, 213 struct attribute *attr, char *buf) 214 { 215 struct amdgpu_hive_info *hive = container_of( 216 kobj, struct amdgpu_hive_info, kobj); 217 218 if (attr == &amdgpu_xgmi_hive_id) 219 return snprintf(buf, PAGE_SIZE, "%llu\n", hive->hive_id); 220 221 return 0; 222 } 223 224 static void amdgpu_xgmi_hive_release(struct kobject *kobj) 225 { 226 struct amdgpu_hive_info *hive = container_of( 227 kobj, struct amdgpu_hive_info, kobj); 228 229 mutex_destroy(&hive->hive_lock); 230 kfree(hive); 231 } 232 233 static const struct sysfs_ops amdgpu_xgmi_hive_ops = { 234 .show = amdgpu_xgmi_show_attrs, 235 }; 236 237 struct kobj_type amdgpu_xgmi_hive_type = { 238 .release = amdgpu_xgmi_hive_release, 239 .sysfs_ops = &amdgpu_xgmi_hive_ops, 240 .default_attrs = amdgpu_xgmi_hive_attrs, 241 }; 242 243 static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, 244 struct device_attribute *attr, 245 char *buf) 246 { 247 struct drm_device *ddev = dev_get_drvdata(dev); 248 struct amdgpu_device *adev = drm_to_adev(ddev); 249 250 return sysfs_emit(buf, "%llu\n", adev->gmc.xgmi.node_id); 251 252 } 253 254 #define AMDGPU_XGMI_SET_FICAA(o) ((o) | 0x456801) 255 static ssize_t amdgpu_xgmi_show_error(struct device *dev, 256 struct device_attribute *attr, 257 char *buf) 258 { 259 struct drm_device *ddev = dev_get_drvdata(dev); 260 struct amdgpu_device *adev = drm_to_adev(ddev); 261 uint32_t ficaa_pie_ctl_in, ficaa_pie_status_in; 262 uint64_t fica_out; 263 unsigned int error_count = 0; 264 265 ficaa_pie_ctl_in = AMDGPU_XGMI_SET_FICAA(0x200); 266 ficaa_pie_status_in = AMDGPU_XGMI_SET_FICAA(0x208); 267 268 if ((!adev->df.funcs) || 269 (!adev->df.funcs->get_fica) || 270 (!adev->df.funcs->set_fica)) 271 return -EINVAL; 272 273 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_ctl_in); 274 if (fica_out != 0x1f) 275 pr_err("xGMI error counters not enabled!\n"); 276 277 fica_out = adev->df.funcs->get_fica(adev, ficaa_pie_status_in); 278 279 if ((fica_out & 0xffff) == 2) 280 error_count = ((fica_out >> 62) & 0x1) + (fica_out >> 63); 281 282 adev->df.funcs->set_fica(adev, ficaa_pie_status_in, 0, 0); 283 284 return sysfs_emit(buf, "%u\n", error_count); 285 } 286 287 288 static DEVICE_ATTR(xgmi_device_id, S_IRUGO, amdgpu_xgmi_show_device_id, NULL); 289 static DEVICE_ATTR(xgmi_error, S_IRUGO, amdgpu_xgmi_show_error, NULL); 290 291 static int amdgpu_xgmi_sysfs_add_dev_info(struct amdgpu_device *adev, 292 struct amdgpu_hive_info *hive) 293 { 294 int ret = 0; 295 char node[10] = { 0 }; 296 297 /* Create xgmi device id file */ 298 ret = device_create_file(adev->dev, &dev_attr_xgmi_device_id); 299 if (ret) { 300 dev_err(adev->dev, "XGMI: Failed to create device file xgmi_device_id\n"); 301 return ret; 302 } 303 304 /* Create xgmi error file */ 305 ret = device_create_file(adev->dev, &dev_attr_xgmi_error); 306 if (ret) 307 pr_err("failed to create xgmi_error\n"); 308 309 310 /* Create sysfs link to hive info folder on the first device */ 311 if (hive->kobj.parent != (&adev->dev->kobj)) { 312 ret = sysfs_create_link(&adev->dev->kobj, &hive->kobj, 313 "xgmi_hive_info"); 314 if (ret) { 315 dev_err(adev->dev, "XGMI: Failed to create link to hive info"); 316 goto remove_file; 317 } 318 } 319 320 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 321 /* Create sysfs link form the hive folder to yourself */ 322 ret = sysfs_create_link(&hive->kobj, &adev->dev->kobj, node); 323 if (ret) { 324 dev_err(adev->dev, "XGMI: Failed to create link from hive info"); 325 goto remove_link; 326 } 327 328 goto success; 329 330 331 remove_link: 332 sysfs_remove_link(&adev->dev->kobj, adev_to_drm(adev)->unique); 333 334 remove_file: 335 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 336 337 success: 338 return ret; 339 } 340 341 static void amdgpu_xgmi_sysfs_rem_dev_info(struct amdgpu_device *adev, 342 struct amdgpu_hive_info *hive) 343 { 344 char node[10]; 345 memset(node, 0, sizeof(node)); 346 347 device_remove_file(adev->dev, &dev_attr_xgmi_device_id); 348 device_remove_file(adev->dev, &dev_attr_xgmi_error); 349 350 if (hive->kobj.parent != (&adev->dev->kobj)) 351 sysfs_remove_link(&adev->dev->kobj,"xgmi_hive_info"); 352 353 sprintf(node, "node%d", atomic_read(&hive->number_devices)); 354 sysfs_remove_link(&hive->kobj, node); 355 356 } 357 358 359 360 struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) 361 { 362 struct amdgpu_hive_info *hive = NULL; 363 int ret; 364 365 if (!adev->gmc.xgmi.hive_id) 366 return NULL; 367 368 if (adev->hive) { 369 kobject_get(&adev->hive->kobj); 370 return adev->hive; 371 } 372 373 mutex_lock(&xgmi_mutex); 374 375 list_for_each_entry(hive, &xgmi_hive_list, node) { 376 if (hive->hive_id == adev->gmc.xgmi.hive_id) 377 goto pro_end; 378 } 379 380 hive = kzalloc(sizeof(*hive), GFP_KERNEL); 381 if (!hive) { 382 dev_err(adev->dev, "XGMI: allocation failed\n"); 383 hive = NULL; 384 goto pro_end; 385 } 386 387 /* initialize new hive if not exist */ 388 ret = kobject_init_and_add(&hive->kobj, 389 &amdgpu_xgmi_hive_type, 390 &adev->dev->kobj, 391 "%s", "xgmi_hive_info"); 392 if (ret) { 393 dev_err(adev->dev, "XGMI: failed initializing kobject for xgmi hive\n"); 394 kobject_put(&hive->kobj); 395 kfree(hive); 396 hive = NULL; 397 goto pro_end; 398 } 399 400 hive->hive_id = adev->gmc.xgmi.hive_id; 401 INIT_LIST_HEAD(&hive->device_list); 402 INIT_LIST_HEAD(&hive->node); 403 mutex_init(&hive->hive_lock); 404 atomic_set(&hive->in_reset, 0); 405 atomic_set(&hive->number_devices, 0); 406 task_barrier_init(&hive->tb); 407 hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; 408 hive->hi_req_gpu = NULL; 409 /* 410 * hive pstate on boot is high in vega20 so we have to go to low 411 * pstate on after boot. 412 */ 413 hive->hi_req_count = AMDGPU_MAX_XGMI_DEVICE_PER_HIVE; 414 list_add_tail(&hive->node, &xgmi_hive_list); 415 416 pro_end: 417 if (hive) 418 kobject_get(&hive->kobj); 419 mutex_unlock(&xgmi_mutex); 420 return hive; 421 } 422 423 void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive) 424 { 425 if (hive) 426 kobject_put(&hive->kobj); 427 } 428 429 int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate) 430 { 431 int ret = 0; 432 struct amdgpu_hive_info *hive; 433 struct amdgpu_device *request_adev; 434 bool is_hi_req = pstate == AMDGPU_XGMI_PSTATE_MAX_VEGA20; 435 bool init_low; 436 437 hive = amdgpu_get_xgmi_hive(adev); 438 if (!hive) 439 return 0; 440 441 request_adev = hive->hi_req_gpu ? hive->hi_req_gpu : adev; 442 init_low = hive->pstate == AMDGPU_XGMI_PSTATE_UNKNOWN; 443 amdgpu_put_xgmi_hive(hive); 444 /* fw bug so temporarily disable pstate switching */ 445 return 0; 446 447 if (!hive || adev->asic_type != CHIP_VEGA20) 448 return 0; 449 450 mutex_lock(&hive->hive_lock); 451 452 if (is_hi_req) 453 hive->hi_req_count++; 454 else 455 hive->hi_req_count--; 456 457 /* 458 * Vega20 only needs single peer to request pstate high for the hive to 459 * go high but all peers must request pstate low for the hive to go low 460 */ 461 if (hive->pstate == pstate || 462 (!is_hi_req && hive->hi_req_count && !init_low)) 463 goto out; 464 465 dev_dbg(request_adev->dev, "Set xgmi pstate %d.\n", pstate); 466 467 ret = amdgpu_dpm_set_xgmi_pstate(request_adev, pstate); 468 if (ret) { 469 dev_err(request_adev->dev, 470 "XGMI: Set pstate failure on device %llx, hive %llx, ret %d", 471 request_adev->gmc.xgmi.node_id, 472 request_adev->gmc.xgmi.hive_id, ret); 473 goto out; 474 } 475 476 if (init_low) 477 hive->pstate = hive->hi_req_count ? 478 hive->pstate : AMDGPU_XGMI_PSTATE_MIN; 479 else { 480 hive->pstate = pstate; 481 hive->hi_req_gpu = pstate != AMDGPU_XGMI_PSTATE_MIN ? 482 adev : NULL; 483 } 484 out: 485 mutex_unlock(&hive->hive_lock); 486 return ret; 487 } 488 489 int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev) 490 { 491 int ret; 492 493 /* Each psp need to set the latest topology */ 494 ret = psp_xgmi_set_topology_info(&adev->psp, 495 atomic_read(&hive->number_devices), 496 &adev->psp.xgmi_context.top_info); 497 if (ret) 498 dev_err(adev->dev, 499 "XGMI: Set topology failure on device %llx, hive %llx, ret %d", 500 adev->gmc.xgmi.node_id, 501 adev->gmc.xgmi.hive_id, ret); 502 503 return ret; 504 } 505 506 507 /* 508 * NOTE psp_xgmi_node_info.num_hops layout is as follows: 509 * num_hops[7:6] = link type (0 = xGMI2, 1 = xGMI3, 2/3 = reserved) 510 * num_hops[5:3] = reserved 511 * num_hops[2:0] = number of hops 512 */ 513 int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev, 514 struct amdgpu_device *peer_adev) 515 { 516 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 517 uint8_t num_hops_mask = 0x7; 518 int i; 519 520 for (i = 0 ; i < top->num_nodes; ++i) 521 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 522 return top->nodes[i].num_hops & num_hops_mask; 523 return -EINVAL; 524 } 525 526 int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev, 527 struct amdgpu_device *peer_adev) 528 { 529 struct psp_xgmi_topology_info *top = &adev->psp.xgmi_context.top_info; 530 int i; 531 532 for (i = 0 ; i < top->num_nodes; ++i) 533 if (top->nodes[i].node_id == peer_adev->gmc.xgmi.node_id) 534 return top->nodes[i].num_links; 535 return -EINVAL; 536 } 537 538 /* 539 * Devices that support extended data require the entire hive to initialize with 540 * the shared memory buffer flag set. 541 * 542 * Hive locks and conditions apply - see amdgpu_xgmi_add_device 543 */ 544 static int amdgpu_xgmi_initialize_hive_get_data_partition(struct amdgpu_hive_info *hive, 545 bool set_extended_data) 546 { 547 struct amdgpu_device *tmp_adev; 548 int ret; 549 550 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 551 ret = psp_xgmi_initialize(&tmp_adev->psp, set_extended_data, false); 552 if (ret) { 553 dev_err(tmp_adev->dev, 554 "XGMI: Failed to initialize xgmi session for data partition %i\n", 555 set_extended_data); 556 return ret; 557 } 558 559 } 560 561 return 0; 562 } 563 564 int amdgpu_xgmi_add_device(struct amdgpu_device *adev) 565 { 566 struct psp_xgmi_topology_info *top_info; 567 struct amdgpu_hive_info *hive; 568 struct amdgpu_xgmi *entry; 569 struct amdgpu_device *tmp_adev = NULL; 570 571 int count = 0, ret = 0; 572 573 if (!adev->gmc.xgmi.supported) 574 return 0; 575 576 if (!adev->gmc.xgmi.pending_reset && 577 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 578 ret = psp_xgmi_initialize(&adev->psp, false, true); 579 if (ret) { 580 dev_err(adev->dev, 581 "XGMI: Failed to initialize xgmi session\n"); 582 return ret; 583 } 584 585 ret = psp_xgmi_get_hive_id(&adev->psp, &adev->gmc.xgmi.hive_id); 586 if (ret) { 587 dev_err(adev->dev, 588 "XGMI: Failed to get hive id\n"); 589 return ret; 590 } 591 592 ret = psp_xgmi_get_node_id(&adev->psp, &adev->gmc.xgmi.node_id); 593 if (ret) { 594 dev_err(adev->dev, 595 "XGMI: Failed to get node id\n"); 596 return ret; 597 } 598 } else { 599 adev->gmc.xgmi.hive_id = 16; 600 adev->gmc.xgmi.node_id = adev->gmc.xgmi.physical_node_id + 16; 601 } 602 603 hive = amdgpu_get_xgmi_hive(adev); 604 if (!hive) { 605 ret = -EINVAL; 606 dev_err(adev->dev, 607 "XGMI: node 0x%llx, can not match hive 0x%llx in the hive list.\n", 608 adev->gmc.xgmi.node_id, adev->gmc.xgmi.hive_id); 609 goto exit; 610 } 611 mutex_lock(&hive->hive_lock); 612 613 top_info = &adev->psp.xgmi_context.top_info; 614 615 list_add_tail(&adev->gmc.xgmi.head, &hive->device_list); 616 list_for_each_entry(entry, &hive->device_list, head) 617 top_info->nodes[count++].node_id = entry->node_id; 618 top_info->num_nodes = count; 619 atomic_set(&hive->number_devices, count); 620 621 task_barrier_add_task(&hive->tb); 622 623 if (!adev->gmc.xgmi.pending_reset && 624 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { 625 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 626 /* update node list for other device in the hive */ 627 if (tmp_adev != adev) { 628 top_info = &tmp_adev->psp.xgmi_context.top_info; 629 top_info->nodes[count - 1].node_id = 630 adev->gmc.xgmi.node_id; 631 top_info->num_nodes = count; 632 } 633 ret = amdgpu_xgmi_update_topology(hive, tmp_adev); 634 if (ret) 635 goto exit_unlock; 636 } 637 638 /* get latest topology info for each device from psp */ 639 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 640 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 641 &tmp_adev->psp.xgmi_context.top_info, false); 642 if (ret) { 643 dev_err(tmp_adev->dev, 644 "XGMI: Get topology failure on device %llx, hive %llx, ret %d", 645 tmp_adev->gmc.xgmi.node_id, 646 tmp_adev->gmc.xgmi.hive_id, ret); 647 /* To do : continue with some node failed or disable the whole hive */ 648 goto exit_unlock; 649 } 650 } 651 652 /* get topology again for hives that support extended data */ 653 if (adev->psp.xgmi_context.supports_extended_data) { 654 655 /* initialize the hive to get extended data. */ 656 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, true); 657 if (ret) 658 goto exit_unlock; 659 660 /* get the extended data. */ 661 list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { 662 ret = psp_xgmi_get_topology_info(&tmp_adev->psp, count, 663 &tmp_adev->psp.xgmi_context.top_info, true); 664 if (ret) { 665 dev_err(tmp_adev->dev, 666 "XGMI: Get topology for extended data failure on device %llx, hive %llx, ret %d", 667 tmp_adev->gmc.xgmi.node_id, 668 tmp_adev->gmc.xgmi.hive_id, ret); 669 goto exit_unlock; 670 } 671 } 672 673 /* initialize the hive to get non-extended data for the next round. */ 674 ret = amdgpu_xgmi_initialize_hive_get_data_partition(hive, false); 675 if (ret) 676 goto exit_unlock; 677 678 } 679 } 680 681 if (!ret && !adev->gmc.xgmi.pending_reset) 682 ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); 683 684 exit_unlock: 685 mutex_unlock(&hive->hive_lock); 686 exit: 687 if (!ret) { 688 adev->hive = hive; 689 dev_info(adev->dev, "XGMI: Add node %d, hive 0x%llx.\n", 690 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id); 691 } else { 692 amdgpu_put_xgmi_hive(hive); 693 dev_err(adev->dev, "XGMI: Failed to add node %d, hive 0x%llx ret: %d\n", 694 adev->gmc.xgmi.physical_node_id, adev->gmc.xgmi.hive_id, 695 ret); 696 } 697 698 return ret; 699 } 700 701 int amdgpu_xgmi_remove_device(struct amdgpu_device *adev) 702 { 703 struct amdgpu_hive_info *hive = adev->hive; 704 705 if (!adev->gmc.xgmi.supported) 706 return -EINVAL; 707 708 if (!hive) 709 return -EINVAL; 710 711 mutex_lock(&hive->hive_lock); 712 task_barrier_rem_task(&hive->tb); 713 amdgpu_xgmi_sysfs_rem_dev_info(adev, hive); 714 if (hive->hi_req_gpu == adev) 715 hive->hi_req_gpu = NULL; 716 list_del(&adev->gmc.xgmi.head); 717 mutex_unlock(&hive->hive_lock); 718 719 amdgpu_put_xgmi_hive(hive); 720 adev->hive = NULL; 721 722 if (atomic_dec_return(&hive->number_devices) == 0) { 723 /* Remove the hive from global hive list */ 724 mutex_lock(&xgmi_mutex); 725 list_del(&hive->node); 726 mutex_unlock(&xgmi_mutex); 727 728 amdgpu_put_xgmi_hive(hive); 729 } 730 731 return psp_xgmi_terminate(&adev->psp); 732 } 733 734 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev) 735 { 736 int r; 737 struct ras_ih_if ih_info = { 738 .cb = NULL, 739 }; 740 struct ras_fs_if fs_info = { 741 .sysfs_name = "xgmi_wafl_err_count", 742 }; 743 744 if (!adev->gmc.xgmi.supported || 745 adev->gmc.xgmi.num_physical_nodes == 0) 746 return 0; 747 748 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 749 750 if (!adev->gmc.xgmi.ras_if) { 751 adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL); 752 if (!adev->gmc.xgmi.ras_if) 753 return -ENOMEM; 754 adev->gmc.xgmi.ras_if->block = AMDGPU_RAS_BLOCK__XGMI_WAFL; 755 adev->gmc.xgmi.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; 756 adev->gmc.xgmi.ras_if->sub_block_index = 0; 757 } 758 ih_info.head = fs_info.head = *adev->gmc.xgmi.ras_if; 759 r = amdgpu_ras_late_init(adev, adev->gmc.xgmi.ras_if, 760 &fs_info, &ih_info); 761 if (r || !amdgpu_ras_is_supported(adev, adev->gmc.xgmi.ras_if->block)) { 762 kfree(adev->gmc.xgmi.ras_if); 763 adev->gmc.xgmi.ras_if = NULL; 764 } 765 766 return r; 767 } 768 769 static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev) 770 { 771 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) && 772 adev->gmc.xgmi.ras_if) { 773 struct ras_common_if *ras_if = adev->gmc.xgmi.ras_if; 774 struct ras_ih_if ih_info = { 775 .cb = NULL, 776 }; 777 778 amdgpu_ras_late_fini(adev, ras_if, &ih_info); 779 kfree(ras_if); 780 } 781 } 782 783 uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev, 784 uint64_t addr) 785 { 786 struct amdgpu_xgmi *xgmi = &adev->gmc.xgmi; 787 return (addr + xgmi->physical_node_id * xgmi->node_segment_size); 788 } 789 790 static void pcs_clear_status(struct amdgpu_device *adev, uint32_t pcs_status_reg) 791 { 792 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); 793 WREG32_PCIE(pcs_status_reg, 0); 794 } 795 796 static void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev) 797 { 798 uint32_t i; 799 800 switch (adev->asic_type) { 801 case CHIP_ARCTURUS: 802 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) 803 pcs_clear_status(adev, 804 xgmi_pcs_err_status_reg_arct[i]); 805 break; 806 case CHIP_VEGA20: 807 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) 808 pcs_clear_status(adev, 809 xgmi_pcs_err_status_reg_vg20[i]); 810 break; 811 case CHIP_ALDEBARAN: 812 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) 813 pcs_clear_status(adev, 814 xgmi23_pcs_err_status_reg_aldebaran[i]); 815 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) 816 pcs_clear_status(adev, 817 xgmi3x16_pcs_err_status_reg_aldebaran[i]); 818 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) 819 pcs_clear_status(adev, 820 walf_pcs_err_status_reg_aldebaran[i]); 821 break; 822 default: 823 break; 824 } 825 } 826 827 static int amdgpu_xgmi_query_pcs_error_status(struct amdgpu_device *adev, 828 uint32_t value, 829 uint32_t *ue_count, 830 uint32_t *ce_count, 831 bool is_xgmi_pcs) 832 { 833 int i; 834 int ue_cnt; 835 836 if (is_xgmi_pcs) { 837 /* query xgmi pcs error status, 838 * only ue is supported */ 839 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_ras_fields); i ++) { 840 ue_cnt = (value & 841 xgmi_pcs_ras_fields[i].pcs_err_mask) >> 842 xgmi_pcs_ras_fields[i].pcs_err_shift; 843 if (ue_cnt) { 844 dev_info(adev->dev, "%s detected\n", 845 xgmi_pcs_ras_fields[i].err_name); 846 *ue_count += ue_cnt; 847 } 848 } 849 } else { 850 /* query wafl pcs error status, 851 * only ue is supported */ 852 for (i = 0; i < ARRAY_SIZE(wafl_pcs_ras_fields); i++) { 853 ue_cnt = (value & 854 wafl_pcs_ras_fields[i].pcs_err_mask) >> 855 wafl_pcs_ras_fields[i].pcs_err_shift; 856 if (ue_cnt) { 857 dev_info(adev->dev, "%s detected\n", 858 wafl_pcs_ras_fields[i].err_name); 859 *ue_count += ue_cnt; 860 } 861 } 862 } 863 864 return 0; 865 } 866 867 static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev, 868 void *ras_error_status) 869 { 870 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; 871 int i; 872 uint32_t data; 873 uint32_t ue_cnt = 0, ce_cnt = 0; 874 875 if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL)) 876 return -EINVAL; 877 878 err_data->ue_count = 0; 879 err_data->ce_count = 0; 880 881 switch (adev->asic_type) { 882 case CHIP_ARCTURUS: 883 /* check xgmi pcs error */ 884 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_arct); i++) { 885 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); 886 if (data) 887 amdgpu_xgmi_query_pcs_error_status(adev, 888 data, &ue_cnt, &ce_cnt, true); 889 } 890 /* check wafl pcs error */ 891 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_arct); i++) { 892 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); 893 if (data) 894 amdgpu_xgmi_query_pcs_error_status(adev, 895 data, &ue_cnt, &ce_cnt, false); 896 } 897 break; 898 case CHIP_VEGA20: 899 /* check xgmi pcs error */ 900 for (i = 0; i < ARRAY_SIZE(xgmi_pcs_err_status_reg_vg20); i++) { 901 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); 902 if (data) 903 amdgpu_xgmi_query_pcs_error_status(adev, 904 data, &ue_cnt, &ce_cnt, true); 905 } 906 /* check wafl pcs error */ 907 for (i = 0; i < ARRAY_SIZE(wafl_pcs_err_status_reg_vg20); i++) { 908 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); 909 if (data) 910 amdgpu_xgmi_query_pcs_error_status(adev, 911 data, &ue_cnt, &ce_cnt, false); 912 } 913 break; 914 case CHIP_ALDEBARAN: 915 /* check xgmi23 pcs error */ 916 for (i = 0; i < ARRAY_SIZE(xgmi23_pcs_err_status_reg_aldebaran); i++) { 917 data = RREG32_PCIE(xgmi23_pcs_err_status_reg_aldebaran[i]); 918 if (data) 919 amdgpu_xgmi_query_pcs_error_status(adev, 920 data, &ue_cnt, &ce_cnt, true); 921 } 922 /* check xgmi3x16 pcs error */ 923 for (i = 0; i < ARRAY_SIZE(xgmi3x16_pcs_err_status_reg_aldebaran); i++) { 924 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); 925 if (data) 926 amdgpu_xgmi_query_pcs_error_status(adev, 927 data, &ue_cnt, &ce_cnt, true); 928 } 929 /* check wafl pcs error */ 930 for (i = 0; i < ARRAY_SIZE(walf_pcs_err_status_reg_aldebaran); i++) { 931 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); 932 if (data) 933 amdgpu_xgmi_query_pcs_error_status(adev, 934 data, &ue_cnt, &ce_cnt, false); 935 } 936 break; 937 default: 938 dev_warn(adev->dev, "XGMI RAS error query not supported"); 939 break; 940 } 941 942 adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev); 943 944 err_data->ue_count += ue_cnt; 945 err_data->ce_count += ce_cnt; 946 947 return 0; 948 } 949 950 const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = { 951 .ras_late_init = amdgpu_xgmi_ras_late_init, 952 .ras_fini = amdgpu_xgmi_ras_fini, 953 .query_ras_error_count = amdgpu_xgmi_query_ras_error_count, 954 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count, 955 }; 956