1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef AMDGPU_XCP_H
25 #define AMDGPU_XCP_H
26 
27 #include <linux/xarray.h>
28 
29 #define MAX_XCP 8
30 
31 #define AMDGPU_XCP_MODE_NONE -1
32 
33 enum AMDGPU_XCP_IP_BLOCK {
34 	AMDGPU_XCP_GFXHUB,
35 	AMDGPU_XCP_GFX,
36 	AMDGPU_XCP_SDMA,
37 	AMDGPU_XCP_VCN,
38 	AMDGPU_XCP_MAX_BLOCKS
39 };
40 
41 enum AMDGPU_XCP_STATE {
42 	AMDGPU_XCP_PREPARE_SUSPEND,
43 	AMDGPU_XCP_SUSPEND,
44 	AMDGPU_XCP_PREPARE_RESUME,
45 	AMDGPU_XCP_RESUME,
46 };
47 
48 struct amdgpu_xcp_ip_funcs {
49 	int (*prepare_suspend)(void *handle, uint32_t inst_mask);
50 	int (*suspend)(void *handle, uint32_t inst_mask);
51 	int (*prepare_resume)(void *handle, uint32_t inst_mask);
52 	int (*resume)(void *handle, uint32_t inst_mask);
53 };
54 
55 struct amdgpu_xcp_ip {
56 	struct amdgpu_xcp_ip_funcs *ip_funcs;
57 	uint32_t inst_mask;
58 
59 	enum AMDGPU_XCP_IP_BLOCK ip_id;
60 	bool valid;
61 };
62 
63 struct amdgpu_xcp {
64 	struct amdgpu_xcp_ip ip[AMDGPU_XCP_MAX_BLOCKS];
65 
66 	uint8_t id;
67 	uint8_t mem_node;
68 	bool valid;
69 };
70 
71 struct amdgpu_xcp_mgr {
72 	struct amdgpu_device *adev;
73 	struct mutex xcp_lock;
74 	struct amdgpu_xcp_mgr_funcs *funcs;
75 
76 	struct amdgpu_xcp xcp[MAX_XCP];
77 	uint8_t num_xcps;
78 	int8_t mode;
79 };
80 
81 struct amdgpu_xcp_mgr_funcs {
82 	int (*switch_partition_mode)(struct amdgpu_xcp_mgr *xcp_mgr, int mode,
83 				     int *num_xcps);
84 	int (*query_partition_mode)(struct amdgpu_xcp_mgr *xcp_mgr);
85 	int (*get_ip_details)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id,
86 			      enum AMDGPU_XCP_IP_BLOCK ip_id,
87 			      struct amdgpu_xcp_ip *ip);
88 
89 	int (*prepare_suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
90 	int (*suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
91 	int (*prepare_resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
92 	int (*resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
93 };
94 
95 int amdgpu_xcp_prepare_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
96 int amdgpu_xcp_suspend(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
97 int amdgpu_xcp_prepare_resume(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
98 int amdgpu_xcp_resume(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id);
99 
100 int amdgpu_xcp_mgr_init(struct amdgpu_device *adev, int init_mode,
101 			int init_xcps, struct amdgpu_xcp_mgr_funcs *xcp_funcs);
102 int amdgpu_xcp_query_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr);
103 int amdgpu_xcp_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, int mode);
104 int amdgpu_xcp_get_partition(struct amdgpu_xcp_mgr *xcp_mgr,
105 			     enum AMDGPU_XCP_IP_BLOCK ip, int instance);
106 
107 #endif
108