1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_vm.h" 24 #include "amdgpu_job.h" 25 #include "amdgpu_object.h" 26 #include "amdgpu_trace.h" 27 28 #define AMDGPU_VM_SDMA_MIN_NUM_DW 256u 29 #define AMDGPU_VM_SDMA_MAX_NUM_DW (16u * 1024u) 30 31 /** 32 * amdgpu_vm_sdma_map_table - make sure new PDs/PTs are GTT mapped 33 * 34 * @table: newly allocated or validated PD/PT 35 */ 36 static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) 37 { 38 int r; 39 40 r = amdgpu_ttm_alloc_gart(&table->bo.tbo); 41 if (r) 42 return r; 43 44 if (table->shadow) 45 r = amdgpu_ttm_alloc_gart(&table->shadow->tbo); 46 47 return r; 48 } 49 50 /** 51 * amdgpu_vm_sdma_prepare - prepare SDMA command submission 52 * 53 * @p: see amdgpu_vm_update_params definition 54 * @resv: reservation object with embedded fence 55 * @sync_mode: synchronization mode 56 * 57 * Returns: 58 * Negativ errno, 0 for success. 59 */ 60 static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, 61 struct dma_resv *resv, 62 enum amdgpu_sync_mode sync_mode) 63 { 64 enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE 65 : AMDGPU_IB_POOL_DELAYED; 66 unsigned int ndw = AMDGPU_VM_SDMA_MIN_NUM_DW; 67 int r; 68 69 r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, pool, &p->job); 70 if (r) 71 return r; 72 73 p->num_dw_left = ndw; 74 75 if (!resv) 76 return 0; 77 78 return amdgpu_sync_resv(p->adev, &p->job->sync, resv, sync_mode, p->vm); 79 } 80 81 /** 82 * amdgpu_vm_sdma_commit - commit SDMA command submission 83 * 84 * @p: see amdgpu_vm_update_params definition 85 * @fence: resulting fence 86 * 87 * Returns: 88 * Negativ errno, 0 for success. 89 */ 90 static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, 91 struct dma_fence **fence) 92 { 93 struct amdgpu_ib *ib = p->job->ibs; 94 struct drm_sched_entity *entity; 95 struct amdgpu_ring *ring; 96 struct dma_fence *f; 97 int r; 98 99 entity = p->immediate ? &p->vm->immediate : &p->vm->delayed; 100 ring = container_of(entity->rq->sched, struct amdgpu_ring, sched); 101 102 WARN_ON(ib->length_dw == 0); 103 amdgpu_ring_pad_ib(ring, ib); 104 WARN_ON(ib->length_dw > p->num_dw_left); 105 r = amdgpu_job_submit(p->job, entity, AMDGPU_FENCE_OWNER_VM, &f); 106 if (r) 107 goto error; 108 109 if (p->unlocked) { 110 struct dma_fence *tmp = dma_fence_get(f); 111 112 swap(p->vm->last_unlocked, tmp); 113 dma_fence_put(tmp); 114 } else { 115 dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, 116 DMA_RESV_USAGE_BOOKKEEP); 117 } 118 119 if (fence && !p->immediate) 120 swap(*fence, f); 121 dma_fence_put(f); 122 return 0; 123 124 error: 125 amdgpu_job_free(p->job); 126 return r; 127 } 128 129 /** 130 * amdgpu_vm_sdma_copy_ptes - copy the PTEs from mapping 131 * 132 * @p: see amdgpu_vm_update_params definition 133 * @bo: PD/PT to update 134 * @pe: addr of the page entry 135 * @count: number of page entries to copy 136 * 137 * Traces the parameters and calls the DMA function to copy the PTEs. 138 */ 139 static void amdgpu_vm_sdma_copy_ptes(struct amdgpu_vm_update_params *p, 140 struct amdgpu_bo *bo, uint64_t pe, 141 unsigned count) 142 { 143 struct amdgpu_ib *ib = p->job->ibs; 144 uint64_t src = ib->gpu_addr; 145 146 src += p->num_dw_left * 4; 147 148 pe += amdgpu_gmc_sign_extend(amdgpu_bo_gpu_offset_no_check(bo)); 149 trace_amdgpu_vm_copy_ptes(pe, src, count, p->immediate); 150 151 amdgpu_vm_copy_pte(p->adev, ib, pe, src, count); 152 } 153 154 /** 155 * amdgpu_vm_sdma_set_ptes - helper to call the right asic function 156 * 157 * @p: see amdgpu_vm_update_params definition 158 * @bo: PD/PT to update 159 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB 160 * @addr: dst addr to write into pe 161 * @count: number of page entries to update 162 * @incr: increase next addr by incr bytes 163 * @flags: hw access flags 164 * 165 * Traces the parameters and calls the right asic functions 166 * to setup the page table using the DMA. 167 */ 168 static void amdgpu_vm_sdma_set_ptes(struct amdgpu_vm_update_params *p, 169 struct amdgpu_bo *bo, uint64_t pe, 170 uint64_t addr, unsigned count, 171 uint32_t incr, uint64_t flags) 172 { 173 struct amdgpu_ib *ib = p->job->ibs; 174 175 pe += amdgpu_gmc_sign_extend(amdgpu_bo_gpu_offset_no_check(bo)); 176 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags, p->immediate); 177 if (count < 3) { 178 amdgpu_vm_write_pte(p->adev, ib, pe, addr | flags, 179 count, incr); 180 } else { 181 amdgpu_vm_set_pte_pde(p->adev, ib, pe, addr, 182 count, incr, flags); 183 } 184 } 185 186 /** 187 * amdgpu_vm_sdma_update - execute VM update 188 * 189 * @p: see amdgpu_vm_update_params definition 190 * @vmbo: PD/PT to update 191 * @pe: byte offset of the PDE/PTE, relative to start of PDB/PTB 192 * @addr: dst addr to write into pe 193 * @count: number of page entries to update 194 * @incr: increase next addr by incr bytes 195 * @flags: hw access flags 196 * 197 * Reserve space in the IB, setup mapping buffer on demand and write commands to 198 * the IB. 199 */ 200 static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, 201 struct amdgpu_bo_vm *vmbo, uint64_t pe, 202 uint64_t addr, unsigned count, uint32_t incr, 203 uint64_t flags) 204 { 205 struct amdgpu_bo *bo = &vmbo->bo; 206 enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE 207 : AMDGPU_IB_POOL_DELAYED; 208 struct dma_resv_iter cursor; 209 unsigned int i, ndw, nptes; 210 struct dma_fence *fence; 211 uint64_t *pte; 212 int r; 213 214 /* Wait for PD/PT moves to be completed */ 215 dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); 216 dma_resv_for_each_fence_unlocked(&cursor, fence) { 217 r = amdgpu_sync_fence(&p->job->sync, fence); 218 if (r) { 219 dma_resv_iter_end(&cursor); 220 return r; 221 } 222 } 223 dma_resv_iter_end(&cursor); 224 225 do { 226 ndw = p->num_dw_left; 227 ndw -= p->job->ibs->length_dw; 228 229 if (ndw < 32) { 230 r = amdgpu_vm_sdma_commit(p, NULL); 231 if (r) 232 return r; 233 234 /* estimate how many dw we need */ 235 ndw = 32; 236 if (p->pages_addr) 237 ndw += count * 2; 238 ndw = max(ndw, AMDGPU_VM_SDMA_MIN_NUM_DW); 239 ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW); 240 241 r = amdgpu_job_alloc_with_ib(p->adev, ndw * 4, pool, 242 &p->job); 243 if (r) 244 return r; 245 246 p->num_dw_left = ndw; 247 } 248 249 if (!p->pages_addr) { 250 /* set page commands needed */ 251 if (vmbo->shadow) 252 amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr, 253 count, incr, flags); 254 amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, 255 incr, flags); 256 return 0; 257 } 258 259 /* copy commands needed */ 260 ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * 261 (vmbo->shadow ? 2 : 1); 262 263 /* for padding */ 264 ndw -= 7; 265 266 nptes = min(count, ndw / 2); 267 268 /* Put the PTEs at the end of the IB. */ 269 p->num_dw_left -= nptes * 2; 270 pte = (uint64_t *)&(p->job->ibs->ptr[p->num_dw_left]); 271 for (i = 0; i < nptes; ++i, addr += incr) { 272 pte[i] = amdgpu_vm_map_gart(p->pages_addr, addr); 273 pte[i] |= flags; 274 } 275 276 if (vmbo->shadow) 277 amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes); 278 amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); 279 280 pe += nptes * 8; 281 count -= nptes; 282 } while (count); 283 284 return 0; 285 } 286 287 const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs = { 288 .map_table = amdgpu_vm_sdma_map_table, 289 .prepare = amdgpu_vm_sdma_prepare, 290 .update = amdgpu_vm_sdma_update, 291 .commit = amdgpu_vm_sdma_commit 292 }; 293