1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "amdgpu_vm.h"
24 #include "amdgpu_object.h"
25 #include "amdgpu_trace.h"
26 
27 /**
28  * amdgpu_vm_cpu_map_table - make sure new PDs/PTs are kmapped
29  *
30  * @table: newly allocated or validated PD/PT
31  */
32 static int amdgpu_vm_cpu_map_table(struct amdgpu_bo *table)
33 {
34 	return amdgpu_bo_kmap(table, NULL);
35 }
36 
37 /**
38  * amdgpu_vm_cpu_prepare - prepare page table update with the CPU
39  *
40  * @p: see amdgpu_vm_update_params definition
41  * @owner: owner we need to sync to
42  * @exclusive: exclusive move fence we need to sync to
43  *
44  * Returns:
45  * Negativ errno, 0 for success.
46  */
47 static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, void *owner,
48 				 struct dma_fence *exclusive)
49 {
50 	int r;
51 
52 	/* Wait for PT BOs to be idle. PTs share the same resv. object
53 	 * as the root PD BO
54 	 */
55 	r = amdgpu_bo_sync_wait(p->vm->root.base.bo, owner, true);
56 	if (unlikely(r))
57 		return r;
58 
59 	/* Wait for any BO move to be completed */
60 	if (exclusive) {
61 		r = dma_fence_wait(exclusive, true);
62 		if (unlikely(r))
63 			return r;
64 	}
65 
66 	return 0;
67 }
68 
69 /**
70  * amdgpu_vm_cpu_update - helper to update page tables via CPU
71  *
72  * @p: see amdgpu_vm_update_params definition
73  * @bo: PD/PT to update
74  * @pe: kmap addr of the page entry
75  * @addr: dst addr to write into pe
76  * @count: number of page entries to update
77  * @incr: increase next addr by incr bytes
78  * @flags: hw access flags
79  *
80  * Write count number of PT/PD entries directly.
81  */
82 static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p,
83 				struct amdgpu_bo *bo, uint64_t pe,
84 				uint64_t addr, unsigned count, uint32_t incr,
85 				uint64_t flags)
86 {
87 	unsigned int i;
88 	uint64_t value;
89 
90 	pe += (unsigned long)amdgpu_bo_kptr(bo);
91 
92 	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
93 
94 	for (i = 0; i < count; i++) {
95 		value = p->pages_addr ?
96 			amdgpu_vm_map_gart(p->pages_addr, addr) :
97 			addr;
98 		amdgpu_gmc_set_pte_pde(p->adev, (void *)(uintptr_t)pe,
99 				       i, value, flags);
100 		addr += incr;
101 	}
102 	return 0;
103 }
104 
105 /**
106  * amdgpu_vm_cpu_commit - commit page table update to the HW
107  *
108  * @p: see amdgpu_vm_update_params definition
109  * @fence: unused
110  *
111  * Make sure that the hardware sees the page table updates.
112  */
113 static int amdgpu_vm_cpu_commit(struct amdgpu_vm_update_params *p,
114 				struct dma_fence **fence)
115 {
116 	/* Flush HDP */
117 	mb();
118 	amdgpu_asic_flush_hdp(p->adev, NULL);
119 	return 0;
120 }
121 
122 const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs = {
123 	.map_table = amdgpu_vm_cpu_map_table,
124 	.prepare = amdgpu_vm_cpu_prepare,
125 	.update = amdgpu_vm_cpu_update,
126 	.commit = amdgpu_vm_cpu_commit
127 };
128