1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/rbtree.h> 28 #include <linux/idr.h> 29 30 #include "gpu_scheduler.h" 31 #include "amdgpu_sync.h" 32 #include "amdgpu_ring.h" 33 34 struct amdgpu_bo_va; 35 struct amdgpu_job; 36 struct amdgpu_bo_list_entry; 37 38 /* 39 * GPUVM handling 40 */ 41 42 /* maximum number of VMIDs */ 43 #define AMDGPU_NUM_VM 16 44 45 /* Maximum number of PTEs the hardware can write with one command */ 46 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 47 48 /* number of entries in page table */ 49 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 50 51 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 52 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 53 54 #define AMDGPU_PTE_VALID (1ULL << 0) 55 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 56 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 57 58 /* VI only */ 59 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 60 61 #define AMDGPU_PTE_READABLE (1ULL << 5) 62 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 63 64 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 65 66 /* TILED for VEGA10, reserved for older ASICs */ 67 #define AMDGPU_PTE_PRT (1ULL << 51) 68 69 /* PDE is handled as PTE for VEGA10 */ 70 #define AMDGPU_PDE_PTE (1ULL << 54) 71 72 /* VEGA10 only */ 73 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) 74 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) 75 76 /* For Raven */ 77 #define AMDGPU_MTYPE_CC 2 78 79 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 80 | AMDGPU_PTE_SNOOPED \ 81 | AMDGPU_PTE_EXECUTABLE \ 82 | AMDGPU_PTE_READABLE \ 83 | AMDGPU_PTE_WRITEABLE \ 84 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) 85 86 /* How to programm VM fault handling */ 87 #define AMDGPU_VM_FAULT_STOP_NEVER 0 88 #define AMDGPU_VM_FAULT_STOP_FIRST 1 89 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 90 91 /* max number of VMHUB */ 92 #define AMDGPU_MAX_VMHUBS 2 93 #define AMDGPU_GFXHUB 0 94 #define AMDGPU_MMHUB 1 95 96 /* hardcode that limit for now */ 97 #define AMDGPU_VA_RESERVED_SIZE (8ULL << 20) 98 99 /* VA hole for 48bit addresses on Vega10 */ 100 #define AMDGPU_VA_HOLE_START 0x0000800000000000ULL 101 #define AMDGPU_VA_HOLE_END 0xffff800000000000ULL 102 103 /* 104 * Hardware is programmed as if the hole doesn't exists with start and end 105 * address values. 106 * 107 * This mask is used to remove the upper 16bits of the VA and so come up with 108 * the linear addr value. 109 */ 110 #define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL 111 112 /* max vmids dedicated for process */ 113 #define AMDGPU_VM_MAX_RESERVED_VMID 1 114 115 #define AMDGPU_VM_CONTEXT_GFX 0 116 #define AMDGPU_VM_CONTEXT_COMPUTE 1 117 118 /* See vm_update_mode */ 119 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 120 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 121 122 /* base structure for tracking BO usage in a VM */ 123 struct amdgpu_vm_bo_base { 124 /* constant after initialization */ 125 struct amdgpu_vm *vm; 126 struct amdgpu_bo *bo; 127 128 /* protected by bo being reserved */ 129 struct list_head bo_list; 130 131 /* protected by spinlock */ 132 struct list_head vm_status; 133 134 /* protected by the BO being reserved */ 135 bool moved; 136 }; 137 138 struct amdgpu_vm_pt { 139 struct amdgpu_vm_bo_base base; 140 uint64_t addr; 141 142 /* array of page tables, one for each directory entry */ 143 struct amdgpu_vm_pt *entries; 144 unsigned last_entry_used; 145 }; 146 147 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) 148 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48) 149 #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL) 150 151 struct amdgpu_vm { 152 /* tree of virtual addresses mapped */ 153 struct rb_root_cached va; 154 155 /* protecting invalidated */ 156 spinlock_t status_lock; 157 158 /* BOs who needs a validation */ 159 struct list_head evicted; 160 161 /* PT BOs which relocated and their parent need an update */ 162 struct list_head relocated; 163 164 /* BOs moved, but not yet updated in the PT */ 165 struct list_head moved; 166 167 /* BO mappings freed, but not yet updated in the PT */ 168 struct list_head freed; 169 170 /* contains the page directory */ 171 struct amdgpu_vm_pt root; 172 struct dma_fence *last_update; 173 174 /* protecting freed */ 175 spinlock_t freed_lock; 176 177 /* Scheduler entity for page table updates */ 178 struct amd_sched_entity entity; 179 180 /* client id and PASID (TODO: replace client_id with PASID) */ 181 u64 client_id; 182 unsigned int pasid; 183 /* dedicated to vm */ 184 struct amdgpu_vm_id *reserved_vmid[AMDGPU_MAX_VMHUBS]; 185 186 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 187 bool use_cpu_for_update; 188 189 /* Flag to indicate ATS support from PTE for GFX9 */ 190 bool pte_support_ats; 191 192 /* Up to 128 pending retry page faults */ 193 DECLARE_KFIFO(faults, u64, 128); 194 195 /* Limit non-retry fault storms */ 196 unsigned int fault_credit; 197 }; 198 199 struct amdgpu_vm_id { 200 struct list_head list; 201 struct amdgpu_sync active; 202 struct dma_fence *last_flush; 203 atomic64_t owner; 204 205 uint64_t pd_gpu_addr; 206 /* last flushed PD/PT update */ 207 struct dma_fence *flushed_updates; 208 209 uint32_t current_gpu_reset_count; 210 211 uint32_t gds_base; 212 uint32_t gds_size; 213 uint32_t gws_base; 214 uint32_t gws_size; 215 uint32_t oa_base; 216 uint32_t oa_size; 217 }; 218 219 struct amdgpu_vm_id_manager { 220 struct mutex lock; 221 unsigned num_ids; 222 struct list_head ids_lru; 223 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 224 atomic_t reserved_vmid_num; 225 }; 226 227 struct amdgpu_vm_manager { 228 /* Handling of VMIDs */ 229 struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS]; 230 231 /* Handling of VM fences */ 232 u64 fence_context; 233 unsigned seqno[AMDGPU_MAX_RINGS]; 234 235 uint64_t max_pfn; 236 uint32_t num_level; 237 uint32_t block_size; 238 uint32_t fragment_size; 239 /* vram base address for page table entry */ 240 u64 vram_base_offset; 241 /* vm pte handling */ 242 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 243 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 244 unsigned vm_pte_num_rings; 245 atomic_t vm_pte_next_ring; 246 /* client id counter */ 247 atomic64_t client_counter; 248 249 /* partial resident texture handling */ 250 spinlock_t prt_lock; 251 atomic_t num_prt_users; 252 253 /* controls how VM page tables are updated for Graphics and Compute. 254 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 255 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 256 */ 257 int vm_update_mode; 258 259 /* PASID to VM mapping, will be used in interrupt context to 260 * look up VM of a page fault 261 */ 262 struct idr pasid_idr; 263 spinlock_t pasid_lock; 264 }; 265 266 int amdgpu_vm_alloc_pasid(unsigned int bits); 267 void amdgpu_vm_free_pasid(unsigned int pasid); 268 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 269 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 270 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 271 int vm_context, unsigned int pasid); 272 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 273 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, 274 unsigned int pasid); 275 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 276 struct list_head *validated, 277 struct amdgpu_bo_list_entry *entry); 278 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 279 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 280 int (*callback)(void *p, struct amdgpu_bo *bo), 281 void *param); 282 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, 283 struct amdgpu_vm *vm, 284 uint64_t saddr, uint64_t size); 285 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 286 struct amdgpu_sync *sync, struct dma_fence *fence, 287 struct amdgpu_job *job); 288 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 289 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, 290 unsigned vmid); 291 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev); 292 int amdgpu_vm_update_directories(struct amdgpu_device *adev, 293 struct amdgpu_vm *vm); 294 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 295 struct amdgpu_vm *vm, 296 struct dma_fence **fence); 297 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 298 struct amdgpu_vm *vm); 299 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 300 struct amdgpu_bo_va *bo_va, 301 bool clear); 302 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 303 struct amdgpu_bo *bo, bool evicted); 304 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 305 struct amdgpu_bo *bo); 306 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 307 struct amdgpu_vm *vm, 308 struct amdgpu_bo *bo); 309 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 310 struct amdgpu_bo_va *bo_va, 311 uint64_t addr, uint64_t offset, 312 uint64_t size, uint64_t flags); 313 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 314 struct amdgpu_bo_va *bo_va, 315 uint64_t addr, uint64_t offset, 316 uint64_t size, uint64_t flags); 317 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 318 struct amdgpu_bo_va *bo_va, 319 uint64_t addr); 320 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 321 struct amdgpu_vm *vm, 322 uint64_t saddr, uint64_t size); 323 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 324 uint64_t addr); 325 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 326 struct amdgpu_bo_va *bo_va); 327 void amdgpu_vm_set_fragment_size(struct amdgpu_device *adev, 328 uint32_t fragment_size_default); 329 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, 330 uint32_t fragment_size_default); 331 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 332 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 333 struct amdgpu_job *job); 334 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 335 336 #endif 337