1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/rbtree.h> 28 29 #include "gpu_scheduler.h" 30 #include "amdgpu_sync.h" 31 #include "amdgpu_ring.h" 32 33 struct amdgpu_bo_va; 34 struct amdgpu_job; 35 struct amdgpu_bo_list_entry; 36 37 /* 38 * GPUVM handling 39 */ 40 41 /* maximum number of VMIDs */ 42 #define AMDGPU_NUM_VM 16 43 44 /* Maximum number of PTEs the hardware can write with one command */ 45 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 46 47 /* number of entries in page table */ 48 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 49 50 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 51 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 52 53 /* LOG2 number of continuous pages for the fragment field */ 54 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 55 56 #define AMDGPU_PTE_VALID (1ULL << 0) 57 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 58 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 59 60 /* VI only */ 61 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 62 63 #define AMDGPU_PTE_READABLE (1ULL << 5) 64 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 65 66 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 67 68 /* TILED for VEGA10, reserved for older ASICs */ 69 #define AMDGPU_PTE_PRT (1ULL << 51) 70 71 /* VEGA10 only */ 72 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) 73 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) 74 75 /* How to programm VM fault handling */ 76 #define AMDGPU_VM_FAULT_STOP_NEVER 0 77 #define AMDGPU_VM_FAULT_STOP_FIRST 1 78 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 79 80 /* max number of VMHUB */ 81 #define AMDGPU_MAX_VMHUBS 2 82 #define AMDGPU_GFXHUB 0 83 #define AMDGPU_MMHUB 1 84 85 /* hardcode that limit for now */ 86 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 87 88 struct amdgpu_vm_pt { 89 struct amdgpu_bo *bo; 90 uint64_t addr; 91 92 /* array of page tables, one for each directory entry */ 93 struct amdgpu_vm_pt *entries; 94 unsigned last_entry_used; 95 }; 96 97 struct amdgpu_vm { 98 /* tree of virtual addresses mapped */ 99 struct rb_root va; 100 101 /* protecting invalidated */ 102 spinlock_t status_lock; 103 104 /* BOs moved, but not yet updated in the PT */ 105 struct list_head invalidated; 106 107 /* BOs cleared in the PT because of a move */ 108 struct list_head cleared; 109 110 /* BO mappings freed, but not yet updated in the PT */ 111 struct list_head freed; 112 113 /* contains the page directory */ 114 struct amdgpu_vm_pt root; 115 struct dma_fence *last_dir_update; 116 uint64_t last_eviction_counter; 117 118 /* protecting freed */ 119 spinlock_t freed_lock; 120 121 /* Scheduler entity for page table updates */ 122 struct amd_sched_entity entity; 123 124 /* client id */ 125 u64 client_id; 126 /* each VM will map on CSA */ 127 struct amdgpu_bo_va *csa_bo_va; 128 }; 129 130 struct amdgpu_vm_id { 131 struct list_head list; 132 struct amdgpu_sync active; 133 struct dma_fence *last_flush; 134 atomic64_t owner; 135 136 uint64_t pd_gpu_addr; 137 /* last flushed PD/PT update */ 138 struct dma_fence *flushed_updates; 139 140 uint32_t current_gpu_reset_count; 141 142 uint32_t gds_base; 143 uint32_t gds_size; 144 uint32_t gws_base; 145 uint32_t gws_size; 146 uint32_t oa_base; 147 uint32_t oa_size; 148 }; 149 150 struct amdgpu_vm_id_manager { 151 struct mutex lock; 152 unsigned num_ids; 153 struct list_head ids_lru; 154 struct amdgpu_vm_id ids[AMDGPU_NUM_VM]; 155 }; 156 157 struct amdgpu_vm_manager { 158 /* Handling of VMIDs */ 159 struct amdgpu_vm_id_manager id_mgr[AMDGPU_MAX_VMHUBS]; 160 161 /* Handling of VM fences */ 162 u64 fence_context; 163 unsigned seqno[AMDGPU_MAX_RINGS]; 164 165 uint64_t max_pfn; 166 uint32_t num_level; 167 uint64_t vm_size; 168 uint32_t block_size; 169 /* vram base address for page table entry */ 170 u64 vram_base_offset; 171 /* is vm enabled? */ 172 bool enabled; 173 /* vm pte handling */ 174 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 175 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 176 unsigned vm_pte_num_rings; 177 atomic_t vm_pte_next_ring; 178 /* client id counter */ 179 atomic64_t client_counter; 180 181 /* partial resident texture handling */ 182 spinlock_t prt_lock; 183 atomic_t num_prt_users; 184 }; 185 186 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 187 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 188 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 189 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 190 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 191 struct list_head *validated, 192 struct amdgpu_bo_list_entry *entry); 193 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 194 int (*callback)(void *p, struct amdgpu_bo *bo), 195 void *param); 196 void amdgpu_vm_move_pt_bos_in_lru(struct amdgpu_device *adev, 197 struct amdgpu_vm *vm); 198 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, 199 struct amdgpu_vm *vm, 200 uint64_t saddr, uint64_t size); 201 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 202 struct amdgpu_sync *sync, struct dma_fence *fence, 203 struct amdgpu_job *job); 204 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job); 205 void amdgpu_vm_reset_id(struct amdgpu_device *adev, unsigned vmhub, 206 unsigned vmid); 207 void amdgpu_vm_reset_all_ids(struct amdgpu_device *adev); 208 int amdgpu_vm_update_directories(struct amdgpu_device *adev, 209 struct amdgpu_vm *vm); 210 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 211 struct amdgpu_vm *vm, 212 struct dma_fence **fence); 213 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 214 struct amdgpu_sync *sync); 215 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 216 struct amdgpu_bo_va *bo_va, 217 bool clear); 218 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 219 struct amdgpu_bo *bo); 220 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 221 struct amdgpu_bo *bo); 222 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 223 struct amdgpu_vm *vm, 224 struct amdgpu_bo *bo); 225 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 226 struct amdgpu_bo_va *bo_va, 227 uint64_t addr, uint64_t offset, 228 uint64_t size, uint64_t flags); 229 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 230 struct amdgpu_bo_va *bo_va, 231 uint64_t addr, uint64_t offset, 232 uint64_t size, uint64_t flags); 233 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 234 struct amdgpu_bo_va *bo_va, 235 uint64_t addr); 236 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 237 struct amdgpu_vm *vm, 238 uint64_t saddr, uint64_t size); 239 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 240 struct amdgpu_bo_va *bo_va); 241 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size); 242 243 #endif 244