1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct amdgpu_bo_va; 40 struct amdgpu_job; 41 struct amdgpu_bo_list_entry; 42 struct amdgpu_bo_vm; 43 44 /* 45 * GPUVM handling 46 */ 47 48 /* Maximum number of PTEs the hardware can write with one command */ 49 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 50 51 /* number of entries in page table */ 52 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 53 54 #define AMDGPU_PTE_VALID (1ULL << 0) 55 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 56 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 57 58 /* RV+ */ 59 #define AMDGPU_PTE_TMZ (1ULL << 3) 60 61 /* VI only */ 62 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 63 64 #define AMDGPU_PTE_READABLE (1ULL << 5) 65 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 66 67 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 68 69 /* TILED for VEGA10, reserved for older ASICs */ 70 #define AMDGPU_PTE_PRT (1ULL << 51) 71 72 /* PDE is handled as PTE for VEGA10 */ 73 #define AMDGPU_PDE_PTE (1ULL << 54) 74 75 #define AMDGPU_PTE_LOG (1ULL << 55) 76 77 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 78 #define AMDGPU_PTE_TF (1ULL << 56) 79 80 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 81 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 82 83 /* PDE Block Fragment Size for VEGA10 */ 84 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 85 86 87 /* For GFX9 */ 88 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 89 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 90 91 #define AMDGPU_MTYPE_NC 0 92 #define AMDGPU_MTYPE_CC 2 93 94 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 95 | AMDGPU_PTE_SNOOPED \ 96 | AMDGPU_PTE_EXECUTABLE \ 97 | AMDGPU_PTE_READABLE \ 98 | AMDGPU_PTE_WRITEABLE \ 99 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 100 101 /* gfx10 */ 102 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 103 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 104 105 /* How to program VM fault handling */ 106 #define AMDGPU_VM_FAULT_STOP_NEVER 0 107 #define AMDGPU_VM_FAULT_STOP_FIRST 1 108 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 109 110 /* Reserve 4MB VRAM for page tables */ 111 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 112 113 /* max number of VMHUB */ 114 #define AMDGPU_MAX_VMHUBS 3 115 #define AMDGPU_GFXHUB_0 0 116 #define AMDGPU_MMHUB_0 1 117 #define AMDGPU_MMHUB_1 2 118 119 /* Reserve 2MB at top/bottom of address space for kernel use */ 120 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20) 121 122 /* See vm_update_mode */ 123 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 124 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 125 126 /* VMPT level enumerate, and the hiberachy is: 127 * PDB2->PDB1->PDB0->PTB 128 */ 129 enum amdgpu_vm_level { 130 AMDGPU_VM_PDB2, 131 AMDGPU_VM_PDB1, 132 AMDGPU_VM_PDB0, 133 AMDGPU_VM_PTB 134 }; 135 136 /* base structure for tracking BO usage in a VM */ 137 struct amdgpu_vm_bo_base { 138 /* constant after initialization */ 139 struct amdgpu_vm *vm; 140 struct amdgpu_bo *bo; 141 142 /* protected by bo being reserved */ 143 struct amdgpu_vm_bo_base *next; 144 145 /* protected by spinlock */ 146 struct list_head vm_status; 147 148 /* protected by the BO being reserved */ 149 bool moved; 150 }; 151 152 /* provided by hw blocks that can write ptes, e.g., sdma */ 153 struct amdgpu_vm_pte_funcs { 154 /* number of dw to reserve per operation */ 155 unsigned copy_pte_num_dw; 156 157 /* copy pte entries from GART */ 158 void (*copy_pte)(struct amdgpu_ib *ib, 159 uint64_t pe, uint64_t src, 160 unsigned count); 161 162 /* write pte one entry at a time with addr mapping */ 163 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 164 uint64_t value, unsigned count, 165 uint32_t incr); 166 /* for linear pte/pde updates without addr mapping */ 167 void (*set_pte_pde)(struct amdgpu_ib *ib, 168 uint64_t pe, 169 uint64_t addr, unsigned count, 170 uint32_t incr, uint64_t flags); 171 }; 172 173 struct amdgpu_task_info { 174 char process_name[TASK_COMM_LEN]; 175 char task_name[TASK_COMM_LEN]; 176 pid_t pid; 177 pid_t tgid; 178 }; 179 180 /** 181 * struct amdgpu_vm_update_params 182 * 183 * Encapsulate some VM table update parameters to reduce 184 * the number of function parameters 185 * 186 */ 187 struct amdgpu_vm_update_params { 188 189 /** 190 * @adev: amdgpu device we do this update for 191 */ 192 struct amdgpu_device *adev; 193 194 /** 195 * @vm: optional amdgpu_vm we do this update for 196 */ 197 struct amdgpu_vm *vm; 198 199 /** 200 * @immediate: if changes should be made immediately 201 */ 202 bool immediate; 203 204 /** 205 * @unlocked: true if the root BO is not locked 206 */ 207 bool unlocked; 208 209 /** 210 * @pages_addr: 211 * 212 * DMA addresses to use for mapping 213 */ 214 dma_addr_t *pages_addr; 215 216 /** 217 * @job: job to used for hw submission 218 */ 219 struct amdgpu_job *job; 220 221 /** 222 * @num_dw_left: number of dw left for the IB 223 */ 224 unsigned int num_dw_left; 225 226 /** 227 * @table_freed: return true if page table is freed when updating 228 */ 229 bool table_freed; 230 }; 231 232 struct amdgpu_vm_update_funcs { 233 int (*map_table)(struct amdgpu_bo_vm *bo); 234 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 235 enum amdgpu_sync_mode sync_mode); 236 int (*update)(struct amdgpu_vm_update_params *p, 237 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 238 unsigned count, uint32_t incr, uint64_t flags); 239 int (*commit)(struct amdgpu_vm_update_params *p, 240 struct dma_fence **fence); 241 }; 242 243 struct amdgpu_vm { 244 /* tree of virtual addresses mapped */ 245 struct rb_root_cached va; 246 247 /* Lock to prevent eviction while we are updating page tables 248 * use vm_eviction_lock/unlock(vm) 249 */ 250 struct mutex eviction_lock; 251 bool evicting; 252 unsigned int saved_flags; 253 254 /* Lock to protect vm_bo add/del/move on all lists of vm */ 255 spinlock_t status_lock; 256 257 /* BOs who needs a validation */ 258 struct list_head evicted; 259 260 /* PT BOs which relocated and their parent need an update */ 261 struct list_head relocated; 262 263 /* per VM BOs moved, but not yet updated in the PT */ 264 struct list_head moved; 265 266 /* All BOs of this VM not currently in the state machine */ 267 struct list_head idle; 268 269 /* regular invalidated BOs, but not yet updated in the PT */ 270 struct list_head invalidated; 271 272 /* BO mappings freed, but not yet updated in the PT */ 273 struct list_head freed; 274 275 /* BOs which are invalidated, has been updated in the PTs */ 276 struct list_head done; 277 278 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 279 struct list_head pt_freed; 280 struct work_struct pt_free_work; 281 282 /* contains the page directory */ 283 struct amdgpu_vm_bo_base root; 284 struct dma_fence *last_update; 285 286 /* Scheduler entities for page table updates */ 287 struct drm_sched_entity immediate; 288 struct drm_sched_entity delayed; 289 290 /* Last finished delayed update */ 291 atomic64_t tlb_seq; 292 struct dma_fence *last_tlb_flush; 293 294 /* Last unlocked submission to the scheduler entities */ 295 struct dma_fence *last_unlocked; 296 297 unsigned int pasid; 298 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 299 300 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 301 bool use_cpu_for_update; 302 303 /* Functions to use for VM table updates */ 304 const struct amdgpu_vm_update_funcs *update_funcs; 305 306 /* Flag to indicate ATS support from PTE for GFX9 */ 307 bool pte_support_ats; 308 309 /* Up to 128 pending retry page faults */ 310 DECLARE_KFIFO(faults, u64, 128); 311 312 /* Points to the KFD process VM info */ 313 struct amdkfd_process_info *process_info; 314 315 /* List node in amdkfd_process_info.vm_list_head */ 316 struct list_head vm_list_node; 317 318 /* Valid while the PD is reserved or fenced */ 319 uint64_t pd_phys_addr; 320 321 /* Some basic info about the task */ 322 struct amdgpu_task_info task_info; 323 324 /* Store positions of group of BOs */ 325 struct ttm_lru_bulk_move lru_bulk_move; 326 /* Flag to indicate if VM is used for compute */ 327 bool is_compute_context; 328 }; 329 330 struct amdgpu_vm_manager { 331 /* Handling of VMIDs */ 332 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 333 unsigned int first_kfd_vmid; 334 bool concurrent_flush; 335 336 /* Handling of VM fences */ 337 u64 fence_context; 338 unsigned seqno[AMDGPU_MAX_RINGS]; 339 340 uint64_t max_pfn; 341 uint32_t num_level; 342 uint32_t block_size; 343 uint32_t fragment_size; 344 enum amdgpu_vm_level root_level; 345 /* vram base address for page table entry */ 346 u64 vram_base_offset; 347 /* vm pte handling */ 348 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 349 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 350 unsigned vm_pte_num_scheds; 351 struct amdgpu_ring *page_fault; 352 353 /* partial resident texture handling */ 354 spinlock_t prt_lock; 355 atomic_t num_prt_users; 356 357 /* controls how VM page tables are updated for Graphics and Compute. 358 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 359 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 360 */ 361 int vm_update_mode; 362 363 /* PASID to VM mapping, will be used in interrupt context to 364 * look up VM of a page fault 365 */ 366 struct xarray pasids; 367 }; 368 369 struct amdgpu_bo_va_mapping; 370 371 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 372 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 373 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 374 375 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 376 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 377 378 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 379 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 380 381 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 382 u32 pasid); 383 384 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 385 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 386 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 387 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 388 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 389 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 390 struct list_head *validated, 391 struct amdgpu_bo_list_entry *entry); 392 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 393 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 394 int (*callback)(void *p, struct amdgpu_bo *bo), 395 void *param); 396 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 397 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 398 struct amdgpu_vm *vm, bool immediate); 399 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 400 struct amdgpu_vm *vm, 401 struct dma_fence **fence); 402 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 403 struct amdgpu_vm *vm); 404 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 405 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 406 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 407 bool immediate, bool unlocked, bool flush_tlb, 408 struct dma_resv *resv, uint64_t start, uint64_t last, 409 uint64_t flags, uint64_t offset, uint64_t vram_base, 410 struct ttm_resource *res, dma_addr_t *pages_addr, 411 struct dma_fence **fence); 412 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 413 struct amdgpu_bo_va *bo_va, 414 bool clear); 415 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 416 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 417 struct amdgpu_bo *bo, bool evicted); 418 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 419 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 420 struct amdgpu_bo *bo); 421 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 422 struct amdgpu_vm *vm, 423 struct amdgpu_bo *bo); 424 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 425 struct amdgpu_bo_va *bo_va, 426 uint64_t addr, uint64_t offset, 427 uint64_t size, uint64_t flags); 428 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 429 struct amdgpu_bo_va *bo_va, 430 uint64_t addr, uint64_t offset, 431 uint64_t size, uint64_t flags); 432 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 433 struct amdgpu_bo_va *bo_va, 434 uint64_t addr); 435 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 436 struct amdgpu_vm *vm, 437 uint64_t saddr, uint64_t size); 438 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 439 uint64_t addr); 440 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 441 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 442 struct amdgpu_bo_va *bo_va); 443 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 444 uint32_t fragment_size_default, unsigned max_level, 445 unsigned max_bits); 446 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 447 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 448 struct amdgpu_job *job); 449 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 450 451 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 452 struct amdgpu_task_info *task_info); 453 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 454 uint64_t addr, bool write_fault); 455 456 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 457 458 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 459 struct amdgpu_vm *vm); 460 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, 461 uint64_t *gtt_mem, uint64_t *cpu_mem); 462 463 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 464 struct amdgpu_bo_vm *vmbo, bool immediate); 465 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 466 int level, bool immediate, struct amdgpu_bo_vm **vmbo); 467 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 468 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 469 struct amdgpu_vm *vm); 470 471 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 472 struct amdgpu_vm_bo_base *entry); 473 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 474 uint64_t start, uint64_t end, 475 uint64_t dst, uint64_t flags); 476 void amdgpu_vm_pt_free_work(struct work_struct *work); 477 478 #if defined(CONFIG_DEBUG_FS) 479 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 480 #endif 481 482 /** 483 * amdgpu_vm_tlb_seq - return tlb flush sequence number 484 * @vm: the amdgpu_vm structure to query 485 * 486 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 487 * to be invalidated whenever the sequence number change. 488 */ 489 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 490 { 491 unsigned long flags; 492 spinlock_t *lock; 493 494 /* 495 * Workaround to stop racing between the fence signaling and handling 496 * the cb. The lock is static after initially setting it up, just make 497 * sure that the dma_fence structure isn't freed up. 498 */ 499 rcu_read_lock(); 500 lock = vm->last_tlb_flush->lock; 501 rcu_read_unlock(); 502 503 spin_lock_irqsave(lock, flags); 504 spin_unlock_irqrestore(lock, flags); 505 506 return atomic64_read(&vm->tlb_seq); 507 } 508 509 /* 510 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 511 * happens while holding this lock anywhere to prevent deadlocks when 512 * an MMU notifier runs in reclaim-FS context. 513 */ 514 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 515 { 516 mutex_lock(&vm->eviction_lock); 517 vm->saved_flags = memalloc_noreclaim_save(); 518 } 519 520 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 521 { 522 if (mutex_trylock(&vm->eviction_lock)) { 523 vm->saved_flags = memalloc_noreclaim_save(); 524 return true; 525 } 526 return false; 527 } 528 529 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 530 { 531 memalloc_noreclaim_restore(vm->saved_flags); 532 mutex_unlock(&vm->eviction_lock); 533 } 534 535 #endif 536