1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo_driver.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct amdgpu_bo_va; 40 struct amdgpu_job; 41 struct amdgpu_bo_list_entry; 42 struct amdgpu_bo_vm; 43 44 /* 45 * GPUVM handling 46 */ 47 48 /* Maximum number of PTEs the hardware can write with one command */ 49 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 50 51 /* number of entries in page table */ 52 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 53 54 #define AMDGPU_PTE_VALID (1ULL << 0) 55 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 56 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 57 58 /* RV+ */ 59 #define AMDGPU_PTE_TMZ (1ULL << 3) 60 61 /* VI only */ 62 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 63 64 #define AMDGPU_PTE_READABLE (1ULL << 5) 65 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 66 67 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 68 69 /* TILED for VEGA10, reserved for older ASICs */ 70 #define AMDGPU_PTE_PRT (1ULL << 51) 71 72 /* PDE is handled as PTE for VEGA10 */ 73 #define AMDGPU_PDE_PTE (1ULL << 54) 74 75 #define AMDGPU_PTE_LOG (1ULL << 55) 76 77 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 78 #define AMDGPU_PTE_TF (1ULL << 56) 79 80 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 81 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 82 83 /* PDE Block Fragment Size for VEGA10 */ 84 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 85 86 87 /* For GFX9 */ 88 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 89 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 90 91 #define AMDGPU_MTYPE_NC 0 92 #define AMDGPU_MTYPE_CC 2 93 94 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 95 | AMDGPU_PTE_SNOOPED \ 96 | AMDGPU_PTE_EXECUTABLE \ 97 | AMDGPU_PTE_READABLE \ 98 | AMDGPU_PTE_WRITEABLE \ 99 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 100 101 /* gfx10 */ 102 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 103 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 104 105 /* How to program VM fault handling */ 106 #define AMDGPU_VM_FAULT_STOP_NEVER 0 107 #define AMDGPU_VM_FAULT_STOP_FIRST 1 108 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 109 110 /* Reserve 4MB VRAM for page tables */ 111 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 112 113 /* max number of VMHUB */ 114 #define AMDGPU_MAX_VMHUBS 3 115 #define AMDGPU_GFXHUB_0 0 116 #define AMDGPU_MMHUB_0 1 117 #define AMDGPU_MMHUB_1 2 118 119 /* Reserve 2MB at top/bottom of address space for kernel use */ 120 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20) 121 122 /* max vmids dedicated for process */ 123 #define AMDGPU_VM_MAX_RESERVED_VMID 1 124 125 /* See vm_update_mode */ 126 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 127 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 128 129 /* VMPT level enumerate, and the hiberachy is: 130 * PDB2->PDB1->PDB0->PTB 131 */ 132 enum amdgpu_vm_level { 133 AMDGPU_VM_PDB2, 134 AMDGPU_VM_PDB1, 135 AMDGPU_VM_PDB0, 136 AMDGPU_VM_PTB 137 }; 138 139 /* base structure for tracking BO usage in a VM */ 140 struct amdgpu_vm_bo_base { 141 /* constant after initialization */ 142 struct amdgpu_vm *vm; 143 struct amdgpu_bo *bo; 144 145 /* protected by bo being reserved */ 146 struct amdgpu_vm_bo_base *next; 147 148 /* protected by spinlock */ 149 struct list_head vm_status; 150 151 /* protected by the BO being reserved */ 152 bool moved; 153 }; 154 155 struct amdgpu_vm_pt { 156 struct amdgpu_vm_bo_base base; 157 158 /* array of page tables, one for each directory entry */ 159 struct amdgpu_vm_pt *entries; 160 }; 161 162 /* provided by hw blocks that can write ptes, e.g., sdma */ 163 struct amdgpu_vm_pte_funcs { 164 /* number of dw to reserve per operation */ 165 unsigned copy_pte_num_dw; 166 167 /* copy pte entries from GART */ 168 void (*copy_pte)(struct amdgpu_ib *ib, 169 uint64_t pe, uint64_t src, 170 unsigned count); 171 172 /* write pte one entry at a time with addr mapping */ 173 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 174 uint64_t value, unsigned count, 175 uint32_t incr); 176 /* for linear pte/pde updates without addr mapping */ 177 void (*set_pte_pde)(struct amdgpu_ib *ib, 178 uint64_t pe, 179 uint64_t addr, unsigned count, 180 uint32_t incr, uint64_t flags); 181 }; 182 183 struct amdgpu_task_info { 184 char process_name[TASK_COMM_LEN]; 185 char task_name[TASK_COMM_LEN]; 186 pid_t pid; 187 pid_t tgid; 188 }; 189 190 /** 191 * struct amdgpu_vm_update_params 192 * 193 * Encapsulate some VM table update parameters to reduce 194 * the number of function parameters 195 * 196 */ 197 struct amdgpu_vm_update_params { 198 199 /** 200 * @adev: amdgpu device we do this update for 201 */ 202 struct amdgpu_device *adev; 203 204 /** 205 * @vm: optional amdgpu_vm we do this update for 206 */ 207 struct amdgpu_vm *vm; 208 209 /** 210 * @immediate: if changes should be made immediately 211 */ 212 bool immediate; 213 214 /** 215 * @unlocked: true if the root BO is not locked 216 */ 217 bool unlocked; 218 219 /** 220 * @pages_addr: 221 * 222 * DMA addresses to use for mapping 223 */ 224 dma_addr_t *pages_addr; 225 226 /** 227 * @job: job to used for hw submission 228 */ 229 struct amdgpu_job *job; 230 231 /** 232 * @num_dw_left: number of dw left for the IB 233 */ 234 unsigned int num_dw_left; 235 236 /** 237 * @table_freed: return true if page table is freed when updating 238 */ 239 bool table_freed; 240 }; 241 242 struct amdgpu_vm_update_funcs { 243 int (*map_table)(struct amdgpu_bo_vm *bo); 244 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 245 enum amdgpu_sync_mode sync_mode); 246 int (*update)(struct amdgpu_vm_update_params *p, 247 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 248 unsigned count, uint32_t incr, uint64_t flags); 249 int (*commit)(struct amdgpu_vm_update_params *p, 250 struct dma_fence **fence); 251 }; 252 253 struct amdgpu_vm { 254 /* tree of virtual addresses mapped */ 255 struct rb_root_cached va; 256 257 /* Lock to prevent eviction while we are updating page tables 258 * use vm_eviction_lock/unlock(vm) 259 */ 260 struct mutex eviction_lock; 261 bool evicting; 262 unsigned int saved_flags; 263 264 /* BOs who needs a validation */ 265 struct list_head evicted; 266 267 /* PT BOs which relocated and their parent need an update */ 268 struct list_head relocated; 269 270 /* per VM BOs moved, but not yet updated in the PT */ 271 struct list_head moved; 272 273 /* All BOs of this VM not currently in the state machine */ 274 struct list_head idle; 275 276 /* regular invalidated BOs, but not yet updated in the PT */ 277 struct list_head invalidated; 278 spinlock_t invalidated_lock; 279 280 /* BO mappings freed, but not yet updated in the PT */ 281 struct list_head freed; 282 283 /* BOs which are invalidated, has been updated in the PTs */ 284 struct list_head done; 285 286 /* contains the page directory */ 287 struct amdgpu_vm_pt root; 288 struct dma_fence *last_update; 289 290 /* Scheduler entities for page table updates */ 291 struct drm_sched_entity immediate; 292 struct drm_sched_entity delayed; 293 294 /* Last unlocked submission to the scheduler entities */ 295 struct dma_fence *last_unlocked; 296 297 unsigned int pasid; 298 /* dedicated to vm */ 299 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 300 301 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 302 bool use_cpu_for_update; 303 304 /* Functions to use for VM table updates */ 305 const struct amdgpu_vm_update_funcs *update_funcs; 306 307 /* Flag to indicate ATS support from PTE for GFX9 */ 308 bool pte_support_ats; 309 310 /* Up to 128 pending retry page faults */ 311 DECLARE_KFIFO(faults, u64, 128); 312 313 /* Points to the KFD process VM info */ 314 struct amdkfd_process_info *process_info; 315 316 /* List node in amdkfd_process_info.vm_list_head */ 317 struct list_head vm_list_node; 318 319 /* Valid while the PD is reserved or fenced */ 320 uint64_t pd_phys_addr; 321 322 /* Some basic info about the task */ 323 struct amdgpu_task_info task_info; 324 325 /* Store positions of group of BOs */ 326 struct ttm_lru_bulk_move lru_bulk_move; 327 /* mark whether can do the bulk move */ 328 bool bulk_moveable; 329 /* Flag to indicate if VM is used for compute */ 330 bool is_compute_context; 331 }; 332 333 struct amdgpu_vm_manager { 334 /* Handling of VMIDs */ 335 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 336 unsigned int first_kfd_vmid; 337 bool concurrent_flush; 338 339 /* Handling of VM fences */ 340 u64 fence_context; 341 unsigned seqno[AMDGPU_MAX_RINGS]; 342 343 uint64_t max_pfn; 344 uint32_t num_level; 345 uint32_t block_size; 346 uint32_t fragment_size; 347 enum amdgpu_vm_level root_level; 348 /* vram base address for page table entry */ 349 u64 vram_base_offset; 350 /* vm pte handling */ 351 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 352 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 353 unsigned vm_pte_num_scheds; 354 struct amdgpu_ring *page_fault; 355 356 /* partial resident texture handling */ 357 spinlock_t prt_lock; 358 atomic_t num_prt_users; 359 360 /* controls how VM page tables are updated for Graphics and Compute. 361 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 362 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 363 */ 364 int vm_update_mode; 365 366 /* PASID to VM mapping, will be used in interrupt context to 367 * look up VM of a page fault 368 */ 369 struct idr pasid_idr; 370 spinlock_t pasid_lock; 371 }; 372 373 struct amdgpu_bo_va_mapping; 374 375 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 376 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 377 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 378 379 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 380 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 381 382 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 383 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 384 385 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 386 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid); 387 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid); 388 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 389 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 390 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 391 struct list_head *validated, 392 struct amdgpu_bo_list_entry *entry); 393 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 394 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 395 int (*callback)(void *p, struct amdgpu_bo *bo), 396 void *param); 397 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 398 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 399 struct amdgpu_vm *vm, bool immediate); 400 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 401 struct amdgpu_vm *vm, 402 struct dma_fence **fence); 403 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 404 struct amdgpu_vm *vm); 405 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, 406 struct amdgpu_device *bo_adev, 407 struct amdgpu_vm *vm, bool immediate, 408 bool unlocked, struct dma_resv *resv, 409 uint64_t start, uint64_t last, 410 uint64_t flags, uint64_t offset, 411 struct ttm_resource *res, 412 dma_addr_t *pages_addr, 413 struct dma_fence **fence, bool *free_table); 414 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 415 struct amdgpu_bo_va *bo_va, 416 bool clear, bool *table_freed); 417 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 418 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 419 struct amdgpu_bo *bo, bool evicted); 420 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 421 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 422 struct amdgpu_bo *bo); 423 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 424 struct amdgpu_vm *vm, 425 struct amdgpu_bo *bo); 426 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 427 struct amdgpu_bo_va *bo_va, 428 uint64_t addr, uint64_t offset, 429 uint64_t size, uint64_t flags); 430 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 431 struct amdgpu_bo_va *bo_va, 432 uint64_t addr, uint64_t offset, 433 uint64_t size, uint64_t flags); 434 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 435 struct amdgpu_bo_va *bo_va, 436 uint64_t addr); 437 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 438 struct amdgpu_vm *vm, 439 uint64_t saddr, uint64_t size); 440 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 441 uint64_t addr); 442 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 443 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 444 struct amdgpu_bo_va *bo_va); 445 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 446 uint32_t fragment_size_default, unsigned max_level, 447 unsigned max_bits); 448 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 449 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 450 struct amdgpu_job *job); 451 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 452 453 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 454 struct amdgpu_task_info *task_info); 455 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 456 uint64_t addr); 457 458 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 459 460 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 461 struct amdgpu_vm *vm); 462 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo); 463 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem, 464 uint64_t *gtt_mem, uint64_t *cpu_mem); 465 466 #if defined(CONFIG_DEBUG_FS) 467 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 468 #endif 469 470 #endif 471