1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Christian König
23  */
24 #ifndef __AMDGPU_VM_H__
25 #define __AMDGPU_VM_H__
26 
27 #include <linux/idr.h>
28 #include <linux/kfifo.h>
29 #include <linux/rbtree.h>
30 #include <drm/gpu_scheduler.h>
31 #include <drm/drm_file.h>
32 #include <drm/ttm/ttm_bo.h>
33 #include <linux/sched/mm.h>
34 
35 #include "amdgpu_sync.h"
36 #include "amdgpu_ring.h"
37 #include "amdgpu_ids.h"
38 
39 struct amdgpu_bo_va;
40 struct amdgpu_job;
41 struct amdgpu_bo_list_entry;
42 struct amdgpu_bo_vm;
43 struct amdgpu_mem_stats;
44 
45 /*
46  * GPUVM handling
47  */
48 
49 /* Maximum number of PTEs the hardware can write with one command */
50 #define AMDGPU_VM_MAX_UPDATE_SIZE	0x3FFFF
51 
52 /* number of entries in page table */
53 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
54 
55 #define AMDGPU_PTE_VALID	(1ULL << 0)
56 #define AMDGPU_PTE_SYSTEM	(1ULL << 1)
57 #define AMDGPU_PTE_SNOOPED	(1ULL << 2)
58 
59 /* RV+ */
60 #define AMDGPU_PTE_TMZ		(1ULL << 3)
61 
62 /* VI only */
63 #define AMDGPU_PTE_EXECUTABLE	(1ULL << 4)
64 
65 #define AMDGPU_PTE_READABLE	(1ULL << 5)
66 #define AMDGPU_PTE_WRITEABLE	(1ULL << 6)
67 
68 #define AMDGPU_PTE_FRAG(x)	((x & 0x1fULL) << 7)
69 
70 /* TILED for VEGA10, reserved for older ASICs  */
71 #define AMDGPU_PTE_PRT		(1ULL << 51)
72 
73 /* PDE is handled as PTE for VEGA10 */
74 #define AMDGPU_PDE_PTE		(1ULL << 54)
75 
76 #define AMDGPU_PTE_LOG          (1ULL << 55)
77 
78 /* PTE is handled as PDE for VEGA10 (Translate Further) */
79 #define AMDGPU_PTE_TF		(1ULL << 56)
80 
81 /* MALL noalloc for sienna_cichlid, reserved for older ASICs  */
82 #define AMDGPU_PTE_NOALLOC	(1ULL << 58)
83 
84 /* PDE Block Fragment Size for VEGA10 */
85 #define AMDGPU_PDE_BFS(a)	((uint64_t)a << 59)
86 
87 
88 /* For GFX9 */
89 #define AMDGPU_PTE_MTYPE_VG10(a)	((uint64_t)(a) << 57)
90 #define AMDGPU_PTE_MTYPE_VG10_MASK	AMDGPU_PTE_MTYPE_VG10(3ULL)
91 
92 #define AMDGPU_MTYPE_NC 0
93 #define AMDGPU_MTYPE_CC 2
94 
95 #define AMDGPU_PTE_DEFAULT_ATC  (AMDGPU_PTE_SYSTEM      \
96                                 | AMDGPU_PTE_SNOOPED    \
97                                 | AMDGPU_PTE_EXECUTABLE \
98                                 | AMDGPU_PTE_READABLE   \
99                                 | AMDGPU_PTE_WRITEABLE  \
100                                 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC))
101 
102 /* gfx10 */
103 #define AMDGPU_PTE_MTYPE_NV10(a)       ((uint64_t)(a) << 48)
104 #define AMDGPU_PTE_MTYPE_NV10_MASK     AMDGPU_PTE_MTYPE_NV10(7ULL)
105 
106 /* How to program VM fault handling */
107 #define AMDGPU_VM_FAULT_STOP_NEVER	0
108 #define AMDGPU_VM_FAULT_STOP_FIRST	1
109 #define AMDGPU_VM_FAULT_STOP_ALWAYS	2
110 
111 /* Reserve 4MB VRAM for page tables */
112 #define AMDGPU_VM_RESERVED_VRAM		(8ULL << 20)
113 
114 /* max number of VMHUB */
115 #define AMDGPU_MAX_VMHUBS			3
116 #define AMDGPU_GFXHUB_0				0
117 #define AMDGPU_MMHUB_0				1
118 #define AMDGPU_MMHUB_1				2
119 
120 /* Reserve 2MB at top/bottom of address space for kernel use */
121 #define AMDGPU_VA_RESERVED_SIZE			(2ULL << 20)
122 
123 /* See vm_update_mode */
124 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0)
125 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1)
126 
127 /* VMPT level enumerate, and the hiberachy is:
128  * PDB2->PDB1->PDB0->PTB
129  */
130 enum amdgpu_vm_level {
131 	AMDGPU_VM_PDB2,
132 	AMDGPU_VM_PDB1,
133 	AMDGPU_VM_PDB0,
134 	AMDGPU_VM_PTB
135 };
136 
137 /* base structure for tracking BO usage in a VM */
138 struct amdgpu_vm_bo_base {
139 	/* constant after initialization */
140 	struct amdgpu_vm		*vm;
141 	struct amdgpu_bo		*bo;
142 
143 	/* protected by bo being reserved */
144 	struct amdgpu_vm_bo_base	*next;
145 
146 	/* protected by spinlock */
147 	struct list_head		vm_status;
148 
149 	/* protected by the BO being reserved */
150 	bool				moved;
151 };
152 
153 /* provided by hw blocks that can write ptes, e.g., sdma */
154 struct amdgpu_vm_pte_funcs {
155 	/* number of dw to reserve per operation */
156 	unsigned	copy_pte_num_dw;
157 
158 	/* copy pte entries from GART */
159 	void (*copy_pte)(struct amdgpu_ib *ib,
160 			 uint64_t pe, uint64_t src,
161 			 unsigned count);
162 
163 	/* write pte one entry at a time with addr mapping */
164 	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
165 			  uint64_t value, unsigned count,
166 			  uint32_t incr);
167 	/* for linear pte/pde updates without addr mapping */
168 	void (*set_pte_pde)(struct amdgpu_ib *ib,
169 			    uint64_t pe,
170 			    uint64_t addr, unsigned count,
171 			    uint32_t incr, uint64_t flags);
172 };
173 
174 struct amdgpu_task_info {
175 	char	process_name[TASK_COMM_LEN];
176 	char	task_name[TASK_COMM_LEN];
177 	pid_t	pid;
178 	pid_t	tgid;
179 };
180 
181 /**
182  * struct amdgpu_vm_update_params
183  *
184  * Encapsulate some VM table update parameters to reduce
185  * the number of function parameters
186  *
187  */
188 struct amdgpu_vm_update_params {
189 
190 	/**
191 	 * @adev: amdgpu device we do this update for
192 	 */
193 	struct amdgpu_device *adev;
194 
195 	/**
196 	 * @vm: optional amdgpu_vm we do this update for
197 	 */
198 	struct amdgpu_vm *vm;
199 
200 	/**
201 	 * @immediate: if changes should be made immediately
202 	 */
203 	bool immediate;
204 
205 	/**
206 	 * @unlocked: true if the root BO is not locked
207 	 */
208 	bool unlocked;
209 
210 	/**
211 	 * @pages_addr:
212 	 *
213 	 * DMA addresses to use for mapping
214 	 */
215 	dma_addr_t *pages_addr;
216 
217 	/**
218 	 * @job: job to used for hw submission
219 	 */
220 	struct amdgpu_job *job;
221 
222 	/**
223 	 * @num_dw_left: number of dw left for the IB
224 	 */
225 	unsigned int num_dw_left;
226 
227 	/**
228 	 * @table_freed: return true if page table is freed when updating
229 	 */
230 	bool table_freed;
231 };
232 
233 struct amdgpu_vm_update_funcs {
234 	int (*map_table)(struct amdgpu_bo_vm *bo);
235 	int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv,
236 		       enum amdgpu_sync_mode sync_mode);
237 	int (*update)(struct amdgpu_vm_update_params *p,
238 		      struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
239 		      unsigned count, uint32_t incr, uint64_t flags);
240 	int (*commit)(struct amdgpu_vm_update_params *p,
241 		      struct dma_fence **fence);
242 };
243 
244 struct amdgpu_vm {
245 	/* tree of virtual addresses mapped */
246 	struct rb_root_cached	va;
247 
248 	/* Lock to prevent eviction while we are updating page tables
249 	 * use vm_eviction_lock/unlock(vm)
250 	 */
251 	struct mutex		eviction_lock;
252 	bool			evicting;
253 	unsigned int		saved_flags;
254 
255 	/* Lock to protect vm_bo add/del/move on all lists of vm */
256 	spinlock_t		status_lock;
257 
258 	/* BOs who needs a validation */
259 	struct list_head	evicted;
260 
261 	/* PT BOs which relocated and their parent need an update */
262 	struct list_head	relocated;
263 
264 	/* per VM BOs moved, but not yet updated in the PT */
265 	struct list_head	moved;
266 
267 	/* All BOs of this VM not currently in the state machine */
268 	struct list_head	idle;
269 
270 	/* regular invalidated BOs, but not yet updated in the PT */
271 	struct list_head	invalidated;
272 
273 	/* BO mappings freed, but not yet updated in the PT */
274 	struct list_head	freed;
275 
276 	/* BOs which are invalidated, has been updated in the PTs */
277 	struct list_head        done;
278 
279 	/* PT BOs scheduled to free and fill with zero if vm_resv is not hold */
280 	struct list_head	pt_freed;
281 	struct work_struct	pt_free_work;
282 
283 	/* contains the page directory */
284 	struct amdgpu_vm_bo_base     root;
285 	struct dma_fence	*last_update;
286 
287 	/* Scheduler entities for page table updates */
288 	struct drm_sched_entity	immediate;
289 	struct drm_sched_entity	delayed;
290 
291 	/* Last finished delayed update */
292 	atomic64_t		tlb_seq;
293 	struct dma_fence	*last_tlb_flush;
294 
295 	/* Last unlocked submission to the scheduler entities */
296 	struct dma_fence	*last_unlocked;
297 
298 	unsigned int		pasid;
299 	bool			reserved_vmid[AMDGPU_MAX_VMHUBS];
300 
301 	/* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */
302 	bool					use_cpu_for_update;
303 
304 	/* Functions to use for VM table updates */
305 	const struct amdgpu_vm_update_funcs	*update_funcs;
306 
307 	/* Flag to indicate ATS support from PTE for GFX9 */
308 	bool			pte_support_ats;
309 
310 	/* Up to 128 pending retry page faults */
311 	DECLARE_KFIFO(faults, u64, 128);
312 
313 	/* Points to the KFD process VM info */
314 	struct amdkfd_process_info *process_info;
315 
316 	/* List node in amdkfd_process_info.vm_list_head */
317 	struct list_head	vm_list_node;
318 
319 	/* Valid while the PD is reserved or fenced */
320 	uint64_t		pd_phys_addr;
321 
322 	/* Some basic info about the task */
323 	struct amdgpu_task_info task_info;
324 
325 	/* Store positions of group of BOs */
326 	struct ttm_lru_bulk_move lru_bulk_move;
327 	/* Flag to indicate if VM is used for compute */
328 	bool			is_compute_context;
329 };
330 
331 struct amdgpu_vm_manager {
332 	/* Handling of VMIDs */
333 	struct amdgpu_vmid_mgr			id_mgr[AMDGPU_MAX_VMHUBS];
334 	unsigned int				first_kfd_vmid;
335 	bool					concurrent_flush;
336 
337 	/* Handling of VM fences */
338 	u64					fence_context;
339 	unsigned				seqno[AMDGPU_MAX_RINGS];
340 
341 	uint64_t				max_pfn;
342 	uint32_t				num_level;
343 	uint32_t				block_size;
344 	uint32_t				fragment_size;
345 	enum amdgpu_vm_level			root_level;
346 	/* vram base address for page table entry  */
347 	u64					vram_base_offset;
348 	/* vm pte handling */
349 	const struct amdgpu_vm_pte_funcs	*vm_pte_funcs;
350 	struct drm_gpu_scheduler		*vm_pte_scheds[AMDGPU_MAX_RINGS];
351 	unsigned				vm_pte_num_scheds;
352 	struct amdgpu_ring			*page_fault;
353 
354 	/* partial resident texture handling */
355 	spinlock_t				prt_lock;
356 	atomic_t				num_prt_users;
357 
358 	/* controls how VM page tables are updated for Graphics and Compute.
359 	 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU
360 	 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU
361 	 */
362 	int					vm_update_mode;
363 
364 	/* PASID to VM mapping, will be used in interrupt context to
365 	 * look up VM of a page fault
366 	 */
367 	struct xarray				pasids;
368 };
369 
370 struct amdgpu_bo_va_mapping;
371 
372 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
373 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
374 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
375 
376 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs;
377 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs;
378 
379 void amdgpu_vm_manager_init(struct amdgpu_device *adev);
380 void amdgpu_vm_manager_fini(struct amdgpu_device *adev);
381 
382 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
383 			u32 pasid);
384 
385 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout);
386 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm);
387 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
388 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm);
389 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm);
390 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
391 			 struct list_head *validated,
392 			 struct amdgpu_bo_list_entry *entry);
393 bool amdgpu_vm_ready(struct amdgpu_vm *vm);
394 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
395 			      int (*callback)(void *p, struct amdgpu_bo *bo),
396 			      void *param);
397 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync);
398 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
399 			  struct amdgpu_vm *vm, bool immediate);
400 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
401 			  struct amdgpu_vm *vm,
402 			  struct dma_fence **fence);
403 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
404 			   struct amdgpu_vm *vm);
405 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
406 			    struct amdgpu_vm *vm, struct amdgpu_bo *bo);
407 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
408 			   bool immediate, bool unlocked, bool flush_tlb,
409 			   struct dma_resv *resv, uint64_t start, uint64_t last,
410 			   uint64_t flags, uint64_t offset, uint64_t vram_base,
411 			   struct ttm_resource *res, dma_addr_t *pages_addr,
412 			   struct dma_fence **fence);
413 int amdgpu_vm_bo_update(struct amdgpu_device *adev,
414 			struct amdgpu_bo_va *bo_va,
415 			bool clear);
416 bool amdgpu_vm_evictable(struct amdgpu_bo *bo);
417 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
418 			     struct amdgpu_bo *bo, bool evicted);
419 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr);
420 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
421 				       struct amdgpu_bo *bo);
422 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
423 				      struct amdgpu_vm *vm,
424 				      struct amdgpu_bo *bo);
425 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
426 		     struct amdgpu_bo_va *bo_va,
427 		     uint64_t addr, uint64_t offset,
428 		     uint64_t size, uint64_t flags);
429 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
430 			     struct amdgpu_bo_va *bo_va,
431 			     uint64_t addr, uint64_t offset,
432 			     uint64_t size, uint64_t flags);
433 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
434 		       struct amdgpu_bo_va *bo_va,
435 		       uint64_t addr);
436 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
437 				struct amdgpu_vm *vm,
438 				uint64_t saddr, uint64_t size);
439 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
440 							 uint64_t addr);
441 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket);
442 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
443 		      struct amdgpu_bo_va *bo_va);
444 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
445 			   uint32_t fragment_size_default, unsigned max_level,
446 			   unsigned max_bits);
447 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
448 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
449 				  struct amdgpu_job *job);
450 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
451 
452 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
453 			     struct amdgpu_task_info *task_info);
454 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
455 			    uint64_t addr, bool write_fault);
456 
457 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
458 
459 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
460 				struct amdgpu_vm *vm);
461 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
462 			  struct amdgpu_mem_stats *stats);
463 
464 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
465 		       struct amdgpu_bo_vm *vmbo, bool immediate);
466 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
467 			int level, bool immediate, struct amdgpu_bo_vm **vmbo);
468 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm);
469 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev,
470 				struct amdgpu_vm *vm);
471 
472 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params,
473 			 struct amdgpu_vm_bo_base *entry);
474 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params,
475 			  uint64_t start, uint64_t end,
476 			  uint64_t dst, uint64_t flags);
477 void amdgpu_vm_pt_free_work(struct work_struct *work);
478 
479 #if defined(CONFIG_DEBUG_FS)
480 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m);
481 #endif
482 
483 /**
484  * amdgpu_vm_tlb_seq - return tlb flush sequence number
485  * @vm: the amdgpu_vm structure to query
486  *
487  * Returns the tlb flush sequence number which indicates that the VM TLBs needs
488  * to be invalidated whenever the sequence number change.
489  */
490 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm)
491 {
492 	unsigned long flags;
493 	spinlock_t *lock;
494 
495 	/*
496 	 * Workaround to stop racing between the fence signaling and handling
497 	 * the cb. The lock is static after initially setting it up, just make
498 	 * sure that the dma_fence structure isn't freed up.
499 	 */
500 	rcu_read_lock();
501 	lock = vm->last_tlb_flush->lock;
502 	rcu_read_unlock();
503 
504 	spin_lock_irqsave(lock, flags);
505 	spin_unlock_irqrestore(lock, flags);
506 
507 	return atomic64_read(&vm->tlb_seq);
508 }
509 
510 /*
511  * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
512  * happens while holding this lock anywhere to prevent deadlocks when
513  * an MMU notifier runs in reclaim-FS context.
514  */
515 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
516 {
517 	mutex_lock(&vm->eviction_lock);
518 	vm->saved_flags = memalloc_noreclaim_save();
519 }
520 
521 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
522 {
523 	if (mutex_trylock(&vm->eviction_lock)) {
524 		vm->saved_flags = memalloc_noreclaim_save();
525 		return true;
526 	}
527 	return false;
528 }
529 
530 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
531 {
532 	memalloc_noreclaim_restore(vm->saved_flags);
533 	mutex_unlock(&vm->eviction_lock);
534 }
535 
536 #endif
537