1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 33 #include "amdgpu_sync.h" 34 #include "amdgpu_ring.h" 35 #include "amdgpu_ids.h" 36 37 struct amdgpu_bo_va; 38 struct amdgpu_job; 39 struct amdgpu_bo_list_entry; 40 41 /* 42 * GPUVM handling 43 */ 44 45 /* Maximum number of PTEs the hardware can write with one command */ 46 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 47 48 /* number of entries in page table */ 49 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 50 51 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 52 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 53 54 #define AMDGPU_PTE_VALID (1ULL << 0) 55 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 56 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 57 58 /* VI only */ 59 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 60 61 #define AMDGPU_PTE_READABLE (1ULL << 5) 62 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 63 64 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 65 66 /* TILED for VEGA10, reserved for older ASICs */ 67 #define AMDGPU_PTE_PRT (1ULL << 51) 68 69 /* PDE is handled as PTE for VEGA10 */ 70 #define AMDGPU_PDE_PTE (1ULL << 54) 71 72 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 73 #define AMDGPU_PTE_TF (1ULL << 56) 74 75 /* PDE Block Fragment Size for VEGA10 */ 76 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 77 78 /* VEGA10 only */ 79 #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57) 80 #define AMDGPU_PTE_MTYPE_MASK AMDGPU_PTE_MTYPE(3ULL) 81 82 /* For Raven */ 83 #define AMDGPU_MTYPE_CC 2 84 85 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 86 | AMDGPU_PTE_SNOOPED \ 87 | AMDGPU_PTE_EXECUTABLE \ 88 | AMDGPU_PTE_READABLE \ 89 | AMDGPU_PTE_WRITEABLE \ 90 | AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_CC)) 91 92 /* How to programm VM fault handling */ 93 #define AMDGPU_VM_FAULT_STOP_NEVER 0 94 #define AMDGPU_VM_FAULT_STOP_FIRST 1 95 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 96 97 /* max number of VMHUB */ 98 #define AMDGPU_MAX_VMHUBS 2 99 #define AMDGPU_GFXHUB 0 100 #define AMDGPU_MMHUB 1 101 102 /* hardcode that limit for now */ 103 #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20) 104 105 /* VA hole for 48bit addresses on Vega10 */ 106 #define AMDGPU_VA_HOLE_START 0x0000800000000000ULL 107 #define AMDGPU_VA_HOLE_END 0xffff800000000000ULL 108 109 /* 110 * Hardware is programmed as if the hole doesn't exists with start and end 111 * address values. 112 * 113 * This mask is used to remove the upper 16bits of the VA and so come up with 114 * the linear addr value. 115 */ 116 #define AMDGPU_VA_HOLE_MASK 0x0000ffffffffffffULL 117 118 /* max vmids dedicated for process */ 119 #define AMDGPU_VM_MAX_RESERVED_VMID 1 120 121 #define AMDGPU_VM_CONTEXT_GFX 0 122 #define AMDGPU_VM_CONTEXT_COMPUTE 1 123 124 /* See vm_update_mode */ 125 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 126 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 127 128 /* VMPT level enumerate, and the hiberachy is: 129 * PDB2->PDB1->PDB0->PTB 130 */ 131 enum amdgpu_vm_level { 132 AMDGPU_VM_PDB2, 133 AMDGPU_VM_PDB1, 134 AMDGPU_VM_PDB0, 135 AMDGPU_VM_PTB 136 }; 137 138 /* base structure for tracking BO usage in a VM */ 139 struct amdgpu_vm_bo_base { 140 /* constant after initialization */ 141 struct amdgpu_vm *vm; 142 struct amdgpu_bo *bo; 143 144 /* protected by bo being reserved */ 145 struct list_head bo_list; 146 147 /* protected by spinlock */ 148 struct list_head vm_status; 149 150 /* protected by the BO being reserved */ 151 bool moved; 152 }; 153 154 struct amdgpu_vm_pt { 155 struct amdgpu_vm_bo_base base; 156 bool huge; 157 158 /* array of page tables, one for each directory entry */ 159 struct amdgpu_vm_pt *entries; 160 }; 161 162 #define AMDGPU_VM_FAULT(pasid, addr) (((u64)(pasid) << 48) | (addr)) 163 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48) 164 #define AMDGPU_VM_FAULT_ADDR(fault) ((u64)(fault) & 0xfffffffff000ULL) 165 166 struct amdgpu_vm { 167 /* tree of virtual addresses mapped */ 168 struct rb_root_cached va; 169 170 /* protecting invalidated */ 171 spinlock_t status_lock; 172 173 /* BOs who needs a validation */ 174 struct list_head evicted; 175 176 /* PT BOs which relocated and their parent need an update */ 177 struct list_head relocated; 178 179 /* BOs moved, but not yet updated in the PT */ 180 struct list_head moved; 181 182 /* BO mappings freed, but not yet updated in the PT */ 183 struct list_head freed; 184 185 /* contains the page directory */ 186 struct amdgpu_vm_pt root; 187 struct dma_fence *last_update; 188 189 /* protecting freed */ 190 spinlock_t freed_lock; 191 192 /* Scheduler entity for page table updates */ 193 struct drm_sched_entity entity; 194 195 unsigned int pasid; 196 /* dedicated to vm */ 197 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 198 199 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 200 bool use_cpu_for_update; 201 202 /* Flag to indicate ATS support from PTE for GFX9 */ 203 bool pte_support_ats; 204 205 /* Up to 128 pending retry page faults */ 206 DECLARE_KFIFO(faults, u64, 128); 207 208 /* Limit non-retry fault storms */ 209 unsigned int fault_credit; 210 211 /* Points to the KFD process VM info */ 212 struct amdkfd_process_info *process_info; 213 214 /* List node in amdkfd_process_info.vm_list_head */ 215 struct list_head vm_list_node; 216 217 /* Valid while the PD is reserved or fenced */ 218 uint64_t pd_phys_addr; 219 }; 220 221 struct amdgpu_vm_manager { 222 /* Handling of VMIDs */ 223 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 224 225 /* Handling of VM fences */ 226 u64 fence_context; 227 unsigned seqno[AMDGPU_MAX_RINGS]; 228 229 uint64_t max_pfn; 230 uint32_t num_level; 231 uint32_t block_size; 232 uint32_t fragment_size; 233 enum amdgpu_vm_level root_level; 234 /* vram base address for page table entry */ 235 u64 vram_base_offset; 236 /* vm pte handling */ 237 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 238 struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS]; 239 unsigned vm_pte_num_rings; 240 atomic_t vm_pte_next_ring; 241 242 /* partial resident texture handling */ 243 spinlock_t prt_lock; 244 atomic_t num_prt_users; 245 246 /* controls how VM page tables are updated for Graphics and Compute. 247 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 248 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 249 */ 250 int vm_update_mode; 251 252 /* PASID to VM mapping, will be used in interrupt context to 253 * look up VM of a page fault 254 */ 255 struct idr pasid_idr; 256 spinlock_t pasid_lock; 257 }; 258 259 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 260 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 261 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 262 int vm_context, unsigned int pasid); 263 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 264 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 265 bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev, 266 unsigned int pasid); 267 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 268 struct list_head *validated, 269 struct amdgpu_bo_list_entry *entry); 270 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 271 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 272 int (*callback)(void *p, struct amdgpu_bo *bo), 273 void *param); 274 int amdgpu_vm_alloc_pts(struct amdgpu_device *adev, 275 struct amdgpu_vm *vm, 276 uint64_t saddr, uint64_t size); 277 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 278 int amdgpu_vm_update_directories(struct amdgpu_device *adev, 279 struct amdgpu_vm *vm); 280 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 281 struct amdgpu_vm *vm, 282 struct dma_fence **fence); 283 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 284 struct amdgpu_vm *vm); 285 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 286 struct amdgpu_bo_va *bo_va, 287 bool clear); 288 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 289 struct amdgpu_bo *bo, bool evicted); 290 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 291 struct amdgpu_bo *bo); 292 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 293 struct amdgpu_vm *vm, 294 struct amdgpu_bo *bo); 295 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 296 struct amdgpu_bo_va *bo_va, 297 uint64_t addr, uint64_t offset, 298 uint64_t size, uint64_t flags); 299 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 300 struct amdgpu_bo_va *bo_va, 301 uint64_t addr, uint64_t offset, 302 uint64_t size, uint64_t flags); 303 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 304 struct amdgpu_bo_va *bo_va, 305 uint64_t addr); 306 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 307 struct amdgpu_vm *vm, 308 uint64_t saddr, uint64_t size); 309 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 310 uint64_t addr); 311 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 312 struct amdgpu_bo_va *bo_va); 313 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size, 314 uint32_t fragment_size_default, unsigned max_level, 315 unsigned max_bits); 316 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 317 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 318 struct amdgpu_job *job); 319 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 320 321 #endif 322