1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct amdgpu_bo_va; 40 struct amdgpu_job; 41 struct amdgpu_bo_list_entry; 42 struct amdgpu_bo_vm; 43 struct amdgpu_mem_stats; 44 45 /* 46 * GPUVM handling 47 */ 48 49 /* Maximum number of PTEs the hardware can write with one command */ 50 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 51 52 /* number of entries in page table */ 53 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 54 55 #define AMDGPU_PTE_VALID (1ULL << 0) 56 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 57 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 58 59 /* RV+ */ 60 #define AMDGPU_PTE_TMZ (1ULL << 3) 61 62 /* VI only */ 63 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 64 65 #define AMDGPU_PTE_READABLE (1ULL << 5) 66 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 67 68 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 69 70 /* TILED for VEGA10, reserved for older ASICs */ 71 #define AMDGPU_PTE_PRT (1ULL << 51) 72 73 /* PDE is handled as PTE for VEGA10 */ 74 #define AMDGPU_PDE_PTE (1ULL << 54) 75 76 #define AMDGPU_PTE_LOG (1ULL << 55) 77 78 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 79 #define AMDGPU_PTE_TF (1ULL << 56) 80 81 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 82 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 83 84 /* PDE Block Fragment Size for VEGA10 */ 85 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 86 87 /* Flag combination to set no-retry with TF disabled */ 88 #define AMDGPU_VM_NORETRY_FLAGS (AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE | \ 89 AMDGPU_PTE_TF) 90 91 /* Flag combination to set no-retry with TF enabled */ 92 #define AMDGPU_VM_NORETRY_FLAGS_TF (AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM | \ 93 AMDGPU_PTE_PRT) 94 /* For GFX9 */ 95 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 96 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 97 98 #define AMDGPU_MTYPE_NC 0 99 #define AMDGPU_MTYPE_CC 2 100 101 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 102 | AMDGPU_PTE_SNOOPED \ 103 | AMDGPU_PTE_EXECUTABLE \ 104 | AMDGPU_PTE_READABLE \ 105 | AMDGPU_PTE_WRITEABLE \ 106 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 107 108 /* gfx10 */ 109 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 110 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 111 112 /* How to program VM fault handling */ 113 #define AMDGPU_VM_FAULT_STOP_NEVER 0 114 #define AMDGPU_VM_FAULT_STOP_FIRST 1 115 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 116 117 /* Reserve 4MB VRAM for page tables */ 118 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 119 120 /* 121 * max number of VMHUB 122 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 123 */ 124 #define AMDGPU_MAX_VMHUBS 13 125 #define AMDGPU_GFXHUB(x) (x) 126 #define AMDGPU_MMHUB0(x) (8 + x) 127 #define AMDGPU_MMHUB1(x) (8 + 4 + x) 128 129 /* Reserve 2MB at top/bottom of address space for kernel use */ 130 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20) 131 132 /* See vm_update_mode */ 133 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 134 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 135 136 /* VMPT level enumerate, and the hiberachy is: 137 * PDB2->PDB1->PDB0->PTB 138 */ 139 enum amdgpu_vm_level { 140 AMDGPU_VM_PDB2, 141 AMDGPU_VM_PDB1, 142 AMDGPU_VM_PDB0, 143 AMDGPU_VM_PTB 144 }; 145 146 /* base structure for tracking BO usage in a VM */ 147 struct amdgpu_vm_bo_base { 148 /* constant after initialization */ 149 struct amdgpu_vm *vm; 150 struct amdgpu_bo *bo; 151 152 /* protected by bo being reserved */ 153 struct amdgpu_vm_bo_base *next; 154 155 /* protected by spinlock */ 156 struct list_head vm_status; 157 158 /* protected by the BO being reserved */ 159 bool moved; 160 }; 161 162 /* provided by hw blocks that can write ptes, e.g., sdma */ 163 struct amdgpu_vm_pte_funcs { 164 /* number of dw to reserve per operation */ 165 unsigned copy_pte_num_dw; 166 167 /* copy pte entries from GART */ 168 void (*copy_pte)(struct amdgpu_ib *ib, 169 uint64_t pe, uint64_t src, 170 unsigned count); 171 172 /* write pte one entry at a time with addr mapping */ 173 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 174 uint64_t value, unsigned count, 175 uint32_t incr); 176 /* for linear pte/pde updates without addr mapping */ 177 void (*set_pte_pde)(struct amdgpu_ib *ib, 178 uint64_t pe, 179 uint64_t addr, unsigned count, 180 uint32_t incr, uint64_t flags); 181 }; 182 183 struct amdgpu_task_info { 184 char process_name[TASK_COMM_LEN]; 185 char task_name[TASK_COMM_LEN]; 186 pid_t pid; 187 pid_t tgid; 188 }; 189 190 /** 191 * struct amdgpu_vm_update_params 192 * 193 * Encapsulate some VM table update parameters to reduce 194 * the number of function parameters 195 * 196 */ 197 struct amdgpu_vm_update_params { 198 199 /** 200 * @adev: amdgpu device we do this update for 201 */ 202 struct amdgpu_device *adev; 203 204 /** 205 * @vm: optional amdgpu_vm we do this update for 206 */ 207 struct amdgpu_vm *vm; 208 209 /** 210 * @immediate: if changes should be made immediately 211 */ 212 bool immediate; 213 214 /** 215 * @unlocked: true if the root BO is not locked 216 */ 217 bool unlocked; 218 219 /** 220 * @pages_addr: 221 * 222 * DMA addresses to use for mapping 223 */ 224 dma_addr_t *pages_addr; 225 226 /** 227 * @job: job to used for hw submission 228 */ 229 struct amdgpu_job *job; 230 231 /** 232 * @num_dw_left: number of dw left for the IB 233 */ 234 unsigned int num_dw_left; 235 236 /** 237 * @table_freed: return true if page table is freed when updating 238 */ 239 bool table_freed; 240 }; 241 242 struct amdgpu_vm_update_funcs { 243 int (*map_table)(struct amdgpu_bo_vm *bo); 244 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 245 enum amdgpu_sync_mode sync_mode); 246 int (*update)(struct amdgpu_vm_update_params *p, 247 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 248 unsigned count, uint32_t incr, uint64_t flags); 249 int (*commit)(struct amdgpu_vm_update_params *p, 250 struct dma_fence **fence); 251 }; 252 253 struct amdgpu_vm { 254 /* tree of virtual addresses mapped */ 255 struct rb_root_cached va; 256 257 /* Lock to prevent eviction while we are updating page tables 258 * use vm_eviction_lock/unlock(vm) 259 */ 260 struct mutex eviction_lock; 261 bool evicting; 262 unsigned int saved_flags; 263 264 /* Lock to protect vm_bo add/del/move on all lists of vm */ 265 spinlock_t status_lock; 266 267 /* BOs who needs a validation */ 268 struct list_head evicted; 269 270 /* PT BOs which relocated and their parent need an update */ 271 struct list_head relocated; 272 273 /* per VM BOs moved, but not yet updated in the PT */ 274 struct list_head moved; 275 276 /* All BOs of this VM not currently in the state machine */ 277 struct list_head idle; 278 279 /* regular invalidated BOs, but not yet updated in the PT */ 280 struct list_head invalidated; 281 282 /* BO mappings freed, but not yet updated in the PT */ 283 struct list_head freed; 284 285 /* BOs which are invalidated, has been updated in the PTs */ 286 struct list_head done; 287 288 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 289 struct list_head pt_freed; 290 struct work_struct pt_free_work; 291 292 /* contains the page directory */ 293 struct amdgpu_vm_bo_base root; 294 struct dma_fence *last_update; 295 296 /* Scheduler entities for page table updates */ 297 struct drm_sched_entity immediate; 298 struct drm_sched_entity delayed; 299 300 /* Last finished delayed update */ 301 atomic64_t tlb_seq; 302 struct dma_fence *last_tlb_flush; 303 304 /* How many times we had to re-generate the page tables */ 305 uint64_t generation; 306 307 /* Last unlocked submission to the scheduler entities */ 308 struct dma_fence *last_unlocked; 309 310 unsigned int pasid; 311 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 312 313 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 314 bool use_cpu_for_update; 315 316 /* Functions to use for VM table updates */ 317 const struct amdgpu_vm_update_funcs *update_funcs; 318 319 /* Flag to indicate ATS support from PTE for GFX9 */ 320 bool pte_support_ats; 321 322 /* Up to 128 pending retry page faults */ 323 DECLARE_KFIFO(faults, u64, 128); 324 325 /* Points to the KFD process VM info */ 326 struct amdkfd_process_info *process_info; 327 328 /* List node in amdkfd_process_info.vm_list_head */ 329 struct list_head vm_list_node; 330 331 /* Valid while the PD is reserved or fenced */ 332 uint64_t pd_phys_addr; 333 334 /* Some basic info about the task */ 335 struct amdgpu_task_info task_info; 336 337 /* Store positions of group of BOs */ 338 struct ttm_lru_bulk_move lru_bulk_move; 339 /* Flag to indicate if VM is used for compute */ 340 bool is_compute_context; 341 342 /* Memory partition number, -1 means any partition */ 343 int8_t mem_id; 344 }; 345 346 struct amdgpu_vm_manager { 347 /* Handling of VMIDs */ 348 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 349 unsigned int first_kfd_vmid; 350 bool concurrent_flush; 351 352 /* Handling of VM fences */ 353 u64 fence_context; 354 unsigned seqno[AMDGPU_MAX_RINGS]; 355 356 uint64_t max_pfn; 357 uint32_t num_level; 358 uint32_t block_size; 359 uint32_t fragment_size; 360 enum amdgpu_vm_level root_level; 361 /* vram base address for page table entry */ 362 u64 vram_base_offset; 363 /* vm pte handling */ 364 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 365 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 366 unsigned vm_pte_num_scheds; 367 struct amdgpu_ring *page_fault; 368 369 /* partial resident texture handling */ 370 spinlock_t prt_lock; 371 atomic_t num_prt_users; 372 373 /* controls how VM page tables are updated for Graphics and Compute. 374 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 375 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 376 */ 377 int vm_update_mode; 378 379 /* PASID to VM mapping, will be used in interrupt context to 380 * look up VM of a page fault 381 */ 382 struct xarray pasids; 383 }; 384 385 struct amdgpu_bo_va_mapping; 386 387 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 388 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 389 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 390 391 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 392 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 393 394 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 395 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 396 397 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 398 u32 pasid); 399 400 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 401 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 402 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 403 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 404 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 405 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 406 struct list_head *validated, 407 struct amdgpu_bo_list_entry *entry); 408 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 409 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm); 410 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 411 int (*callback)(void *p, struct amdgpu_bo *bo), 412 void *param); 413 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 414 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 415 struct amdgpu_vm *vm, bool immediate); 416 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 417 struct amdgpu_vm *vm, 418 struct dma_fence **fence); 419 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 420 struct amdgpu_vm *vm); 421 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 422 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 423 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 424 bool immediate, bool unlocked, bool flush_tlb, 425 struct dma_resv *resv, uint64_t start, uint64_t last, 426 uint64_t flags, uint64_t offset, uint64_t vram_base, 427 struct ttm_resource *res, dma_addr_t *pages_addr, 428 struct dma_fence **fence); 429 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 430 struct amdgpu_bo_va *bo_va, 431 bool clear); 432 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 433 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 434 struct amdgpu_bo *bo, bool evicted); 435 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 436 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 437 struct amdgpu_bo *bo); 438 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 439 struct amdgpu_vm *vm, 440 struct amdgpu_bo *bo); 441 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 442 struct amdgpu_bo_va *bo_va, 443 uint64_t addr, uint64_t offset, 444 uint64_t size, uint64_t flags); 445 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 446 struct amdgpu_bo_va *bo_va, 447 uint64_t addr, uint64_t offset, 448 uint64_t size, uint64_t flags); 449 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 450 struct amdgpu_bo_va *bo_va, 451 uint64_t addr); 452 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 453 struct amdgpu_vm *vm, 454 uint64_t saddr, uint64_t size); 455 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 456 uint64_t addr); 457 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 458 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 459 struct amdgpu_bo_va *bo_va); 460 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 461 uint32_t fragment_size_default, unsigned max_level, 462 unsigned max_bits); 463 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 464 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 465 struct amdgpu_job *job); 466 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 467 468 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 469 struct amdgpu_task_info *task_info); 470 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 471 u32 vmid, u32 node_id, uint64_t addr, 472 bool write_fault); 473 474 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 475 476 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 477 struct amdgpu_vm *vm); 478 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 479 struct amdgpu_mem_stats *stats); 480 481 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 482 struct amdgpu_bo_vm *vmbo, bool immediate); 483 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 484 int level, bool immediate, struct amdgpu_bo_vm **vmbo); 485 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 486 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 487 struct amdgpu_vm *vm); 488 489 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 490 struct amdgpu_vm_bo_base *entry); 491 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 492 uint64_t start, uint64_t end, 493 uint64_t dst, uint64_t flags); 494 void amdgpu_vm_pt_free_work(struct work_struct *work); 495 496 #if defined(CONFIG_DEBUG_FS) 497 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 498 #endif 499 500 int amdgpu_vm_pt_map_tables(struct amdgpu_device *adev, struct amdgpu_vm *vm); 501 502 /** 503 * amdgpu_vm_tlb_seq - return tlb flush sequence number 504 * @vm: the amdgpu_vm structure to query 505 * 506 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 507 * to be invalidated whenever the sequence number change. 508 */ 509 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 510 { 511 unsigned long flags; 512 spinlock_t *lock; 513 514 /* 515 * Workaround to stop racing between the fence signaling and handling 516 * the cb. The lock is static after initially setting it up, just make 517 * sure that the dma_fence structure isn't freed up. 518 */ 519 rcu_read_lock(); 520 lock = vm->last_tlb_flush->lock; 521 rcu_read_unlock(); 522 523 spin_lock_irqsave(lock, flags); 524 spin_unlock_irqrestore(lock, flags); 525 526 return atomic64_read(&vm->tlb_seq); 527 } 528 529 /* 530 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 531 * happens while holding this lock anywhere to prevent deadlocks when 532 * an MMU notifier runs in reclaim-FS context. 533 */ 534 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 535 { 536 mutex_lock(&vm->eviction_lock); 537 vm->saved_flags = memalloc_noreclaim_save(); 538 } 539 540 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 541 { 542 if (mutex_trylock(&vm->eviction_lock)) { 543 vm->saved_flags = memalloc_noreclaim_save(); 544 return true; 545 } 546 return false; 547 } 548 549 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 550 { 551 memalloc_noreclaim_restore(vm->saved_flags); 552 mutex_unlock(&vm->eviction_lock); 553 } 554 555 #endif 556