1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct amdgpu_bo_va; 40 struct amdgpu_job; 41 struct amdgpu_bo_list_entry; 42 struct amdgpu_bo_vm; 43 struct amdgpu_mem_stats; 44 45 /* 46 * GPUVM handling 47 */ 48 49 /* Maximum number of PTEs the hardware can write with one command */ 50 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 51 52 /* number of entries in page table */ 53 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 54 55 #define AMDGPU_PTE_VALID (1ULL << 0) 56 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 57 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 58 59 /* RV+ */ 60 #define AMDGPU_PTE_TMZ (1ULL << 3) 61 62 /* VI only */ 63 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 64 65 #define AMDGPU_PTE_READABLE (1ULL << 5) 66 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 67 68 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 69 70 /* TILED for VEGA10, reserved for older ASICs */ 71 #define AMDGPU_PTE_PRT (1ULL << 51) 72 73 /* PDE is handled as PTE for VEGA10 */ 74 #define AMDGPU_PDE_PTE (1ULL << 54) 75 76 #define AMDGPU_PTE_LOG (1ULL << 55) 77 78 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 79 #define AMDGPU_PTE_TF (1ULL << 56) 80 81 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 82 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 83 84 /* PDE Block Fragment Size for VEGA10 */ 85 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 86 87 88 /* For GFX9 */ 89 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 90 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 91 92 #define AMDGPU_MTYPE_NC 0 93 #define AMDGPU_MTYPE_CC 2 94 95 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 96 | AMDGPU_PTE_SNOOPED \ 97 | AMDGPU_PTE_EXECUTABLE \ 98 | AMDGPU_PTE_READABLE \ 99 | AMDGPU_PTE_WRITEABLE \ 100 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 101 102 /* gfx10 */ 103 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 104 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 105 106 /* How to program VM fault handling */ 107 #define AMDGPU_VM_FAULT_STOP_NEVER 0 108 #define AMDGPU_VM_FAULT_STOP_FIRST 1 109 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 110 111 /* Reserve 4MB VRAM for page tables */ 112 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 113 114 /* 115 * max number of VMHUB 116 * layout: max 8 GFXHUB + 4 MMHUB0 + 1 MMHUB1 117 */ 118 #define AMDGPU_MAX_VMHUBS 13 119 #define AMDGPU_GFXHUB(x) (x) 120 #define AMDGPU_MMHUB0(x) (8 + x) 121 #define AMDGPU_MMHUB1(x) (8 + 4 + x) 122 123 /* Reserve 2MB at top/bottom of address space for kernel use */ 124 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20) 125 126 /* See vm_update_mode */ 127 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 128 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 129 130 /* VMPT level enumerate, and the hiberachy is: 131 * PDB2->PDB1->PDB0->PTB 132 */ 133 enum amdgpu_vm_level { 134 AMDGPU_VM_PDB2, 135 AMDGPU_VM_PDB1, 136 AMDGPU_VM_PDB0, 137 AMDGPU_VM_PTB 138 }; 139 140 /* base structure for tracking BO usage in a VM */ 141 struct amdgpu_vm_bo_base { 142 /* constant after initialization */ 143 struct amdgpu_vm *vm; 144 struct amdgpu_bo *bo; 145 146 /* protected by bo being reserved */ 147 struct amdgpu_vm_bo_base *next; 148 149 /* protected by spinlock */ 150 struct list_head vm_status; 151 152 /* protected by the BO being reserved */ 153 bool moved; 154 }; 155 156 /* provided by hw blocks that can write ptes, e.g., sdma */ 157 struct amdgpu_vm_pte_funcs { 158 /* number of dw to reserve per operation */ 159 unsigned copy_pte_num_dw; 160 161 /* copy pte entries from GART */ 162 void (*copy_pte)(struct amdgpu_ib *ib, 163 uint64_t pe, uint64_t src, 164 unsigned count); 165 166 /* write pte one entry at a time with addr mapping */ 167 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 168 uint64_t value, unsigned count, 169 uint32_t incr); 170 /* for linear pte/pde updates without addr mapping */ 171 void (*set_pte_pde)(struct amdgpu_ib *ib, 172 uint64_t pe, 173 uint64_t addr, unsigned count, 174 uint32_t incr, uint64_t flags); 175 }; 176 177 struct amdgpu_task_info { 178 char process_name[TASK_COMM_LEN]; 179 char task_name[TASK_COMM_LEN]; 180 pid_t pid; 181 pid_t tgid; 182 }; 183 184 /** 185 * struct amdgpu_vm_update_params 186 * 187 * Encapsulate some VM table update parameters to reduce 188 * the number of function parameters 189 * 190 */ 191 struct amdgpu_vm_update_params { 192 193 /** 194 * @adev: amdgpu device we do this update for 195 */ 196 struct amdgpu_device *adev; 197 198 /** 199 * @vm: optional amdgpu_vm we do this update for 200 */ 201 struct amdgpu_vm *vm; 202 203 /** 204 * @immediate: if changes should be made immediately 205 */ 206 bool immediate; 207 208 /** 209 * @unlocked: true if the root BO is not locked 210 */ 211 bool unlocked; 212 213 /** 214 * @pages_addr: 215 * 216 * DMA addresses to use for mapping 217 */ 218 dma_addr_t *pages_addr; 219 220 /** 221 * @job: job to used for hw submission 222 */ 223 struct amdgpu_job *job; 224 225 /** 226 * @num_dw_left: number of dw left for the IB 227 */ 228 unsigned int num_dw_left; 229 230 /** 231 * @table_freed: return true if page table is freed when updating 232 */ 233 bool table_freed; 234 }; 235 236 struct amdgpu_vm_update_funcs { 237 int (*map_table)(struct amdgpu_bo_vm *bo); 238 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 239 enum amdgpu_sync_mode sync_mode); 240 int (*update)(struct amdgpu_vm_update_params *p, 241 struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, 242 unsigned count, uint32_t incr, uint64_t flags); 243 int (*commit)(struct amdgpu_vm_update_params *p, 244 struct dma_fence **fence); 245 }; 246 247 struct amdgpu_vm { 248 /* tree of virtual addresses mapped */ 249 struct rb_root_cached va; 250 251 /* Lock to prevent eviction while we are updating page tables 252 * use vm_eviction_lock/unlock(vm) 253 */ 254 struct mutex eviction_lock; 255 bool evicting; 256 unsigned int saved_flags; 257 258 /* Lock to protect vm_bo add/del/move on all lists of vm */ 259 spinlock_t status_lock; 260 261 /* BOs who needs a validation */ 262 struct list_head evicted; 263 264 /* PT BOs which relocated and their parent need an update */ 265 struct list_head relocated; 266 267 /* per VM BOs moved, but not yet updated in the PT */ 268 struct list_head moved; 269 270 /* All BOs of this VM not currently in the state machine */ 271 struct list_head idle; 272 273 /* regular invalidated BOs, but not yet updated in the PT */ 274 struct list_head invalidated; 275 276 /* BO mappings freed, but not yet updated in the PT */ 277 struct list_head freed; 278 279 /* BOs which are invalidated, has been updated in the PTs */ 280 struct list_head done; 281 282 /* PT BOs scheduled to free and fill with zero if vm_resv is not hold */ 283 struct list_head pt_freed; 284 struct work_struct pt_free_work; 285 286 /* contains the page directory */ 287 struct amdgpu_vm_bo_base root; 288 struct dma_fence *last_update; 289 290 /* Scheduler entities for page table updates */ 291 struct drm_sched_entity immediate; 292 struct drm_sched_entity delayed; 293 294 /* Last finished delayed update */ 295 atomic64_t tlb_seq; 296 struct dma_fence *last_tlb_flush; 297 298 /* Last unlocked submission to the scheduler entities */ 299 struct dma_fence *last_unlocked; 300 301 unsigned int pasid; 302 bool reserved_vmid[AMDGPU_MAX_VMHUBS]; 303 304 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 305 bool use_cpu_for_update; 306 307 /* Functions to use for VM table updates */ 308 const struct amdgpu_vm_update_funcs *update_funcs; 309 310 /* Flag to indicate ATS support from PTE for GFX9 */ 311 bool pte_support_ats; 312 313 /* Up to 128 pending retry page faults */ 314 DECLARE_KFIFO(faults, u64, 128); 315 316 /* Points to the KFD process VM info */ 317 struct amdkfd_process_info *process_info; 318 319 /* List node in amdkfd_process_info.vm_list_head */ 320 struct list_head vm_list_node; 321 322 /* Valid while the PD is reserved or fenced */ 323 uint64_t pd_phys_addr; 324 325 /* Some basic info about the task */ 326 struct amdgpu_task_info task_info; 327 328 /* Store positions of group of BOs */ 329 struct ttm_lru_bulk_move lru_bulk_move; 330 /* Flag to indicate if VM is used for compute */ 331 bool is_compute_context; 332 333 /* Memory partition number, -1 means any partition */ 334 int8_t mem_id; 335 }; 336 337 struct amdgpu_vm_manager { 338 /* Handling of VMIDs */ 339 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 340 unsigned int first_kfd_vmid; 341 bool concurrent_flush; 342 343 /* Handling of VM fences */ 344 u64 fence_context; 345 unsigned seqno[AMDGPU_MAX_RINGS]; 346 347 uint64_t max_pfn; 348 uint32_t num_level; 349 uint32_t block_size; 350 uint32_t fragment_size; 351 enum amdgpu_vm_level root_level; 352 /* vram base address for page table entry */ 353 u64 vram_base_offset; 354 /* vm pte handling */ 355 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 356 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 357 unsigned vm_pte_num_scheds; 358 struct amdgpu_ring *page_fault; 359 360 /* partial resident texture handling */ 361 spinlock_t prt_lock; 362 atomic_t num_prt_users; 363 364 /* controls how VM page tables are updated for Graphics and Compute. 365 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 366 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 367 */ 368 int vm_update_mode; 369 370 /* PASID to VM mapping, will be used in interrupt context to 371 * look up VM of a page fault 372 */ 373 struct xarray pasids; 374 }; 375 376 struct amdgpu_bo_va_mapping; 377 378 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 379 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 380 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 381 382 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 383 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 384 385 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 386 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 387 388 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, 389 u32 pasid); 390 391 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 392 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 393 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 394 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 395 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 396 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 397 struct list_head *validated, 398 struct amdgpu_bo_list_entry *entry); 399 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 400 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 401 int (*callback)(void *p, struct amdgpu_bo *bo), 402 void *param); 403 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 404 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 405 struct amdgpu_vm *vm, bool immediate); 406 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 407 struct amdgpu_vm *vm, 408 struct dma_fence **fence); 409 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 410 struct amdgpu_vm *vm); 411 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, 412 struct amdgpu_vm *vm, struct amdgpu_bo *bo); 413 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, 414 bool immediate, bool unlocked, bool flush_tlb, 415 struct dma_resv *resv, uint64_t start, uint64_t last, 416 uint64_t flags, uint64_t offset, uint64_t vram_base, 417 struct ttm_resource *res, dma_addr_t *pages_addr, 418 struct dma_fence **fence); 419 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 420 struct amdgpu_bo_va *bo_va, 421 bool clear); 422 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 423 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 424 struct amdgpu_bo *bo, bool evicted); 425 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 426 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 427 struct amdgpu_bo *bo); 428 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 429 struct amdgpu_vm *vm, 430 struct amdgpu_bo *bo); 431 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 432 struct amdgpu_bo_va *bo_va, 433 uint64_t addr, uint64_t offset, 434 uint64_t size, uint64_t flags); 435 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 436 struct amdgpu_bo_va *bo_va, 437 uint64_t addr, uint64_t offset, 438 uint64_t size, uint64_t flags); 439 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 440 struct amdgpu_bo_va *bo_va, 441 uint64_t addr); 442 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 443 struct amdgpu_vm *vm, 444 uint64_t saddr, uint64_t size); 445 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 446 uint64_t addr); 447 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 448 void amdgpu_vm_bo_del(struct amdgpu_device *adev, 449 struct amdgpu_bo_va *bo_va); 450 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 451 uint32_t fragment_size_default, unsigned max_level, 452 unsigned max_bits); 453 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 454 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 455 struct amdgpu_job *job); 456 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 457 458 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 459 struct amdgpu_task_info *task_info); 460 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 461 u32 vmid, u32 node_id, uint64_t addr, 462 bool write_fault); 463 464 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 465 466 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 467 struct amdgpu_vm *vm); 468 void amdgpu_vm_get_memory(struct amdgpu_vm *vm, 469 struct amdgpu_mem_stats *stats); 470 471 int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, 472 struct amdgpu_bo_vm *vmbo, bool immediate); 473 int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, 474 int level, bool immediate, struct amdgpu_bo_vm **vmbo); 475 void amdgpu_vm_pt_free_root(struct amdgpu_device *adev, struct amdgpu_vm *vm); 476 bool amdgpu_vm_pt_is_root_clean(struct amdgpu_device *adev, 477 struct amdgpu_vm *vm); 478 479 int amdgpu_vm_pde_update(struct amdgpu_vm_update_params *params, 480 struct amdgpu_vm_bo_base *entry); 481 int amdgpu_vm_ptes_update(struct amdgpu_vm_update_params *params, 482 uint64_t start, uint64_t end, 483 uint64_t dst, uint64_t flags); 484 void amdgpu_vm_pt_free_work(struct work_struct *work); 485 486 #if defined(CONFIG_DEBUG_FS) 487 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 488 #endif 489 490 /** 491 * amdgpu_vm_tlb_seq - return tlb flush sequence number 492 * @vm: the amdgpu_vm structure to query 493 * 494 * Returns the tlb flush sequence number which indicates that the VM TLBs needs 495 * to be invalidated whenever the sequence number change. 496 */ 497 static inline uint64_t amdgpu_vm_tlb_seq(struct amdgpu_vm *vm) 498 { 499 unsigned long flags; 500 spinlock_t *lock; 501 502 /* 503 * Workaround to stop racing between the fence signaling and handling 504 * the cb. The lock is static after initially setting it up, just make 505 * sure that the dma_fence structure isn't freed up. 506 */ 507 rcu_read_lock(); 508 lock = vm->last_tlb_flush->lock; 509 rcu_read_unlock(); 510 511 spin_lock_irqsave(lock, flags); 512 spin_unlock_irqrestore(lock, flags); 513 514 return atomic64_read(&vm->tlb_seq); 515 } 516 517 /* 518 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS 519 * happens while holding this lock anywhere to prevent deadlocks when 520 * an MMU notifier runs in reclaim-FS context. 521 */ 522 static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm) 523 { 524 mutex_lock(&vm->eviction_lock); 525 vm->saved_flags = memalloc_noreclaim_save(); 526 } 527 528 static inline bool amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm) 529 { 530 if (mutex_trylock(&vm->eviction_lock)) { 531 vm->saved_flags = memalloc_noreclaim_save(); 532 return true; 533 } 534 return false; 535 } 536 537 static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) 538 { 539 memalloc_noreclaim_restore(vm->saved_flags); 540 mutex_unlock(&vm->eviction_lock); 541 } 542 543 #endif 544