1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo_driver.h> 33 #include <linux/sched/mm.h> 34 35 #include "amdgpu_sync.h" 36 #include "amdgpu_ring.h" 37 #include "amdgpu_ids.h" 38 39 struct amdgpu_bo_va; 40 struct amdgpu_job; 41 struct amdgpu_bo_list_entry; 42 43 /* 44 * GPUVM handling 45 */ 46 47 /* Maximum number of PTEs the hardware can write with one command */ 48 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 49 50 /* number of entries in page table */ 51 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 52 53 #define AMDGPU_PTE_VALID (1ULL << 0) 54 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 55 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 56 57 /* RV+ */ 58 #define AMDGPU_PTE_TMZ (1ULL << 3) 59 60 /* VI only */ 61 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 62 63 #define AMDGPU_PTE_READABLE (1ULL << 5) 64 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 65 66 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 67 68 /* TILED for VEGA10, reserved for older ASICs */ 69 #define AMDGPU_PTE_PRT (1ULL << 51) 70 71 /* PDE is handled as PTE for VEGA10 */ 72 #define AMDGPU_PDE_PTE (1ULL << 54) 73 74 #define AMDGPU_PTE_LOG (1ULL << 55) 75 76 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 77 #define AMDGPU_PTE_TF (1ULL << 56) 78 79 /* MALL noalloc for sienna_cichlid, reserved for older ASICs */ 80 #define AMDGPU_PTE_NOALLOC (1ULL << 58) 81 82 /* PDE Block Fragment Size for VEGA10 */ 83 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 84 85 86 /* For GFX9 */ 87 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 88 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 89 90 #define AMDGPU_MTYPE_NC 0 91 #define AMDGPU_MTYPE_CC 2 92 93 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 94 | AMDGPU_PTE_SNOOPED \ 95 | AMDGPU_PTE_EXECUTABLE \ 96 | AMDGPU_PTE_READABLE \ 97 | AMDGPU_PTE_WRITEABLE \ 98 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 99 100 /* gfx10 */ 101 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 102 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 103 104 /* How to program VM fault handling */ 105 #define AMDGPU_VM_FAULT_STOP_NEVER 0 106 #define AMDGPU_VM_FAULT_STOP_FIRST 1 107 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 108 109 /* Reserve 4MB VRAM for page tables */ 110 #define AMDGPU_VM_RESERVED_VRAM (8ULL << 20) 111 112 /* max number of VMHUB */ 113 #define AMDGPU_MAX_VMHUBS 3 114 #define AMDGPU_GFXHUB_0 0 115 #define AMDGPU_MMHUB_0 1 116 #define AMDGPU_MMHUB_1 2 117 118 /* Reserve 2MB at top/bottom of address space for kernel use */ 119 #define AMDGPU_VA_RESERVED_SIZE (2ULL << 20) 120 121 /* max vmids dedicated for process */ 122 #define AMDGPU_VM_MAX_RESERVED_VMID 1 123 124 /* See vm_update_mode */ 125 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 126 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 127 128 /* VMPT level enumerate, and the hiberachy is: 129 * PDB2->PDB1->PDB0->PTB 130 */ 131 enum amdgpu_vm_level { 132 AMDGPU_VM_PDB2, 133 AMDGPU_VM_PDB1, 134 AMDGPU_VM_PDB0, 135 AMDGPU_VM_PTB 136 }; 137 138 /* base structure for tracking BO usage in a VM */ 139 struct amdgpu_vm_bo_base { 140 /* constant after initialization */ 141 struct amdgpu_vm *vm; 142 struct amdgpu_bo *bo; 143 144 /* protected by bo being reserved */ 145 struct amdgpu_vm_bo_base *next; 146 147 /* protected by spinlock */ 148 struct list_head vm_status; 149 150 /* protected by the BO being reserved */ 151 bool moved; 152 }; 153 154 struct amdgpu_vm_pt { 155 struct amdgpu_vm_bo_base base; 156 157 /* array of page tables, one for each directory entry */ 158 struct amdgpu_vm_pt *entries; 159 }; 160 161 /* provided by hw blocks that can write ptes, e.g., sdma */ 162 struct amdgpu_vm_pte_funcs { 163 /* number of dw to reserve per operation */ 164 unsigned copy_pte_num_dw; 165 166 /* copy pte entries from GART */ 167 void (*copy_pte)(struct amdgpu_ib *ib, 168 uint64_t pe, uint64_t src, 169 unsigned count); 170 171 /* write pte one entry at a time with addr mapping */ 172 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 173 uint64_t value, unsigned count, 174 uint32_t incr); 175 /* for linear pte/pde updates without addr mapping */ 176 void (*set_pte_pde)(struct amdgpu_ib *ib, 177 uint64_t pe, 178 uint64_t addr, unsigned count, 179 uint32_t incr, uint64_t flags); 180 }; 181 182 struct amdgpu_task_info { 183 char process_name[TASK_COMM_LEN]; 184 char task_name[TASK_COMM_LEN]; 185 pid_t pid; 186 pid_t tgid; 187 }; 188 189 /** 190 * struct amdgpu_vm_update_params 191 * 192 * Encapsulate some VM table update parameters to reduce 193 * the number of function parameters 194 * 195 */ 196 struct amdgpu_vm_update_params { 197 198 /** 199 * @adev: amdgpu device we do this update for 200 */ 201 struct amdgpu_device *adev; 202 203 /** 204 * @vm: optional amdgpu_vm we do this update for 205 */ 206 struct amdgpu_vm *vm; 207 208 /** 209 * @immediate: if changes should be made immediately 210 */ 211 bool immediate; 212 213 /** 214 * @unlocked: true if the root BO is not locked 215 */ 216 bool unlocked; 217 218 /** 219 * @pages_addr: 220 * 221 * DMA addresses to use for mapping 222 */ 223 dma_addr_t *pages_addr; 224 225 /** 226 * @job: job to used for hw submission 227 */ 228 struct amdgpu_job *job; 229 230 /** 231 * @num_dw_left: number of dw left for the IB 232 */ 233 unsigned int num_dw_left; 234 235 /** 236 * @table_freed: return true if page table is freed when updating 237 */ 238 bool table_freed; 239 }; 240 241 struct amdgpu_vm_update_funcs { 242 int (*map_table)(struct amdgpu_bo *bo); 243 int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, 244 enum amdgpu_sync_mode sync_mode); 245 int (*update)(struct amdgpu_vm_update_params *p, 246 struct amdgpu_bo *bo, uint64_t pe, uint64_t addr, 247 unsigned count, uint32_t incr, uint64_t flags); 248 int (*commit)(struct amdgpu_vm_update_params *p, 249 struct dma_fence **fence); 250 }; 251 252 struct amdgpu_vm { 253 /* tree of virtual addresses mapped */ 254 struct rb_root_cached va; 255 256 /* Lock to prevent eviction while we are updating page tables 257 * use vm_eviction_lock/unlock(vm) 258 */ 259 struct mutex eviction_lock; 260 bool evicting; 261 unsigned int saved_flags; 262 263 /* BOs who needs a validation */ 264 struct list_head evicted; 265 266 /* PT BOs which relocated and their parent need an update */ 267 struct list_head relocated; 268 269 /* per VM BOs moved, but not yet updated in the PT */ 270 struct list_head moved; 271 272 /* All BOs of this VM not currently in the state machine */ 273 struct list_head idle; 274 275 /* regular invalidated BOs, but not yet updated in the PT */ 276 struct list_head invalidated; 277 spinlock_t invalidated_lock; 278 279 /* BO mappings freed, but not yet updated in the PT */ 280 struct list_head freed; 281 282 /* BOs which are invalidated, has been updated in the PTs */ 283 struct list_head done; 284 285 /* contains the page directory */ 286 struct amdgpu_vm_pt root; 287 struct dma_fence *last_update; 288 289 /* Scheduler entities for page table updates */ 290 struct drm_sched_entity immediate; 291 struct drm_sched_entity delayed; 292 293 /* Last unlocked submission to the scheduler entities */ 294 struct dma_fence *last_unlocked; 295 296 unsigned int pasid; 297 /* dedicated to vm */ 298 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 299 300 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 301 bool use_cpu_for_update; 302 303 /* Functions to use for VM table updates */ 304 const struct amdgpu_vm_update_funcs *update_funcs; 305 306 /* Flag to indicate ATS support from PTE for GFX9 */ 307 bool pte_support_ats; 308 309 /* Up to 128 pending retry page faults */ 310 DECLARE_KFIFO(faults, u64, 128); 311 312 /* Points to the KFD process VM info */ 313 struct amdkfd_process_info *process_info; 314 315 /* List node in amdkfd_process_info.vm_list_head */ 316 struct list_head vm_list_node; 317 318 /* Valid while the PD is reserved or fenced */ 319 uint64_t pd_phys_addr; 320 321 /* Some basic info about the task */ 322 struct amdgpu_task_info task_info; 323 324 /* Store positions of group of BOs */ 325 struct ttm_lru_bulk_move lru_bulk_move; 326 /* mark whether can do the bulk move */ 327 bool bulk_moveable; 328 /* Flag to indicate if VM is used for compute */ 329 bool is_compute_context; 330 }; 331 332 struct amdgpu_vm_manager { 333 /* Handling of VMIDs */ 334 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 335 unsigned int first_kfd_vmid; 336 bool concurrent_flush; 337 338 /* Handling of VM fences */ 339 u64 fence_context; 340 unsigned seqno[AMDGPU_MAX_RINGS]; 341 342 uint64_t max_pfn; 343 uint32_t num_level; 344 uint32_t block_size; 345 uint32_t fragment_size; 346 enum amdgpu_vm_level root_level; 347 /* vram base address for page table entry */ 348 u64 vram_base_offset; 349 /* vm pte handling */ 350 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 351 struct drm_gpu_scheduler *vm_pte_scheds[AMDGPU_MAX_RINGS]; 352 unsigned vm_pte_num_scheds; 353 struct amdgpu_ring *page_fault; 354 355 /* partial resident texture handling */ 356 spinlock_t prt_lock; 357 atomic_t num_prt_users; 358 359 /* controls how VM page tables are updated for Graphics and Compute. 360 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 361 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 362 */ 363 int vm_update_mode; 364 365 /* PASID to VM mapping, will be used in interrupt context to 366 * look up VM of a page fault 367 */ 368 struct idr pasid_idr; 369 spinlock_t pasid_lock; 370 }; 371 372 struct amdgpu_bo_va_mapping; 373 374 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 375 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 376 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 377 378 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 379 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 380 381 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 382 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 383 384 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 385 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid); 386 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid); 387 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 388 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 389 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 390 struct list_head *validated, 391 struct amdgpu_bo_list_entry *entry); 392 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 393 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 394 int (*callback)(void *p, struct amdgpu_bo *bo), 395 void *param); 396 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 397 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 398 struct amdgpu_vm *vm, bool immediate); 399 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 400 struct amdgpu_vm *vm, 401 struct dma_fence **fence); 402 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 403 struct amdgpu_vm *vm); 404 int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev, 405 struct amdgpu_device *bo_adev, 406 struct amdgpu_vm *vm, bool immediate, 407 bool unlocked, struct dma_resv *resv, 408 uint64_t start, uint64_t last, 409 uint64_t flags, uint64_t offset, 410 struct ttm_resource *res, 411 dma_addr_t *pages_addr, 412 struct dma_fence **fence, bool *free_table); 413 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 414 struct amdgpu_bo_va *bo_va, 415 bool clear); 416 bool amdgpu_vm_evictable(struct amdgpu_bo *bo); 417 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 418 struct amdgpu_bo *bo, bool evicted); 419 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 420 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 421 struct amdgpu_bo *bo); 422 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 423 struct amdgpu_vm *vm, 424 struct amdgpu_bo *bo); 425 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 426 struct amdgpu_bo_va *bo_va, 427 uint64_t addr, uint64_t offset, 428 uint64_t size, uint64_t flags); 429 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 430 struct amdgpu_bo_va *bo_va, 431 uint64_t addr, uint64_t offset, 432 uint64_t size, uint64_t flags); 433 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 434 struct amdgpu_bo_va *bo_va, 435 uint64_t addr); 436 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 437 struct amdgpu_vm *vm, 438 uint64_t saddr, uint64_t size); 439 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 440 uint64_t addr); 441 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 442 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 443 struct amdgpu_bo_va *bo_va); 444 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 445 uint32_t fragment_size_default, unsigned max_level, 446 unsigned max_bits); 447 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 448 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 449 struct amdgpu_job *job); 450 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 451 452 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid, 453 struct amdgpu_task_info *task_info); 454 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, 455 uint64_t addr); 456 457 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 458 459 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 460 struct amdgpu_vm *vm); 461 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo); 462 463 #if defined(CONFIG_DEBUG_FS) 464 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m); 465 #endif 466 467 #endif 468