1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Christian König 23 */ 24 #ifndef __AMDGPU_VM_H__ 25 #define __AMDGPU_VM_H__ 26 27 #include <linux/idr.h> 28 #include <linux/kfifo.h> 29 #include <linux/rbtree.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_file.h> 32 #include <drm/ttm/ttm_bo_driver.h> 33 34 #include "amdgpu_sync.h" 35 #include "amdgpu_ring.h" 36 #include "amdgpu_ids.h" 37 38 struct amdgpu_bo_va; 39 struct amdgpu_job; 40 struct amdgpu_bo_list_entry; 41 42 /* 43 * GPUVM handling 44 */ 45 46 /* Maximum number of PTEs the hardware can write with one command */ 47 #define AMDGPU_VM_MAX_UPDATE_SIZE 0x3FFFF 48 49 /* number of entries in page table */ 50 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size) 51 52 #define AMDGPU_PTE_VALID (1ULL << 0) 53 #define AMDGPU_PTE_SYSTEM (1ULL << 1) 54 #define AMDGPU_PTE_SNOOPED (1ULL << 2) 55 56 /* VI only */ 57 #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) 58 59 #define AMDGPU_PTE_READABLE (1ULL << 5) 60 #define AMDGPU_PTE_WRITEABLE (1ULL << 6) 61 62 #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7) 63 64 /* TILED for VEGA10, reserved for older ASICs */ 65 #define AMDGPU_PTE_PRT (1ULL << 51) 66 67 /* PDE is handled as PTE for VEGA10 */ 68 #define AMDGPU_PDE_PTE (1ULL << 54) 69 70 #define AMDGPU_PTE_LOG (1ULL << 55) 71 72 /* PTE is handled as PDE for VEGA10 (Translate Further) */ 73 #define AMDGPU_PTE_TF (1ULL << 56) 74 75 /* PDE Block Fragment Size for VEGA10 */ 76 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59) 77 78 79 /* For GFX9 */ 80 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57) 81 #define AMDGPU_PTE_MTYPE_VG10_MASK AMDGPU_PTE_MTYPE_VG10(3ULL) 82 83 #define AMDGPU_MTYPE_NC 0 84 #define AMDGPU_MTYPE_CC 2 85 86 #define AMDGPU_PTE_DEFAULT_ATC (AMDGPU_PTE_SYSTEM \ 87 | AMDGPU_PTE_SNOOPED \ 88 | AMDGPU_PTE_EXECUTABLE \ 89 | AMDGPU_PTE_READABLE \ 90 | AMDGPU_PTE_WRITEABLE \ 91 | AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_CC)) 92 93 /* gfx10 */ 94 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48) 95 #define AMDGPU_PTE_MTYPE_NV10_MASK AMDGPU_PTE_MTYPE_NV10(7ULL) 96 97 /* How to programm VM fault handling */ 98 #define AMDGPU_VM_FAULT_STOP_NEVER 0 99 #define AMDGPU_VM_FAULT_STOP_FIRST 1 100 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 101 102 /* Reserve 4MB VRAM for page tables */ 103 #define AMDGPU_VM_RESERVED_VRAM (4ULL << 20) 104 105 /* max number of VMHUB */ 106 #define AMDGPU_MAX_VMHUBS 3 107 #define AMDGPU_GFXHUB_0 0 108 #define AMDGPU_MMHUB_0 1 109 #define AMDGPU_MMHUB_1 2 110 111 /* hardcode that limit for now */ 112 #define AMDGPU_VA_RESERVED_SIZE (1ULL << 20) 113 114 /* max vmids dedicated for process */ 115 #define AMDGPU_VM_MAX_RESERVED_VMID 1 116 117 #define AMDGPU_VM_CONTEXT_GFX 0 118 #define AMDGPU_VM_CONTEXT_COMPUTE 1 119 120 /* See vm_update_mode */ 121 #define AMDGPU_VM_USE_CPU_FOR_GFX (1 << 0) 122 #define AMDGPU_VM_USE_CPU_FOR_COMPUTE (1 << 1) 123 124 /* VMPT level enumerate, and the hiberachy is: 125 * PDB2->PDB1->PDB0->PTB 126 */ 127 enum amdgpu_vm_level { 128 AMDGPU_VM_PDB2, 129 AMDGPU_VM_PDB1, 130 AMDGPU_VM_PDB0, 131 AMDGPU_VM_PTB 132 }; 133 134 /* base structure for tracking BO usage in a VM */ 135 struct amdgpu_vm_bo_base { 136 /* constant after initialization */ 137 struct amdgpu_vm *vm; 138 struct amdgpu_bo *bo; 139 140 /* protected by bo being reserved */ 141 struct amdgpu_vm_bo_base *next; 142 143 /* protected by spinlock */ 144 struct list_head vm_status; 145 146 /* protected by the BO being reserved */ 147 bool moved; 148 }; 149 150 struct amdgpu_vm_pt { 151 struct amdgpu_vm_bo_base base; 152 153 /* array of page tables, one for each directory entry */ 154 struct amdgpu_vm_pt *entries; 155 }; 156 157 /* provided by hw blocks that can write ptes, e.g., sdma */ 158 struct amdgpu_vm_pte_funcs { 159 /* number of dw to reserve per operation */ 160 unsigned copy_pte_num_dw; 161 162 /* copy pte entries from GART */ 163 void (*copy_pte)(struct amdgpu_ib *ib, 164 uint64_t pe, uint64_t src, 165 unsigned count); 166 167 /* write pte one entry at a time with addr mapping */ 168 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 169 uint64_t value, unsigned count, 170 uint32_t incr); 171 /* for linear pte/pde updates without addr mapping */ 172 void (*set_pte_pde)(struct amdgpu_ib *ib, 173 uint64_t pe, 174 uint64_t addr, unsigned count, 175 uint32_t incr, uint64_t flags); 176 }; 177 178 struct amdgpu_task_info { 179 char process_name[TASK_COMM_LEN]; 180 char task_name[TASK_COMM_LEN]; 181 pid_t pid; 182 pid_t tgid; 183 }; 184 185 /** 186 * struct amdgpu_vm_update_params 187 * 188 * Encapsulate some VM table update parameters to reduce 189 * the number of function parameters 190 * 191 */ 192 struct amdgpu_vm_update_params { 193 194 /** 195 * @adev: amdgpu device we do this update for 196 */ 197 struct amdgpu_device *adev; 198 199 /** 200 * @vm: optional amdgpu_vm we do this update for 201 */ 202 struct amdgpu_vm *vm; 203 204 /** 205 * @direct: if changes should be made directly 206 */ 207 bool direct; 208 209 /** 210 * @pages_addr: 211 * 212 * DMA addresses to use for mapping 213 */ 214 dma_addr_t *pages_addr; 215 216 /** 217 * @job: job to used for hw submission 218 */ 219 struct amdgpu_job *job; 220 221 /** 222 * @num_dw_left: number of dw left for the IB 223 */ 224 unsigned int num_dw_left; 225 }; 226 227 struct amdgpu_vm_update_funcs { 228 int (*map_table)(struct amdgpu_bo *bo); 229 int (*prepare)(struct amdgpu_vm_update_params *p, void * owner, 230 struct dma_fence *exclusive); 231 int (*update)(struct amdgpu_vm_update_params *p, 232 struct amdgpu_bo *bo, uint64_t pe, uint64_t addr, 233 unsigned count, uint32_t incr, uint64_t flags); 234 int (*commit)(struct amdgpu_vm_update_params *p, 235 struct dma_fence **fence); 236 }; 237 238 struct amdgpu_vm { 239 /* tree of virtual addresses mapped */ 240 struct rb_root_cached va; 241 242 /* BOs who needs a validation */ 243 struct list_head evicted; 244 245 /* PT BOs which relocated and their parent need an update */ 246 struct list_head relocated; 247 248 /* per VM BOs moved, but not yet updated in the PT */ 249 struct list_head moved; 250 251 /* All BOs of this VM not currently in the state machine */ 252 struct list_head idle; 253 254 /* regular invalidated BOs, but not yet updated in the PT */ 255 struct list_head invalidated; 256 spinlock_t invalidated_lock; 257 258 /* BO mappings freed, but not yet updated in the PT */ 259 struct list_head freed; 260 261 /* contains the page directory */ 262 struct amdgpu_vm_pt root; 263 struct dma_fence *last_update; 264 265 /* Scheduler entities for page table updates */ 266 struct drm_sched_entity direct; 267 struct drm_sched_entity delayed; 268 269 unsigned int pasid; 270 /* dedicated to vm */ 271 struct amdgpu_vmid *reserved_vmid[AMDGPU_MAX_VMHUBS]; 272 273 /* Flag to indicate if VM tables are updated by CPU or GPU (SDMA) */ 274 bool use_cpu_for_update; 275 276 /* Functions to use for VM table updates */ 277 const struct amdgpu_vm_update_funcs *update_funcs; 278 279 /* Flag to indicate ATS support from PTE for GFX9 */ 280 bool pte_support_ats; 281 282 /* Up to 128 pending retry page faults */ 283 DECLARE_KFIFO(faults, u64, 128); 284 285 /* Points to the KFD process VM info */ 286 struct amdkfd_process_info *process_info; 287 288 /* List node in amdkfd_process_info.vm_list_head */ 289 struct list_head vm_list_node; 290 291 /* Valid while the PD is reserved or fenced */ 292 uint64_t pd_phys_addr; 293 294 /* Some basic info about the task */ 295 struct amdgpu_task_info task_info; 296 297 /* Store positions of group of BOs */ 298 struct ttm_lru_bulk_move lru_bulk_move; 299 /* mark whether can do the bulk move */ 300 bool bulk_moveable; 301 }; 302 303 struct amdgpu_vm_manager { 304 /* Handling of VMIDs */ 305 struct amdgpu_vmid_mgr id_mgr[AMDGPU_MAX_VMHUBS]; 306 307 /* Handling of VM fences */ 308 u64 fence_context; 309 unsigned seqno[AMDGPU_MAX_RINGS]; 310 311 uint64_t max_pfn; 312 uint32_t num_level; 313 uint32_t block_size; 314 uint32_t fragment_size; 315 enum amdgpu_vm_level root_level; 316 /* vram base address for page table entry */ 317 u64 vram_base_offset; 318 /* vm pte handling */ 319 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 320 struct drm_sched_rq *vm_pte_rqs[AMDGPU_MAX_RINGS]; 321 unsigned vm_pte_num_rqs; 322 struct amdgpu_ring *page_fault; 323 324 /* partial resident texture handling */ 325 spinlock_t prt_lock; 326 atomic_t num_prt_users; 327 328 /* controls how VM page tables are updated for Graphics and Compute. 329 * BIT0[= 0] Graphics updated by SDMA [= 1] by CPU 330 * BIT1[= 0] Compute updated by SDMA [= 1] by CPU 331 */ 332 int vm_update_mode; 333 334 /* PASID to VM mapping, will be used in interrupt context to 335 * look up VM of a page fault 336 */ 337 struct idr pasid_idr; 338 spinlock_t pasid_lock; 339 340 /* counter of mapped memory through xgmi */ 341 uint32_t xgmi_map_counter; 342 struct mutex lock_pstate; 343 }; 344 345 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 346 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 347 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 348 349 extern const struct amdgpu_vm_update_funcs amdgpu_vm_cpu_funcs; 350 extern const struct amdgpu_vm_update_funcs amdgpu_vm_sdma_funcs; 351 352 void amdgpu_vm_manager_init(struct amdgpu_device *adev); 353 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 354 355 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout); 356 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, 357 int vm_context, unsigned int pasid); 358 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid); 359 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm); 360 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 361 void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm, 362 struct list_head *validated, 363 struct amdgpu_bo_list_entry *entry); 364 bool amdgpu_vm_ready(struct amdgpu_vm *vm); 365 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm, 366 int (*callback)(void *p, struct amdgpu_bo *bo), 367 void *param); 368 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync); 369 int amdgpu_vm_update_pdes(struct amdgpu_device *adev, 370 struct amdgpu_vm *vm, bool direct); 371 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 372 struct amdgpu_vm *vm, 373 struct dma_fence **fence); 374 int amdgpu_vm_handle_moved(struct amdgpu_device *adev, 375 struct amdgpu_vm *vm); 376 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 377 struct amdgpu_bo_va *bo_va, 378 bool clear); 379 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 380 struct amdgpu_bo *bo, bool evicted); 381 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr); 382 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 383 struct amdgpu_bo *bo); 384 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 385 struct amdgpu_vm *vm, 386 struct amdgpu_bo *bo); 387 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 388 struct amdgpu_bo_va *bo_va, 389 uint64_t addr, uint64_t offset, 390 uint64_t size, uint64_t flags); 391 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev, 392 struct amdgpu_bo_va *bo_va, 393 uint64_t addr, uint64_t offset, 394 uint64_t size, uint64_t flags); 395 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 396 struct amdgpu_bo_va *bo_va, 397 uint64_t addr); 398 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev, 399 struct amdgpu_vm *vm, 400 uint64_t saddr, uint64_t size); 401 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm, 402 uint64_t addr); 403 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket); 404 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 405 struct amdgpu_bo_va *bo_va); 406 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, 407 uint32_t fragment_size_default, unsigned max_level, 408 unsigned max_bits); 409 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 410 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring, 411 struct amdgpu_job *job); 412 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev); 413 414 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid, 415 struct amdgpu_task_info *task_info); 416 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, unsigned int pasid, 417 uint64_t addr); 418 419 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); 420 421 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev, 422 struct amdgpu_vm *vm); 423 void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo); 424 425 #endif 426