1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 
29 #include <linux/dma-fence-array.h>
30 #include <linux/interval_tree_generic.h>
31 #include <linux/idr.h>
32 #include <linux/dma-buf.h>
33 
34 #include <drm/amdgpu_drm.h>
35 #include <drm/drm_drv.h>
36 #include <drm/ttm/ttm_tt.h>
37 #include <drm/drm_exec.h>
38 #include "amdgpu.h"
39 #include "amdgpu_trace.h"
40 #include "amdgpu_amdkfd.h"
41 #include "amdgpu_gmc.h"
42 #include "amdgpu_xgmi.h"
43 #include "amdgpu_dma_buf.h"
44 #include "amdgpu_res_cursor.h"
45 #include "kfd_svm.h"
46 
47 /**
48  * DOC: GPUVM
49  *
50  * GPUVM is the MMU functionality provided on the GPU.
51  * GPUVM is similar to the legacy GART on older asics, however
52  * rather than there being a single global GART table
53  * for the entire GPU, there can be multiple GPUVM page tables active
54  * at any given time.  The GPUVM page tables can contain a mix
55  * VRAM pages and system pages (both memory and MMIO) and system pages
56  * can be mapped as snooped (cached system pages) or unsnooped
57  * (uncached system pages).
58  *
59  * Each active GPUVM has an ID associated with it and there is a page table
60  * linked with each VMID.  When executing a command buffer,
61  * the kernel tells the engine what VMID to use for that command
62  * buffer.  VMIDs are allocated dynamically as commands are submitted.
63  * The userspace drivers maintain their own address space and the kernel
64  * sets up their pages tables accordingly when they submit their
65  * command buffers and a VMID is assigned.
66  * The hardware supports up to 16 active GPUVMs at any given time.
67  *
68  * Each GPUVM is represented by a 1-2 or 1-5 level page table, depending
69  * on the ASIC family.  GPUVM supports RWX attributes on each page as well
70  * as other features such as encryption and caching attributes.
71  *
72  * VMID 0 is special.  It is the GPUVM used for the kernel driver.  In
73  * addition to an aperture managed by a page table, VMID 0 also has
74  * several other apertures.  There is an aperture for direct access to VRAM
75  * and there is a legacy AGP aperture which just forwards accesses directly
76  * to the matching system physical addresses (or IOVAs when an IOMMU is
77  * present).  These apertures provide direct access to these memories without
78  * incurring the overhead of a page table.  VMID 0 is used by the kernel
79  * driver for tasks like memory management.
80  *
81  * GPU clients (i.e., engines on the GPU) use GPUVM VMIDs to access memory.
82  * For user applications, each application can have their own unique GPUVM
83  * address space.  The application manages the address space and the kernel
84  * driver manages the GPUVM page tables for each process.  If an GPU client
85  * accesses an invalid page, it will generate a GPU page fault, similar to
86  * accessing an invalid page on a CPU.
87  */
88 
89 #define START(node) ((node)->start)
90 #define LAST(node) ((node)->last)
91 
92 INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
93 		     START, LAST, static, amdgpu_vm_it)
94 
95 #undef START
96 #undef LAST
97 
98 /**
99  * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
100  */
101 struct amdgpu_prt_cb {
102 
103 	/**
104 	 * @adev: amdgpu device
105 	 */
106 	struct amdgpu_device *adev;
107 
108 	/**
109 	 * @cb: callback
110 	 */
111 	struct dma_fence_cb cb;
112 };
113 
114 /**
115  * struct amdgpu_vm_tlb_seq_struct - Helper to increment the TLB flush sequence
116  */
117 struct amdgpu_vm_tlb_seq_struct {
118 	/**
119 	 * @vm: pointer to the amdgpu_vm structure to set the fence sequence on
120 	 */
121 	struct amdgpu_vm *vm;
122 
123 	/**
124 	 * @cb: callback
125 	 */
126 	struct dma_fence_cb cb;
127 };
128 
129 /**
130  * amdgpu_vm_set_pasid - manage pasid and vm ptr mapping
131  *
132  * @adev: amdgpu_device pointer
133  * @vm: amdgpu_vm pointer
134  * @pasid: the pasid the VM is using on this GPU
135  *
136  * Set the pasid this VM is using on this GPU, can also be used to remove the
137  * pasid by passing in zero.
138  *
139  */
140 int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm,
141 			u32 pasid)
142 {
143 	int r;
144 
145 	if (vm->pasid == pasid)
146 		return 0;
147 
148 	if (vm->pasid) {
149 		r = xa_err(xa_erase_irq(&adev->vm_manager.pasids, vm->pasid));
150 		if (r < 0)
151 			return r;
152 
153 		vm->pasid = 0;
154 	}
155 
156 	if (pasid) {
157 		r = xa_err(xa_store_irq(&adev->vm_manager.pasids, pasid, vm,
158 					GFP_KERNEL));
159 		if (r < 0)
160 			return r;
161 
162 		vm->pasid = pasid;
163 	}
164 
165 
166 	return 0;
167 }
168 
169 /**
170  * amdgpu_vm_bo_evicted - vm_bo is evicted
171  *
172  * @vm_bo: vm_bo which is evicted
173  *
174  * State for PDs/PTs and per VM BOs which are not at the location they should
175  * be.
176  */
177 static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
178 {
179 	struct amdgpu_vm *vm = vm_bo->vm;
180 	struct amdgpu_bo *bo = vm_bo->bo;
181 
182 	vm_bo->moved = true;
183 	spin_lock(&vm_bo->vm->status_lock);
184 	if (bo->tbo.type == ttm_bo_type_kernel)
185 		list_move(&vm_bo->vm_status, &vm->evicted);
186 	else
187 		list_move_tail(&vm_bo->vm_status, &vm->evicted);
188 	spin_unlock(&vm_bo->vm->status_lock);
189 }
190 /**
191  * amdgpu_vm_bo_moved - vm_bo is moved
192  *
193  * @vm_bo: vm_bo which is moved
194  *
195  * State for per VM BOs which are moved, but that change is not yet reflected
196  * in the page tables.
197  */
198 static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
199 {
200 	spin_lock(&vm_bo->vm->status_lock);
201 	list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
202 	spin_unlock(&vm_bo->vm->status_lock);
203 }
204 
205 /**
206  * amdgpu_vm_bo_idle - vm_bo is idle
207  *
208  * @vm_bo: vm_bo which is now idle
209  *
210  * State for PDs/PTs and per VM BOs which have gone through the state machine
211  * and are now idle.
212  */
213 static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
214 {
215 	spin_lock(&vm_bo->vm->status_lock);
216 	list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
217 	spin_unlock(&vm_bo->vm->status_lock);
218 	vm_bo->moved = false;
219 }
220 
221 /**
222  * amdgpu_vm_bo_invalidated - vm_bo is invalidated
223  *
224  * @vm_bo: vm_bo which is now invalidated
225  *
226  * State for normal BOs which are invalidated and that change not yet reflected
227  * in the PTs.
228  */
229 static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
230 {
231 	spin_lock(&vm_bo->vm->status_lock);
232 	list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
233 	spin_unlock(&vm_bo->vm->status_lock);
234 }
235 
236 /**
237  * amdgpu_vm_bo_relocated - vm_bo is reloacted
238  *
239  * @vm_bo: vm_bo which is relocated
240  *
241  * State for PDs/PTs which needs to update their parent PD.
242  * For the root PD, just move to idle state.
243  */
244 static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
245 {
246 	if (vm_bo->bo->parent) {
247 		spin_lock(&vm_bo->vm->status_lock);
248 		list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
249 		spin_unlock(&vm_bo->vm->status_lock);
250 	} else {
251 		amdgpu_vm_bo_idle(vm_bo);
252 	}
253 }
254 
255 /**
256  * amdgpu_vm_bo_done - vm_bo is done
257  *
258  * @vm_bo: vm_bo which is now done
259  *
260  * State for normal BOs which are invalidated and that change has been updated
261  * in the PTs.
262  */
263 static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
264 {
265 	spin_lock(&vm_bo->vm->status_lock);
266 	list_move(&vm_bo->vm_status, &vm_bo->vm->done);
267 	spin_unlock(&vm_bo->vm->status_lock);
268 }
269 
270 /**
271  * amdgpu_vm_bo_reset_state_machine - reset the vm_bo state machine
272  * @vm: the VM which state machine to reset
273  *
274  * Move all vm_bo object in the VM into a state where they will be updated
275  * again during validation.
276  */
277 static void amdgpu_vm_bo_reset_state_machine(struct amdgpu_vm *vm)
278 {
279 	struct amdgpu_vm_bo_base *vm_bo, *tmp;
280 
281 	spin_lock(&vm->status_lock);
282 	list_splice_init(&vm->done, &vm->invalidated);
283 	list_for_each_entry(vm_bo, &vm->invalidated, vm_status)
284 		vm_bo->moved = true;
285 	list_for_each_entry_safe(vm_bo, tmp, &vm->idle, vm_status) {
286 		struct amdgpu_bo *bo = vm_bo->bo;
287 
288 		vm_bo->moved = true;
289 		if (!bo || bo->tbo.type != ttm_bo_type_kernel)
290 			list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
291 		else if (bo->parent)
292 			list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
293 	}
294 	spin_unlock(&vm->status_lock);
295 }
296 
297 /**
298  * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
299  *
300  * @base: base structure for tracking BO usage in a VM
301  * @vm: vm to which bo is to be added
302  * @bo: amdgpu buffer object
303  *
304  * Initialize a bo_va_base structure and add it to the appropriate lists
305  *
306  */
307 void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
308 			    struct amdgpu_vm *vm, struct amdgpu_bo *bo)
309 {
310 	base->vm = vm;
311 	base->bo = bo;
312 	base->next = NULL;
313 	INIT_LIST_HEAD(&base->vm_status);
314 
315 	if (!bo)
316 		return;
317 	base->next = bo->vm_bo;
318 	bo->vm_bo = base;
319 
320 	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
321 		return;
322 
323 	dma_resv_assert_held(vm->root.bo->tbo.base.resv);
324 
325 	ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move);
326 	if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
327 		amdgpu_vm_bo_relocated(base);
328 	else
329 		amdgpu_vm_bo_idle(base);
330 
331 	if (bo->preferred_domains &
332 	    amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
333 		return;
334 
335 	/*
336 	 * we checked all the prerequisites, but it looks like this per vm bo
337 	 * is currently evicted. add the bo to the evicted list to make sure it
338 	 * is validated on next vm use to avoid fault.
339 	 * */
340 	amdgpu_vm_bo_evicted(base);
341 }
342 
343 /**
344  * amdgpu_vm_lock_pd - lock PD in drm_exec
345  *
346  * @vm: vm providing the BOs
347  * @exec: drm execution context
348  * @num_fences: number of extra fences to reserve
349  *
350  * Lock the VM root PD in the DRM execution context.
351  */
352 int amdgpu_vm_lock_pd(struct amdgpu_vm *vm, struct drm_exec *exec,
353 		      unsigned int num_fences)
354 {
355 	/* We need at least two fences for the VM PD/PT updates */
356 	return drm_exec_prepare_obj(exec, &vm->root.bo->tbo.base,
357 				    2 + num_fences);
358 }
359 
360 /**
361  * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
362  *
363  * @adev: amdgpu device pointer
364  * @vm: vm providing the BOs
365  *
366  * Move all BOs to the end of LRU and remember their positions to put them
367  * together.
368  */
369 void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
370 				struct amdgpu_vm *vm)
371 {
372 	spin_lock(&adev->mman.bdev.lru_lock);
373 	ttm_lru_bulk_move_tail(&vm->lru_bulk_move);
374 	spin_unlock(&adev->mman.bdev.lru_lock);
375 }
376 
377 /* Create scheduler entities for page table updates */
378 static int amdgpu_vm_init_entities(struct amdgpu_device *adev,
379 				   struct amdgpu_vm *vm)
380 {
381 	int r;
382 
383 	r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
384 				  adev->vm_manager.vm_pte_scheds,
385 				  adev->vm_manager.vm_pte_num_scheds, NULL);
386 	if (r)
387 		goto error;
388 
389 	return drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
390 				     adev->vm_manager.vm_pte_scheds,
391 				     adev->vm_manager.vm_pte_num_scheds, NULL);
392 
393 error:
394 	drm_sched_entity_destroy(&vm->immediate);
395 	return r;
396 }
397 
398 /* Destroy the entities for page table updates again */
399 static void amdgpu_vm_fini_entities(struct amdgpu_vm *vm)
400 {
401 	drm_sched_entity_destroy(&vm->immediate);
402 	drm_sched_entity_destroy(&vm->delayed);
403 }
404 
405 /**
406  * amdgpu_vm_generation - return the page table re-generation counter
407  * @adev: the amdgpu_device
408  * @vm: optional VM to check, might be NULL
409  *
410  * Returns a page table re-generation token to allow checking if submissions
411  * are still valid to use this VM. The VM parameter might be NULL in which case
412  * just the VRAM lost counter will be used.
413  */
414 uint64_t amdgpu_vm_generation(struct amdgpu_device *adev, struct amdgpu_vm *vm)
415 {
416 	uint64_t result = (u64)atomic_read(&adev->vram_lost_counter) << 32;
417 
418 	if (!vm)
419 		return result;
420 
421 	result += vm->generation;
422 	/* Add one if the page tables will be re-generated on next CS */
423 	if (drm_sched_entity_error(&vm->delayed))
424 		++result;
425 
426 	return result;
427 }
428 
429 /**
430  * amdgpu_vm_validate_pt_bos - validate the page table BOs
431  *
432  * @adev: amdgpu device pointer
433  * @vm: vm providing the BOs
434  * @validate: callback to do the validation
435  * @param: parameter for the validation callback
436  *
437  * Validate the page table BOs on command submission if neccessary.
438  *
439  * Returns:
440  * Validation result.
441  */
442 int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
443 			      int (*validate)(void *p, struct amdgpu_bo *bo),
444 			      void *param)
445 {
446 	struct amdgpu_vm_bo_base *bo_base;
447 	struct amdgpu_bo *shadow;
448 	struct amdgpu_bo *bo;
449 	int r;
450 
451 	if (drm_sched_entity_error(&vm->delayed)) {
452 		++vm->generation;
453 		amdgpu_vm_bo_reset_state_machine(vm);
454 		amdgpu_vm_fini_entities(vm);
455 		r = amdgpu_vm_init_entities(adev, vm);
456 		if (r)
457 			return r;
458 	}
459 
460 	spin_lock(&vm->status_lock);
461 	while (!list_empty(&vm->evicted)) {
462 		bo_base = list_first_entry(&vm->evicted,
463 					   struct amdgpu_vm_bo_base,
464 					   vm_status);
465 		spin_unlock(&vm->status_lock);
466 
467 		bo = bo_base->bo;
468 		shadow = amdgpu_bo_shadowed(bo);
469 
470 		r = validate(param, bo);
471 		if (r)
472 			return r;
473 		if (shadow) {
474 			r = validate(param, shadow);
475 			if (r)
476 				return r;
477 		}
478 
479 		if (bo->tbo.type != ttm_bo_type_kernel) {
480 			amdgpu_vm_bo_moved(bo_base);
481 		} else {
482 			vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
483 			amdgpu_vm_bo_relocated(bo_base);
484 		}
485 		spin_lock(&vm->status_lock);
486 	}
487 	spin_unlock(&vm->status_lock);
488 
489 	amdgpu_vm_eviction_lock(vm);
490 	vm->evicting = false;
491 	amdgpu_vm_eviction_unlock(vm);
492 
493 	return 0;
494 }
495 
496 /**
497  * amdgpu_vm_ready - check VM is ready for updates
498  *
499  * @vm: VM to check
500  *
501  * Check if all VM PDs/PTs are ready for updates
502  *
503  * Returns:
504  * True if VM is not evicting.
505  */
506 bool amdgpu_vm_ready(struct amdgpu_vm *vm)
507 {
508 	bool empty;
509 	bool ret;
510 
511 	amdgpu_vm_eviction_lock(vm);
512 	ret = !vm->evicting;
513 	amdgpu_vm_eviction_unlock(vm);
514 
515 	spin_lock(&vm->status_lock);
516 	empty = list_empty(&vm->evicted);
517 	spin_unlock(&vm->status_lock);
518 
519 	return ret && empty;
520 }
521 
522 /**
523  * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
524  *
525  * @adev: amdgpu_device pointer
526  */
527 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
528 {
529 	const struct amdgpu_ip_block *ip_block;
530 	bool has_compute_vm_bug;
531 	struct amdgpu_ring *ring;
532 	int i;
533 
534 	has_compute_vm_bug = false;
535 
536 	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
537 	if (ip_block) {
538 		/* Compute has a VM bug for GFX version < 7.
539 		   Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
540 		if (ip_block->version->major <= 7)
541 			has_compute_vm_bug = true;
542 		else if (ip_block->version->major == 8)
543 			if (adev->gfx.mec_fw_version < 673)
544 				has_compute_vm_bug = true;
545 	}
546 
547 	for (i = 0; i < adev->num_rings; i++) {
548 		ring = adev->rings[i];
549 		if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
550 			/* only compute rings */
551 			ring->has_compute_vm_bug = has_compute_vm_bug;
552 		else
553 			ring->has_compute_vm_bug = false;
554 	}
555 }
556 
557 /**
558  * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
559  *
560  * @ring: ring on which the job will be submitted
561  * @job: job to submit
562  *
563  * Returns:
564  * True if sync is needed.
565  */
566 bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
567 				  struct amdgpu_job *job)
568 {
569 	struct amdgpu_device *adev = ring->adev;
570 	unsigned vmhub = ring->vm_hub;
571 	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
572 
573 	if (job->vmid == 0)
574 		return false;
575 
576 	if (job->vm_needs_flush || ring->has_compute_vm_bug)
577 		return true;
578 
579 	if (ring->funcs->emit_gds_switch && job->gds_switch_needed)
580 		return true;
581 
582 	if (amdgpu_vmid_had_gpu_reset(adev, &id_mgr->ids[job->vmid]))
583 		return true;
584 
585 	return false;
586 }
587 
588 /**
589  * amdgpu_vm_flush - hardware flush the vm
590  *
591  * @ring: ring to use for flush
592  * @job:  related job
593  * @need_pipe_sync: is pipe sync needed
594  *
595  * Emit a VM flush when it is necessary.
596  *
597  * Returns:
598  * 0 on success, errno otherwise.
599  */
600 int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
601 		    bool need_pipe_sync)
602 {
603 	struct amdgpu_device *adev = ring->adev;
604 	unsigned vmhub = ring->vm_hub;
605 	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
606 	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
607 	bool spm_update_needed = job->spm_update_needed;
608 	bool gds_switch_needed = ring->funcs->emit_gds_switch &&
609 		job->gds_switch_needed;
610 	bool vm_flush_needed = job->vm_needs_flush;
611 	struct dma_fence *fence = NULL;
612 	bool pasid_mapping_needed = false;
613 	unsigned patch_offset = 0;
614 	int r;
615 
616 	if (amdgpu_vmid_had_gpu_reset(adev, id)) {
617 		gds_switch_needed = true;
618 		vm_flush_needed = true;
619 		pasid_mapping_needed = true;
620 		spm_update_needed = true;
621 	}
622 
623 	mutex_lock(&id_mgr->lock);
624 	if (id->pasid != job->pasid || !id->pasid_mapping ||
625 	    !dma_fence_is_signaled(id->pasid_mapping))
626 		pasid_mapping_needed = true;
627 	mutex_unlock(&id_mgr->lock);
628 
629 	gds_switch_needed &= !!ring->funcs->emit_gds_switch;
630 	vm_flush_needed &= !!ring->funcs->emit_vm_flush  &&
631 			job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
632 	pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
633 		ring->funcs->emit_wreg;
634 
635 	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
636 		return 0;
637 
638 	amdgpu_ring_ib_begin(ring);
639 	if (ring->funcs->init_cond_exec)
640 		patch_offset = amdgpu_ring_init_cond_exec(ring);
641 
642 	if (need_pipe_sync)
643 		amdgpu_ring_emit_pipeline_sync(ring);
644 
645 	if (vm_flush_needed) {
646 		trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
647 		amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
648 	}
649 
650 	if (pasid_mapping_needed)
651 		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
652 
653 	if (spm_update_needed && adev->gfx.rlc.funcs->update_spm_vmid)
654 		adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
655 
656 	if (!ring->is_mes_queue && ring->funcs->emit_gds_switch &&
657 	    gds_switch_needed) {
658 		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
659 					    job->gds_size, job->gws_base,
660 					    job->gws_size, job->oa_base,
661 					    job->oa_size);
662 	}
663 
664 	if (vm_flush_needed || pasid_mapping_needed) {
665 		r = amdgpu_fence_emit(ring, &fence, NULL, 0);
666 		if (r)
667 			return r;
668 	}
669 
670 	if (vm_flush_needed) {
671 		mutex_lock(&id_mgr->lock);
672 		dma_fence_put(id->last_flush);
673 		id->last_flush = dma_fence_get(fence);
674 		id->current_gpu_reset_count =
675 			atomic_read(&adev->gpu_reset_counter);
676 		mutex_unlock(&id_mgr->lock);
677 	}
678 
679 	if (pasid_mapping_needed) {
680 		mutex_lock(&id_mgr->lock);
681 		id->pasid = job->pasid;
682 		dma_fence_put(id->pasid_mapping);
683 		id->pasid_mapping = dma_fence_get(fence);
684 		mutex_unlock(&id_mgr->lock);
685 	}
686 	dma_fence_put(fence);
687 
688 	if (ring->funcs->patch_cond_exec)
689 		amdgpu_ring_patch_cond_exec(ring, patch_offset);
690 
691 	/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
692 	if (ring->funcs->emit_switch_buffer) {
693 		amdgpu_ring_emit_switch_buffer(ring);
694 		amdgpu_ring_emit_switch_buffer(ring);
695 	}
696 	amdgpu_ring_ib_end(ring);
697 	return 0;
698 }
699 
700 /**
701  * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
702  *
703  * @vm: requested vm
704  * @bo: requested buffer object
705  *
706  * Find @bo inside the requested vm.
707  * Search inside the @bos vm list for the requested vm
708  * Returns the found bo_va or NULL if none is found
709  *
710  * Object has to be reserved!
711  *
712  * Returns:
713  * Found bo_va or NULL.
714  */
715 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
716 				       struct amdgpu_bo *bo)
717 {
718 	struct amdgpu_vm_bo_base *base;
719 
720 	for (base = bo->vm_bo; base; base = base->next) {
721 		if (base->vm != vm)
722 			continue;
723 
724 		return container_of(base, struct amdgpu_bo_va, base);
725 	}
726 	return NULL;
727 }
728 
729 /**
730  * amdgpu_vm_map_gart - Resolve gart mapping of addr
731  *
732  * @pages_addr: optional DMA address to use for lookup
733  * @addr: the unmapped addr
734  *
735  * Look up the physical address of the page that the pte resolves
736  * to.
737  *
738  * Returns:
739  * The pointer for the page table entry.
740  */
741 uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
742 {
743 	uint64_t result;
744 
745 	/* page table offset */
746 	result = pages_addr[addr >> PAGE_SHIFT];
747 
748 	/* in case cpu page size != gpu page size*/
749 	result |= addr & (~PAGE_MASK);
750 
751 	result &= 0xFFFFFFFFFFFFF000ULL;
752 
753 	return result;
754 }
755 
756 /**
757  * amdgpu_vm_update_pdes - make sure that all directories are valid
758  *
759  * @adev: amdgpu_device pointer
760  * @vm: requested vm
761  * @immediate: submit immediately to the paging queue
762  *
763  * Makes sure all directories are up to date.
764  *
765  * Returns:
766  * 0 for success, error for failure.
767  */
768 int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
769 			  struct amdgpu_vm *vm, bool immediate)
770 {
771 	struct amdgpu_vm_update_params params;
772 	struct amdgpu_vm_bo_base *entry;
773 	bool flush_tlb_needed = false;
774 	LIST_HEAD(relocated);
775 	int r, idx;
776 
777 	spin_lock(&vm->status_lock);
778 	list_splice_init(&vm->relocated, &relocated);
779 	spin_unlock(&vm->status_lock);
780 
781 	if (list_empty(&relocated))
782 		return 0;
783 
784 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
785 		return -ENODEV;
786 
787 	memset(&params, 0, sizeof(params));
788 	params.adev = adev;
789 	params.vm = vm;
790 	params.immediate = immediate;
791 
792 	r = vm->update_funcs->prepare(&params, NULL, AMDGPU_SYNC_EXPLICIT);
793 	if (r)
794 		goto error;
795 
796 	list_for_each_entry(entry, &relocated, vm_status) {
797 		/* vm_flush_needed after updating moved PDEs */
798 		flush_tlb_needed |= entry->moved;
799 
800 		r = amdgpu_vm_pde_update(&params, entry);
801 		if (r)
802 			goto error;
803 	}
804 
805 	r = vm->update_funcs->commit(&params, &vm->last_update);
806 	if (r)
807 		goto error;
808 
809 	if (flush_tlb_needed)
810 		atomic64_inc(&vm->tlb_seq);
811 
812 	while (!list_empty(&relocated)) {
813 		entry = list_first_entry(&relocated, struct amdgpu_vm_bo_base,
814 					 vm_status);
815 		amdgpu_vm_bo_idle(entry);
816 	}
817 
818 error:
819 	drm_dev_exit(idx);
820 	return r;
821 }
822 
823 /**
824  * amdgpu_vm_tlb_seq_cb - make sure to increment tlb sequence
825  * @fence: unused
826  * @cb: the callback structure
827  *
828  * Increments the tlb sequence to make sure that future CS execute a VM flush.
829  */
830 static void amdgpu_vm_tlb_seq_cb(struct dma_fence *fence,
831 				 struct dma_fence_cb *cb)
832 {
833 	struct amdgpu_vm_tlb_seq_struct *tlb_cb;
834 
835 	tlb_cb = container_of(cb, typeof(*tlb_cb), cb);
836 	atomic64_inc(&tlb_cb->vm->tlb_seq);
837 	kfree(tlb_cb);
838 }
839 
840 /**
841  * amdgpu_vm_update_range - update a range in the vm page table
842  *
843  * @adev: amdgpu_device pointer to use for commands
844  * @vm: the VM to update the range
845  * @immediate: immediate submission in a page fault
846  * @unlocked: unlocked invalidation during MM callback
847  * @flush_tlb: trigger tlb invalidation after update completed
848  * @resv: fences we need to sync to
849  * @start: start of mapped range
850  * @last: last mapped entry
851  * @flags: flags for the entries
852  * @offset: offset into nodes and pages_addr
853  * @vram_base: base for vram mappings
854  * @res: ttm_resource to map
855  * @pages_addr: DMA addresses to use for mapping
856  * @fence: optional resulting fence
857  *
858  * Fill in the page table entries between @start and @last.
859  *
860  * Returns:
861  * 0 for success, negative erro code for failure.
862  */
863 int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
864 			   bool immediate, bool unlocked, bool flush_tlb,
865 			   struct dma_resv *resv, uint64_t start, uint64_t last,
866 			   uint64_t flags, uint64_t offset, uint64_t vram_base,
867 			   struct ttm_resource *res, dma_addr_t *pages_addr,
868 			   struct dma_fence **fence)
869 {
870 	struct amdgpu_vm_update_params params;
871 	struct amdgpu_vm_tlb_seq_struct *tlb_cb;
872 	struct amdgpu_res_cursor cursor;
873 	enum amdgpu_sync_mode sync_mode;
874 	int r, idx;
875 
876 	if (!drm_dev_enter(adev_to_drm(adev), &idx))
877 		return -ENODEV;
878 
879 	tlb_cb = kmalloc(sizeof(*tlb_cb), GFP_KERNEL);
880 	if (!tlb_cb) {
881 		r = -ENOMEM;
882 		goto error_unlock;
883 	}
884 
885 	/* Vega20+XGMI where PTEs get inadvertently cached in L2 texture cache,
886 	 * heavy-weight flush TLB unconditionally.
887 	 */
888 	flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
889 		     adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
890 
891 	/*
892 	 * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
893 	 */
894 	flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
895 
896 	memset(&params, 0, sizeof(params));
897 	params.adev = adev;
898 	params.vm = vm;
899 	params.immediate = immediate;
900 	params.pages_addr = pages_addr;
901 	params.unlocked = unlocked;
902 
903 	/* Implicitly sync to command submissions in the same VM before
904 	 * unmapping. Sync to moving fences before mapping.
905 	 */
906 	if (!(flags & AMDGPU_PTE_VALID))
907 		sync_mode = AMDGPU_SYNC_EQ_OWNER;
908 	else
909 		sync_mode = AMDGPU_SYNC_EXPLICIT;
910 
911 	amdgpu_vm_eviction_lock(vm);
912 	if (vm->evicting) {
913 		r = -EBUSY;
914 		goto error_free;
915 	}
916 
917 	if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
918 		struct dma_fence *tmp = dma_fence_get_stub();
919 
920 		amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
921 		swap(vm->last_unlocked, tmp);
922 		dma_fence_put(tmp);
923 	}
924 
925 	r = vm->update_funcs->prepare(&params, resv, sync_mode);
926 	if (r)
927 		goto error_free;
928 
929 	amdgpu_res_first(pages_addr ? NULL : res, offset,
930 			 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
931 	while (cursor.remaining) {
932 		uint64_t tmp, num_entries, addr;
933 
934 		num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
935 		if (pages_addr) {
936 			bool contiguous = true;
937 
938 			if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
939 				uint64_t pfn = cursor.start >> PAGE_SHIFT;
940 				uint64_t count;
941 
942 				contiguous = pages_addr[pfn + 1] ==
943 					pages_addr[pfn] + PAGE_SIZE;
944 
945 				tmp = num_entries /
946 					AMDGPU_GPU_PAGES_IN_CPU_PAGE;
947 				for (count = 2; count < tmp; ++count) {
948 					uint64_t idx = pfn + count;
949 
950 					if (contiguous != (pages_addr[idx] ==
951 					    pages_addr[idx - 1] + PAGE_SIZE))
952 						break;
953 				}
954 				if (!contiguous)
955 					count--;
956 				num_entries = count *
957 					AMDGPU_GPU_PAGES_IN_CPU_PAGE;
958 			}
959 
960 			if (!contiguous) {
961 				addr = cursor.start;
962 				params.pages_addr = pages_addr;
963 			} else {
964 				addr = pages_addr[cursor.start >> PAGE_SHIFT];
965 				params.pages_addr = NULL;
966 			}
967 
968 		} else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
969 			addr = vram_base + cursor.start;
970 		} else {
971 			addr = 0;
972 		}
973 
974 		tmp = start + num_entries;
975 		r = amdgpu_vm_ptes_update(&params, start, tmp, addr, flags);
976 		if (r)
977 			goto error_free;
978 
979 		amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
980 		start = tmp;
981 	}
982 
983 	r = vm->update_funcs->commit(&params, fence);
984 
985 	if (flush_tlb || params.table_freed) {
986 		tlb_cb->vm = vm;
987 		if (fence && *fence &&
988 		    !dma_fence_add_callback(*fence, &tlb_cb->cb,
989 					   amdgpu_vm_tlb_seq_cb)) {
990 			dma_fence_put(vm->last_tlb_flush);
991 			vm->last_tlb_flush = dma_fence_get(*fence);
992 		} else {
993 			amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb);
994 		}
995 		tlb_cb = NULL;
996 	}
997 
998 error_free:
999 	kfree(tlb_cb);
1000 
1001 error_unlock:
1002 	amdgpu_vm_eviction_unlock(vm);
1003 	drm_dev_exit(idx);
1004 	return r;
1005 }
1006 
1007 static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va,
1008 				    struct amdgpu_mem_stats *stats)
1009 {
1010 	struct amdgpu_vm *vm = bo_va->base.vm;
1011 	struct amdgpu_bo *bo = bo_va->base.bo;
1012 
1013 	if (!bo)
1014 		return;
1015 
1016 	/*
1017 	 * For now ignore BOs which are currently locked and potentially
1018 	 * changing their location.
1019 	 */
1020 	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv &&
1021 	    !dma_resv_trylock(bo->tbo.base.resv))
1022 		return;
1023 
1024 	amdgpu_bo_get_memory(bo, stats);
1025 	if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
1026 	    dma_resv_unlock(bo->tbo.base.resv);
1027 }
1028 
1029 void amdgpu_vm_get_memory(struct amdgpu_vm *vm,
1030 			  struct amdgpu_mem_stats *stats)
1031 {
1032 	struct amdgpu_bo_va *bo_va, *tmp;
1033 
1034 	spin_lock(&vm->status_lock);
1035 	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status)
1036 		amdgpu_vm_bo_get_memory(bo_va, stats);
1037 
1038 	list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status)
1039 		amdgpu_vm_bo_get_memory(bo_va, stats);
1040 
1041 	list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status)
1042 		amdgpu_vm_bo_get_memory(bo_va, stats);
1043 
1044 	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status)
1045 		amdgpu_vm_bo_get_memory(bo_va, stats);
1046 
1047 	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status)
1048 		amdgpu_vm_bo_get_memory(bo_va, stats);
1049 
1050 	list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status)
1051 		amdgpu_vm_bo_get_memory(bo_va, stats);
1052 	spin_unlock(&vm->status_lock);
1053 }
1054 
1055 /**
1056  * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1057  *
1058  * @adev: amdgpu_device pointer
1059  * @bo_va: requested BO and VM object
1060  * @clear: if true clear the entries
1061  *
1062  * Fill in the page table entries for @bo_va.
1063  *
1064  * Returns:
1065  * 0 for success, -EINVAL for failure.
1066  */
1067 int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1068 			bool clear)
1069 {
1070 	struct amdgpu_bo *bo = bo_va->base.bo;
1071 	struct amdgpu_vm *vm = bo_va->base.vm;
1072 	struct amdgpu_bo_va_mapping *mapping;
1073 	dma_addr_t *pages_addr = NULL;
1074 	struct ttm_resource *mem;
1075 	struct dma_fence **last_update;
1076 	bool flush_tlb = clear;
1077 	struct dma_resv *resv;
1078 	uint64_t vram_base;
1079 	uint64_t flags;
1080 	int r;
1081 
1082 	if (clear || !bo) {
1083 		mem = NULL;
1084 		resv = vm->root.bo->tbo.base.resv;
1085 	} else {
1086 		struct drm_gem_object *obj = &bo->tbo.base;
1087 
1088 		resv = bo->tbo.base.resv;
1089 		if (obj->import_attach && bo_va->is_xgmi) {
1090 			struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1091 			struct drm_gem_object *gobj = dma_buf->priv;
1092 			struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1093 
1094 			if (abo->tbo.resource &&
1095 			    abo->tbo.resource->mem_type == TTM_PL_VRAM)
1096 				bo = gem_to_amdgpu_bo(gobj);
1097 		}
1098 		mem = bo->tbo.resource;
1099 		if (mem && (mem->mem_type == TTM_PL_TT ||
1100 			    mem->mem_type == AMDGPU_PL_PREEMPT))
1101 			pages_addr = bo->tbo.ttm->dma_address;
1102 	}
1103 
1104 	if (bo) {
1105 		struct amdgpu_device *bo_adev;
1106 
1107 		flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1108 
1109 		if (amdgpu_bo_encrypted(bo))
1110 			flags |= AMDGPU_PTE_TMZ;
1111 
1112 		bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1113 		vram_base = bo_adev->vm_manager.vram_base_offset;
1114 	} else {
1115 		flags = 0x0;
1116 		vram_base = 0;
1117 	}
1118 
1119 	if (clear || (bo && bo->tbo.base.resv ==
1120 		      vm->root.bo->tbo.base.resv))
1121 		last_update = &vm->last_update;
1122 	else
1123 		last_update = &bo_va->last_pt_update;
1124 
1125 	if (!clear && bo_va->base.moved) {
1126 		flush_tlb = true;
1127 		list_splice_init(&bo_va->valids, &bo_va->invalids);
1128 
1129 	} else if (bo_va->cleared != clear) {
1130 		list_splice_init(&bo_va->valids, &bo_va->invalids);
1131 	}
1132 
1133 	list_for_each_entry(mapping, &bo_va->invalids, list) {
1134 		uint64_t update_flags = flags;
1135 
1136 		/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1137 		 * but in case of something, we filter the flags in first place
1138 		 */
1139 		if (!(mapping->flags & AMDGPU_PTE_READABLE))
1140 			update_flags &= ~AMDGPU_PTE_READABLE;
1141 		if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1142 			update_flags &= ~AMDGPU_PTE_WRITEABLE;
1143 
1144 		/* Apply ASIC specific mapping flags */
1145 		amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1146 
1147 		trace_amdgpu_vm_bo_update(mapping);
1148 
1149 		r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb,
1150 					   resv, mapping->start, mapping->last,
1151 					   update_flags, mapping->offset,
1152 					   vram_base, mem, pages_addr,
1153 					   last_update);
1154 		if (r)
1155 			return r;
1156 	}
1157 
1158 	/* If the BO is not in its preferred location add it back to
1159 	 * the evicted list so that it gets validated again on the
1160 	 * next command submission.
1161 	 */
1162 	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1163 		uint32_t mem_type = bo->tbo.resource->mem_type;
1164 
1165 		if (!(bo->preferred_domains &
1166 		      amdgpu_mem_type_to_domain(mem_type)))
1167 			amdgpu_vm_bo_evicted(&bo_va->base);
1168 		else
1169 			amdgpu_vm_bo_idle(&bo_va->base);
1170 	} else {
1171 		amdgpu_vm_bo_done(&bo_va->base);
1172 	}
1173 
1174 	list_splice_init(&bo_va->invalids, &bo_va->valids);
1175 	bo_va->cleared = clear;
1176 	bo_va->base.moved = false;
1177 
1178 	if (trace_amdgpu_vm_bo_mapping_enabled()) {
1179 		list_for_each_entry(mapping, &bo_va->valids, list)
1180 			trace_amdgpu_vm_bo_mapping(mapping);
1181 	}
1182 
1183 	return 0;
1184 }
1185 
1186 /**
1187  * amdgpu_vm_update_prt_state - update the global PRT state
1188  *
1189  * @adev: amdgpu_device pointer
1190  */
1191 static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1192 {
1193 	unsigned long flags;
1194 	bool enable;
1195 
1196 	spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1197 	enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1198 	adev->gmc.gmc_funcs->set_prt(adev, enable);
1199 	spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1200 }
1201 
1202 /**
1203  * amdgpu_vm_prt_get - add a PRT user
1204  *
1205  * @adev: amdgpu_device pointer
1206  */
1207 static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1208 {
1209 	if (!adev->gmc.gmc_funcs->set_prt)
1210 		return;
1211 
1212 	if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1213 		amdgpu_vm_update_prt_state(adev);
1214 }
1215 
1216 /**
1217  * amdgpu_vm_prt_put - drop a PRT user
1218  *
1219  * @adev: amdgpu_device pointer
1220  */
1221 static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1222 {
1223 	if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1224 		amdgpu_vm_update_prt_state(adev);
1225 }
1226 
1227 /**
1228  * amdgpu_vm_prt_cb - callback for updating the PRT status
1229  *
1230  * @fence: fence for the callback
1231  * @_cb: the callback function
1232  */
1233 static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1234 {
1235 	struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1236 
1237 	amdgpu_vm_prt_put(cb->adev);
1238 	kfree(cb);
1239 }
1240 
1241 /**
1242  * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1243  *
1244  * @adev: amdgpu_device pointer
1245  * @fence: fence for the callback
1246  */
1247 static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1248 				 struct dma_fence *fence)
1249 {
1250 	struct amdgpu_prt_cb *cb;
1251 
1252 	if (!adev->gmc.gmc_funcs->set_prt)
1253 		return;
1254 
1255 	cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1256 	if (!cb) {
1257 		/* Last resort when we are OOM */
1258 		if (fence)
1259 			dma_fence_wait(fence, false);
1260 
1261 		amdgpu_vm_prt_put(adev);
1262 	} else {
1263 		cb->adev = adev;
1264 		if (!fence || dma_fence_add_callback(fence, &cb->cb,
1265 						     amdgpu_vm_prt_cb))
1266 			amdgpu_vm_prt_cb(fence, &cb->cb);
1267 	}
1268 }
1269 
1270 /**
1271  * amdgpu_vm_free_mapping - free a mapping
1272  *
1273  * @adev: amdgpu_device pointer
1274  * @vm: requested vm
1275  * @mapping: mapping to be freed
1276  * @fence: fence of the unmap operation
1277  *
1278  * Free a mapping and make sure we decrease the PRT usage count if applicable.
1279  */
1280 static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1281 				   struct amdgpu_vm *vm,
1282 				   struct amdgpu_bo_va_mapping *mapping,
1283 				   struct dma_fence *fence)
1284 {
1285 	if (mapping->flags & AMDGPU_PTE_PRT)
1286 		amdgpu_vm_add_prt_cb(adev, fence);
1287 	kfree(mapping);
1288 }
1289 
1290 /**
1291  * amdgpu_vm_prt_fini - finish all prt mappings
1292  *
1293  * @adev: amdgpu_device pointer
1294  * @vm: requested vm
1295  *
1296  * Register a cleanup callback to disable PRT support after VM dies.
1297  */
1298 static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1299 {
1300 	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1301 	struct dma_resv_iter cursor;
1302 	struct dma_fence *fence;
1303 
1304 	dma_resv_for_each_fence(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP, fence) {
1305 		/* Add a callback for each fence in the reservation object */
1306 		amdgpu_vm_prt_get(adev);
1307 		amdgpu_vm_add_prt_cb(adev, fence);
1308 	}
1309 }
1310 
1311 /**
1312  * amdgpu_vm_clear_freed - clear freed BOs in the PT
1313  *
1314  * @adev: amdgpu_device pointer
1315  * @vm: requested vm
1316  * @fence: optional resulting fence (unchanged if no work needed to be done
1317  * or if an error occurred)
1318  *
1319  * Make sure all freed BOs are cleared in the PT.
1320  * PTs have to be reserved and mutex must be locked!
1321  *
1322  * Returns:
1323  * 0 for success.
1324  *
1325  */
1326 int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1327 			  struct amdgpu_vm *vm,
1328 			  struct dma_fence **fence)
1329 {
1330 	struct dma_resv *resv = vm->root.bo->tbo.base.resv;
1331 	struct amdgpu_bo_va_mapping *mapping;
1332 	uint64_t init_pte_value = 0;
1333 	struct dma_fence *f = NULL;
1334 	int r;
1335 
1336 	while (!list_empty(&vm->freed)) {
1337 		mapping = list_first_entry(&vm->freed,
1338 			struct amdgpu_bo_va_mapping, list);
1339 		list_del(&mapping->list);
1340 
1341 		if (vm->pte_support_ats &&
1342 		    mapping->start < AMDGPU_GMC_HOLE_START)
1343 			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1344 
1345 		r = amdgpu_vm_update_range(adev, vm, false, false, true, resv,
1346 					   mapping->start, mapping->last,
1347 					   init_pte_value, 0, 0, NULL, NULL,
1348 					   &f);
1349 		amdgpu_vm_free_mapping(adev, vm, mapping, f);
1350 		if (r) {
1351 			dma_fence_put(f);
1352 			return r;
1353 		}
1354 	}
1355 
1356 	if (fence && f) {
1357 		dma_fence_put(*fence);
1358 		*fence = f;
1359 	} else {
1360 		dma_fence_put(f);
1361 	}
1362 
1363 	return 0;
1364 
1365 }
1366 
1367 /**
1368  * amdgpu_vm_handle_moved - handle moved BOs in the PT
1369  *
1370  * @adev: amdgpu_device pointer
1371  * @vm: requested vm
1372  *
1373  * Make sure all BOs which are moved are updated in the PTs.
1374  *
1375  * Returns:
1376  * 0 for success.
1377  *
1378  * PTs have to be reserved!
1379  */
1380 int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1381 			   struct amdgpu_vm *vm)
1382 {
1383 	struct amdgpu_bo_va *bo_va;
1384 	struct dma_resv *resv;
1385 	bool clear;
1386 	int r;
1387 
1388 	spin_lock(&vm->status_lock);
1389 	while (!list_empty(&vm->moved)) {
1390 		bo_va = list_first_entry(&vm->moved, struct amdgpu_bo_va,
1391 					 base.vm_status);
1392 		spin_unlock(&vm->status_lock);
1393 
1394 		/* Per VM BOs never need to bo cleared in the page tables */
1395 		r = amdgpu_vm_bo_update(adev, bo_va, false);
1396 		if (r)
1397 			return r;
1398 		spin_lock(&vm->status_lock);
1399 	}
1400 
1401 	while (!list_empty(&vm->invalidated)) {
1402 		bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1403 					 base.vm_status);
1404 		resv = bo_va->base.bo->tbo.base.resv;
1405 		spin_unlock(&vm->status_lock);
1406 
1407 		/* Try to reserve the BO to avoid clearing its ptes */
1408 		if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1409 			clear = false;
1410 		/* Somebody else is using the BO right now */
1411 		else
1412 			clear = true;
1413 
1414 		r = amdgpu_vm_bo_update(adev, bo_va, clear);
1415 		if (r)
1416 			return r;
1417 
1418 		if (!clear)
1419 			dma_resv_unlock(resv);
1420 		spin_lock(&vm->status_lock);
1421 	}
1422 	spin_unlock(&vm->status_lock);
1423 
1424 	return 0;
1425 }
1426 
1427 /**
1428  * amdgpu_vm_bo_add - add a bo to a specific vm
1429  *
1430  * @adev: amdgpu_device pointer
1431  * @vm: requested vm
1432  * @bo: amdgpu buffer object
1433  *
1434  * Add @bo into the requested vm.
1435  * Add @bo to the list of bos associated with the vm
1436  *
1437  * Returns:
1438  * Newly added bo_va or NULL for failure
1439  *
1440  * Object has to be reserved!
1441  */
1442 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1443 				      struct amdgpu_vm *vm,
1444 				      struct amdgpu_bo *bo)
1445 {
1446 	struct amdgpu_bo_va *bo_va;
1447 
1448 	bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1449 	if (bo_va == NULL) {
1450 		return NULL;
1451 	}
1452 	amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
1453 
1454 	bo_va->ref_count = 1;
1455 	bo_va->last_pt_update = dma_fence_get_stub();
1456 	INIT_LIST_HEAD(&bo_va->valids);
1457 	INIT_LIST_HEAD(&bo_va->invalids);
1458 
1459 	if (!bo)
1460 		return bo_va;
1461 
1462 	dma_resv_assert_held(bo->tbo.base.resv);
1463 	if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
1464 		bo_va->is_xgmi = true;
1465 		/* Power up XGMI if it can be potentially used */
1466 		amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
1467 	}
1468 
1469 	return bo_va;
1470 }
1471 
1472 
1473 /**
1474  * amdgpu_vm_bo_insert_map - insert a new mapping
1475  *
1476  * @adev: amdgpu_device pointer
1477  * @bo_va: bo_va to store the address
1478  * @mapping: the mapping to insert
1479  *
1480  * Insert a new mapping into all structures.
1481  */
1482 static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1483 				    struct amdgpu_bo_va *bo_va,
1484 				    struct amdgpu_bo_va_mapping *mapping)
1485 {
1486 	struct amdgpu_vm *vm = bo_va->base.vm;
1487 	struct amdgpu_bo *bo = bo_va->base.bo;
1488 
1489 	mapping->bo_va = bo_va;
1490 	list_add(&mapping->list, &bo_va->invalids);
1491 	amdgpu_vm_it_insert(mapping, &vm->va);
1492 
1493 	if (mapping->flags & AMDGPU_PTE_PRT)
1494 		amdgpu_vm_prt_get(adev);
1495 
1496 	if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1497 	    !bo_va->base.moved) {
1498 		amdgpu_vm_bo_moved(&bo_va->base);
1499 	}
1500 	trace_amdgpu_vm_bo_map(bo_va, mapping);
1501 }
1502 
1503 /**
1504  * amdgpu_vm_bo_map - map bo inside a vm
1505  *
1506  * @adev: amdgpu_device pointer
1507  * @bo_va: bo_va to store the address
1508  * @saddr: where to map the BO
1509  * @offset: requested offset in the BO
1510  * @size: BO size in bytes
1511  * @flags: attributes of pages (read/write/valid/etc.)
1512  *
1513  * Add a mapping of the BO at the specefied addr into the VM.
1514  *
1515  * Returns:
1516  * 0 for success, error for failure.
1517  *
1518  * Object has to be reserved and unreserved outside!
1519  */
1520 int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1521 		     struct amdgpu_bo_va *bo_va,
1522 		     uint64_t saddr, uint64_t offset,
1523 		     uint64_t size, uint64_t flags)
1524 {
1525 	struct amdgpu_bo_va_mapping *mapping, *tmp;
1526 	struct amdgpu_bo *bo = bo_va->base.bo;
1527 	struct amdgpu_vm *vm = bo_va->base.vm;
1528 	uint64_t eaddr;
1529 
1530 	/* validate the parameters */
1531 	if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1532 		return -EINVAL;
1533 	if (saddr + size <= saddr || offset + size <= offset)
1534 		return -EINVAL;
1535 
1536 	/* make sure object fit at this offset */
1537 	eaddr = saddr + size - 1;
1538 	if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1539 	    (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1540 		return -EINVAL;
1541 
1542 	saddr /= AMDGPU_GPU_PAGE_SIZE;
1543 	eaddr /= AMDGPU_GPU_PAGE_SIZE;
1544 
1545 	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1546 	if (tmp) {
1547 		/* bo and tmp overlap, invalid addr */
1548 		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1549 			"0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1550 			tmp->start, tmp->last + 1);
1551 		return -EINVAL;
1552 	}
1553 
1554 	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1555 	if (!mapping)
1556 		return -ENOMEM;
1557 
1558 	mapping->start = saddr;
1559 	mapping->last = eaddr;
1560 	mapping->offset = offset;
1561 	mapping->flags = flags;
1562 
1563 	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1564 
1565 	return 0;
1566 }
1567 
1568 /**
1569  * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1570  *
1571  * @adev: amdgpu_device pointer
1572  * @bo_va: bo_va to store the address
1573  * @saddr: where to map the BO
1574  * @offset: requested offset in the BO
1575  * @size: BO size in bytes
1576  * @flags: attributes of pages (read/write/valid/etc.)
1577  *
1578  * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1579  * mappings as we do so.
1580  *
1581  * Returns:
1582  * 0 for success, error for failure.
1583  *
1584  * Object has to be reserved and unreserved outside!
1585  */
1586 int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1587 			     struct amdgpu_bo_va *bo_va,
1588 			     uint64_t saddr, uint64_t offset,
1589 			     uint64_t size, uint64_t flags)
1590 {
1591 	struct amdgpu_bo_va_mapping *mapping;
1592 	struct amdgpu_bo *bo = bo_va->base.bo;
1593 	uint64_t eaddr;
1594 	int r;
1595 
1596 	/* validate the parameters */
1597 	if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK || size & ~PAGE_MASK)
1598 		return -EINVAL;
1599 	if (saddr + size <= saddr || offset + size <= offset)
1600 		return -EINVAL;
1601 
1602 	/* make sure object fit at this offset */
1603 	eaddr = saddr + size - 1;
1604 	if ((bo && offset + size > amdgpu_bo_size(bo)) ||
1605 	    (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
1606 		return -EINVAL;
1607 
1608 	/* Allocate all the needed memory */
1609 	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1610 	if (!mapping)
1611 		return -ENOMEM;
1612 
1613 	r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1614 	if (r) {
1615 		kfree(mapping);
1616 		return r;
1617 	}
1618 
1619 	saddr /= AMDGPU_GPU_PAGE_SIZE;
1620 	eaddr /= AMDGPU_GPU_PAGE_SIZE;
1621 
1622 	mapping->start = saddr;
1623 	mapping->last = eaddr;
1624 	mapping->offset = offset;
1625 	mapping->flags = flags;
1626 
1627 	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1628 
1629 	return 0;
1630 }
1631 
1632 /**
1633  * amdgpu_vm_bo_unmap - remove bo mapping from vm
1634  *
1635  * @adev: amdgpu_device pointer
1636  * @bo_va: bo_va to remove the address from
1637  * @saddr: where to the BO is mapped
1638  *
1639  * Remove a mapping of the BO at the specefied addr from the VM.
1640  *
1641  * Returns:
1642  * 0 for success, error for failure.
1643  *
1644  * Object has to be reserved and unreserved outside!
1645  */
1646 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
1647 		       struct amdgpu_bo_va *bo_va,
1648 		       uint64_t saddr)
1649 {
1650 	struct amdgpu_bo_va_mapping *mapping;
1651 	struct amdgpu_vm *vm = bo_va->base.vm;
1652 	bool valid = true;
1653 
1654 	saddr /= AMDGPU_GPU_PAGE_SIZE;
1655 
1656 	list_for_each_entry(mapping, &bo_va->valids, list) {
1657 		if (mapping->start == saddr)
1658 			break;
1659 	}
1660 
1661 	if (&mapping->list == &bo_va->valids) {
1662 		valid = false;
1663 
1664 		list_for_each_entry(mapping, &bo_va->invalids, list) {
1665 			if (mapping->start == saddr)
1666 				break;
1667 		}
1668 
1669 		if (&mapping->list == &bo_va->invalids)
1670 			return -ENOENT;
1671 	}
1672 
1673 	list_del(&mapping->list);
1674 	amdgpu_vm_it_remove(mapping, &vm->va);
1675 	mapping->bo_va = NULL;
1676 	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1677 
1678 	if (valid)
1679 		list_add(&mapping->list, &vm->freed);
1680 	else
1681 		amdgpu_vm_free_mapping(adev, vm, mapping,
1682 				       bo_va->last_pt_update);
1683 
1684 	return 0;
1685 }
1686 
1687 /**
1688  * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
1689  *
1690  * @adev: amdgpu_device pointer
1691  * @vm: VM structure to use
1692  * @saddr: start of the range
1693  * @size: size of the range
1694  *
1695  * Remove all mappings in a range, split them as appropriate.
1696  *
1697  * Returns:
1698  * 0 for success, error for failure.
1699  */
1700 int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
1701 				struct amdgpu_vm *vm,
1702 				uint64_t saddr, uint64_t size)
1703 {
1704 	struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
1705 	LIST_HEAD(removed);
1706 	uint64_t eaddr;
1707 
1708 	eaddr = saddr + size - 1;
1709 	saddr /= AMDGPU_GPU_PAGE_SIZE;
1710 	eaddr /= AMDGPU_GPU_PAGE_SIZE;
1711 
1712 	/* Allocate all the needed memory */
1713 	before = kzalloc(sizeof(*before), GFP_KERNEL);
1714 	if (!before)
1715 		return -ENOMEM;
1716 	INIT_LIST_HEAD(&before->list);
1717 
1718 	after = kzalloc(sizeof(*after), GFP_KERNEL);
1719 	if (!after) {
1720 		kfree(before);
1721 		return -ENOMEM;
1722 	}
1723 	INIT_LIST_HEAD(&after->list);
1724 
1725 	/* Now gather all removed mappings */
1726 	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1727 	while (tmp) {
1728 		/* Remember mapping split at the start */
1729 		if (tmp->start < saddr) {
1730 			before->start = tmp->start;
1731 			before->last = saddr - 1;
1732 			before->offset = tmp->offset;
1733 			before->flags = tmp->flags;
1734 			before->bo_va = tmp->bo_va;
1735 			list_add(&before->list, &tmp->bo_va->invalids);
1736 		}
1737 
1738 		/* Remember mapping split at the end */
1739 		if (tmp->last > eaddr) {
1740 			after->start = eaddr + 1;
1741 			after->last = tmp->last;
1742 			after->offset = tmp->offset;
1743 			after->offset += (after->start - tmp->start) << PAGE_SHIFT;
1744 			after->flags = tmp->flags;
1745 			after->bo_va = tmp->bo_va;
1746 			list_add(&after->list, &tmp->bo_va->invalids);
1747 		}
1748 
1749 		list_del(&tmp->list);
1750 		list_add(&tmp->list, &removed);
1751 
1752 		tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
1753 	}
1754 
1755 	/* And free them up */
1756 	list_for_each_entry_safe(tmp, next, &removed, list) {
1757 		amdgpu_vm_it_remove(tmp, &vm->va);
1758 		list_del(&tmp->list);
1759 
1760 		if (tmp->start < saddr)
1761 		    tmp->start = saddr;
1762 		if (tmp->last > eaddr)
1763 		    tmp->last = eaddr;
1764 
1765 		tmp->bo_va = NULL;
1766 		list_add(&tmp->list, &vm->freed);
1767 		trace_amdgpu_vm_bo_unmap(NULL, tmp);
1768 	}
1769 
1770 	/* Insert partial mapping before the range */
1771 	if (!list_empty(&before->list)) {
1772 		struct amdgpu_bo *bo = before->bo_va->base.bo;
1773 
1774 		amdgpu_vm_it_insert(before, &vm->va);
1775 		if (before->flags & AMDGPU_PTE_PRT)
1776 			amdgpu_vm_prt_get(adev);
1777 
1778 		if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1779 		    !before->bo_va->base.moved)
1780 			amdgpu_vm_bo_moved(&before->bo_va->base);
1781 	} else {
1782 		kfree(before);
1783 	}
1784 
1785 	/* Insert partial mapping after the range */
1786 	if (!list_empty(&after->list)) {
1787 		struct amdgpu_bo *bo = after->bo_va->base.bo;
1788 
1789 		amdgpu_vm_it_insert(after, &vm->va);
1790 		if (after->flags & AMDGPU_PTE_PRT)
1791 			amdgpu_vm_prt_get(adev);
1792 
1793 		if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
1794 		    !after->bo_va->base.moved)
1795 			amdgpu_vm_bo_moved(&after->bo_va->base);
1796 	} else {
1797 		kfree(after);
1798 	}
1799 
1800 	return 0;
1801 }
1802 
1803 /**
1804  * amdgpu_vm_bo_lookup_mapping - find mapping by address
1805  *
1806  * @vm: the requested VM
1807  * @addr: the address
1808  *
1809  * Find a mapping by it's address.
1810  *
1811  * Returns:
1812  * The amdgpu_bo_va_mapping matching for addr or NULL
1813  *
1814  */
1815 struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
1816 							 uint64_t addr)
1817 {
1818 	return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
1819 }
1820 
1821 /**
1822  * amdgpu_vm_bo_trace_cs - trace all reserved mappings
1823  *
1824  * @vm: the requested vm
1825  * @ticket: CS ticket
1826  *
1827  * Trace all mappings of BOs reserved during a command submission.
1828  */
1829 void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
1830 {
1831 	struct amdgpu_bo_va_mapping *mapping;
1832 
1833 	if (!trace_amdgpu_vm_bo_cs_enabled())
1834 		return;
1835 
1836 	for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
1837 	     mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
1838 		if (mapping->bo_va && mapping->bo_va->base.bo) {
1839 			struct amdgpu_bo *bo;
1840 
1841 			bo = mapping->bo_va->base.bo;
1842 			if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
1843 			    ticket)
1844 				continue;
1845 		}
1846 
1847 		trace_amdgpu_vm_bo_cs(mapping);
1848 	}
1849 }
1850 
1851 /**
1852  * amdgpu_vm_bo_del - remove a bo from a specific vm
1853  *
1854  * @adev: amdgpu_device pointer
1855  * @bo_va: requested bo_va
1856  *
1857  * Remove @bo_va->bo from the requested vm.
1858  *
1859  * Object have to be reserved!
1860  */
1861 void amdgpu_vm_bo_del(struct amdgpu_device *adev,
1862 		      struct amdgpu_bo_va *bo_va)
1863 {
1864 	struct amdgpu_bo_va_mapping *mapping, *next;
1865 	struct amdgpu_bo *bo = bo_va->base.bo;
1866 	struct amdgpu_vm *vm = bo_va->base.vm;
1867 	struct amdgpu_vm_bo_base **base;
1868 
1869 	dma_resv_assert_held(vm->root.bo->tbo.base.resv);
1870 
1871 	if (bo) {
1872 		dma_resv_assert_held(bo->tbo.base.resv);
1873 		if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1874 			ttm_bo_set_bulk_move(&bo->tbo, NULL);
1875 
1876 		for (base = &bo_va->base.bo->vm_bo; *base;
1877 		     base = &(*base)->next) {
1878 			if (*base != &bo_va->base)
1879 				continue;
1880 
1881 			*base = bo_va->base.next;
1882 			break;
1883 		}
1884 	}
1885 
1886 	spin_lock(&vm->status_lock);
1887 	list_del(&bo_va->base.vm_status);
1888 	spin_unlock(&vm->status_lock);
1889 
1890 	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
1891 		list_del(&mapping->list);
1892 		amdgpu_vm_it_remove(mapping, &vm->va);
1893 		mapping->bo_va = NULL;
1894 		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
1895 		list_add(&mapping->list, &vm->freed);
1896 	}
1897 	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
1898 		list_del(&mapping->list);
1899 		amdgpu_vm_it_remove(mapping, &vm->va);
1900 		amdgpu_vm_free_mapping(adev, vm, mapping,
1901 				       bo_va->last_pt_update);
1902 	}
1903 
1904 	dma_fence_put(bo_va->last_pt_update);
1905 
1906 	if (bo && bo_va->is_xgmi)
1907 		amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
1908 
1909 	kfree(bo_va);
1910 }
1911 
1912 /**
1913  * amdgpu_vm_evictable - check if we can evict a VM
1914  *
1915  * @bo: A page table of the VM.
1916  *
1917  * Check if it is possible to evict a VM.
1918  */
1919 bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
1920 {
1921 	struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
1922 
1923 	/* Page tables of a destroyed VM can go away immediately */
1924 	if (!bo_base || !bo_base->vm)
1925 		return true;
1926 
1927 	/* Don't evict VM page tables while they are busy */
1928 	if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP))
1929 		return false;
1930 
1931 	/* Try to block ongoing updates */
1932 	if (!amdgpu_vm_eviction_trylock(bo_base->vm))
1933 		return false;
1934 
1935 	/* Don't evict VM page tables while they are updated */
1936 	if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
1937 		amdgpu_vm_eviction_unlock(bo_base->vm);
1938 		return false;
1939 	}
1940 
1941 	bo_base->vm->evicting = true;
1942 	amdgpu_vm_eviction_unlock(bo_base->vm);
1943 	return true;
1944 }
1945 
1946 /**
1947  * amdgpu_vm_bo_invalidate - mark the bo as invalid
1948  *
1949  * @adev: amdgpu_device pointer
1950  * @bo: amdgpu buffer object
1951  * @evicted: is the BO evicted
1952  *
1953  * Mark @bo as invalid.
1954  */
1955 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
1956 			     struct amdgpu_bo *bo, bool evicted)
1957 {
1958 	struct amdgpu_vm_bo_base *bo_base;
1959 
1960 	/* shadow bo doesn't have bo base, its validation needs its parent */
1961 	if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
1962 		bo = bo->parent;
1963 
1964 	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
1965 		struct amdgpu_vm *vm = bo_base->vm;
1966 
1967 		if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1968 			amdgpu_vm_bo_evicted(bo_base);
1969 			continue;
1970 		}
1971 
1972 		if (bo_base->moved)
1973 			continue;
1974 		bo_base->moved = true;
1975 
1976 		if (bo->tbo.type == ttm_bo_type_kernel)
1977 			amdgpu_vm_bo_relocated(bo_base);
1978 		else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
1979 			amdgpu_vm_bo_moved(bo_base);
1980 		else
1981 			amdgpu_vm_bo_invalidated(bo_base);
1982 	}
1983 }
1984 
1985 /**
1986  * amdgpu_vm_get_block_size - calculate VM page table size as power of two
1987  *
1988  * @vm_size: VM size
1989  *
1990  * Returns:
1991  * VM page table as power of two
1992  */
1993 static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
1994 {
1995 	/* Total bits covered by PD + PTs */
1996 	unsigned bits = ilog2(vm_size) + 18;
1997 
1998 	/* Make sure the PD is 4K in size up to 8GB address space.
1999 	   Above that split equal between PD and PTs */
2000 	if (vm_size <= 8)
2001 		return (bits - 9);
2002 	else
2003 		return ((bits + 3) / 2);
2004 }
2005 
2006 /**
2007  * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2008  *
2009  * @adev: amdgpu_device pointer
2010  * @min_vm_size: the minimum vm size in GB if it's set auto
2011  * @fragment_size_default: Default PTE fragment size
2012  * @max_level: max VMPT level
2013  * @max_bits: max address space size in bits
2014  *
2015  */
2016 void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2017 			   uint32_t fragment_size_default, unsigned max_level,
2018 			   unsigned max_bits)
2019 {
2020 	unsigned int max_size = 1 << (max_bits - 30);
2021 	unsigned int vm_size;
2022 	uint64_t tmp;
2023 
2024 	/* adjust vm size first */
2025 	if (amdgpu_vm_size != -1) {
2026 		vm_size = amdgpu_vm_size;
2027 		if (vm_size > max_size) {
2028 			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2029 				 amdgpu_vm_size, max_size);
2030 			vm_size = max_size;
2031 		}
2032 	} else {
2033 		struct sysinfo si;
2034 		unsigned int phys_ram_gb;
2035 
2036 		/* Optimal VM size depends on the amount of physical
2037 		 * RAM available. Underlying requirements and
2038 		 * assumptions:
2039 		 *
2040 		 *  - Need to map system memory and VRAM from all GPUs
2041 		 *     - VRAM from other GPUs not known here
2042 		 *     - Assume VRAM <= system memory
2043 		 *  - On GFX8 and older, VM space can be segmented for
2044 		 *    different MTYPEs
2045 		 *  - Need to allow room for fragmentation, guard pages etc.
2046 		 *
2047 		 * This adds up to a rough guess of system memory x3.
2048 		 * Round up to power of two to maximize the available
2049 		 * VM size with the given page table size.
2050 		 */
2051 		si_meminfo(&si);
2052 		phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2053 			       (1 << 30) - 1) >> 30;
2054 		vm_size = roundup_pow_of_two(
2055 			min(max(phys_ram_gb * 3, min_vm_size), max_size));
2056 	}
2057 
2058 	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2059 
2060 	tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2061 	if (amdgpu_vm_block_size != -1)
2062 		tmp >>= amdgpu_vm_block_size - 9;
2063 	tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2064 	adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2065 	switch (adev->vm_manager.num_level) {
2066 	case 3:
2067 		adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2068 		break;
2069 	case 2:
2070 		adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2071 		break;
2072 	case 1:
2073 		adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2074 		break;
2075 	default:
2076 		dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2077 	}
2078 	/* block size depends on vm size and hw setup*/
2079 	if (amdgpu_vm_block_size != -1)
2080 		adev->vm_manager.block_size =
2081 			min((unsigned)amdgpu_vm_block_size, max_bits
2082 			    - AMDGPU_GPU_PAGE_SHIFT
2083 			    - 9 * adev->vm_manager.num_level);
2084 	else if (adev->vm_manager.num_level > 1)
2085 		adev->vm_manager.block_size = 9;
2086 	else
2087 		adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2088 
2089 	if (amdgpu_vm_fragment_size == -1)
2090 		adev->vm_manager.fragment_size = fragment_size_default;
2091 	else
2092 		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2093 
2094 	DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2095 		 vm_size, adev->vm_manager.num_level + 1,
2096 		 adev->vm_manager.block_size,
2097 		 adev->vm_manager.fragment_size);
2098 }
2099 
2100 /**
2101  * amdgpu_vm_wait_idle - wait for the VM to become idle
2102  *
2103  * @vm: VM object to wait for
2104  * @timeout: timeout to wait for VM to become idle
2105  */
2106 long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2107 {
2108 	timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv,
2109 					DMA_RESV_USAGE_BOOKKEEP,
2110 					true, timeout);
2111 	if (timeout <= 0)
2112 		return timeout;
2113 
2114 	return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2115 }
2116 
2117 /**
2118  * amdgpu_vm_init - initialize a vm instance
2119  *
2120  * @adev: amdgpu_device pointer
2121  * @vm: requested vm
2122  * @xcp_id: GPU partition selection id
2123  *
2124  * Init @vm fields.
2125  *
2126  * Returns:
2127  * 0 for success, error for failure.
2128  */
2129 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2130 		   int32_t xcp_id)
2131 {
2132 	struct amdgpu_bo *root_bo;
2133 	struct amdgpu_bo_vm *root;
2134 	int r, i;
2135 
2136 	vm->va = RB_ROOT_CACHED;
2137 	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2138 		vm->reserved_vmid[i] = NULL;
2139 	INIT_LIST_HEAD(&vm->evicted);
2140 	INIT_LIST_HEAD(&vm->relocated);
2141 	INIT_LIST_HEAD(&vm->moved);
2142 	INIT_LIST_HEAD(&vm->idle);
2143 	INIT_LIST_HEAD(&vm->invalidated);
2144 	spin_lock_init(&vm->status_lock);
2145 	INIT_LIST_HEAD(&vm->freed);
2146 	INIT_LIST_HEAD(&vm->done);
2147 	INIT_LIST_HEAD(&vm->pt_freed);
2148 	INIT_WORK(&vm->pt_free_work, amdgpu_vm_pt_free_work);
2149 	INIT_KFIFO(vm->faults);
2150 
2151 	r = amdgpu_vm_init_entities(adev, vm);
2152 	if (r)
2153 		return r;
2154 
2155 	vm->pte_support_ats = false;
2156 	vm->is_compute_context = false;
2157 
2158 	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2159 				    AMDGPU_VM_USE_CPU_FOR_GFX);
2160 
2161 	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2162 			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2163 	WARN_ONCE((vm->use_cpu_for_update &&
2164 		   !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2165 		  "CPU update of VM recommended only for large BAR system\n");
2166 
2167 	if (vm->use_cpu_for_update)
2168 		vm->update_funcs = &amdgpu_vm_cpu_funcs;
2169 	else
2170 		vm->update_funcs = &amdgpu_vm_sdma_funcs;
2171 
2172 	vm->last_update = dma_fence_get_stub();
2173 	vm->last_unlocked = dma_fence_get_stub();
2174 	vm->last_tlb_flush = dma_fence_get_stub();
2175 	vm->generation = 0;
2176 
2177 	mutex_init(&vm->eviction_lock);
2178 	vm->evicting = false;
2179 
2180 	r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2181 				false, &root, xcp_id);
2182 	if (r)
2183 		goto error_free_delayed;
2184 
2185 	root_bo = amdgpu_bo_ref(&root->bo);
2186 	r = amdgpu_bo_reserve(root_bo, true);
2187 	if (r) {
2188 		amdgpu_bo_unref(&root->shadow);
2189 		amdgpu_bo_unref(&root_bo);
2190 		goto error_free_delayed;
2191 	}
2192 
2193 	amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2194 	r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
2195 	if (r)
2196 		goto error_free_root;
2197 
2198 	r = amdgpu_vm_pt_clear(adev, vm, root, false);
2199 	if (r)
2200 		goto error_free_root;
2201 
2202 	amdgpu_bo_unreserve(vm->root.bo);
2203 	amdgpu_bo_unref(&root_bo);
2204 
2205 	return 0;
2206 
2207 error_free_root:
2208 	amdgpu_vm_pt_free_root(adev, vm);
2209 	amdgpu_bo_unreserve(vm->root.bo);
2210 	amdgpu_bo_unref(&root_bo);
2211 
2212 error_free_delayed:
2213 	dma_fence_put(vm->last_tlb_flush);
2214 	dma_fence_put(vm->last_unlocked);
2215 	amdgpu_vm_fini_entities(vm);
2216 
2217 	return r;
2218 }
2219 
2220 /**
2221  * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2222  *
2223  * @adev: amdgpu_device pointer
2224  * @vm: requested vm
2225  *
2226  * This only works on GFX VMs that don't have any BOs added and no
2227  * page tables allocated yet.
2228  *
2229  * Changes the following VM parameters:
2230  * - use_cpu_for_update
2231  * - pte_supports_ats
2232  *
2233  * Reinitializes the page directory to reflect the changed ATS
2234  * setting.
2235  *
2236  * Returns:
2237  * 0 for success, -errno for errors.
2238  */
2239 int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2240 {
2241 	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2242 	int r;
2243 
2244 	r = amdgpu_bo_reserve(vm->root.bo, true);
2245 	if (r)
2246 		return r;
2247 
2248 	/* Check if PD needs to be reinitialized and do it before
2249 	 * changing any other state, in case it fails.
2250 	 */
2251 	if (pte_support_ats != vm->pte_support_ats) {
2252 		/* Sanity checks */
2253 		if (!amdgpu_vm_pt_is_root_clean(adev, vm)) {
2254 			r = -EINVAL;
2255 			goto unreserve_bo;
2256 		}
2257 
2258 		vm->pte_support_ats = pte_support_ats;
2259 		r = amdgpu_vm_pt_clear(adev, vm, to_amdgpu_bo_vm(vm->root.bo),
2260 				       false);
2261 		if (r)
2262 			goto unreserve_bo;
2263 	}
2264 
2265 	/* Update VM state */
2266 	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2267 				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2268 	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2269 			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2270 	WARN_ONCE((vm->use_cpu_for_update &&
2271 		   !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2272 		  "CPU update of VM recommended only for large BAR system\n");
2273 
2274 	if (vm->use_cpu_for_update) {
2275 		/* Sync with last SDMA update/clear before switching to CPU */
2276 		r = amdgpu_bo_sync_wait(vm->root.bo,
2277 					AMDGPU_FENCE_OWNER_UNDEFINED, true);
2278 		if (r)
2279 			goto unreserve_bo;
2280 
2281 		vm->update_funcs = &amdgpu_vm_cpu_funcs;
2282 		r = amdgpu_vm_pt_map_tables(adev, vm);
2283 		if (r)
2284 			goto unreserve_bo;
2285 
2286 	} else {
2287 		vm->update_funcs = &amdgpu_vm_sdma_funcs;
2288 	}
2289 
2290 	dma_fence_put(vm->last_update);
2291 	vm->last_update = dma_fence_get_stub();
2292 	vm->is_compute_context = true;
2293 
2294 	/* Free the shadow bo for compute VM */
2295 	amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
2296 
2297 	goto unreserve_bo;
2298 
2299 unreserve_bo:
2300 	amdgpu_bo_unreserve(vm->root.bo);
2301 	return r;
2302 }
2303 
2304 /**
2305  * amdgpu_vm_release_compute - release a compute vm
2306  * @adev: amdgpu_device pointer
2307  * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
2308  *
2309  * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2310  * pasid from vm. Compute should stop use of vm after this call.
2311  */
2312 void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2313 {
2314 	amdgpu_vm_set_pasid(adev, vm, 0);
2315 	vm->is_compute_context = false;
2316 }
2317 
2318 /**
2319  * amdgpu_vm_fini - tear down a vm instance
2320  *
2321  * @adev: amdgpu_device pointer
2322  * @vm: requested vm
2323  *
2324  * Tear down @vm.
2325  * Unbind the VM and remove all bos from the vm bo list
2326  */
2327 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2328 {
2329 	struct amdgpu_bo_va_mapping *mapping, *tmp;
2330 	bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2331 	struct amdgpu_bo *root;
2332 	unsigned long flags;
2333 	int i;
2334 
2335 	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2336 
2337 	flush_work(&vm->pt_free_work);
2338 
2339 	root = amdgpu_bo_ref(vm->root.bo);
2340 	amdgpu_bo_reserve(root, true);
2341 	amdgpu_vm_set_pasid(adev, vm, 0);
2342 	dma_fence_wait(vm->last_unlocked, false);
2343 	dma_fence_put(vm->last_unlocked);
2344 	dma_fence_wait(vm->last_tlb_flush, false);
2345 	/* Make sure that all fence callbacks have completed */
2346 	spin_lock_irqsave(vm->last_tlb_flush->lock, flags);
2347 	spin_unlock_irqrestore(vm->last_tlb_flush->lock, flags);
2348 	dma_fence_put(vm->last_tlb_flush);
2349 
2350 	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2351 		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2352 			amdgpu_vm_prt_fini(adev, vm);
2353 			prt_fini_needed = false;
2354 		}
2355 
2356 		list_del(&mapping->list);
2357 		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2358 	}
2359 
2360 	amdgpu_vm_pt_free_root(adev, vm);
2361 	amdgpu_bo_unreserve(root);
2362 	amdgpu_bo_unref(&root);
2363 	WARN_ON(vm->root.bo);
2364 
2365 	amdgpu_vm_fini_entities(vm);
2366 
2367 	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2368 		dev_err(adev->dev, "still active bo inside vm\n");
2369 	}
2370 	rbtree_postorder_for_each_entry_safe(mapping, tmp,
2371 					     &vm->va.rb_root, rb) {
2372 		/* Don't remove the mapping here, we don't want to trigger a
2373 		 * rebalance and the tree is about to be destroyed anyway.
2374 		 */
2375 		list_del(&mapping->list);
2376 		kfree(mapping);
2377 	}
2378 
2379 	dma_fence_put(vm->last_update);
2380 
2381 	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) {
2382 		if (vm->reserved_vmid[i]) {
2383 			amdgpu_vmid_free_reserved(adev, i);
2384 			vm->reserved_vmid[i] = false;
2385 		}
2386 	}
2387 
2388 }
2389 
2390 /**
2391  * amdgpu_vm_manager_init - init the VM manager
2392  *
2393  * @adev: amdgpu_device pointer
2394  *
2395  * Initialize the VM manager structures
2396  */
2397 void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2398 {
2399 	unsigned i;
2400 
2401 	/* Concurrent flushes are only possible starting with Vega10 and
2402 	 * are broken on Navi10 and Navi14.
2403 	 */
2404 	adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
2405 					      adev->asic_type == CHIP_NAVI10 ||
2406 					      adev->asic_type == CHIP_NAVI14);
2407 	amdgpu_vmid_mgr_init(adev);
2408 
2409 	adev->vm_manager.fence_context =
2410 		dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2411 	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2412 		adev->vm_manager.seqno[i] = 0;
2413 
2414 	spin_lock_init(&adev->vm_manager.prt_lock);
2415 	atomic_set(&adev->vm_manager.num_prt_users, 0);
2416 
2417 	/* If not overridden by the user, by default, only in large BAR systems
2418 	 * Compute VM tables will be updated by CPU
2419 	 */
2420 #ifdef CONFIG_X86_64
2421 	if (amdgpu_vm_update_mode == -1) {
2422 		/* For asic with VF MMIO access protection
2423 		 * avoid using CPU for VM table updates
2424 		 */
2425 		if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
2426 		    !amdgpu_sriov_vf_mmio_access_protection(adev))
2427 			adev->vm_manager.vm_update_mode =
2428 				AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2429 		else
2430 			adev->vm_manager.vm_update_mode = 0;
2431 	} else
2432 		adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2433 #else
2434 	adev->vm_manager.vm_update_mode = 0;
2435 #endif
2436 
2437 	xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ);
2438 }
2439 
2440 /**
2441  * amdgpu_vm_manager_fini - cleanup VM manager
2442  *
2443  * @adev: amdgpu_device pointer
2444  *
2445  * Cleanup the VM manager and free resources.
2446  */
2447 void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2448 {
2449 	WARN_ON(!xa_empty(&adev->vm_manager.pasids));
2450 	xa_destroy(&adev->vm_manager.pasids);
2451 
2452 	amdgpu_vmid_mgr_fini(adev);
2453 }
2454 
2455 /**
2456  * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
2457  *
2458  * @dev: drm device pointer
2459  * @data: drm_amdgpu_vm
2460  * @filp: drm file pointer
2461  *
2462  * Returns:
2463  * 0 for success, -errno for errors.
2464  */
2465 int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2466 {
2467 	union drm_amdgpu_vm *args = data;
2468 	struct amdgpu_device *adev = drm_to_adev(dev);
2469 	struct amdgpu_fpriv *fpriv = filp->driver_priv;
2470 
2471 	/* No valid flags defined yet */
2472 	if (args->in.flags)
2473 		return -EINVAL;
2474 
2475 	switch (args->in.op) {
2476 	case AMDGPU_VM_OP_RESERVE_VMID:
2477 		/* We only have requirement to reserve vmid from gfxhub */
2478 		if (!fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2479 			amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0));
2480 			fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = true;
2481 		}
2482 
2483 		break;
2484 	case AMDGPU_VM_OP_UNRESERVE_VMID:
2485 		if (fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)]) {
2486 			amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(0));
2487 			fpriv->vm.reserved_vmid[AMDGPU_GFXHUB(0)] = false;
2488 		}
2489 		break;
2490 	default:
2491 		return -EINVAL;
2492 	}
2493 
2494 	return 0;
2495 }
2496 
2497 /**
2498  * amdgpu_vm_get_task_info - Extracts task info for a PASID.
2499  *
2500  * @adev: drm device pointer
2501  * @pasid: PASID identifier for VM
2502  * @task_info: task_info to fill.
2503  */
2504 void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
2505 			 struct amdgpu_task_info *task_info)
2506 {
2507 	struct amdgpu_vm *vm;
2508 	unsigned long flags;
2509 
2510 	xa_lock_irqsave(&adev->vm_manager.pasids, flags);
2511 
2512 	vm = xa_load(&adev->vm_manager.pasids, pasid);
2513 	if (vm)
2514 		*task_info = vm->task_info;
2515 
2516 	xa_unlock_irqrestore(&adev->vm_manager.pasids, flags);
2517 }
2518 
2519 /**
2520  * amdgpu_vm_set_task_info - Sets VMs task info.
2521  *
2522  * @vm: vm for which to set the info
2523  */
2524 void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
2525 {
2526 	if (vm->task_info.pid)
2527 		return;
2528 
2529 	vm->task_info.pid = current->pid;
2530 	get_task_comm(vm->task_info.task_name, current);
2531 
2532 	if (current->group_leader->mm != current->mm)
2533 		return;
2534 
2535 	vm->task_info.tgid = current->group_leader->pid;
2536 	get_task_comm(vm->task_info.process_name, current->group_leader);
2537 }
2538 
2539 /**
2540  * amdgpu_vm_handle_fault - graceful handling of VM faults.
2541  * @adev: amdgpu device pointer
2542  * @pasid: PASID of the VM
2543  * @vmid: VMID, only used for GFX 9.4.3.
2544  * @node_id: Node_id received in IH cookie. Only applicable for
2545  *           GFX 9.4.3.
2546  * @addr: Address of the fault
2547  * @write_fault: true is write fault, false is read fault
2548  *
2549  * Try to gracefully handle a VM fault. Return true if the fault was handled and
2550  * shouldn't be reported any more.
2551  */
2552 bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
2553 			    u32 vmid, u32 node_id, uint64_t addr,
2554 			    bool write_fault)
2555 {
2556 	bool is_compute_context = false;
2557 	struct amdgpu_bo *root;
2558 	unsigned long irqflags;
2559 	uint64_t value, flags;
2560 	struct amdgpu_vm *vm;
2561 	int r;
2562 
2563 	xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2564 	vm = xa_load(&adev->vm_manager.pasids, pasid);
2565 	if (vm) {
2566 		root = amdgpu_bo_ref(vm->root.bo);
2567 		is_compute_context = vm->is_compute_context;
2568 	} else {
2569 		root = NULL;
2570 	}
2571 	xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2572 
2573 	if (!root)
2574 		return false;
2575 
2576 	addr /= AMDGPU_GPU_PAGE_SIZE;
2577 
2578 	if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
2579 	    node_id, addr, write_fault)) {
2580 		amdgpu_bo_unref(&root);
2581 		return true;
2582 	}
2583 
2584 	r = amdgpu_bo_reserve(root, true);
2585 	if (r)
2586 		goto error_unref;
2587 
2588 	/* Double check that the VM still exists */
2589 	xa_lock_irqsave(&adev->vm_manager.pasids, irqflags);
2590 	vm = xa_load(&adev->vm_manager.pasids, pasid);
2591 	if (vm && vm->root.bo != root)
2592 		vm = NULL;
2593 	xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags);
2594 	if (!vm)
2595 		goto error_unlock;
2596 
2597 	flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
2598 		AMDGPU_PTE_SYSTEM;
2599 
2600 	if (is_compute_context) {
2601 		/* Intentionally setting invalid PTE flag
2602 		 * combination to force a no-retry-fault
2603 		 */
2604 		flags = AMDGPU_VM_NORETRY_FLAGS;
2605 		value = 0;
2606 	} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
2607 		/* Redirect the access to the dummy page */
2608 		value = adev->dummy_page_addr;
2609 		flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
2610 			AMDGPU_PTE_WRITEABLE;
2611 
2612 	} else {
2613 		/* Let the hw retry silently on the PTE */
2614 		value = 0;
2615 	}
2616 
2617 	r = dma_resv_reserve_fences(root->tbo.base.resv, 1);
2618 	if (r) {
2619 		pr_debug("failed %d to reserve fence slot\n", r);
2620 		goto error_unlock;
2621 	}
2622 
2623 	r = amdgpu_vm_update_range(adev, vm, true, false, false, NULL, addr,
2624 				   addr, flags, value, 0, NULL, NULL, NULL);
2625 	if (r)
2626 		goto error_unlock;
2627 
2628 	r = amdgpu_vm_update_pdes(adev, vm, true);
2629 
2630 error_unlock:
2631 	amdgpu_bo_unreserve(root);
2632 	if (r < 0)
2633 		DRM_ERROR("Can't handle page fault (%d)\n", r);
2634 
2635 error_unref:
2636 	amdgpu_bo_unref(&root);
2637 
2638 	return false;
2639 }
2640 
2641 #if defined(CONFIG_DEBUG_FS)
2642 /**
2643  * amdgpu_debugfs_vm_bo_info  - print BO info for the VM
2644  *
2645  * @vm: Requested VM for printing BO info
2646  * @m: debugfs file
2647  *
2648  * Print BO information in debugfs file for the VM
2649  */
2650 void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
2651 {
2652 	struct amdgpu_bo_va *bo_va, *tmp;
2653 	u64 total_idle = 0;
2654 	u64 total_evicted = 0;
2655 	u64 total_relocated = 0;
2656 	u64 total_moved = 0;
2657 	u64 total_invalidated = 0;
2658 	u64 total_done = 0;
2659 	unsigned int total_idle_objs = 0;
2660 	unsigned int total_evicted_objs = 0;
2661 	unsigned int total_relocated_objs = 0;
2662 	unsigned int total_moved_objs = 0;
2663 	unsigned int total_invalidated_objs = 0;
2664 	unsigned int total_done_objs = 0;
2665 	unsigned int id = 0;
2666 
2667 	spin_lock(&vm->status_lock);
2668 	seq_puts(m, "\tIdle BOs:\n");
2669 	list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
2670 		if (!bo_va->base.bo)
2671 			continue;
2672 		total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2673 	}
2674 	total_idle_objs = id;
2675 	id = 0;
2676 
2677 	seq_puts(m, "\tEvicted BOs:\n");
2678 	list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
2679 		if (!bo_va->base.bo)
2680 			continue;
2681 		total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2682 	}
2683 	total_evicted_objs = id;
2684 	id = 0;
2685 
2686 	seq_puts(m, "\tRelocated BOs:\n");
2687 	list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
2688 		if (!bo_va->base.bo)
2689 			continue;
2690 		total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2691 	}
2692 	total_relocated_objs = id;
2693 	id = 0;
2694 
2695 	seq_puts(m, "\tMoved BOs:\n");
2696 	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2697 		if (!bo_va->base.bo)
2698 			continue;
2699 		total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2700 	}
2701 	total_moved_objs = id;
2702 	id = 0;
2703 
2704 	seq_puts(m, "\tInvalidated BOs:\n");
2705 	list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
2706 		if (!bo_va->base.bo)
2707 			continue;
2708 		total_invalidated += amdgpu_bo_print_info(id++,	bo_va->base.bo, m);
2709 	}
2710 	total_invalidated_objs = id;
2711 	id = 0;
2712 
2713 	seq_puts(m, "\tDone BOs:\n");
2714 	list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
2715 		if (!bo_va->base.bo)
2716 			continue;
2717 		total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
2718 	}
2719 	spin_unlock(&vm->status_lock);
2720 	total_done_objs = id;
2721 
2722 	seq_printf(m, "\tTotal idle size:        %12lld\tobjs:\t%d\n", total_idle,
2723 		   total_idle_objs);
2724 	seq_printf(m, "\tTotal evicted size:     %12lld\tobjs:\t%d\n", total_evicted,
2725 		   total_evicted_objs);
2726 	seq_printf(m, "\tTotal relocated size:   %12lld\tobjs:\t%d\n", total_relocated,
2727 		   total_relocated_objs);
2728 	seq_printf(m, "\tTotal moved size:       %12lld\tobjs:\t%d\n", total_moved,
2729 		   total_moved_objs);
2730 	seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
2731 		   total_invalidated_objs);
2732 	seq_printf(m, "\tTotal done size:        %12lld\tobjs:\t%d\n", total_done,
2733 		   total_done_objs);
2734 }
2735 #endif
2736