1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 35 /* flags for indirect register access path supported by rlcg for sriov */ 36 #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 37 #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 38 #define AMDGPU_RLCG_GC_READ (0x1 << 28) 39 #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 40 41 /* error code for indirect register access path supported by rlcg for sriov */ 42 #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 43 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 44 #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 45 46 /* all asic after AI use this offset */ 47 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 48 /* tonga/fiji use this offset */ 49 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 50 51 enum amdgpu_sriov_vf_mode { 52 SRIOV_VF_MODE_BARE_METAL = 0, 53 SRIOV_VF_MODE_ONE_VF, 54 SRIOV_VF_MODE_MULTI_VF, 55 }; 56 57 struct amdgpu_mm_table { 58 struct amdgpu_bo *bo; 59 uint32_t *cpu_addr; 60 uint64_t gpu_addr; 61 }; 62 63 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 64 65 /* struct error_entry - amdgpu VF error information. */ 66 struct amdgpu_vf_error_buffer { 67 struct mutex lock; 68 int read_count; 69 int write_count; 70 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 71 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 72 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 73 }; 74 75 /** 76 * struct amdgpu_virt_ops - amdgpu device virt operations 77 */ 78 struct amdgpu_virt_ops { 79 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 80 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 81 int (*req_init_data)(struct amdgpu_device *adev); 82 int (*reset_gpu)(struct amdgpu_device *adev); 83 int (*wait_reset)(struct amdgpu_device *adev); 84 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); 85 }; 86 87 /* 88 * Firmware Reserve Frame buffer 89 */ 90 struct amdgpu_virt_fw_reserve { 91 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 92 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 93 unsigned int checksum_key; 94 }; 95 96 /* 97 * Legacy GIM header 98 * 99 * Defination between PF and VF 100 * Structures forcibly aligned to 4 to keep the same style as PF. 101 */ 102 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 103 104 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 105 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 106 107 enum AMDGIM_FEATURE_FLAG { 108 /* GIM supports feature of Error log collecting */ 109 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 110 /* GIM supports feature of loading uCodes */ 111 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 112 /* VRAM LOST by GIM */ 113 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 114 /* MM bandwidth */ 115 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 116 /* PP ONE VF MODE in GIM */ 117 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 118 /* Indirect Reg Access enabled */ 119 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 120 }; 121 122 enum AMDGIM_REG_ACCESS_FLAG { 123 /* Use PSP to program IH_RB_CNTL */ 124 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 125 /* Use RLC to program MMHUB regs */ 126 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 127 /* Use RLC to program GC regs */ 128 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 129 }; 130 131 struct amdgim_pf2vf_info_v1 { 132 /* header contains size and version */ 133 struct amd_sriov_msg_pf2vf_info_header header; 134 /* max_width * max_height */ 135 unsigned int uvd_enc_max_pixels_count; 136 /* 16x16 pixels/sec, codec independent */ 137 unsigned int uvd_enc_max_bandwidth; 138 /* max_width * max_height */ 139 unsigned int vce_enc_max_pixels_count; 140 /* 16x16 pixels/sec, codec independent */ 141 unsigned int vce_enc_max_bandwidth; 142 /* MEC FW position in kb from the start of visible frame buffer */ 143 unsigned int mecfw_kboffset; 144 /* The features flags of the GIM driver supports. */ 145 unsigned int feature_flags; 146 /* use private key from mailbox 2 to create chueksum */ 147 unsigned int checksum; 148 } __aligned(4); 149 150 struct amdgim_vf2pf_info_v1 { 151 /* header contains size and version */ 152 struct amd_sriov_msg_vf2pf_info_header header; 153 /* driver version */ 154 char driver_version[64]; 155 /* driver certification, 1=WHQL, 0=None */ 156 unsigned int driver_cert; 157 /* guest OS type and version: need a define */ 158 unsigned int os_info; 159 /* in the unit of 1M */ 160 unsigned int fb_usage; 161 /* guest gfx engine usage percentage */ 162 unsigned int gfx_usage; 163 /* guest gfx engine health percentage */ 164 unsigned int gfx_health; 165 /* guest compute engine usage percentage */ 166 unsigned int compute_usage; 167 /* guest compute engine health percentage */ 168 unsigned int compute_health; 169 /* guest vce engine usage percentage. 0xffff means N/A. */ 170 unsigned int vce_enc_usage; 171 /* guest vce engine health percentage. 0xffff means N/A. */ 172 unsigned int vce_enc_health; 173 /* guest uvd engine usage percentage. 0xffff means N/A. */ 174 unsigned int uvd_enc_usage; 175 /* guest uvd engine usage percentage. 0xffff means N/A. */ 176 unsigned int uvd_enc_health; 177 unsigned int checksum; 178 } __aligned(4); 179 180 struct amdgim_vf2pf_info_v2 { 181 /* header contains size and version */ 182 struct amd_sriov_msg_vf2pf_info_header header; 183 uint32_t checksum; 184 /* driver version */ 185 uint8_t driver_version[64]; 186 /* driver certification, 1=WHQL, 0=None */ 187 uint32_t driver_cert; 188 /* guest OS type and version: need a define */ 189 uint32_t os_info; 190 /* in the unit of 1M */ 191 uint32_t fb_usage; 192 /* guest gfx engine usage percentage */ 193 uint32_t gfx_usage; 194 /* guest gfx engine health percentage */ 195 uint32_t gfx_health; 196 /* guest compute engine usage percentage */ 197 uint32_t compute_usage; 198 /* guest compute engine health percentage */ 199 uint32_t compute_health; 200 /* guest vce engine usage percentage. 0xffff means N/A. */ 201 uint32_t vce_enc_usage; 202 /* guest vce engine health percentage. 0xffff means N/A. */ 203 uint32_t vce_enc_health; 204 /* guest uvd engine usage percentage. 0xffff means N/A. */ 205 uint32_t uvd_enc_usage; 206 /* guest uvd engine usage percentage. 0xffff means N/A. */ 207 uint32_t uvd_enc_health; 208 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 209 } __aligned(4); 210 211 struct amdgpu_virt_ras_err_handler_data { 212 /* point to bad page records array */ 213 struct eeprom_table_record *bps; 214 /* point to reserved bo array */ 215 struct amdgpu_bo **bps_bo; 216 /* the count of entries */ 217 int count; 218 /* last reserved entry's index + 1 */ 219 int last_reserved; 220 }; 221 222 /* GPU virtualization */ 223 struct amdgpu_virt { 224 uint32_t caps; 225 struct amdgpu_bo *csa_obj; 226 void *csa_cpu_addr; 227 bool chained_ib_support; 228 uint32_t reg_val_offs; 229 struct amdgpu_irq_src ack_irq; 230 struct amdgpu_irq_src rcv_irq; 231 struct work_struct flr_work; 232 struct amdgpu_mm_table mm_table; 233 const struct amdgpu_virt_ops *ops; 234 struct amdgpu_vf_error_buffer vf_errors; 235 struct amdgpu_virt_fw_reserve fw_reserve; 236 uint32_t gim_feature; 237 uint32_t reg_access_mode; 238 int req_init_data_ver; 239 bool tdr_debug; 240 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 241 bool ras_init_done; 242 uint32_t reg_access; 243 244 /* vf2pf message */ 245 struct delayed_work vf2pf_work; 246 uint32_t vf2pf_update_interval_ms; 247 248 /* multimedia bandwidth config */ 249 bool is_mm_bw_enabled; 250 uint32_t decode_max_dimension_pixels; 251 uint32_t decode_max_frame_pixels; 252 uint32_t encode_max_dimension_pixels; 253 uint32_t encode_max_frame_pixels; 254 }; 255 256 struct amdgpu_video_codec_info; 257 258 #define amdgpu_sriov_enabled(adev) \ 259 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 260 261 #define amdgpu_sriov_vf(adev) \ 262 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 263 264 #define amdgpu_sriov_bios(adev) \ 265 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 266 267 #define amdgpu_sriov_runtime(adev) \ 268 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 269 270 #define amdgpu_sriov_fullaccess(adev) \ 271 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 272 273 #define amdgpu_sriov_reg_indirect_en(adev) \ 274 (amdgpu_sriov_vf((adev)) && \ 275 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 276 277 #define amdgpu_sriov_reg_indirect_ih(adev) \ 278 (amdgpu_sriov_vf((adev)) && \ 279 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 280 281 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 282 (amdgpu_sriov_vf((adev)) && \ 283 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 284 285 #define amdgpu_sriov_reg_indirect_gc(adev) \ 286 (amdgpu_sriov_vf((adev)) && \ 287 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 288 289 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 290 (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 291 292 #define amdgpu_passthrough(adev) \ 293 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 294 295 static inline bool is_virtual_machine(void) 296 { 297 #if defined(CONFIG_X86) 298 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 299 #elif defined(CONFIG_ARM64) 300 return !is_kernel_in_hyp_mode(); 301 #else 302 return false; 303 #endif 304 } 305 306 #define amdgpu_sriov_is_pp_one_vf(adev) \ 307 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 308 #define amdgpu_sriov_is_debug(adev) \ 309 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 310 #define amdgpu_sriov_is_normal(adev) \ 311 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 312 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 313 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 314 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 315 uint32_t reg0, uint32_t rreg1, 316 uint32_t ref, uint32_t mask); 317 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 318 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 319 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 320 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 321 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 322 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 323 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 324 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 325 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 326 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 327 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 328 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 329 330 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 331 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 332 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 333 334 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 335 336 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 337 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 338 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 339 void amdgpu_sriov_wreg(struct amdgpu_device *adev, 340 u32 offset, u32 value, 341 u32 acc_flags, u32 hwip); 342 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 343 u32 offset, u32 acc_flags, u32 hwip); 344 #endif 345