1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 35 /* all asic after AI use this offset */ 36 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 37 /* tonga/fiji use this offset */ 38 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 39 40 enum amdgpu_sriov_vf_mode { 41 SRIOV_VF_MODE_BARE_METAL = 0, 42 SRIOV_VF_MODE_ONE_VF, 43 SRIOV_VF_MODE_MULTI_VF, 44 }; 45 46 struct amdgpu_mm_table { 47 struct amdgpu_bo *bo; 48 uint32_t *cpu_addr; 49 uint64_t gpu_addr; 50 }; 51 52 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 53 54 /* struct error_entry - amdgpu VF error information. */ 55 struct amdgpu_vf_error_buffer { 56 struct mutex lock; 57 int read_count; 58 int write_count; 59 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 60 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 61 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 62 }; 63 64 /** 65 * struct amdgpu_virt_ops - amdgpu device virt operations 66 */ 67 struct amdgpu_virt_ops { 68 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 69 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 70 int (*req_init_data)(struct amdgpu_device *adev); 71 int (*reset_gpu)(struct amdgpu_device *adev); 72 int (*wait_reset)(struct amdgpu_device *adev); 73 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); 74 }; 75 76 /* 77 * Firmware Reserve Frame buffer 78 */ 79 struct amdgpu_virt_fw_reserve { 80 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 81 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 82 unsigned int checksum_key; 83 }; 84 85 /* 86 * Legacy GIM header 87 * 88 * Defination between PF and VF 89 * Structures forcibly aligned to 4 to keep the same style as PF. 90 */ 91 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 92 93 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 94 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 95 96 enum AMDGIM_FEATURE_FLAG { 97 /* GIM supports feature of Error log collecting */ 98 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 99 /* GIM supports feature of loading uCodes */ 100 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 101 /* VRAM LOST by GIM */ 102 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 103 /* MM bandwidth */ 104 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 105 /* PP ONE VF MODE in GIM */ 106 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 107 }; 108 109 struct amdgim_pf2vf_info_v1 { 110 /* header contains size and version */ 111 struct amd_sriov_msg_pf2vf_info_header header; 112 /* max_width * max_height */ 113 unsigned int uvd_enc_max_pixels_count; 114 /* 16x16 pixels/sec, codec independent */ 115 unsigned int uvd_enc_max_bandwidth; 116 /* max_width * max_height */ 117 unsigned int vce_enc_max_pixels_count; 118 /* 16x16 pixels/sec, codec independent */ 119 unsigned int vce_enc_max_bandwidth; 120 /* MEC FW position in kb from the start of visible frame buffer */ 121 unsigned int mecfw_kboffset; 122 /* The features flags of the GIM driver supports. */ 123 unsigned int feature_flags; 124 /* use private key from mailbox 2 to create chueksum */ 125 unsigned int checksum; 126 } __aligned(4); 127 128 struct amdgim_vf2pf_info_v1 { 129 /* header contains size and version */ 130 struct amd_sriov_msg_vf2pf_info_header header; 131 /* driver version */ 132 char driver_version[64]; 133 /* driver certification, 1=WHQL, 0=None */ 134 unsigned int driver_cert; 135 /* guest OS type and version: need a define */ 136 unsigned int os_info; 137 /* in the unit of 1M */ 138 unsigned int fb_usage; 139 /* guest gfx engine usage percentage */ 140 unsigned int gfx_usage; 141 /* guest gfx engine health percentage */ 142 unsigned int gfx_health; 143 /* guest compute engine usage percentage */ 144 unsigned int compute_usage; 145 /* guest compute engine health percentage */ 146 unsigned int compute_health; 147 /* guest vce engine usage percentage. 0xffff means N/A. */ 148 unsigned int vce_enc_usage; 149 /* guest vce engine health percentage. 0xffff means N/A. */ 150 unsigned int vce_enc_health; 151 /* guest uvd engine usage percentage. 0xffff means N/A. */ 152 unsigned int uvd_enc_usage; 153 /* guest uvd engine usage percentage. 0xffff means N/A. */ 154 unsigned int uvd_enc_health; 155 unsigned int checksum; 156 } __aligned(4); 157 158 struct amdgim_vf2pf_info_v2 { 159 /* header contains size and version */ 160 struct amd_sriov_msg_vf2pf_info_header header; 161 uint32_t checksum; 162 /* driver version */ 163 uint8_t driver_version[64]; 164 /* driver certification, 1=WHQL, 0=None */ 165 uint32_t driver_cert; 166 /* guest OS type and version: need a define */ 167 uint32_t os_info; 168 /* in the unit of 1M */ 169 uint32_t fb_usage; 170 /* guest gfx engine usage percentage */ 171 uint32_t gfx_usage; 172 /* guest gfx engine health percentage */ 173 uint32_t gfx_health; 174 /* guest compute engine usage percentage */ 175 uint32_t compute_usage; 176 /* guest compute engine health percentage */ 177 uint32_t compute_health; 178 /* guest vce engine usage percentage. 0xffff means N/A. */ 179 uint32_t vce_enc_usage; 180 /* guest vce engine health percentage. 0xffff means N/A. */ 181 uint32_t vce_enc_health; 182 /* guest uvd engine usage percentage. 0xffff means N/A. */ 183 uint32_t uvd_enc_usage; 184 /* guest uvd engine usage percentage. 0xffff means N/A. */ 185 uint32_t uvd_enc_health; 186 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 187 } __aligned(4); 188 189 struct amdgpu_virt_ras_err_handler_data { 190 /* point to bad page records array */ 191 struct eeprom_table_record *bps; 192 /* point to reserved bo array */ 193 struct amdgpu_bo **bps_bo; 194 /* the count of entries */ 195 int count; 196 /* last reserved entry's index + 1 */ 197 int last_reserved; 198 }; 199 200 /* GPU virtualization */ 201 struct amdgpu_virt { 202 uint32_t caps; 203 struct amdgpu_bo *csa_obj; 204 void *csa_cpu_addr; 205 bool chained_ib_support; 206 uint32_t reg_val_offs; 207 struct amdgpu_irq_src ack_irq; 208 struct amdgpu_irq_src rcv_irq; 209 struct work_struct flr_work; 210 struct amdgpu_mm_table mm_table; 211 const struct amdgpu_virt_ops *ops; 212 struct amdgpu_vf_error_buffer vf_errors; 213 struct amdgpu_virt_fw_reserve fw_reserve; 214 uint32_t gim_feature; 215 uint32_t reg_access_mode; 216 int req_init_data_ver; 217 bool tdr_debug; 218 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 219 bool ras_init_done; 220 221 /* vf2pf message */ 222 struct delayed_work vf2pf_work; 223 uint32_t vf2pf_update_interval_ms; 224 }; 225 226 #define amdgpu_sriov_enabled(adev) \ 227 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 228 229 #define amdgpu_sriov_vf(adev) \ 230 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 231 232 #define amdgpu_sriov_bios(adev) \ 233 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 234 235 #define amdgpu_sriov_runtime(adev) \ 236 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 237 238 #define amdgpu_sriov_fullaccess(adev) \ 239 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 240 241 #define amdgpu_passthrough(adev) \ 242 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 243 244 static inline bool is_virtual_machine(void) 245 { 246 #ifdef CONFIG_X86 247 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 248 #else 249 return false; 250 #endif 251 } 252 253 #define amdgpu_sriov_is_pp_one_vf(adev) \ 254 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 255 #define amdgpu_sriov_is_debug(adev) \ 256 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 257 #define amdgpu_sriov_is_normal(adev) \ 258 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 259 260 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 261 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 262 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 263 uint32_t reg0, uint32_t rreg1, 264 uint32_t ref, uint32_t mask); 265 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 266 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 267 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 268 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 269 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 270 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 271 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 272 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 273 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 274 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 275 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 276 277 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 278 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 279 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 280 281 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 282 #endif 283