1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #include "amdgv_sriovmsg.h" 28 29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 33 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34 35 /* all asic after AI use this offset */ 36 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 37 /* tonga/fiji use this offset */ 38 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 39 40 enum amdgpu_sriov_vf_mode { 41 SRIOV_VF_MODE_BARE_METAL = 0, 42 SRIOV_VF_MODE_ONE_VF, 43 SRIOV_VF_MODE_MULTI_VF, 44 }; 45 46 struct amdgpu_mm_table { 47 struct amdgpu_bo *bo; 48 uint32_t *cpu_addr; 49 uint64_t gpu_addr; 50 }; 51 52 #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 53 54 /* struct error_entry - amdgpu VF error information. */ 55 struct amdgpu_vf_error_buffer { 56 struct mutex lock; 57 int read_count; 58 int write_count; 59 uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 60 uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 61 uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 62 }; 63 64 /** 65 * struct amdgpu_virt_ops - amdgpu device virt operations 66 */ 67 struct amdgpu_virt_ops { 68 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 69 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 70 int (*req_init_data)(struct amdgpu_device *adev); 71 int (*reset_gpu)(struct amdgpu_device *adev); 72 int (*wait_reset)(struct amdgpu_device *adev); 73 void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); 74 }; 75 76 /* 77 * Firmware Reserve Frame buffer 78 */ 79 struct amdgpu_virt_fw_reserve { 80 struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 81 struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 82 unsigned int checksum_key; 83 }; 84 85 /* 86 * Legacy GIM header 87 * 88 * Defination between PF and VF 89 * Structures forcibly aligned to 4 to keep the same style as PF. 90 */ 91 #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 92 93 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 94 (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 95 96 enum AMDGIM_FEATURE_FLAG { 97 /* GIM supports feature of Error log collecting */ 98 AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 99 /* GIM supports feature of loading uCodes */ 100 AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 101 /* VRAM LOST by GIM */ 102 AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 103 /* MM bandwidth */ 104 AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 105 /* PP ONE VF MODE in GIM */ 106 AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 107 /* Indirect Reg Access enabled */ 108 AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 109 }; 110 111 enum AMDGIM_REG_ACCESS_FLAG { 112 /* Use PSP to program IH_RB_CNTL */ 113 AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 114 /* Use RLC to program MMHUB regs */ 115 AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 116 /* Use RLC to program GC regs */ 117 AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 118 }; 119 120 struct amdgim_pf2vf_info_v1 { 121 /* header contains size and version */ 122 struct amd_sriov_msg_pf2vf_info_header header; 123 /* max_width * max_height */ 124 unsigned int uvd_enc_max_pixels_count; 125 /* 16x16 pixels/sec, codec independent */ 126 unsigned int uvd_enc_max_bandwidth; 127 /* max_width * max_height */ 128 unsigned int vce_enc_max_pixels_count; 129 /* 16x16 pixels/sec, codec independent */ 130 unsigned int vce_enc_max_bandwidth; 131 /* MEC FW position in kb from the start of visible frame buffer */ 132 unsigned int mecfw_kboffset; 133 /* The features flags of the GIM driver supports. */ 134 unsigned int feature_flags; 135 /* use private key from mailbox 2 to create chueksum */ 136 unsigned int checksum; 137 } __aligned(4); 138 139 struct amdgim_vf2pf_info_v1 { 140 /* header contains size and version */ 141 struct amd_sriov_msg_vf2pf_info_header header; 142 /* driver version */ 143 char driver_version[64]; 144 /* driver certification, 1=WHQL, 0=None */ 145 unsigned int driver_cert; 146 /* guest OS type and version: need a define */ 147 unsigned int os_info; 148 /* in the unit of 1M */ 149 unsigned int fb_usage; 150 /* guest gfx engine usage percentage */ 151 unsigned int gfx_usage; 152 /* guest gfx engine health percentage */ 153 unsigned int gfx_health; 154 /* guest compute engine usage percentage */ 155 unsigned int compute_usage; 156 /* guest compute engine health percentage */ 157 unsigned int compute_health; 158 /* guest vce engine usage percentage. 0xffff means N/A. */ 159 unsigned int vce_enc_usage; 160 /* guest vce engine health percentage. 0xffff means N/A. */ 161 unsigned int vce_enc_health; 162 /* guest uvd engine usage percentage. 0xffff means N/A. */ 163 unsigned int uvd_enc_usage; 164 /* guest uvd engine usage percentage. 0xffff means N/A. */ 165 unsigned int uvd_enc_health; 166 unsigned int checksum; 167 } __aligned(4); 168 169 struct amdgim_vf2pf_info_v2 { 170 /* header contains size and version */ 171 struct amd_sriov_msg_vf2pf_info_header header; 172 uint32_t checksum; 173 /* driver version */ 174 uint8_t driver_version[64]; 175 /* driver certification, 1=WHQL, 0=None */ 176 uint32_t driver_cert; 177 /* guest OS type and version: need a define */ 178 uint32_t os_info; 179 /* in the unit of 1M */ 180 uint32_t fb_usage; 181 /* guest gfx engine usage percentage */ 182 uint32_t gfx_usage; 183 /* guest gfx engine health percentage */ 184 uint32_t gfx_health; 185 /* guest compute engine usage percentage */ 186 uint32_t compute_usage; 187 /* guest compute engine health percentage */ 188 uint32_t compute_health; 189 /* guest vce engine usage percentage. 0xffff means N/A. */ 190 uint32_t vce_enc_usage; 191 /* guest vce engine health percentage. 0xffff means N/A. */ 192 uint32_t vce_enc_health; 193 /* guest uvd engine usage percentage. 0xffff means N/A. */ 194 uint32_t uvd_enc_usage; 195 /* guest uvd engine usage percentage. 0xffff means N/A. */ 196 uint32_t uvd_enc_health; 197 uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 198 } __aligned(4); 199 200 struct amdgpu_virt_ras_err_handler_data { 201 /* point to bad page records array */ 202 struct eeprom_table_record *bps; 203 /* point to reserved bo array */ 204 struct amdgpu_bo **bps_bo; 205 /* the count of entries */ 206 int count; 207 /* last reserved entry's index + 1 */ 208 int last_reserved; 209 }; 210 211 /* GPU virtualization */ 212 struct amdgpu_virt { 213 uint32_t caps; 214 struct amdgpu_bo *csa_obj; 215 void *csa_cpu_addr; 216 bool chained_ib_support; 217 uint32_t reg_val_offs; 218 struct amdgpu_irq_src ack_irq; 219 struct amdgpu_irq_src rcv_irq; 220 struct work_struct flr_work; 221 struct amdgpu_mm_table mm_table; 222 const struct amdgpu_virt_ops *ops; 223 struct amdgpu_vf_error_buffer vf_errors; 224 struct amdgpu_virt_fw_reserve fw_reserve; 225 uint32_t gim_feature; 226 uint32_t reg_access_mode; 227 int req_init_data_ver; 228 bool tdr_debug; 229 struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 230 bool ras_init_done; 231 uint32_t reg_access; 232 233 /* vf2pf message */ 234 struct delayed_work vf2pf_work; 235 uint32_t vf2pf_update_interval_ms; 236 237 /* multimedia bandwidth config */ 238 bool is_mm_bw_enabled; 239 uint32_t decode_max_dimension_pixels; 240 uint32_t decode_max_frame_pixels; 241 uint32_t encode_max_dimension_pixels; 242 uint32_t encode_max_frame_pixels; 243 }; 244 245 struct amdgpu_video_codec_info; 246 247 #define amdgpu_sriov_enabled(adev) \ 248 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 249 250 #define amdgpu_sriov_vf(adev) \ 251 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 252 253 #define amdgpu_sriov_bios(adev) \ 254 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 255 256 #define amdgpu_sriov_runtime(adev) \ 257 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 258 259 #define amdgpu_sriov_fullaccess(adev) \ 260 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 261 262 #define amdgpu_sriov_reg_indirect_en(adev) \ 263 (amdgpu_sriov_vf((adev)) && \ 264 ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 265 266 #define amdgpu_sriov_reg_indirect_ih(adev) \ 267 (amdgpu_sriov_vf((adev)) && \ 268 ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 269 270 #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 271 (amdgpu_sriov_vf((adev)) && \ 272 ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 273 274 #define amdgpu_sriov_reg_indirect_gc(adev) \ 275 (amdgpu_sriov_vf((adev)) && \ 276 ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 277 278 #define amdgpu_passthrough(adev) \ 279 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 280 281 static inline bool is_virtual_machine(void) 282 { 283 #ifdef CONFIG_X86 284 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 285 #else 286 return false; 287 #endif 288 } 289 290 #define amdgpu_sriov_is_pp_one_vf(adev) \ 291 ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 292 #define amdgpu_sriov_is_debug(adev) \ 293 ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 294 #define amdgpu_sriov_is_normal(adev) \ 295 ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 296 297 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 298 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 299 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 300 uint32_t reg0, uint32_t rreg1, 301 uint32_t ref, uint32_t mask); 302 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 303 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 304 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 305 void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 306 int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 307 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 308 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 309 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 310 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 311 void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 312 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 313 void amdgpu_detect_virtualization(struct amdgpu_device *adev); 314 315 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 316 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 317 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 318 319 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 320 321 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 322 struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 323 struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 324 #endif 325