1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Author: Monk.liu@amd.com 23 */ 24 #ifndef AMDGPU_VIRT_H 25 #define AMDGPU_VIRT_H 26 27 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 28 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 29 #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 30 #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 31 #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 32 33 /** 34 * struct amdgpu_virt_ops - amdgpu device virt operations 35 */ 36 struct amdgpu_virt_ops { 37 int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 38 int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 39 int (*reset_gpu)(struct amdgpu_device *adev); 40 }; 41 42 /* GPU virtualization */ 43 struct amdgpu_virt { 44 uint32_t caps; 45 struct amdgpu_bo *csa_obj; 46 uint64_t csa_vmid0_addr; 47 bool chained_ib_support; 48 uint32_t reg_val_offs; 49 struct mutex lock; 50 struct amdgpu_irq_src ack_irq; 51 struct amdgpu_irq_src rcv_irq; 52 struct delayed_work flr_work; 53 const struct amdgpu_virt_ops *ops; 54 }; 55 56 #define AMDGPU_CSA_SIZE (8 * 1024) 57 #define AMDGPU_CSA_VADDR (AMDGPU_VA_RESERVED_SIZE - AMDGPU_CSA_SIZE) 58 59 #define amdgpu_sriov_enabled(adev) \ 60 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 61 62 #define amdgpu_sriov_vf(adev) \ 63 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 64 65 #define amdgpu_sriov_bios(adev) \ 66 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 67 68 #define amdgpu_sriov_runtime(adev) \ 69 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 70 71 #define amdgpu_passthrough(adev) \ 72 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 73 74 static inline bool is_virtual_machine(void) 75 { 76 #ifdef CONFIG_X86 77 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 78 #else 79 return false; 80 #endif 81 } 82 83 struct amdgpu_vm; 84 int amdgpu_allocate_static_csa(struct amdgpu_device *adev); 85 int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm); 86 void amdgpu_virt_init_setting(struct amdgpu_device *adev); 87 uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg); 88 void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 89 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 90 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 91 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 92 93 #endif 94