1 /*
2  * Copyright 2016 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Author: Monk.liu@amd.com
23  */
24 #ifndef AMDGPU_VIRT_H
25 #define AMDGPU_VIRT_H
26 
27 #include "amdgv_sriovmsg.h"
28 
29 #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS  (1 << 0) /* vBIOS is sr-iov ready */
30 #define AMDGPU_SRIOV_CAPS_ENABLE_IOV   (1 << 1) /* sr-iov is enabled on this GPU */
31 #define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */
32 #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
33 #define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
34 #define AMDGPU_VF_MMIO_ACCESS_PROTECT  (1 << 5) /* MMIO write access is not allowed in sriov runtime */
35 
36 /* flags for indirect register access path supported by rlcg for sriov */
37 #define AMDGPU_RLCG_GC_WRITE_LEGACY    (0x8 << 28)
38 #define AMDGPU_RLCG_GC_WRITE           (0x0 << 28)
39 #define AMDGPU_RLCG_GC_READ            (0x1 << 28)
40 #define AMDGPU_RLCG_MMHUB_WRITE        (0x2 << 28)
41 
42 /* error code for indirect register access path supported by rlcg for sriov */
43 #define AMDGPU_RLCG_VFGATE_DISABLED		0x4000000
44 #define AMDGPU_RLCG_WRONG_OPERATION_TYPE	0x2000000
45 #define AMDGPU_RLCG_REG_NOT_IN_RANGE		0x1000000
46 
47 #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK	0xFFFFF
48 
49 /* all asic after AI use this offset */
50 #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
51 /* tonga/fiji use this offset */
52 #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503
53 
54 enum amdgpu_sriov_vf_mode {
55 	SRIOV_VF_MODE_BARE_METAL = 0,
56 	SRIOV_VF_MODE_ONE_VF,
57 	SRIOV_VF_MODE_MULTI_VF,
58 };
59 
60 struct amdgpu_mm_table {
61 	struct amdgpu_bo	*bo;
62 	uint32_t		*cpu_addr;
63 	uint64_t		gpu_addr;
64 };
65 
66 #define AMDGPU_VF_ERROR_ENTRY_SIZE    16
67 
68 /* struct error_entry - amdgpu VF error information. */
69 struct amdgpu_vf_error_buffer {
70 	struct mutex lock;
71 	int read_count;
72 	int write_count;
73 	uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
74 	uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
75 	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
76 };
77 
78 enum idh_request;
79 
80 /**
81  * struct amdgpu_virt_ops - amdgpu device virt operations
82  */
83 struct amdgpu_virt_ops {
84 	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
85 	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
86 	int (*req_init_data)(struct amdgpu_device *adev);
87 	int (*reset_gpu)(struct amdgpu_device *adev);
88 	int (*wait_reset)(struct amdgpu_device *adev);
89 	void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
90 			  u32 data1, u32 data2, u32 data3);
91 	void (*ras_poison_handler)(struct amdgpu_device *adev);
92 };
93 
94 /*
95  * Firmware Reserve Frame buffer
96  */
97 struct amdgpu_virt_fw_reserve {
98 	struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
99 	struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
100 	unsigned int checksum_key;
101 };
102 
103 /*
104  * Legacy GIM header
105  *
106  * Defination between PF and VF
107  * Structures forcibly aligned to 4 to keep the same style as PF.
108  */
109 #define AMDGIM_DATAEXCHANGE_OFFSET		(64 * 1024)
110 
111 #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
112 		(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))
113 
114 enum AMDGIM_FEATURE_FLAG {
115 	/* GIM supports feature of Error log collecting */
116 	AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
117 	/* GIM supports feature of loading uCodes */
118 	AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
119 	/* VRAM LOST by GIM */
120 	AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
121 	/* MM bandwidth */
122 	AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
123 	/* PP ONE VF MODE in GIM */
124 	AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
125 	/* Indirect Reg Access enabled */
126 	AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
127 	/* AV1 Support MODE*/
128 	AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
129 };
130 
131 enum AMDGIM_REG_ACCESS_FLAG {
132 	/* Use PSP to program IH_RB_CNTL */
133 	AMDGIM_FEATURE_IH_REG_PSP_EN     = (1 << 0),
134 	/* Use RLC to program MMHUB regs */
135 	AMDGIM_FEATURE_MMHUB_REG_RLC_EN  = (1 << 1),
136 	/* Use RLC to program GC regs */
137 	AMDGIM_FEATURE_GC_REG_RLC_EN     = (1 << 2),
138 };
139 
140 struct amdgim_pf2vf_info_v1 {
141 	/* header contains size and version */
142 	struct amd_sriov_msg_pf2vf_info_header header;
143 	/* max_width * max_height */
144 	unsigned int uvd_enc_max_pixels_count;
145 	/* 16x16 pixels/sec, codec independent */
146 	unsigned int uvd_enc_max_bandwidth;
147 	/* max_width * max_height */
148 	unsigned int vce_enc_max_pixels_count;
149 	/* 16x16 pixels/sec, codec independent */
150 	unsigned int vce_enc_max_bandwidth;
151 	/* MEC FW position in kb from the start of visible frame buffer */
152 	unsigned int mecfw_kboffset;
153 	/* The features flags of the GIM driver supports. */
154 	unsigned int feature_flags;
155 	/* use private key from mailbox 2 to create chueksum */
156 	unsigned int checksum;
157 } __aligned(4);
158 
159 struct amdgim_vf2pf_info_v1 {
160 	/* header contains size and version */
161 	struct amd_sriov_msg_vf2pf_info_header header;
162 	/* driver version */
163 	char driver_version[64];
164 	/* driver certification, 1=WHQL, 0=None */
165 	unsigned int driver_cert;
166 	/* guest OS type and version: need a define */
167 	unsigned int os_info;
168 	/* in the unit of 1M */
169 	unsigned int fb_usage;
170 	/* guest gfx engine usage percentage */
171 	unsigned int gfx_usage;
172 	/* guest gfx engine health percentage */
173 	unsigned int gfx_health;
174 	/* guest compute engine usage percentage */
175 	unsigned int compute_usage;
176 	/* guest compute engine health percentage */
177 	unsigned int compute_health;
178 	/* guest vce engine usage percentage. 0xffff means N/A. */
179 	unsigned int vce_enc_usage;
180 	/* guest vce engine health percentage. 0xffff means N/A. */
181 	unsigned int vce_enc_health;
182 	/* guest uvd engine usage percentage. 0xffff means N/A. */
183 	unsigned int uvd_enc_usage;
184 	/* guest uvd engine usage percentage. 0xffff means N/A. */
185 	unsigned int uvd_enc_health;
186 	unsigned int checksum;
187 } __aligned(4);
188 
189 struct amdgim_vf2pf_info_v2 {
190 	/* header contains size and version */
191 	struct amd_sriov_msg_vf2pf_info_header header;
192 	uint32_t checksum;
193 	/* driver version */
194 	uint8_t driver_version[64];
195 	/* driver certification, 1=WHQL, 0=None */
196 	uint32_t driver_cert;
197 	/* guest OS type and version: need a define */
198 	uint32_t os_info;
199 	/* in the unit of 1M */
200 	uint32_t fb_usage;
201 	/* guest gfx engine usage percentage */
202 	uint32_t gfx_usage;
203 	/* guest gfx engine health percentage */
204 	uint32_t gfx_health;
205 	/* guest compute engine usage percentage */
206 	uint32_t compute_usage;
207 	/* guest compute engine health percentage */
208 	uint32_t compute_health;
209 	/* guest vce engine usage percentage. 0xffff means N/A. */
210 	uint32_t vce_enc_usage;
211 	/* guest vce engine health percentage. 0xffff means N/A. */
212 	uint32_t vce_enc_health;
213 	/* guest uvd engine usage percentage. 0xffff means N/A. */
214 	uint32_t uvd_enc_usage;
215 	/* guest uvd engine usage percentage. 0xffff means N/A. */
216 	uint32_t uvd_enc_health;
217 	uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)];
218 } __aligned(4);
219 
220 struct amdgpu_virt_ras_err_handler_data {
221 	/* point to bad page records array */
222 	struct eeprom_table_record *bps;
223 	/* point to reserved bo array */
224 	struct amdgpu_bo **bps_bo;
225 	/* the count of entries */
226 	int count;
227 	/* last reserved entry's index + 1 */
228 	int last_reserved;
229 };
230 
231 /* GPU virtualization */
232 struct amdgpu_virt {
233 	uint32_t			caps;
234 	struct amdgpu_bo		*csa_obj;
235 	void				*csa_cpu_addr;
236 	bool chained_ib_support;
237 	uint32_t			reg_val_offs;
238 	struct amdgpu_irq_src		ack_irq;
239 	struct amdgpu_irq_src		rcv_irq;
240 	struct work_struct		flr_work;
241 	struct amdgpu_mm_table		mm_table;
242 	const struct amdgpu_virt_ops	*ops;
243 	struct amdgpu_vf_error_buffer	vf_errors;
244 	struct amdgpu_virt_fw_reserve	fw_reserve;
245 	uint32_t gim_feature;
246 	uint32_t reg_access_mode;
247 	int req_init_data_ver;
248 	bool tdr_debug;
249 	struct amdgpu_virt_ras_err_handler_data *virt_eh_data;
250 	bool ras_init_done;
251 	uint32_t reg_access;
252 
253 	/* vf2pf message */
254 	struct delayed_work vf2pf_work;
255 	uint32_t vf2pf_update_interval_ms;
256 
257 	/* multimedia bandwidth config */
258 	bool     is_mm_bw_enabled;
259 	uint32_t decode_max_dimension_pixels;
260 	uint32_t decode_max_frame_pixels;
261 	uint32_t encode_max_dimension_pixels;
262 	uint32_t encode_max_frame_pixels;
263 
264 	/* the ucode id to signal the autoload */
265 	uint32_t autoload_ucode_id;
266 };
267 
268 struct amdgpu_video_codec_info;
269 
270 #define amdgpu_sriov_enabled(adev) \
271 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV)
272 
273 #define amdgpu_sriov_vf(adev) \
274 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF)
275 
276 #define amdgpu_sriov_bios(adev) \
277 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS)
278 
279 #define amdgpu_sriov_runtime(adev) \
280 ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME)
281 
282 #define amdgpu_sriov_fullaccess(adev) \
283 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
284 
285 #define amdgpu_sriov_reg_indirect_en(adev) \
286 (amdgpu_sriov_vf((adev)) && \
287 	((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS)))
288 
289 #define amdgpu_sriov_reg_indirect_ih(adev) \
290 (amdgpu_sriov_vf((adev)) && \
291 	((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN)))
292 
293 #define amdgpu_sriov_reg_indirect_mmhub(adev) \
294 (amdgpu_sriov_vf((adev)) && \
295 	((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN)))
296 
297 #define amdgpu_sriov_reg_indirect_gc(adev) \
298 (amdgpu_sriov_vf((adev)) && \
299 	((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN)))
300 
301 #define amdgpu_sriov_rlcg_error_report_enabled(adev) \
302         (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev))
303 
304 #define amdgpu_passthrough(adev) \
305 ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
306 
307 #define amdgpu_sriov_vf_mmio_access_protection(adev) \
308 ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT)
309 
310 static inline bool is_virtual_machine(void)
311 {
312 #if defined(CONFIG_X86)
313 	return boot_cpu_has(X86_FEATURE_HYPERVISOR);
314 #elif defined(CONFIG_ARM64)
315 	return !is_kernel_in_hyp_mode();
316 #else
317 	return false;
318 #endif
319 }
320 
321 #define amdgpu_sriov_is_pp_one_vf(adev) \
322 	((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
323 #define amdgpu_sriov_is_debug(adev) \
324 	((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug)
325 #define amdgpu_sriov_is_normal(adev) \
326 	((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug))
327 #define amdgpu_sriov_is_av1_support(adev) \
328 	((adev)->virt.gim_feature & AMDGIM_FEATURE_AV1_SUPPORT)
329 bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
330 void amdgpu_virt_init_setting(struct amdgpu_device *adev);
331 void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev,
332 					uint32_t reg0, uint32_t rreg1,
333 					uint32_t ref, uint32_t mask);
334 int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init);
335 int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init);
336 int amdgpu_virt_reset_gpu(struct amdgpu_device *adev);
337 void amdgpu_virt_request_init_data(struct amdgpu_device *adev);
338 int amdgpu_virt_wait_reset(struct amdgpu_device *adev);
339 int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev);
340 void amdgpu_virt_free_mm_table(struct amdgpu_device *adev);
341 void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev);
342 void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
343 void amdgpu_virt_exchange_data(struct amdgpu_device *adev);
344 void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev);
345 void amdgpu_detect_virtualization(struct amdgpu_device *adev);
346 
347 bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev);
348 int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev);
349 void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev);
350 
351 enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev);
352 
353 void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
354 			struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
355 			struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
356 void amdgpu_sriov_wreg(struct amdgpu_device *adev,
357 		       u32 offset, u32 value,
358 		       u32 acc_flags, u32 hwip, u32 xcc_id);
359 u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
360 		      u32 offset, u32 acc_flags, u32 hwip, u32 xcc_id);
361 bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev,
362 			uint32_t ucode_id);
363 void amdgpu_virt_post_reset(struct amdgpu_device *adev);
364 #endif
365