1ceeb50edSMonk Liu /* 2ceeb50edSMonk Liu * Copyright 2016 Advanced Micro Devices, Inc. 3ceeb50edSMonk Liu * 4ceeb50edSMonk Liu * Permission is hereby granted, free of charge, to any person obtaining a 5ceeb50edSMonk Liu * copy of this software and associated documentation files (the "Software"), 6ceeb50edSMonk Liu * to deal in the Software without restriction, including without limitation 7ceeb50edSMonk Liu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8ceeb50edSMonk Liu * and/or sell copies of the Software, and to permit persons to whom the 9ceeb50edSMonk Liu * Software is furnished to do so, subject to the following conditions: 10ceeb50edSMonk Liu * 11ceeb50edSMonk Liu * The above copyright notice and this permission notice shall be included in 12ceeb50edSMonk Liu * all copies or substantial portions of the Software. 13ceeb50edSMonk Liu * 14ceeb50edSMonk Liu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15ceeb50edSMonk Liu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16ceeb50edSMonk Liu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17ceeb50edSMonk Liu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18ceeb50edSMonk Liu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19ceeb50edSMonk Liu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20ceeb50edSMonk Liu * OTHER DEALINGS IN THE SOFTWARE. 21ceeb50edSMonk Liu * 22ceeb50edSMonk Liu * Author: Monk.liu@amd.com 23ceeb50edSMonk Liu */ 24ceeb50edSMonk Liu #ifndef AMDGPU_VIRT_H 25ceeb50edSMonk Liu #define AMDGPU_VIRT_H 26ceeb50edSMonk Liu 271721bc1bSBokun Zhang #include "amdgv_sriovmsg.h" 281721bc1bSBokun Zhang 29ceeb50edSMonk Liu #define AMDGPU_SRIOV_CAPS_SRIOV_VBIOS (1 << 0) /* vBIOS is sr-iov ready */ 30ceeb50edSMonk Liu #define AMDGPU_SRIOV_CAPS_ENABLE_IOV (1 << 1) /* sr-iov is enabled on this GPU */ 31ceeb50edSMonk Liu #define AMDGPU_SRIOV_CAPS_IS_VF (1 << 2) /* this GPU is a virtual function */ 32ceeb50edSMonk Liu #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is pass through for VM */ 335ec9f06eSXiangliang Yu #define AMDGPU_SRIOV_CAPS_RUNTIME (1 << 4) /* is out of full access mode */ 34*a7310d8dSDanijel Slivka #define AMDGPU_VF_MMIO_ACCESS_PROTECT (1 << 5) /* MMIO write access is not allowed in sriov runtime */ 35bd7de27dSMonk Liu 3629dbcac8SHawking Zhang /* flags for indirect register access path supported by rlcg for sriov */ 3729dbcac8SHawking Zhang #define AMDGPU_RLCG_GC_WRITE_LEGACY (0x8 << 28) 3829dbcac8SHawking Zhang #define AMDGPU_RLCG_GC_WRITE (0x0 << 28) 3929dbcac8SHawking Zhang #define AMDGPU_RLCG_GC_READ (0x1 << 28) 4029dbcac8SHawking Zhang #define AMDGPU_RLCG_MMHUB_WRITE (0x2 << 28) 4129dbcac8SHawking Zhang 425d447e29SHawking Zhang /* error code for indirect register access path supported by rlcg for sriov */ 435d447e29SHawking Zhang #define AMDGPU_RLCG_VFGATE_DISABLED 0x4000000 445d447e29SHawking Zhang #define AMDGPU_RLCG_WRONG_OPERATION_TYPE 0x2000000 455d447e29SHawking Zhang #define AMDGPU_RLCG_REG_NOT_IN_RANGE 0x1000000 465d447e29SHawking Zhang 47aa79d380SVictor Skvortsov #define AMDGPU_RLCG_SCRATCH1_ADDRESS_MASK 0xFFFFF 48aa79d380SVictor Skvortsov 493aa0115dSMonk Liu /* all asic after AI use this offset */ 503aa0115dSMonk Liu #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5 513aa0115dSMonk Liu /* tonga/fiji use this offset */ 523aa0115dSMonk Liu #define mmBIF_IOV_FUNC_IDENTIFIER 0x1503 533aa0115dSMonk Liu 54a7f28103SKevin Wang enum amdgpu_sriov_vf_mode { 55a7f28103SKevin Wang SRIOV_VF_MODE_BARE_METAL = 0, 56a7f28103SKevin Wang SRIOV_VF_MODE_ONE_VF, 57a7f28103SKevin Wang SRIOV_VF_MODE_MULTI_VF, 58a7f28103SKevin Wang }; 59a7f28103SKevin Wang 60ecb2b9c6SXiangliang Yu struct amdgpu_mm_table { 61ecb2b9c6SXiangliang Yu struct amdgpu_bo *bo; 62ecb2b9c6SXiangliang Yu uint32_t *cpu_addr; 63ecb2b9c6SXiangliang Yu uint64_t gpu_addr; 64ecb2b9c6SXiangliang Yu }; 65ecb2b9c6SXiangliang Yu 66e23b74aaSAlex Deucher #define AMDGPU_VF_ERROR_ENTRY_SIZE 16 67e23b74aaSAlex Deucher 68e23b74aaSAlex Deucher /* struct error_entry - amdgpu VF error information. */ 69e23b74aaSAlex Deucher struct amdgpu_vf_error_buffer { 70e23b74aaSAlex Deucher struct mutex lock; 71e23b74aaSAlex Deucher int read_count; 72e23b74aaSAlex Deucher int write_count; 73e23b74aaSAlex Deucher uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE]; 74e23b74aaSAlex Deucher uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE]; 75e23b74aaSAlex Deucher uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE]; 76e23b74aaSAlex Deucher }; 77e23b74aaSAlex Deucher 781e9f1392SXiangliang Yu /** 791e9f1392SXiangliang Yu * struct amdgpu_virt_ops - amdgpu device virt operations 801e9f1392SXiangliang Yu */ 811e9f1392SXiangliang Yu struct amdgpu_virt_ops { 821e9f1392SXiangliang Yu int (*req_full_gpu)(struct amdgpu_device *adev, bool init); 831e9f1392SXiangliang Yu int (*rel_full_gpu)(struct amdgpu_device *adev, bool init); 84aa53bc2eSMonk Liu int (*req_init_data)(struct amdgpu_device *adev); 851e9f1392SXiangliang Yu int (*reset_gpu)(struct amdgpu_device *adev); 86b636176eSpding int (*wait_reset)(struct amdgpu_device *adev); 8789041940SGavin Wan void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3); 881e9f1392SXiangliang Yu }; 891e9f1392SXiangliang Yu 902dc8f81eSHorace Chen /* 912dc8f81eSHorace Chen * Firmware Reserve Frame buffer 922dc8f81eSHorace Chen */ 932dc8f81eSHorace Chen struct amdgpu_virt_fw_reserve { 94bed1ed36SEmily Deng struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; 95bed1ed36SEmily Deng struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; 962dc8f81eSHorace Chen unsigned int checksum_key; 972dc8f81eSHorace Chen }; 981721bc1bSBokun Zhang 992dc8f81eSHorace Chen /* 1001721bc1bSBokun Zhang * Legacy GIM header 1011721bc1bSBokun Zhang * 1022dc8f81eSHorace Chen * Defination between PF and VF 1032dc8f81eSHorace Chen * Structures forcibly aligned to 4 to keep the same style as PF. 1042dc8f81eSHorace Chen */ 1052dc8f81eSHorace Chen #define AMDGIM_DATAEXCHANGE_OFFSET (64 * 1024) 1062dc8f81eSHorace Chen 1072dc8f81eSHorace Chen #define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \ 1082dc8f81eSHorace Chen (total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2)) 1092dc8f81eSHorace Chen 1102dc8f81eSHorace Chen enum AMDGIM_FEATURE_FLAG { 1112dc8f81eSHorace Chen /* GIM supports feature of Error log collecting */ 1122dc8f81eSHorace Chen AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1, 1132dc8f81eSHorace Chen /* GIM supports feature of loading uCodes */ 1142dc8f81eSHorace Chen AMDGIM_FEATURE_GIM_LOAD_UCODES = 0x2, 11575bc6099SMonk Liu /* VRAM LOST by GIM */ 11675bc6099SMonk Liu AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4, 117b89659b7SMonk Liu /* MM bandwidth */ 118b89659b7SMonk Liu AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8, 119c9ffa427SYintian Tao /* PP ONE VF MODE in GIM */ 120c9ffa427SYintian Tao AMDGIM_FEATURE_PP_ONE_VF = (1 << 4), 1214d675e1eSRohit Khaire /* Indirect Reg Access enabled */ 1224d675e1eSRohit Khaire AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5), 1234d675e1eSRohit Khaire }; 1244d675e1eSRohit Khaire 1254d675e1eSRohit Khaire enum AMDGIM_REG_ACCESS_FLAG { 1264d675e1eSRohit Khaire /* Use PSP to program IH_RB_CNTL */ 1274d675e1eSRohit Khaire AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0), 1284d675e1eSRohit Khaire /* Use RLC to program MMHUB regs */ 1298b8a162dSPeng Ju Zhou AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1), 1304d675e1eSRohit Khaire /* Use RLC to program GC regs */ 1318b8a162dSPeng Ju Zhou AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2), 1322dc8f81eSHorace Chen }; 1332dc8f81eSHorace Chen 1342dc8f81eSHorace Chen struct amdgim_pf2vf_info_v1 { 1352dc8f81eSHorace Chen /* header contains size and version */ 136bed1ed36SEmily Deng struct amd_sriov_msg_pf2vf_info_header header; 1372dc8f81eSHorace Chen /* max_width * max_height */ 1382dc8f81eSHorace Chen unsigned int uvd_enc_max_pixels_count; 1392dc8f81eSHorace Chen /* 16x16 pixels/sec, codec independent */ 1402dc8f81eSHorace Chen unsigned int uvd_enc_max_bandwidth; 1412dc8f81eSHorace Chen /* max_width * max_height */ 1422dc8f81eSHorace Chen unsigned int vce_enc_max_pixels_count; 1432dc8f81eSHorace Chen /* 16x16 pixels/sec, codec independent */ 1442dc8f81eSHorace Chen unsigned int vce_enc_max_bandwidth; 1452dc8f81eSHorace Chen /* MEC FW position in kb from the start of visible frame buffer */ 1462dc8f81eSHorace Chen unsigned int mecfw_kboffset; 1472dc8f81eSHorace Chen /* The features flags of the GIM driver supports. */ 1482dc8f81eSHorace Chen unsigned int feature_flags; 1492dc8f81eSHorace Chen /* use private key from mailbox 2 to create chueksum */ 1502dc8f81eSHorace Chen unsigned int checksum; 1512dc8f81eSHorace Chen } __aligned(4); 1522dc8f81eSHorace Chen 1532dc8f81eSHorace Chen struct amdgim_vf2pf_info_v1 { 1542dc8f81eSHorace Chen /* header contains size and version */ 155bed1ed36SEmily Deng struct amd_sriov_msg_vf2pf_info_header header; 1562dc8f81eSHorace Chen /* driver version */ 1572dc8f81eSHorace Chen char driver_version[64]; 1582dc8f81eSHorace Chen /* driver certification, 1=WHQL, 0=None */ 1592dc8f81eSHorace Chen unsigned int driver_cert; 1602dc8f81eSHorace Chen /* guest OS type and version: need a define */ 1612dc8f81eSHorace Chen unsigned int os_info; 1622dc8f81eSHorace Chen /* in the unit of 1M */ 1632dc8f81eSHorace Chen unsigned int fb_usage; 1642dc8f81eSHorace Chen /* guest gfx engine usage percentage */ 1652dc8f81eSHorace Chen unsigned int gfx_usage; 1662dc8f81eSHorace Chen /* guest gfx engine health percentage */ 1672dc8f81eSHorace Chen unsigned int gfx_health; 1682dc8f81eSHorace Chen /* guest compute engine usage percentage */ 1692dc8f81eSHorace Chen unsigned int compute_usage; 1702dc8f81eSHorace Chen /* guest compute engine health percentage */ 1712dc8f81eSHorace Chen unsigned int compute_health; 1722dc8f81eSHorace Chen /* guest vce engine usage percentage. 0xffff means N/A. */ 1732dc8f81eSHorace Chen unsigned int vce_enc_usage; 1742dc8f81eSHorace Chen /* guest vce engine health percentage. 0xffff means N/A. */ 1752dc8f81eSHorace Chen unsigned int vce_enc_health; 1762dc8f81eSHorace Chen /* guest uvd engine usage percentage. 0xffff means N/A. */ 1772dc8f81eSHorace Chen unsigned int uvd_enc_usage; 1782dc8f81eSHorace Chen /* guest uvd engine usage percentage. 0xffff means N/A. */ 1792dc8f81eSHorace Chen unsigned int uvd_enc_health; 1802dc8f81eSHorace Chen unsigned int checksum; 1812dc8f81eSHorace Chen } __aligned(4); 1822dc8f81eSHorace Chen 1832dc8f81eSHorace Chen struct amdgim_vf2pf_info_v2 { 1842dc8f81eSHorace Chen /* header contains size and version */ 185bed1ed36SEmily Deng struct amd_sriov_msg_vf2pf_info_header header; 1862dc8f81eSHorace Chen uint32_t checksum; 1872dc8f81eSHorace Chen /* driver version */ 1882dc8f81eSHorace Chen uint8_t driver_version[64]; 1892dc8f81eSHorace Chen /* driver certification, 1=WHQL, 0=None */ 1902dc8f81eSHorace Chen uint32_t driver_cert; 1912dc8f81eSHorace Chen /* guest OS type and version: need a define */ 1922dc8f81eSHorace Chen uint32_t os_info; 1932dc8f81eSHorace Chen /* in the unit of 1M */ 1942dc8f81eSHorace Chen uint32_t fb_usage; 1952dc8f81eSHorace Chen /* guest gfx engine usage percentage */ 1962dc8f81eSHorace Chen uint32_t gfx_usage; 1972dc8f81eSHorace Chen /* guest gfx engine health percentage */ 1982dc8f81eSHorace Chen uint32_t gfx_health; 1992dc8f81eSHorace Chen /* guest compute engine usage percentage */ 2002dc8f81eSHorace Chen uint32_t compute_usage; 2012dc8f81eSHorace Chen /* guest compute engine health percentage */ 2022dc8f81eSHorace Chen uint32_t compute_health; 2032dc8f81eSHorace Chen /* guest vce engine usage percentage. 0xffff means N/A. */ 2042dc8f81eSHorace Chen uint32_t vce_enc_usage; 2052dc8f81eSHorace Chen /* guest vce engine health percentage. 0xffff means N/A. */ 2062dc8f81eSHorace Chen uint32_t vce_enc_health; 2072dc8f81eSHorace Chen /* guest uvd engine usage percentage. 0xffff means N/A. */ 2082dc8f81eSHorace Chen uint32_t uvd_enc_usage; 2092dc8f81eSHorace Chen /* guest uvd engine usage percentage. 0xffff means N/A. */ 2102dc8f81eSHorace Chen uint32_t uvd_enc_health; 211bed1ed36SEmily Deng uint32_t reserved[AMDGIM_GET_STRUCTURE_RESERVED_SIZE(256, 64, 0, (12 + sizeof(struct amd_sriov_msg_vf2pf_info_header)/sizeof(uint32_t)), 0)]; 2122dc8f81eSHorace Chen } __aligned(4); 2132dc8f81eSHorace Chen 2145278a159SStanley.Yang struct amdgpu_virt_ras_err_handler_data { 2155278a159SStanley.Yang /* point to bad page records array */ 2165278a159SStanley.Yang struct eeprom_table_record *bps; 2175278a159SStanley.Yang /* point to reserved bo array */ 2185278a159SStanley.Yang struct amdgpu_bo **bps_bo; 2195278a159SStanley.Yang /* the count of entries */ 2205278a159SStanley.Yang int count; 2215278a159SStanley.Yang /* last reserved entry's index + 1 */ 2225278a159SStanley.Yang int last_reserved; 2235278a159SStanley.Yang }; 2245278a159SStanley.Yang 225ceeb50edSMonk Liu /* GPU virtualization */ 2265a5099cbSXiangliang Yu struct amdgpu_virt { 2275a5099cbSXiangliang Yu uint32_t caps; 228bd7de27dSMonk Liu struct amdgpu_bo *csa_obj; 22943974dacSJack Xiao void *csa_cpu_addr; 230ae65a26dSMonk Liu bool chained_ib_support; 231880e87e3SXiangliang Yu uint32_t reg_val_offs; 232ab71ac56SXiangliang Yu struct amdgpu_irq_src ack_irq; 233ab71ac56SXiangliang Yu struct amdgpu_irq_src rcv_irq; 234480da262SMonk Liu struct work_struct flr_work; 235ecb2b9c6SXiangliang Yu struct amdgpu_mm_table mm_table; 2361e9f1392SXiangliang Yu const struct amdgpu_virt_ops *ops; 237e23b74aaSAlex Deucher struct amdgpu_vf_error_buffer vf_errors; 2382dc8f81eSHorace Chen struct amdgpu_virt_fw_reserve fw_reserve; 23975bc6099SMonk Liu uint32_t gim_feature; 24078d48112STrigger Huang uint32_t reg_access_mode; 241aa53bc2eSMonk Liu int req_init_data_ver; 24295a2f917SYintian Tao bool tdr_debug; 2435278a159SStanley.Yang struct amdgpu_virt_ras_err_handler_data *virt_eh_data; 2445278a159SStanley.Yang bool ras_init_done; 2455d238510SPeng Ju Zhou uint32_t reg_access; 246519b8b76SBokun Zhang 247519b8b76SBokun Zhang /* vf2pf message */ 248519b8b76SBokun Zhang struct delayed_work vf2pf_work; 249519b8b76SBokun Zhang uint32_t vf2pf_update_interval_ms; 250ed9d2053SBokun Zhang 251ed9d2053SBokun Zhang /* multimedia bandwidth config */ 252ed9d2053SBokun Zhang bool is_mm_bw_enabled; 253ed9d2053SBokun Zhang uint32_t decode_max_dimension_pixels; 254ed9d2053SBokun Zhang uint32_t decode_max_frame_pixels; 255ed9d2053SBokun Zhang uint32_t encode_max_dimension_pixels; 256ed9d2053SBokun Zhang uint32_t encode_max_frame_pixels; 257f8bd7321SHorace Chen 258f8bd7321SHorace Chen /* the ucode id to signal the autoload */ 259f8bd7321SHorace Chen uint32_t autoload_ucode_id; 260ceeb50edSMonk Liu }; 261ceeb50edSMonk Liu 262ed9d2053SBokun Zhang struct amdgpu_video_codec_info; 263ed9d2053SBokun Zhang 264ceeb50edSMonk Liu #define amdgpu_sriov_enabled(adev) \ 2655a5099cbSXiangliang Yu ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_ENABLE_IOV) 266ceeb50edSMonk Liu 267ceeb50edSMonk Liu #define amdgpu_sriov_vf(adev) \ 2685a5099cbSXiangliang Yu ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_IS_VF) 269ceeb50edSMonk Liu 270ceeb50edSMonk Liu #define amdgpu_sriov_bios(adev) \ 2715a5099cbSXiangliang Yu ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS) 272ceeb50edSMonk Liu 2735ec9f06eSXiangliang Yu #define amdgpu_sriov_runtime(adev) \ 2745ec9f06eSXiangliang Yu ((adev)->virt.caps & AMDGPU_SRIOV_CAPS_RUNTIME) 2755ec9f06eSXiangliang Yu 2762e0cc4d4SMonk Liu #define amdgpu_sriov_fullaccess(adev) \ 2772e0cc4d4SMonk Liu (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev))) 2782e0cc4d4SMonk Liu 2795d238510SPeng Ju Zhou #define amdgpu_sriov_reg_indirect_en(adev) \ 2805d238510SPeng Ju Zhou (amdgpu_sriov_vf((adev)) && \ 2815d238510SPeng Ju Zhou ((adev)->virt.gim_feature & (AMDGIM_FEATURE_INDIRECT_REG_ACCESS))) 2825d238510SPeng Ju Zhou 2835d238510SPeng Ju Zhou #define amdgpu_sriov_reg_indirect_ih(adev) \ 2845d238510SPeng Ju Zhou (amdgpu_sriov_vf((adev)) && \ 2855d238510SPeng Ju Zhou ((adev)->virt.reg_access & (AMDGIM_FEATURE_IH_REG_PSP_EN))) 2865d238510SPeng Ju Zhou 2875d238510SPeng Ju Zhou #define amdgpu_sriov_reg_indirect_mmhub(adev) \ 2885d238510SPeng Ju Zhou (amdgpu_sriov_vf((adev)) && \ 2895d238510SPeng Ju Zhou ((adev)->virt.reg_access & (AMDGIM_FEATURE_MMHUB_REG_RLC_EN))) 2905d238510SPeng Ju Zhou 2915d238510SPeng Ju Zhou #define amdgpu_sriov_reg_indirect_gc(adev) \ 2925d238510SPeng Ju Zhou (amdgpu_sriov_vf((adev)) && \ 2935d238510SPeng Ju Zhou ((adev)->virt.reg_access & (AMDGIM_FEATURE_GC_REG_RLC_EN))) 2945d238510SPeng Ju Zhou 2955d447e29SHawking Zhang #define amdgpu_sriov_rlcg_error_report_enabled(adev) \ 2965d447e29SHawking Zhang (amdgpu_sriov_reg_indirect_mmhub(adev) || amdgpu_sriov_reg_indirect_gc(adev)) 2975d447e29SHawking Zhang 298ceeb50edSMonk Liu #define amdgpu_passthrough(adev) \ 2995a5099cbSXiangliang Yu ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE) 300ceeb50edSMonk Liu 301*a7310d8dSDanijel Slivka #define amdgpu_sriov_vf_mmio_access_protection(adev) \ 302*a7310d8dSDanijel Slivka ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) 303*a7310d8dSDanijel Slivka 304ceeb50edSMonk Liu static inline bool is_virtual_machine(void) 305ceeb50edSMonk Liu { 306039cacd2SVictor Zhao #if defined(CONFIG_X86) 307ceeb50edSMonk Liu return boot_cpu_has(X86_FEATURE_HYPERVISOR); 308039cacd2SVictor Zhao #elif defined(CONFIG_ARM64) 309039cacd2SVictor Zhao return !is_kernel_in_hyp_mode(); 310ceeb50edSMonk Liu #else 311ceeb50edSMonk Liu return false; 312ceeb50edSMonk Liu #endif 313ceeb50edSMonk Liu } 314ceeb50edSMonk Liu 315c9ffa427SYintian Tao #define amdgpu_sriov_is_pp_one_vf(adev) \ 316c9ffa427SYintian Tao ((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF) 31795a2f917SYintian Tao #define amdgpu_sriov_is_debug(adev) \ 31853b3f8f4SDennis Li ((!amdgpu_in_reset(adev)) && adev->virt.tdr_debug) 319d32709daSYintian Tao #define amdgpu_sriov_is_normal(adev) \ 32053b3f8f4SDennis Li ((!amdgpu_in_reset(adev)) && (!adev->virt.tdr_debug)) 321a16f8f11Spding bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev); 322bc992ba5SXiangliang Yu void amdgpu_virt_init_setting(struct amdgpu_device *adev); 323af5fe1e9SChristian König void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device *adev, 324af5fe1e9SChristian König uint32_t reg0, uint32_t rreg1, 325af5fe1e9SChristian König uint32_t ref, uint32_t mask); 3261e9f1392SXiangliang Yu int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init); 3271e9f1392SXiangliang Yu int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init); 3281e9f1392SXiangliang Yu int amdgpu_virt_reset_gpu(struct amdgpu_device *adev); 329aa53bc2eSMonk Liu void amdgpu_virt_request_init_data(struct amdgpu_device *adev); 330b636176eSpding int amdgpu_virt_wait_reset(struct amdgpu_device *adev); 331904cd389SXiangliang Yu int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev); 332904cd389SXiangliang Yu void amdgpu_virt_free_mm_table(struct amdgpu_device *adev); 3335278a159SStanley.Yang void amdgpu_virt_release_ras_err_handler_data(struct amdgpu_device *adev); 3342dc8f81eSHorace Chen void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev); 335892deb48SVictor Skvortsov void amdgpu_virt_exchange_data(struct amdgpu_device *adev); 336519b8b76SBokun Zhang void amdgpu_virt_fini_data_exchange(struct amdgpu_device *adev); 3373aa0115dSMonk Liu void amdgpu_detect_virtualization(struct amdgpu_device *adev); 33895a2f917SYintian Tao 33995a2f917SYintian Tao bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev); 34095a2f917SYintian Tao int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev); 34195a2f917SYintian Tao void amdgpu_virt_disable_access_debugfs(struct amdgpu_device *adev); 342a7f28103SKevin Wang 343a7f28103SKevin Wang enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *adev); 344ed9d2053SBokun Zhang 345ed9d2053SBokun Zhang void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev, 346ed9d2053SBokun Zhang struct amdgpu_video_codec_info *encode, uint32_t encode_array_size, 347ed9d2053SBokun Zhang struct amdgpu_video_codec_info *decode, uint32_t decode_array_size); 3485d447e29SHawking Zhang void amdgpu_sriov_wreg(struct amdgpu_device *adev, 3495d447e29SHawking Zhang u32 offset, u32 value, 3505d447e29SHawking Zhang u32 acc_flags, u32 hwip); 3515d447e29SHawking Zhang u32 amdgpu_sriov_rreg(struct amdgpu_device *adev, 3525d447e29SHawking Zhang u32 offset, u32 acc_flags, u32 hwip); 353d9d86d08SHorace Chen bool amdgpu_virt_fw_load_skip_check(struct amdgpu_device *adev, 354d9d86d08SHorace Chen uint32_t ucode_id); 355ceeb50edSMonk Liu #endif 356